2 * Copyright (c) 2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 MODULE_AUTHOR("Atheros Communications");
20 MODULE_LICENSE("Dual BSD/GPL");
21 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
23 static unsigned int ath9k_debug
= ATH_DBG_DEFAULT
;
24 module_param_named(debug
, ath9k_debug
, uint
, 0);
25 MODULE_PARM_DESC(debug
, "Debugging mask");
27 int htc_modparam_nohwcrypt
;
28 module_param_named(nohwcrypt
, htc_modparam_nohwcrypt
, int, 0444);
29 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption");
31 #define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
37 #define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
44 #define ATH_HTC_BTCOEX_PRODUCT_ID "wb193"
46 static struct ieee80211_channel ath9k_2ghz_channels
[] = {
47 CHAN2G(2412, 0), /* Channel 1 */
48 CHAN2G(2417, 1), /* Channel 2 */
49 CHAN2G(2422, 2), /* Channel 3 */
50 CHAN2G(2427, 3), /* Channel 4 */
51 CHAN2G(2432, 4), /* Channel 5 */
52 CHAN2G(2437, 5), /* Channel 6 */
53 CHAN2G(2442, 6), /* Channel 7 */
54 CHAN2G(2447, 7), /* Channel 8 */
55 CHAN2G(2452, 8), /* Channel 9 */
56 CHAN2G(2457, 9), /* Channel 10 */
57 CHAN2G(2462, 10), /* Channel 11 */
58 CHAN2G(2467, 11), /* Channel 12 */
59 CHAN2G(2472, 12), /* Channel 13 */
60 CHAN2G(2484, 13), /* Channel 14 */
63 static struct ieee80211_channel ath9k_5ghz_channels
[] = {
64 /* _We_ call this UNII 1 */
65 CHAN5G(5180, 14), /* Channel 36 */
66 CHAN5G(5200, 15), /* Channel 40 */
67 CHAN5G(5220, 16), /* Channel 44 */
68 CHAN5G(5240, 17), /* Channel 48 */
69 /* _We_ call this UNII 2 */
70 CHAN5G(5260, 18), /* Channel 52 */
71 CHAN5G(5280, 19), /* Channel 56 */
72 CHAN5G(5300, 20), /* Channel 60 */
73 CHAN5G(5320, 21), /* Channel 64 */
74 /* _We_ call this "Middle band" */
75 CHAN5G(5500, 22), /* Channel 100 */
76 CHAN5G(5520, 23), /* Channel 104 */
77 CHAN5G(5540, 24), /* Channel 108 */
78 CHAN5G(5560, 25), /* Channel 112 */
79 CHAN5G(5580, 26), /* Channel 116 */
80 CHAN5G(5600, 27), /* Channel 120 */
81 CHAN5G(5620, 28), /* Channel 124 */
82 CHAN5G(5640, 29), /* Channel 128 */
83 CHAN5G(5660, 30), /* Channel 132 */
84 CHAN5G(5680, 31), /* Channel 136 */
85 CHAN5G(5700, 32), /* Channel 140 */
86 /* _We_ call this UNII 3 */
87 CHAN5G(5745, 33), /* Channel 149 */
88 CHAN5G(5765, 34), /* Channel 153 */
89 CHAN5G(5785, 35), /* Channel 157 */
90 CHAN5G(5805, 36), /* Channel 161 */
91 CHAN5G(5825, 37), /* Channel 165 */
94 /* Atheros hardware rate code addition for short premble */
95 #define SHPCHECK(__hw_rate, __flags) \
96 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
98 #define RATE(_bitrate, _hw_rate, _flags) { \
99 .bitrate = (_bitrate), \
101 .hw_value = (_hw_rate), \
102 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
105 static struct ieee80211_rate ath9k_legacy_rates
[] = {
107 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE
), /* shortp : 0x1e */
108 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE
), /* shortp: 0x1d */
109 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE
), /* short: 0x1c */
120 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv
*priv
)
124 if (atomic_read(&priv
->htc
->tgt_ready
) > 0) {
125 atomic_dec(&priv
->htc
->tgt_ready
);
129 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
130 time_left
= wait_for_completion_timeout(&priv
->htc
->target_wait
, HZ
);
132 dev_err(priv
->dev
, "ath9k_htc: Target is unresponsive\n");
136 atomic_dec(&priv
->htc
->tgt_ready
);
141 static void ath9k_deinit_priv(struct ath9k_htc_priv
*priv
)
143 ath9k_htc_exit_debug(priv
->ah
);
144 ath9k_hw_deinit(priv
->ah
);
149 static void ath9k_deinit_device(struct ath9k_htc_priv
*priv
)
151 struct ieee80211_hw
*hw
= priv
->hw
;
153 wiphy_rfkill_stop_polling(hw
->wiphy
);
154 ath9k_deinit_leds(priv
);
155 ieee80211_unregister_hw(hw
);
156 ath9k_rx_cleanup(priv
);
157 ath9k_tx_cleanup(priv
);
158 ath9k_deinit_priv(priv
);
161 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv
*priv
,
165 enum htc_endpoint_id
,
167 enum htc_endpoint_id
*ep_id
)
169 struct htc_service_connreq req
;
171 memset(&req
, 0, sizeof(struct htc_service_connreq
));
173 req
.service_id
= service_id
;
174 req
.ep_callbacks
.priv
= priv
;
175 req
.ep_callbacks
.rx
= ath9k_htc_rxep
;
176 req
.ep_callbacks
.tx
= tx
;
178 return htc_connect_service(priv
->htc
, &req
, ep_id
);
181 static int ath9k_init_htc_services(struct ath9k_htc_priv
*priv
, u16 devid
,
187 ret
= ath9k_wmi_connect(priv
->htc
, priv
->wmi
, &priv
->wmi_cmd_ep
);
192 ret
= ath9k_htc_connect_svc(priv
, WMI_BEACON_SVC
, ath9k_htc_beaconep
,
198 ret
= ath9k_htc_connect_svc(priv
, WMI_CAB_SVC
, ath9k_htc_txep
,
205 ret
= ath9k_htc_connect_svc(priv
, WMI_UAPSD_SVC
, ath9k_htc_txep
,
211 ret
= ath9k_htc_connect_svc(priv
, WMI_MGMT_SVC
, ath9k_htc_txep
,
217 ret
= ath9k_htc_connect_svc(priv
, WMI_DATA_BE_SVC
, ath9k_htc_txep
,
223 ret
= ath9k_htc_connect_svc(priv
, WMI_DATA_BK_SVC
, ath9k_htc_txep
,
229 ret
= ath9k_htc_connect_svc(priv
, WMI_DATA_VI_SVC
, ath9k_htc_txep
,
235 ret
= ath9k_htc_connect_svc(priv
, WMI_DATA_VO_SVC
, ath9k_htc_txep
,
241 * Setup required credits before initializing HTC.
242 * This is a bit hacky, but, since queuing is done in
243 * the HIF layer, shouldn't matter much.
246 if (IS_AR7010_DEVICE(drv_info
))
247 priv
->htc
->credits
= 45;
249 priv
->htc
->credits
= 33;
251 ret
= htc_init(priv
->htc
);
255 dev_info(priv
->dev
, "ath9k_htc: HTC initialized with %d credits\n",
261 dev_err(priv
->dev
, "ath9k_htc: Unable to initialize HTC services\n");
265 static int ath9k_reg_notifier(struct wiphy
*wiphy
,
266 struct regulatory_request
*request
)
268 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
269 struct ath9k_htc_priv
*priv
= hw
->priv
;
271 return ath_reg_notifier_apply(wiphy
, request
,
272 ath9k_hw_regulatory(priv
->ah
));
275 static unsigned int ath9k_regread(void *hw_priv
, u32 reg_offset
)
277 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
278 struct ath_common
*common
= ath9k_hw_common(ah
);
279 struct ath9k_htc_priv
*priv
= (struct ath9k_htc_priv
*) common
->priv
;
280 __be32 val
, reg
= cpu_to_be32(reg_offset
);
283 r
= ath9k_wmi_cmd(priv
->wmi
, WMI_REG_READ_CMDID
,
284 (u8
*) ®
, sizeof(reg
),
285 (u8
*) &val
, sizeof(val
),
288 ath_dbg(common
, ATH_DBG_WMI
,
289 "REGISTER READ FAILED: (0x%04x, %d)\n",
294 return be32_to_cpu(val
);
297 static void ath9k_multi_regread(void *hw_priv
, u32
*addr
,
300 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
301 struct ath_common
*common
= ath9k_hw_common(ah
);
302 struct ath9k_htc_priv
*priv
= (struct ath9k_htc_priv
*) common
->priv
;
307 for (i
= 0; i
< count
; i
++) {
308 tmpaddr
[i
] = cpu_to_be32(addr
[i
]);
311 ret
= ath9k_wmi_cmd(priv
->wmi
, WMI_REG_READ_CMDID
,
312 (u8
*)tmpaddr
, sizeof(u32
) * count
,
313 (u8
*)tmpval
, sizeof(u32
) * count
,
316 ath_dbg(common
, ATH_DBG_WMI
,
317 "Multiple REGISTER READ FAILED (count: %d)\n", count
);
320 for (i
= 0; i
< count
; i
++) {
321 val
[i
] = be32_to_cpu(tmpval
[i
]);
325 static void ath9k_regwrite_single(void *hw_priv
, u32 val
, u32 reg_offset
)
327 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
328 struct ath_common
*common
= ath9k_hw_common(ah
);
329 struct ath9k_htc_priv
*priv
= (struct ath9k_htc_priv
*) common
->priv
;
330 const __be32 buf
[2] = {
331 cpu_to_be32(reg_offset
),
336 r
= ath9k_wmi_cmd(priv
->wmi
, WMI_REG_WRITE_CMDID
,
337 (u8
*) &buf
, sizeof(buf
),
338 (u8
*) &val
, sizeof(val
),
341 ath_dbg(common
, ATH_DBG_WMI
,
342 "REGISTER WRITE FAILED:(0x%04x, %d)\n",
347 static void ath9k_regwrite_buffer(void *hw_priv
, u32 val
, u32 reg_offset
)
349 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
350 struct ath_common
*common
= ath9k_hw_common(ah
);
351 struct ath9k_htc_priv
*priv
= (struct ath9k_htc_priv
*) common
->priv
;
355 mutex_lock(&priv
->wmi
->multi_write_mutex
);
357 /* Store the register/value */
358 priv
->wmi
->multi_write
[priv
->wmi
->multi_write_idx
].reg
=
359 cpu_to_be32(reg_offset
);
360 priv
->wmi
->multi_write
[priv
->wmi
->multi_write_idx
].val
=
363 priv
->wmi
->multi_write_idx
++;
365 /* If the buffer is full, send it out. */
366 if (priv
->wmi
->multi_write_idx
== MAX_CMD_NUMBER
) {
367 r
= ath9k_wmi_cmd(priv
->wmi
, WMI_REG_WRITE_CMDID
,
368 (u8
*) &priv
->wmi
->multi_write
,
369 sizeof(struct register_write
) * priv
->wmi
->multi_write_idx
,
370 (u8
*) &rsp_status
, sizeof(rsp_status
),
373 ath_dbg(common
, ATH_DBG_WMI
,
374 "REGISTER WRITE FAILED, multi len: %d\n",
375 priv
->wmi
->multi_write_idx
);
377 priv
->wmi
->multi_write_idx
= 0;
380 mutex_unlock(&priv
->wmi
->multi_write_mutex
);
383 static void ath9k_regwrite(void *hw_priv
, u32 val
, u32 reg_offset
)
385 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
386 struct ath_common
*common
= ath9k_hw_common(ah
);
387 struct ath9k_htc_priv
*priv
= (struct ath9k_htc_priv
*) common
->priv
;
389 if (atomic_read(&priv
->wmi
->mwrite_cnt
))
390 ath9k_regwrite_buffer(hw_priv
, val
, reg_offset
);
392 ath9k_regwrite_single(hw_priv
, val
, reg_offset
);
395 static void ath9k_enable_regwrite_buffer(void *hw_priv
)
397 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
398 struct ath_common
*common
= ath9k_hw_common(ah
);
399 struct ath9k_htc_priv
*priv
= (struct ath9k_htc_priv
*) common
->priv
;
401 atomic_inc(&priv
->wmi
->mwrite_cnt
);
404 static void ath9k_regwrite_flush(void *hw_priv
)
406 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
407 struct ath_common
*common
= ath9k_hw_common(ah
);
408 struct ath9k_htc_priv
*priv
= (struct ath9k_htc_priv
*) common
->priv
;
412 atomic_dec(&priv
->wmi
->mwrite_cnt
);
414 mutex_lock(&priv
->wmi
->multi_write_mutex
);
416 if (priv
->wmi
->multi_write_idx
) {
417 r
= ath9k_wmi_cmd(priv
->wmi
, WMI_REG_WRITE_CMDID
,
418 (u8
*) &priv
->wmi
->multi_write
,
419 sizeof(struct register_write
) * priv
->wmi
->multi_write_idx
,
420 (u8
*) &rsp_status
, sizeof(rsp_status
),
423 ath_dbg(common
, ATH_DBG_WMI
,
424 "REGISTER WRITE FAILED, multi len: %d\n",
425 priv
->wmi
->multi_write_idx
);
427 priv
->wmi
->multi_write_idx
= 0;
430 mutex_unlock(&priv
->wmi
->multi_write_mutex
);
433 static const struct ath_ops ath9k_common_ops
= {
434 .read
= ath9k_regread
,
435 .multi_read
= ath9k_multi_regread
,
436 .write
= ath9k_regwrite
,
437 .enable_write_buffer
= ath9k_enable_regwrite_buffer
,
438 .write_flush
= ath9k_regwrite_flush
,
441 static void ath_usb_read_cachesize(struct ath_common
*common
, int *csz
)
443 *csz
= L1_CACHE_BYTES
>> 2;
446 static bool ath_usb_eeprom_read(struct ath_common
*common
, u32 off
, u16
*data
)
448 struct ath_hw
*ah
= (struct ath_hw
*) common
->ah
;
450 (void)REG_READ(ah
, AR5416_EEPROM_OFFSET
+ (off
<< AR5416_EEPROM_S
));
452 if (!ath9k_hw_wait(ah
,
453 AR_EEPROM_STATUS_DATA
,
454 AR_EEPROM_STATUS_DATA_BUSY
|
455 AR_EEPROM_STATUS_DATA_PROT_ACCESS
, 0,
459 *data
= MS(REG_READ(ah
, AR_EEPROM_STATUS_DATA
),
460 AR_EEPROM_STATUS_DATA_VAL
);
465 static const struct ath_bus_ops ath9k_usb_bus_ops
= {
466 .ath_bus_type
= ATH_USB
,
467 .read_cachesize
= ath_usb_read_cachesize
,
468 .eeprom_read
= ath_usb_eeprom_read
,
471 static void setup_ht_cap(struct ath9k_htc_priv
*priv
,
472 struct ieee80211_sta_ht_cap
*ht_info
)
474 struct ath_common
*common
= ath9k_hw_common(priv
->ah
);
475 u8 tx_streams
, rx_streams
;
478 ht_info
->ht_supported
= true;
479 ht_info
->cap
= IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
480 IEEE80211_HT_CAP_SM_PS
|
481 IEEE80211_HT_CAP_SGI_40
|
482 IEEE80211_HT_CAP_DSSSCCK40
;
484 if (priv
->ah
->caps
.hw_caps
& ATH9K_HW_CAP_SGI_20
)
485 ht_info
->cap
|= IEEE80211_HT_CAP_SGI_20
;
487 ht_info
->cap
|= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT
);
489 ht_info
->ampdu_factor
= IEEE80211_HT_MAX_AMPDU_64K
;
490 ht_info
->ampdu_density
= IEEE80211_HT_MPDU_DENSITY_8
;
492 memset(&ht_info
->mcs
, 0, sizeof(ht_info
->mcs
));
494 /* ath9k_htc supports only 1 or 2 stream devices */
495 tx_streams
= ath9k_cmn_count_streams(common
->tx_chainmask
, 2);
496 rx_streams
= ath9k_cmn_count_streams(common
->rx_chainmask
, 2);
498 ath_dbg(common
, ATH_DBG_CONFIG
,
499 "TX streams %d, RX streams: %d\n",
500 tx_streams
, rx_streams
);
502 if (tx_streams
!= rx_streams
) {
503 ht_info
->mcs
.tx_params
|= IEEE80211_HT_MCS_TX_RX_DIFF
;
504 ht_info
->mcs
.tx_params
|= ((tx_streams
- 1) <<
505 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
508 for (i
= 0; i
< rx_streams
; i
++)
509 ht_info
->mcs
.rx_mask
[i
] = 0xff;
511 ht_info
->mcs
.tx_params
|= IEEE80211_HT_MCS_TX_DEFINED
;
514 static int ath9k_init_queues(struct ath9k_htc_priv
*priv
)
516 struct ath_common
*common
= ath9k_hw_common(priv
->ah
);
519 for (i
= 0; i
< ARRAY_SIZE(priv
->hwq_map
); i
++)
520 priv
->hwq_map
[i
] = -1;
522 priv
->beaconq
= ath9k_hw_beaconq_setup(priv
->ah
);
523 if (priv
->beaconq
== -1) {
524 ath_err(common
, "Unable to setup BEACON xmit queue\n");
528 priv
->cabq
= ath9k_htc_cabq_setup(priv
);
529 if (priv
->cabq
== -1) {
530 ath_err(common
, "Unable to setup CAB xmit queue\n");
534 if (!ath9k_htc_txq_setup(priv
, WME_AC_BE
)) {
535 ath_err(common
, "Unable to setup xmit queue for BE traffic\n");
539 if (!ath9k_htc_txq_setup(priv
, WME_AC_BK
)) {
540 ath_err(common
, "Unable to setup xmit queue for BK traffic\n");
543 if (!ath9k_htc_txq_setup(priv
, WME_AC_VI
)) {
544 ath_err(common
, "Unable to setup xmit queue for VI traffic\n");
547 if (!ath9k_htc_txq_setup(priv
, WME_AC_VO
)) {
548 ath_err(common
, "Unable to setup xmit queue for VO traffic\n");
558 static void ath9k_init_crypto(struct ath9k_htc_priv
*priv
)
560 struct ath_common
*common
= ath9k_hw_common(priv
->ah
);
563 /* Get the hardware key cache size. */
564 common
->keymax
= priv
->ah
->caps
.keycache_size
;
565 if (common
->keymax
> ATH_KEYMAX
) {
566 ath_dbg(common
, ATH_DBG_ANY
,
567 "Warning, using only %u entries in %u key cache\n",
568 ATH_KEYMAX
, common
->keymax
);
569 common
->keymax
= ATH_KEYMAX
;
572 if (priv
->ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
)
573 common
->crypt_caps
|= ATH_CRYPT_CAP_MIC_COMBINED
;
576 * Reset the key cache since some parts do not
577 * reset the contents on initial power up.
579 for (i
= 0; i
< common
->keymax
; i
++)
580 ath_hw_keyreset(common
, (u16
) i
);
583 static void ath9k_init_channels_rates(struct ath9k_htc_priv
*priv
)
585 if (priv
->ah
->caps
.hw_caps
& ATH9K_HW_CAP_2GHZ
) {
586 priv
->sbands
[IEEE80211_BAND_2GHZ
].channels
=
588 priv
->sbands
[IEEE80211_BAND_2GHZ
].band
= IEEE80211_BAND_2GHZ
;
589 priv
->sbands
[IEEE80211_BAND_2GHZ
].n_channels
=
590 ARRAY_SIZE(ath9k_2ghz_channels
);
591 priv
->sbands
[IEEE80211_BAND_2GHZ
].bitrates
= ath9k_legacy_rates
;
592 priv
->sbands
[IEEE80211_BAND_2GHZ
].n_bitrates
=
593 ARRAY_SIZE(ath9k_legacy_rates
);
596 if (priv
->ah
->caps
.hw_caps
& ATH9K_HW_CAP_5GHZ
) {
597 priv
->sbands
[IEEE80211_BAND_5GHZ
].channels
= ath9k_5ghz_channels
;
598 priv
->sbands
[IEEE80211_BAND_5GHZ
].band
= IEEE80211_BAND_5GHZ
;
599 priv
->sbands
[IEEE80211_BAND_5GHZ
].n_channels
=
600 ARRAY_SIZE(ath9k_5ghz_channels
);
601 priv
->sbands
[IEEE80211_BAND_5GHZ
].bitrates
=
602 ath9k_legacy_rates
+ 4;
603 priv
->sbands
[IEEE80211_BAND_5GHZ
].n_bitrates
=
604 ARRAY_SIZE(ath9k_legacy_rates
) - 4;
608 static void ath9k_init_misc(struct ath9k_htc_priv
*priv
)
610 struct ath_common
*common
= ath9k_hw_common(priv
->ah
);
612 common
->tx_chainmask
= priv
->ah
->caps
.tx_chainmask
;
613 common
->rx_chainmask
= priv
->ah
->caps
.rx_chainmask
;
615 memcpy(common
->bssidmask
, ath_bcast_mac
, ETH_ALEN
);
617 priv
->ah
->opmode
= NL80211_IFTYPE_STATION
;
620 static void ath9k_init_btcoex(struct ath9k_htc_priv
*priv
)
624 switch (priv
->ah
->btcoex_hw
.scheme
) {
625 case ATH_BTCOEX_CFG_NONE
:
627 case ATH_BTCOEX_CFG_3WIRE
:
628 priv
->ah
->btcoex_hw
.btactive_gpio
= 7;
629 priv
->ah
->btcoex_hw
.btpriority_gpio
= 6;
630 priv
->ah
->btcoex_hw
.wlanactive_gpio
= 8;
631 priv
->btcoex
.bt_stomp_type
= ATH_BTCOEX_STOMP_LOW
;
632 ath9k_hw_btcoex_init_3wire(priv
->ah
);
633 ath_htc_init_btcoex_work(priv
);
634 qnum
= priv
->hwq_map
[WME_AC_BE
];
635 ath9k_hw_init_btcoex_hw(priv
->ah
, qnum
);
643 static int ath9k_init_priv(struct ath9k_htc_priv
*priv
,
644 u16 devid
, char *product
,
647 struct ath_hw
*ah
= NULL
;
648 struct ath_common
*common
;
649 int ret
= 0, csz
= 0;
651 priv
->op_flags
|= OP_INVALID
;
653 ah
= kzalloc(sizeof(struct ath_hw
), GFP_KERNEL
);
657 ah
->hw_version
.devid
= devid
;
658 ah
->hw_version
.subsysid
= 0; /* FIXME */
659 ah
->hw_version
.usbdev
= drv_info
;
660 ah
->ah_flags
|= AH_USE_EEPROM
;
663 common
= ath9k_hw_common(ah
);
664 common
->ops
= &ath9k_common_ops
;
665 common
->bus_ops
= &ath9k_usb_bus_ops
;
667 common
->hw
= priv
->hw
;
669 common
->debug_mask
= ath9k_debug
;
671 spin_lock_init(&priv
->wmi
->wmi_lock
);
672 spin_lock_init(&priv
->beacon_lock
);
673 spin_lock_init(&priv
->tx_lock
);
674 mutex_init(&priv
->mutex
);
675 mutex_init(&priv
->htc_pm_lock
);
676 tasklet_init(&priv
->swba_tasklet
, ath9k_swba_tasklet
,
677 (unsigned long)priv
);
678 tasklet_init(&priv
->rx_tasklet
, ath9k_rx_tasklet
,
679 (unsigned long)priv
);
680 tasklet_init(&priv
->tx_tasklet
, ath9k_tx_tasklet
,
681 (unsigned long)priv
);
682 INIT_DELAYED_WORK(&priv
->ani_work
, ath9k_htc_ani_work
);
683 INIT_WORK(&priv
->ps_work
, ath9k_ps_work
);
684 INIT_WORK(&priv
->fatal_work
, ath9k_fatal_work
);
687 * Cache line size is used to size and align various
688 * structures used to communicate with the hardware.
690 ath_read_cachesize(common
, &csz
);
691 common
->cachelsz
= csz
<< 2; /* convert to bytes */
693 ret
= ath9k_hw_init(ah
);
696 "Unable to initialize hardware; initialization status: %d\n",
701 ret
= ath9k_htc_init_debug(ah
);
703 ath_err(common
, "Unable to create debugfs files\n");
707 ret
= ath9k_init_queues(priv
);
711 ath9k_init_crypto(priv
);
712 ath9k_init_channels_rates(priv
);
713 ath9k_init_misc(priv
);
715 if (product
&& strncmp(product
, ATH_HTC_BTCOEX_PRODUCT_ID
, 5) == 0) {
716 ah
->btcoex_hw
.scheme
= ATH_BTCOEX_CFG_3WIRE
;
717 ath9k_init_btcoex(priv
);
723 ath9k_htc_exit_debug(ah
);
734 static void ath9k_set_hw_capab(struct ath9k_htc_priv
*priv
,
735 struct ieee80211_hw
*hw
)
737 struct ath_common
*common
= ath9k_hw_common(priv
->ah
);
739 hw
->flags
= IEEE80211_HW_SIGNAL_DBM
|
740 IEEE80211_HW_AMPDU_AGGREGATION
|
741 IEEE80211_HW_SPECTRUM_MGMT
|
742 IEEE80211_HW_HAS_RATE_CONTROL
|
743 IEEE80211_HW_RX_INCLUDES_FCS
|
744 IEEE80211_HW_SUPPORTS_PS
|
745 IEEE80211_HW_PS_NULLFUNC_STACK
;
747 hw
->wiphy
->interface_modes
=
748 BIT(NL80211_IFTYPE_STATION
) |
749 BIT(NL80211_IFTYPE_ADHOC
);
751 hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
754 hw
->channel_change_time
= 5000;
755 hw
->max_listen_interval
= 10;
756 hw
->vif_data_size
= sizeof(struct ath9k_htc_vif
);
757 hw
->sta_data_size
= sizeof(struct ath9k_htc_sta
);
759 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
760 hw
->extra_tx_headroom
= sizeof(struct tx_frame_hdr
) +
761 sizeof(struct htc_frame_hdr
) + 4;
763 if (priv
->ah
->caps
.hw_caps
& ATH9K_HW_CAP_2GHZ
)
764 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
765 &priv
->sbands
[IEEE80211_BAND_2GHZ
];
766 if (priv
->ah
->caps
.hw_caps
& ATH9K_HW_CAP_5GHZ
)
767 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
768 &priv
->sbands
[IEEE80211_BAND_5GHZ
];
770 if (priv
->ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
771 if (priv
->ah
->caps
.hw_caps
& ATH9K_HW_CAP_2GHZ
)
773 &priv
->sbands
[IEEE80211_BAND_2GHZ
].ht_cap
);
774 if (priv
->ah
->caps
.hw_caps
& ATH9K_HW_CAP_5GHZ
)
776 &priv
->sbands
[IEEE80211_BAND_5GHZ
].ht_cap
);
779 SET_IEEE80211_PERM_ADDR(hw
, common
->macaddr
);
782 static int ath9k_init_device(struct ath9k_htc_priv
*priv
,
783 u16 devid
, char *product
, u32 drv_info
)
785 struct ieee80211_hw
*hw
= priv
->hw
;
786 struct ath_common
*common
;
789 struct ath_regulatory
*reg
;
792 /* Bring up device */
793 error
= ath9k_init_priv(priv
, devid
, product
, drv_info
);
798 common
= ath9k_hw_common(ah
);
799 ath9k_set_hw_capab(priv
, hw
);
801 /* Initialize regulatory */
802 error
= ath_regd_init(&common
->regulatory
, priv
->hw
->wiphy
,
807 reg
= &common
->regulatory
;
810 error
= ath9k_tx_init(priv
);
815 error
= ath9k_rx_init(priv
);
819 /* Register with mac80211 */
820 error
= ieee80211_register_hw(hw
);
824 /* Handle world regulatory */
825 if (!ath_is_world_regd(reg
)) {
826 error
= regulatory_hint(hw
->wiphy
, reg
->alpha2
);
831 ath_dbg(common
, ATH_DBG_CONFIG
,
832 "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, "
833 "BE:%d, BK:%d, VI:%d, VO:%d\n",
844 ath9k_hw_name(priv
->ah
, hw_name
, sizeof(hw_name
));
845 wiphy_info(hw
->wiphy
, "%s\n", hw_name
);
847 ath9k_init_leds(priv
);
848 ath9k_start_rfkill_poll(priv
);
853 ieee80211_unregister_hw(hw
);
855 ath9k_rx_cleanup(priv
);
857 ath9k_tx_cleanup(priv
);
861 ath9k_deinit_priv(priv
);
866 int ath9k_htc_probe_device(struct htc_target
*htc_handle
, struct device
*dev
,
867 u16 devid
, char *product
, u32 drv_info
)
869 struct ieee80211_hw
*hw
;
870 struct ath9k_htc_priv
*priv
;
873 hw
= ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv
), &ath9k_htc_ops
);
879 priv
->htc
= htc_handle
;
881 htc_handle
->drv_priv
= priv
;
882 SET_IEEE80211_DEV(hw
, priv
->dev
);
884 ret
= ath9k_htc_wait_for_target(priv
);
888 priv
->wmi
= ath9k_init_wmi(priv
);
894 ret
= ath9k_init_htc_services(priv
, devid
, drv_info
);
898 ret
= ath9k_init_device(priv
, devid
, product
, drv_info
);
905 ath9k_deinit_wmi(priv
);
907 ieee80211_free_hw(hw
);
911 void ath9k_htc_disconnect_device(struct htc_target
*htc_handle
, bool hotunplug
)
913 if (htc_handle
->drv_priv
) {
915 /* Check if the device has been yanked out. */
917 htc_handle
->drv_priv
->ah
->ah_flags
|= AH_UNPLUGGED
;
919 ath9k_deinit_device(htc_handle
->drv_priv
);
920 ath9k_deinit_wmi(htc_handle
->drv_priv
);
921 ieee80211_free_hw(htc_handle
->drv_priv
->hw
);
927 void ath9k_htc_suspend(struct htc_target
*htc_handle
)
929 ath9k_htc_setpower(htc_handle
->drv_priv
, ATH9K_PM_FULL_SLEEP
);
932 int ath9k_htc_resume(struct htc_target
*htc_handle
)
934 struct ath9k_htc_priv
*priv
= htc_handle
->drv_priv
;
937 ret
= ath9k_htc_wait_for_target(priv
);
941 ret
= ath9k_init_htc_services(priv
, priv
->ah
->hw_version
.devid
,
942 priv
->ah
->hw_version
.usbdev
);
947 static int __init
ath9k_htc_init(void)
951 error
= ath9k_htc_debug_create_root();
954 "ath9k_htc: Unable to create debugfs root: %d\n",
959 error
= ath9k_hif_usb_init();
962 "ath9k_htc: No USB devices found,"
963 " driver not installed.\n");
971 ath9k_htc_debug_remove_root();
975 module_init(ath9k_htc_init
);
977 static void __exit
ath9k_htc_exit(void)
979 ath9k_hif_usb_exit();
980 ath9k_htc_debug_remove_root();
981 printk(KERN_INFO
"ath9k_htc: Driver unloaded\n");
983 module_exit(ath9k_htc_exit
);