2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
25 #define ATH9K_CLOCK_RATE_CCK 22
26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
29 static void ar9002_hw_attach_ops(struct ath_hw
*ah
);
31 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
33 MODULE_AUTHOR("Atheros Communications");
34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36 MODULE_LICENSE("Dual BSD/GPL");
38 static int __init
ath9k_init(void)
42 module_init(ath9k_init
);
44 static void __exit
ath9k_exit(void)
48 module_exit(ath9k_exit
);
50 /* Private hardware callbacks */
52 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
54 ath9k_hw_private_ops(ah
)->init_cal_settings(ah
);
57 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
59 ath9k_hw_private_ops(ah
)->init_mode_regs(ah
);
62 static bool ath9k_hw_macversion_supported(struct ath_hw
*ah
)
64 struct ath_hw_private_ops
*priv_ops
= ath9k_hw_private_ops(ah
);
66 return priv_ops
->macversion_supported(ah
->hw_version
.macVersion
);
69 static u32
ath9k_hw_compute_pll_control(struct ath_hw
*ah
,
70 struct ath9k_channel
*chan
)
72 return ath9k_hw_private_ops(ah
)->compute_pll_control(ah
, chan
);
75 /********************/
76 /* Helper Functions */
77 /********************/
79 static u32
ath9k_hw_mac_clks(struct ath_hw
*ah
, u32 usecs
)
81 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
83 if (!ah
->curchan
) /* should really check for CCK instead */
84 return usecs
*ATH9K_CLOCK_RATE_CCK
;
85 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
86 return usecs
*ATH9K_CLOCK_RATE_2GHZ_OFDM
;
87 return usecs
*ATH9K_CLOCK_RATE_5GHZ_OFDM
;
90 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
92 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
94 if (conf_is_ht40(conf
))
95 return ath9k_hw_mac_clks(ah
, usecs
) * 2;
97 return ath9k_hw_mac_clks(ah
, usecs
);
100 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
104 BUG_ON(timeout
< AH_TIME_QUANTUM
);
106 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
107 if ((REG_READ(ah
, reg
) & mask
) == val
)
110 udelay(AH_TIME_QUANTUM
);
113 ath_print(ath9k_hw_common(ah
), ATH_DBG_ANY
,
114 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
115 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
119 EXPORT_SYMBOL(ath9k_hw_wait
);
121 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
126 for (i
= 0, retval
= 0; i
< n
; i
++) {
127 retval
= (retval
<< 1) | (val
& 1);
133 bool ath9k_get_channel_edges(struct ath_hw
*ah
,
137 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
139 if (flags
& CHANNEL_5GHZ
) {
140 *low
= pCap
->low_5ghz_chan
;
141 *high
= pCap
->high_5ghz_chan
;
144 if ((flags
& CHANNEL_2GHZ
)) {
145 *low
= pCap
->low_2ghz_chan
;
146 *high
= pCap
->high_2ghz_chan
;
152 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
154 u32 frameLen
, u16 rateix
,
157 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
163 case WLAN_RC_PHY_CCK
:
164 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
167 numBits
= frameLen
<< 3;
168 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
170 case WLAN_RC_PHY_OFDM
:
171 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
172 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
173 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
174 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
175 txTime
= OFDM_SIFS_TIME_QUARTER
176 + OFDM_PREAMBLE_TIME_QUARTER
177 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
178 } else if (ah
->curchan
&&
179 IS_CHAN_HALF_RATE(ah
->curchan
)) {
180 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
181 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
182 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
183 txTime
= OFDM_SIFS_TIME_HALF
+
184 OFDM_PREAMBLE_TIME_HALF
185 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
187 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
188 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
189 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
190 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
191 + (numSymbols
* OFDM_SYMBOL_TIME
);
195 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
196 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
203 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
205 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
206 struct ath9k_channel
*chan
,
207 struct chan_centers
*centers
)
211 if (!IS_CHAN_HT40(chan
)) {
212 centers
->ctl_center
= centers
->ext_center
=
213 centers
->synth_center
= chan
->channel
;
217 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
218 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
219 centers
->synth_center
=
220 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
223 centers
->synth_center
=
224 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
228 centers
->ctl_center
=
229 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
230 /* 25 MHz spacing is supported by hw but not on upper layers */
231 centers
->ext_center
=
232 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
239 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
243 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
246 val
= REG_READ(ah
, AR_SREV
);
247 ah
->hw_version
.macVersion
=
248 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
249 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
250 ah
->is_pciexpress
= (val
& AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
252 if (!AR_SREV_9100(ah
))
253 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
255 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
257 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
258 ah
->is_pciexpress
= true;
262 static int ath9k_hw_get_radiorev(struct ath_hw
*ah
)
267 REG_WRITE(ah
, AR_PHY(0x36), 0x00007058);
269 for (i
= 0; i
< 8; i
++)
270 REG_WRITE(ah
, AR_PHY(0x20), 0x00010000);
271 val
= (REG_READ(ah
, AR_PHY(256)) >> 24) & 0xff;
272 val
= ((val
& 0xf0) >> 4) | ((val
& 0x0f) << 4);
274 return ath9k_hw_reverse_bits(val
, 8);
277 /************************************/
278 /* HW Attach, Detach, Init Routines */
279 /************************************/
281 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
283 if (AR_SREV_9100(ah
))
286 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
287 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
288 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
289 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
290 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
291 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
292 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
293 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
294 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
296 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
299 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
301 struct ath_common
*common
= ath9k_hw_common(ah
);
302 u32 regAddr
[2] = { AR_STA_ID0
, AR_PHY_BASE
+ (8 << 2) };
304 u32 patternData
[4] = { 0x55555555,
310 for (i
= 0; i
< 2; i
++) {
311 u32 addr
= regAddr
[i
];
314 regHold
[i
] = REG_READ(ah
, addr
);
315 for (j
= 0; j
< 0x100; j
++) {
316 wrData
= (j
<< 16) | j
;
317 REG_WRITE(ah
, addr
, wrData
);
318 rdData
= REG_READ(ah
, addr
);
319 if (rdData
!= wrData
) {
320 ath_print(common
, ATH_DBG_FATAL
,
321 "address test failed "
322 "addr: 0x%08x - wr:0x%08x != "
324 addr
, wrData
, rdData
);
328 for (j
= 0; j
< 4; j
++) {
329 wrData
= patternData
[j
];
330 REG_WRITE(ah
, addr
, wrData
);
331 rdData
= REG_READ(ah
, addr
);
332 if (wrData
!= rdData
) {
333 ath_print(common
, ATH_DBG_FATAL
,
334 "address test failed "
335 "addr: 0x%08x - wr:0x%08x != "
337 addr
, wrData
, rdData
);
341 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
348 static void ath9k_hw_init_config(struct ath_hw
*ah
)
352 ah
->config
.dma_beacon_response_time
= 2;
353 ah
->config
.sw_beacon_response_time
= 10;
354 ah
->config
.additional_swba_backoff
= 0;
355 ah
->config
.ack_6mb
= 0x0;
356 ah
->config
.cwm_ignore_extcca
= 0;
357 ah
->config
.pcie_powersave_enable
= 0;
358 ah
->config
.pcie_clock_req
= 0;
359 ah
->config
.pcie_waen
= 0;
360 ah
->config
.analog_shiftreg
= 1;
361 ah
->config
.ofdm_trig_low
= 200;
362 ah
->config
.ofdm_trig_high
= 500;
363 ah
->config
.cck_trig_high
= 200;
364 ah
->config
.cck_trig_low
= 100;
365 ah
->config
.enable_ani
= 1;
367 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
368 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
369 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
372 if (ah
->hw_version
.devid
!= AR2427_DEVID_PCIE
)
373 ah
->config
.ht_enable
= 1;
375 ah
->config
.ht_enable
= 0;
377 ah
->config
.rx_intr_mitigation
= true;
380 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
381 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
382 * This means we use it for all AR5416 devices, and the few
383 * minor PCI AR9280 devices out there.
385 * Serialization is required because these devices do not handle
386 * well the case of two concurrent reads/writes due to the latency
387 * involved. During one read/write another read/write can be issued
388 * on another CPU while the previous read/write may still be working
389 * on our hardware, if we hit this case the hardware poops in a loop.
390 * We prevent this by serializing reads and writes.
392 * This issue is not present on PCI-Express devices or pre-AR5416
393 * devices (legacy, 802.11abg).
395 if (num_possible_cpus() > 1)
396 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
399 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
401 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
403 regulatory
->country_code
= CTRY_DEFAULT
;
404 regulatory
->power_limit
= MAX_RATE_POWER
;
405 regulatory
->tp_scale
= ATH9K_TP_SCALE_MAX
;
407 ah
->hw_version
.magic
= AR5416_MAGIC
;
408 ah
->hw_version
.subvendorid
= 0;
411 if (ah
->hw_version
.devid
== AR5416_AR9100_DEVID
)
412 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
413 if (!AR_SREV_9100(ah
))
414 ah
->ah_flags
= AH_USE_EEPROM
;
417 ah
->sta_id1_defaults
= AR_STA_ID1_CRPT_MIC_ENABLE
;
418 ah
->beacon_interval
= 100;
419 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
420 ah
->slottime
= (u32
) -1;
421 ah
->globaltxtimeout
= (u32
) -1;
422 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
425 static int ath9k_hw_rf_claim(struct ath_hw
*ah
)
429 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
431 val
= ath9k_hw_get_radiorev(ah
);
432 switch (val
& AR_RADIO_SREV_MAJOR
) {
434 val
= AR_RAD5133_SREV_MAJOR
;
436 case AR_RAD5133_SREV_MAJOR
:
437 case AR_RAD5122_SREV_MAJOR
:
438 case AR_RAD2133_SREV_MAJOR
:
439 case AR_RAD2122_SREV_MAJOR
:
442 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
443 "Radio Chip Rev 0x%02X not supported\n",
444 val
& AR_RADIO_SREV_MAJOR
);
448 ah
->hw_version
.analog5GhzRev
= val
;
453 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
455 struct ath_common
*common
= ath9k_hw_common(ah
);
461 for (i
= 0; i
< 3; i
++) {
462 eeval
= ah
->eep_ops
->get_eeprom(ah
, AR_EEPROM_MAC(i
));
464 common
->macaddr
[2 * i
] = eeval
>> 8;
465 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
467 if (sum
== 0 || sum
== 0xffff * 3)
468 return -EADDRNOTAVAIL
;
473 static void ath9k_hw_init_rxgain_ini(struct ath_hw
*ah
)
477 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_17
) {
478 rxgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_RXGAIN_TYPE
);
480 if (rxgain_type
== AR5416_EEP_RXGAIN_13DB_BACKOFF
)
481 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
482 ar9280Modes_backoff_13db_rxgain_9280_2
,
483 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2
), 6);
484 else if (rxgain_type
== AR5416_EEP_RXGAIN_23DB_BACKOFF
)
485 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
486 ar9280Modes_backoff_23db_rxgain_9280_2
,
487 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2
), 6);
489 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
490 ar9280Modes_original_rxgain_9280_2
,
491 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
493 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
494 ar9280Modes_original_rxgain_9280_2
,
495 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
499 static void ath9k_hw_init_txgain_ini(struct ath_hw
*ah
)
503 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_19
) {
504 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
506 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
)
507 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
508 ar9280Modes_high_power_tx_gain_9280_2
,
509 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2
), 6);
511 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
512 ar9280Modes_original_tx_gain_9280_2
,
513 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
515 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
516 ar9280Modes_original_tx_gain_9280_2
,
517 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
521 static int ath9k_hw_post_init(struct ath_hw
*ah
)
525 if (!AR_SREV_9271(ah
)) {
526 if (!ath9k_hw_chip_test(ah
))
530 ecode
= ath9k_hw_rf_claim(ah
);
534 ecode
= ath9k_hw_eeprom_init(ah
);
538 ath_print(ath9k_hw_common(ah
), ATH_DBG_CONFIG
,
539 "Eeprom VER: %d, REV: %d\n",
540 ah
->eep_ops
->get_eeprom_ver(ah
),
541 ah
->eep_ops
->get_eeprom_rev(ah
));
543 ecode
= ath9k_hw_rf_alloc_ext_banks(ah
);
545 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
546 "Failed allocating banks for "
551 if (!AR_SREV_9100(ah
)) {
552 ath9k_hw_ani_setup(ah
);
553 ath9k_hw_ani_init(ah
);
559 static bool ar9002_hw_macversion_supported(u32 macversion
)
561 switch (macversion
) {
562 case AR_SREV_VERSION_5416_PCI
:
563 case AR_SREV_VERSION_5416_PCIE
:
564 case AR_SREV_VERSION_9160
:
565 case AR_SREV_VERSION_9100
:
566 case AR_SREV_VERSION_9280
:
567 case AR_SREV_VERSION_9285
:
568 case AR_SREV_VERSION_9287
:
569 case AR_SREV_VERSION_9271
:
577 static void ar9002_hw_init_cal_settings(struct ath_hw
*ah
)
579 if (AR_SREV_9160_10_OR_LATER(ah
)) {
580 if (AR_SREV_9280_10_OR_LATER(ah
)) {
581 ah
->iq_caldata
.calData
= &iq_cal_single_sample
;
582 ah
->adcgain_caldata
.calData
=
583 &adc_gain_cal_single_sample
;
584 ah
->adcdc_caldata
.calData
=
585 &adc_dc_cal_single_sample
;
586 ah
->adcdc_calinitdata
.calData
=
589 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
590 ah
->adcgain_caldata
.calData
=
591 &adc_gain_cal_multi_sample
;
592 ah
->adcdc_caldata
.calData
=
593 &adc_dc_cal_multi_sample
;
594 ah
->adcdc_calinitdata
.calData
=
597 ah
->supp_cals
= ADC_GAIN_CAL
| ADC_DC_CAL
| IQ_MISMATCH_CAL
;
601 static void ar9002_hw_init_mode_regs(struct ath_hw
*ah
)
603 if (AR_SREV_9271(ah
)) {
604 INIT_INI_ARRAY(&ah
->iniModes
, ar9271Modes_9271
,
605 ARRAY_SIZE(ar9271Modes_9271
), 6);
606 INIT_INI_ARRAY(&ah
->iniCommon
, ar9271Common_9271
,
607 ARRAY_SIZE(ar9271Common_9271
), 2);
608 INIT_INI_ARRAY(&ah
->iniCommon_normal_cck_fir_coeff_9271
,
609 ar9271Common_normal_cck_fir_coeff_9271
,
610 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271
), 2);
611 INIT_INI_ARRAY(&ah
->iniCommon_japan_2484_cck_fir_coeff_9271
,
612 ar9271Common_japan_2484_cck_fir_coeff_9271
,
613 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271
), 2);
614 INIT_INI_ARRAY(&ah
->iniModes_9271_1_0_only
,
615 ar9271Modes_9271_1_0_only
,
616 ARRAY_SIZE(ar9271Modes_9271_1_0_only
), 6);
617 INIT_INI_ARRAY(&ah
->iniModes_9271_ANI_reg
, ar9271Modes_9271_ANI_reg
,
618 ARRAY_SIZE(ar9271Modes_9271_ANI_reg
), 6);
619 INIT_INI_ARRAY(&ah
->iniModes_high_power_tx_gain_9271
,
620 ar9271Modes_high_power_tx_gain_9271
,
621 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271
), 6);
622 INIT_INI_ARRAY(&ah
->iniModes_normal_power_tx_gain_9271
,
623 ar9271Modes_normal_power_tx_gain_9271
,
624 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271
), 6);
628 if (AR_SREV_9287_11_OR_LATER(ah
)) {
629 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_1
,
630 ARRAY_SIZE(ar9287Modes_9287_1_1
), 6);
631 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_1
,
632 ARRAY_SIZE(ar9287Common_9287_1_1
), 2);
633 if (ah
->config
.pcie_clock_req
)
634 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
635 ar9287PciePhy_clkreq_off_L1_9287_1_1
,
636 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1
), 2);
638 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
639 ar9287PciePhy_clkreq_always_on_L1_9287_1_1
,
640 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1
),
642 } else if (AR_SREV_9287_10_OR_LATER(ah
)) {
643 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_0
,
644 ARRAY_SIZE(ar9287Modes_9287_1_0
), 6);
645 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_0
,
646 ARRAY_SIZE(ar9287Common_9287_1_0
), 2);
648 if (ah
->config
.pcie_clock_req
)
649 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
650 ar9287PciePhy_clkreq_off_L1_9287_1_0
,
651 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0
), 2);
653 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
654 ar9287PciePhy_clkreq_always_on_L1_9287_1_0
,
655 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0
),
657 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
660 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285_1_2
,
661 ARRAY_SIZE(ar9285Modes_9285_1_2
), 6);
662 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285_1_2
,
663 ARRAY_SIZE(ar9285Common_9285_1_2
), 2);
665 if (ah
->config
.pcie_clock_req
) {
666 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
667 ar9285PciePhy_clkreq_off_L1_9285_1_2
,
668 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2
), 2);
670 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
671 ar9285PciePhy_clkreq_always_on_L1_9285_1_2
,
672 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2
),
675 } else if (AR_SREV_9285_10_OR_LATER(ah
)) {
676 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285
,
677 ARRAY_SIZE(ar9285Modes_9285
), 6);
678 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285
,
679 ARRAY_SIZE(ar9285Common_9285
), 2);
681 if (ah
->config
.pcie_clock_req
) {
682 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
683 ar9285PciePhy_clkreq_off_L1_9285
,
684 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285
), 2);
686 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
687 ar9285PciePhy_clkreq_always_on_L1_9285
,
688 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285
), 2);
690 } else if (AR_SREV_9280_20_OR_LATER(ah
)) {
691 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280_2
,
692 ARRAY_SIZE(ar9280Modes_9280_2
), 6);
693 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280_2
,
694 ARRAY_SIZE(ar9280Common_9280_2
), 2);
696 if (ah
->config
.pcie_clock_req
) {
697 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
698 ar9280PciePhy_clkreq_off_L1_9280
,
699 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280
),2);
701 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
702 ar9280PciePhy_clkreq_always_on_L1_9280
,
703 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280
), 2);
705 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
706 ar9280Modes_fast_clock_9280_2
,
707 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2
), 3);
708 } else if (AR_SREV_9280_10_OR_LATER(ah
)) {
709 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280
,
710 ARRAY_SIZE(ar9280Modes_9280
), 6);
711 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280
,
712 ARRAY_SIZE(ar9280Common_9280
), 2);
713 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
714 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9160
,
715 ARRAY_SIZE(ar5416Modes_9160
), 6);
716 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9160
,
717 ARRAY_SIZE(ar5416Common_9160
), 2);
718 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9160
,
719 ARRAY_SIZE(ar5416Bank0_9160
), 2);
720 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9160
,
721 ARRAY_SIZE(ar5416BB_RfGain_9160
), 3);
722 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9160
,
723 ARRAY_SIZE(ar5416Bank1_9160
), 2);
724 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9160
,
725 ARRAY_SIZE(ar5416Bank2_9160
), 2);
726 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9160
,
727 ARRAY_SIZE(ar5416Bank3_9160
), 3);
728 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9160
,
729 ARRAY_SIZE(ar5416Bank6_9160
), 3);
730 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9160
,
731 ARRAY_SIZE(ar5416Bank6TPC_9160
), 3);
732 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9160
,
733 ARRAY_SIZE(ar5416Bank7_9160
), 2);
734 if (AR_SREV_9160_11(ah
)) {
735 INIT_INI_ARRAY(&ah
->iniAddac
,
737 ARRAY_SIZE(ar5416Addac_91601_1
), 2);
739 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9160
,
740 ARRAY_SIZE(ar5416Addac_9160
), 2);
742 } else if (AR_SREV_9100_OR_LATER(ah
)) {
743 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9100
,
744 ARRAY_SIZE(ar5416Modes_9100
), 6);
745 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9100
,
746 ARRAY_SIZE(ar5416Common_9100
), 2);
747 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9100
,
748 ARRAY_SIZE(ar5416Bank0_9100
), 2);
749 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9100
,
750 ARRAY_SIZE(ar5416BB_RfGain_9100
), 3);
751 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9100
,
752 ARRAY_SIZE(ar5416Bank1_9100
), 2);
753 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9100
,
754 ARRAY_SIZE(ar5416Bank2_9100
), 2);
755 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9100
,
756 ARRAY_SIZE(ar5416Bank3_9100
), 3);
757 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9100
,
758 ARRAY_SIZE(ar5416Bank6_9100
), 3);
759 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9100
,
760 ARRAY_SIZE(ar5416Bank6TPC_9100
), 3);
761 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9100
,
762 ARRAY_SIZE(ar5416Bank7_9100
), 2);
763 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9100
,
764 ARRAY_SIZE(ar5416Addac_9100
), 2);
766 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes
,
767 ARRAY_SIZE(ar5416Modes
), 6);
768 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common
,
769 ARRAY_SIZE(ar5416Common
), 2);
770 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0
,
771 ARRAY_SIZE(ar5416Bank0
), 2);
772 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain
,
773 ARRAY_SIZE(ar5416BB_RfGain
), 3);
774 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1
,
775 ARRAY_SIZE(ar5416Bank1
), 2);
776 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2
,
777 ARRAY_SIZE(ar5416Bank2
), 2);
778 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3
,
779 ARRAY_SIZE(ar5416Bank3
), 3);
780 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6
,
781 ARRAY_SIZE(ar5416Bank6
), 3);
782 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC
,
783 ARRAY_SIZE(ar5416Bank6TPC
), 3);
784 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7
,
785 ARRAY_SIZE(ar5416Bank7
), 2);
786 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac
,
787 ARRAY_SIZE(ar5416Addac
), 2);
791 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
793 if (AR_SREV_9287_11_OR_LATER(ah
))
794 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
795 ar9287Modes_rx_gain_9287_1_1
,
796 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1
), 6);
797 else if (AR_SREV_9287_10(ah
))
798 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
799 ar9287Modes_rx_gain_9287_1_0
,
800 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0
), 6);
801 else if (AR_SREV_9280_20(ah
))
802 ath9k_hw_init_rxgain_ini(ah
);
804 if (AR_SREV_9287_11_OR_LATER(ah
)) {
805 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
806 ar9287Modes_tx_gain_9287_1_1
,
807 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1
), 6);
808 } else if (AR_SREV_9287_10(ah
)) {
809 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
810 ar9287Modes_tx_gain_9287_1_0
,
811 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0
), 6);
812 } else if (AR_SREV_9280_20(ah
)) {
813 ath9k_hw_init_txgain_ini(ah
);
814 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
815 u32 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
818 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
) {
819 if (AR_SREV_9285E_20(ah
)) {
820 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
821 ar9285Modes_XE2_0_high_power
,
823 ar9285Modes_XE2_0_high_power
), 6);
825 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
826 ar9285Modes_high_power_tx_gain_9285_1_2
,
828 ar9285Modes_high_power_tx_gain_9285_1_2
), 6);
831 if (AR_SREV_9285E_20(ah
)) {
832 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
833 ar9285Modes_XE2_0_normal_power
,
835 ar9285Modes_XE2_0_normal_power
), 6);
837 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
838 ar9285Modes_original_tx_gain_9285_1_2
,
840 ar9285Modes_original_tx_gain_9285_1_2
), 6);
846 static void ath9k_hw_init_eeprom_fix(struct ath_hw
*ah
)
848 struct base_eep_header
*pBase
= &(ah
->eeprom
.def
.baseEepHeader
);
849 struct ath_common
*common
= ath9k_hw_common(ah
);
851 ah
->need_an_top2_fixup
= (ah
->hw_version
.devid
== AR9280_DEVID_PCI
) &&
852 (ah
->eep_map
!= EEP_MAP_4KBITS
) &&
853 ((pBase
->version
& 0xff) > 0x0a) &&
854 (pBase
->pwdclkind
== 0);
856 if (ah
->need_an_top2_fixup
)
857 ath_print(common
, ATH_DBG_EEPROM
,
858 "needs fixup for AR_AN_TOP2 register\n");
861 /* Called for all hardware families */
862 static int __ath9k_hw_init(struct ath_hw
*ah
)
864 struct ath_common
*common
= ath9k_hw_common(ah
);
867 ath9k_hw_init_defaults(ah
);
868 ath9k_hw_init_config(ah
);
870 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
871 ath_print(common
, ATH_DBG_FATAL
,
872 "Couldn't reset chip\n");
876 ar9002_hw_attach_ops(ah
);
878 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
879 ath_print(common
, ATH_DBG_FATAL
, "Couldn't wakeup chip\n");
883 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
884 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
885 (AR_SREV_9280(ah
) && !ah
->is_pciexpress
)) {
886 ah
->config
.serialize_regmode
=
889 ah
->config
.serialize_regmode
=
894 ath_print(common
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
895 ah
->config
.serialize_regmode
);
897 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
898 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
900 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
902 if (!ath9k_hw_macversion_supported(ah
)) {
903 ath_print(common
, ATH_DBG_FATAL
,
904 "Mac Chip Rev 0x%02x.%x is not supported by "
905 "this driver\n", ah
->hw_version
.macVersion
,
906 ah
->hw_version
.macRev
);
910 if (AR_SREV_9100(ah
)) {
911 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
912 ah
->supp_cals
= IQ_MISMATCH_CAL
;
913 ah
->is_pciexpress
= false;
916 if (AR_SREV_9271(ah
))
917 ah
->is_pciexpress
= false;
919 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
920 ath9k_hw_init_cal_settings(ah
);
922 ah
->ani_function
= ATH9K_ANI_ALL
;
923 if (AR_SREV_9280_10_OR_LATER(ah
))
924 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
926 ath9k_hw_init_mode_regs(ah
);
928 if (ah
->is_pciexpress
)
929 ath9k_hw_configpcipowersave(ah
, 0, 0);
931 ath9k_hw_disablepcie(ah
);
933 /* Support for Japan ch.14 (2484) spread */
934 if (AR_SREV_9287_11_OR_LATER(ah
)) {
935 INIT_INI_ARRAY(&ah
->iniCckfirNormal
,
936 ar9287Common_normal_cck_fir_coeff_92871_1
,
937 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1
), 2);
938 INIT_INI_ARRAY(&ah
->iniCckfirJapan2484
,
939 ar9287Common_japan_2484_cck_fir_coeff_92871_1
,
940 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1
), 2);
943 r
= ath9k_hw_post_init(ah
);
947 ath9k_hw_init_mode_gain_regs(ah
);
948 r
= ath9k_hw_fill_cap_info(ah
);
952 ath9k_hw_init_eeprom_fix(ah
);
954 r
= ath9k_hw_init_macaddr(ah
);
956 ath_print(common
, ATH_DBG_FATAL
,
957 "Failed to initialize MAC address\n");
961 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
962 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
964 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
966 ath9k_init_nfcal_hist_buffer(ah
);
968 common
->state
= ATH_HW_INITIALIZED
;
973 int ath9k_hw_init(struct ath_hw
*ah
)
976 struct ath_common
*common
= ath9k_hw_common(ah
);
978 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
979 switch (ah
->hw_version
.devid
) {
980 case AR5416_DEVID_PCI
:
981 case AR5416_DEVID_PCIE
:
982 case AR5416_AR9100_DEVID
:
983 case AR9160_DEVID_PCI
:
984 case AR9280_DEVID_PCI
:
985 case AR9280_DEVID_PCIE
:
986 case AR9285_DEVID_PCIE
:
987 case AR5416_DEVID_AR9287_PCI
:
988 case AR5416_DEVID_AR9287_PCIE
:
989 case AR2427_DEVID_PCIE
:
992 if (common
->bus_ops
->ath_bus_type
== ATH_USB
)
994 ath_print(common
, ATH_DBG_FATAL
,
995 "Hardware device ID 0x%04x not supported\n",
996 ah
->hw_version
.devid
);
1000 ret
= __ath9k_hw_init(ah
);
1002 ath_print(common
, ATH_DBG_FATAL
,
1003 "Unable to initialize hardware; "
1004 "initialization status: %d\n", ret
);
1010 EXPORT_SYMBOL(ath9k_hw_init
);
1012 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
1014 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
1015 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
1017 REG_WRITE(ah
, AR_QOS_NO_ACK
,
1018 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
1019 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
1020 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
1022 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
1023 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
1024 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
1025 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
1026 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
1029 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
1030 struct ath9k_channel
*chan
)
1032 u32 pll
= ath9k_hw_compute_pll_control(ah
, chan
);
1034 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
1036 /* Switch the core clock for ar9271 to 117Mhz */
1037 if (AR_SREV_9271(ah
)) {
1039 REG_WRITE(ah
, 0x50040, 0x304);
1042 udelay(RTC_PLL_SETTLE_DELAY
);
1044 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
1047 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
1048 enum nl80211_iftype opmode
)
1050 u32 imr_reg
= AR_IMR_TXERR
|
1056 if (ah
->config
.rx_intr_mitigation
)
1057 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
1059 imr_reg
|= AR_IMR_RXOK
;
1061 imr_reg
|= AR_IMR_TXOK
;
1063 if (opmode
== NL80211_IFTYPE_AP
)
1064 imr_reg
|= AR_IMR_MIB
;
1066 REG_WRITE(ah
, AR_IMR
, imr_reg
);
1067 ah
->imrs2_reg
|= AR_IMR_S2_GTT
;
1068 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
1070 if (!AR_SREV_9100(ah
)) {
1071 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
1072 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, AR_INTR_SYNC_DEFAULT
);
1073 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
1077 static void ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
1079 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1080 val
= min(val
, (u32
) 0xFFFF);
1081 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, val
);
1084 static void ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
1086 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1087 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_ACK
));
1088 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK
, val
);
1091 static void ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
1093 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1094 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_CTS
));
1095 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_CTS
, val
);
1098 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
1101 ath_print(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
1102 "bad global tx timeout %u\n", tu
);
1103 ah
->globaltxtimeout
= (u32
) -1;
1106 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
1107 ah
->globaltxtimeout
= tu
;
1112 void ath9k_hw_init_global_settings(struct ath_hw
*ah
)
1114 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
1119 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
1122 if (ah
->misc_mode
!= 0)
1123 REG_WRITE(ah
, AR_PCU_MISC
,
1124 REG_READ(ah
, AR_PCU_MISC
) | ah
->misc_mode
);
1126 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_5GHZ
)
1131 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1132 slottime
= ah
->slottime
+ 3 * ah
->coverage_class
;
1133 acktimeout
= slottime
+ sifstime
;
1136 * Workaround for early ACK timeouts, add an offset to match the
1137 * initval's 64us ack timeout value.
1138 * This was initially only meant to work around an issue with delayed
1139 * BA frames in some implementations, but it has been found to fix ACK
1140 * timeout issues in other cases as well.
1142 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
1143 acktimeout
+= 64 - sifstime
- ah
->slottime
;
1145 ath9k_hw_setslottime(ah
, slottime
);
1146 ath9k_hw_set_ack_timeout(ah
, acktimeout
);
1147 ath9k_hw_set_cts_timeout(ah
, acktimeout
);
1148 if (ah
->globaltxtimeout
!= (u32
) -1)
1149 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1151 EXPORT_SYMBOL(ath9k_hw_init_global_settings
);
1153 void ath9k_hw_deinit(struct ath_hw
*ah
)
1155 struct ath_common
*common
= ath9k_hw_common(ah
);
1157 if (common
->state
< ATH_HW_INITIALIZED
)
1160 if (!AR_SREV_9100(ah
))
1161 ath9k_hw_ani_disable(ah
);
1163 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1166 ath9k_hw_rf_free_ext_banks(ah
);
1168 EXPORT_SYMBOL(ath9k_hw_deinit
);
1174 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
)
1176 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
1178 if (IS_CHAN_B(chan
))
1180 else if (IS_CHAN_G(chan
))
1188 /****************************************/
1189 /* Reset and Channel Switching Routines */
1190 /****************************************/
1192 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1197 * set AHB_MODE not to do cacheline prefetches
1199 regval
= REG_READ(ah
, AR_AHB_MODE
);
1200 REG_WRITE(ah
, AR_AHB_MODE
, regval
| AR_AHB_PREFETCH_RD_EN
);
1203 * let mac dma reads be in 128 byte chunks
1205 regval
= REG_READ(ah
, AR_TXCFG
) & ~AR_TXCFG_DMASZ_MASK
;
1206 REG_WRITE(ah
, AR_TXCFG
, regval
| AR_TXCFG_DMASZ_128B
);
1209 * Restore TX Trigger Level to its pre-reset value.
1210 * The initial value depends on whether aggregation is enabled, and is
1211 * adjusted whenever underruns are detected.
1213 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1216 * let mac dma writes be in 128 byte chunks
1218 regval
= REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_DMASZ_MASK
;
1219 REG_WRITE(ah
, AR_RXCFG
, regval
| AR_RXCFG_DMASZ_128B
);
1222 * Setup receive FIFO threshold to hold off TX activities
1224 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1227 * reduce the number of usable entries in PCU TXBUF to avoid
1228 * wrap around issues.
1230 if (AR_SREV_9285(ah
)) {
1231 /* For AR9285 the number of Fifos are reduced to half.
1232 * So set the usable tx buf size also to half to
1233 * avoid data/delimiter underruns
1235 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1236 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
1237 } else if (!AR_SREV_9271(ah
)) {
1238 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1239 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
1243 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1247 val
= REG_READ(ah
, AR_STA_ID1
);
1248 val
&= ~(AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
);
1250 case NL80211_IFTYPE_AP
:
1251 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_STA_AP
1252 | AR_STA_ID1_KSRCH_MODE
);
1253 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1255 case NL80211_IFTYPE_ADHOC
:
1256 case NL80211_IFTYPE_MESH_POINT
:
1257 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_ADHOC
1258 | AR_STA_ID1_KSRCH_MODE
);
1259 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1261 case NL80211_IFTYPE_STATION
:
1262 case NL80211_IFTYPE_MONITOR
:
1263 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
1268 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
1269 u32
*coef_mantissa
, u32
*coef_exponent
)
1271 u32 coef_exp
, coef_man
;
1273 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1274 if ((coef_scaled
>> coef_exp
) & 0x1)
1277 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1279 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1281 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1282 *coef_exponent
= coef_exp
- 16;
1285 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1290 if (AR_SREV_9100(ah
)) {
1291 u32 val
= REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1292 val
&= ~AR_RTC_DERIVED_CLK_PERIOD
;
1293 val
|= SM(1, AR_RTC_DERIVED_CLK_PERIOD
);
1294 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, val
);
1295 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1298 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1299 AR_RTC_FORCE_WAKE_ON_INT
);
1301 if (AR_SREV_9100(ah
)) {
1302 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1303 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1305 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1307 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1308 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1310 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1313 if (!AR_SREV_9300_20_OR_LATER(ah
))
1315 REG_WRITE(ah
, AR_RC
, val
);
1317 } else if (!AR_SREV_9300_20_OR_LATER(ah
))
1318 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1320 rst_flags
= AR_RTC_RC_MAC_WARM
;
1321 if (type
== ATH9K_RESET_COLD
)
1322 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1325 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1328 REG_WRITE(ah
, AR_RTC_RC
, 0);
1329 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1330 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1331 "RTC stuck in MAC reset\n");
1335 if (!AR_SREV_9100(ah
))
1336 REG_WRITE(ah
, AR_RC
, 0);
1338 if (AR_SREV_9100(ah
))
1344 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1346 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1347 AR_RTC_FORCE_WAKE_ON_INT
);
1349 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1350 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1352 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1355 if (!AR_SREV_9100(ah
))
1356 REG_WRITE(ah
, AR_RC
, 0);
1358 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1360 if (!ath9k_hw_wait(ah
,
1365 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1366 "RTC not waking up\n");
1370 ath9k_hw_read_revisions(ah
);
1372 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1375 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1377 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1378 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1381 case ATH9K_RESET_POWER_ON
:
1382 return ath9k_hw_set_reset_power_on(ah
);
1383 case ATH9K_RESET_WARM
:
1384 case ATH9K_RESET_COLD
:
1385 return ath9k_hw_set_reset(ah
, type
);
1391 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1392 struct ath9k_channel
*chan
)
1394 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
1395 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1397 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1400 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1403 ah
->chip_fullsleep
= false;
1404 ath9k_hw_init_pll(ah
, chan
);
1405 ath9k_hw_set_rfmode(ah
, chan
);
1410 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1411 struct ath9k_channel
*chan
)
1413 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1414 struct ath_common
*common
= ath9k_hw_common(ah
);
1415 struct ieee80211_channel
*channel
= chan
->chan
;
1419 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1420 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1421 ath_print(common
, ATH_DBG_QUEUE
,
1422 "Transmit frames pending on "
1423 "queue %d\n", qnum
);
1428 if (!ath9k_hw_rfbus_req(ah
)) {
1429 ath_print(common
, ATH_DBG_FATAL
,
1430 "Could not kill baseband RX\n");
1434 ath9k_hw_set_channel_regs(ah
, chan
);
1436 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1438 ath_print(common
, ATH_DBG_FATAL
,
1439 "Failed to set channel\n");
1443 ah
->eep_ops
->set_txpower(ah
, chan
,
1444 ath9k_regd_get_ctl(regulatory
, chan
),
1445 channel
->max_antenna_gain
* 2,
1446 channel
->max_power
* 2,
1447 min((u32
) MAX_RATE_POWER
,
1448 (u32
) regulatory
->power_limit
));
1450 ath9k_hw_rfbus_done(ah
);
1452 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1453 ath9k_hw_set_delta_slope(ah
, chan
);
1455 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1457 if (!chan
->oneTimeCalsDone
)
1458 chan
->oneTimeCalsDone
= true;
1463 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1464 bool bChannelChange
)
1466 struct ath_common
*common
= ath9k_hw_common(ah
);
1468 struct ath9k_channel
*curchan
= ah
->curchan
;
1474 ah
->txchainmask
= common
->tx_chainmask
;
1475 ah
->rxchainmask
= common
->rx_chainmask
;
1477 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1480 if (curchan
&& !ah
->chip_fullsleep
)
1481 ath9k_hw_getnf(ah
, curchan
);
1483 if (bChannelChange
&&
1484 (ah
->chip_fullsleep
!= true) &&
1485 (ah
->curchan
!= NULL
) &&
1486 (chan
->channel
!= ah
->curchan
->channel
) &&
1487 ((chan
->channelFlags
& CHANNEL_ALL
) ==
1488 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)) &&
1489 !(AR_SREV_9280(ah
) || IS_CHAN_A_5MHZ_SPACED(chan
) ||
1490 IS_CHAN_A_5MHZ_SPACED(ah
->curchan
))) {
1492 if (ath9k_hw_channel_change(ah
, chan
)) {
1493 ath9k_hw_loadnf(ah
, ah
->curchan
);
1494 ath9k_hw_start_nfcal(ah
);
1499 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1500 if (saveDefAntenna
== 0)
1503 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1505 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1506 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1507 tsf
= ath9k_hw_gettsf64(ah
);
1509 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1510 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1511 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1513 ath9k_hw_mark_phy_inactive(ah
);
1515 /* Only required on the first reset */
1516 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1518 AR9271_RESET_POWER_DOWN_CONTROL
,
1519 AR9271_RADIO_RF_RST
);
1523 if (!ath9k_hw_chip_reset(ah
, chan
)) {
1524 ath_print(common
, ATH_DBG_FATAL
, "Chip reset failed\n");
1528 /* Only required on the first reset */
1529 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1530 ah
->htc_reset_init
= false;
1532 AR9271_RESET_POWER_DOWN_CONTROL
,
1533 AR9271_GATE_MAC_CTL
);
1538 if (tsf
&& AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1539 ath9k_hw_settsf64(ah
, tsf
);
1541 if (AR_SREV_9280_10_OR_LATER(ah
))
1542 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
1544 r
= ath9k_hw_process_ini(ah
, chan
);
1548 /* Setup MFP options for CCMP */
1549 if (AR_SREV_9280_20_OR_LATER(ah
)) {
1550 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1551 * frames when constructing CCMP AAD. */
1552 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
1554 ah
->sw_mgmt_crypto
= false;
1555 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1556 /* Disable hardware crypto for management frames */
1557 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
1558 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
1559 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1560 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
1561 ah
->sw_mgmt_crypto
= true;
1563 ah
->sw_mgmt_crypto
= true;
1565 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1566 ath9k_hw_set_delta_slope(ah
, chan
);
1568 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1569 ah
->eep_ops
->set_board_values(ah
, chan
);
1571 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(common
->macaddr
));
1572 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(common
->macaddr
+ 4)
1574 | AR_STA_ID1_RTS_USE_DEF
1576 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
1577 | ah
->sta_id1_defaults
);
1578 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
1580 ath_hw_setbssidmask(common
);
1582 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
1584 ath9k_hw_write_associd(ah
);
1586 REG_WRITE(ah
, AR_ISR
, ~0);
1588 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
1590 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1594 for (i
= 0; i
< AR_NUM_DCU
; i
++)
1595 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
1598 for (i
= 0; i
< ah
->caps
.total_queues
; i
++)
1599 ath9k_hw_resettxqueue(ah
, i
);
1601 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
1602 ath9k_hw_init_qos(ah
);
1604 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1605 ath9k_enable_rfkill(ah
);
1607 ath9k_hw_init_global_settings(ah
);
1609 if (AR_SREV_9287_12_OR_LATER(ah
)) {
1610 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
,
1611 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR
);
1612 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
,
1613 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR
);
1614 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
,
1615 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR
);
1617 REG_WRITE(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR
);
1618 REG_WRITE(ah
, AR_USEC
, AR_USEC_ASYNC_FIFO_DUR
);
1620 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
1621 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
1622 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
1623 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
1625 if (AR_SREV_9287_12_OR_LATER(ah
)) {
1626 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1627 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
1630 REG_WRITE(ah
, AR_STA_ID1
,
1631 REG_READ(ah
, AR_STA_ID1
) | AR_STA_ID1_PRESERVE_SEQNUM
);
1633 ath9k_hw_set_dma(ah
);
1635 REG_WRITE(ah
, AR_OBS
, 8);
1637 if (ah
->config
.rx_intr_mitigation
) {
1638 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
1639 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
1642 ath9k_hw_init_bb(ah
, chan
);
1644 if (!ath9k_hw_init_cal(ah
, chan
))
1647 ath9k_hw_restore_chainmask(ah
);
1648 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
1651 * For big endian systems turn on swapping for descriptors
1653 if (AR_SREV_9100(ah
)) {
1655 mask
= REG_READ(ah
, AR_CFG
);
1656 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
1657 ath_print(common
, ATH_DBG_RESET
,
1658 "CFG Byte Swap Set 0x%x\n", mask
);
1661 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
1662 REG_WRITE(ah
, AR_CFG
, mask
);
1663 ath_print(common
, ATH_DBG_RESET
,
1664 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
1667 /* Configure AR9271 target WLAN */
1668 if (AR_SREV_9271(ah
))
1669 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
1672 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1676 if (ah
->btcoex_hw
.enabled
)
1677 ath9k_hw_btcoex_enable(ah
);
1681 EXPORT_SYMBOL(ath9k_hw_reset
);
1683 /************************/
1684 /* Key Cache Management */
1685 /************************/
1687 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
)
1691 if (entry
>= ah
->caps
.keycache_size
) {
1692 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1693 "keychache entry %u out of range\n", entry
);
1697 keyType
= REG_READ(ah
, AR_KEYTABLE_TYPE(entry
));
1699 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), 0);
1700 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), 0);
1701 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), 0);
1702 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), 0);
1703 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), 0);
1704 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), AR_KEYTABLE_TYPE_CLR
);
1705 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), 0);
1706 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), 0);
1708 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
1709 u16 micentry
= entry
+ 64;
1711 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), 0);
1712 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
1713 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), 0);
1714 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
1720 EXPORT_SYMBOL(ath9k_hw_keyreset
);
1722 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
)
1726 if (entry
>= ah
->caps
.keycache_size
) {
1727 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1728 "keychache entry %u out of range\n", entry
);
1733 macHi
= (mac
[5] << 8) | mac
[4];
1734 macLo
= (mac
[3] << 24) |
1739 macLo
|= (macHi
& 1) << 31;
1744 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), macLo
);
1745 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), macHi
| AR_KEYTABLE_VALID
);
1749 EXPORT_SYMBOL(ath9k_hw_keysetmac
);
1751 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
1752 const struct ath9k_keyval
*k
,
1755 const struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1756 struct ath_common
*common
= ath9k_hw_common(ah
);
1757 u32 key0
, key1
, key2
, key3
, key4
;
1760 if (entry
>= pCap
->keycache_size
) {
1761 ath_print(common
, ATH_DBG_FATAL
,
1762 "keycache entry %u out of range\n", entry
);
1766 switch (k
->kv_type
) {
1767 case ATH9K_CIPHER_AES_OCB
:
1768 keyType
= AR_KEYTABLE_TYPE_AES
;
1770 case ATH9K_CIPHER_AES_CCM
:
1771 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_CIPHER_AESCCM
)) {
1772 ath_print(common
, ATH_DBG_ANY
,
1773 "AES-CCM not supported by mac rev 0x%x\n",
1774 ah
->hw_version
.macRev
);
1777 keyType
= AR_KEYTABLE_TYPE_CCM
;
1779 case ATH9K_CIPHER_TKIP
:
1780 keyType
= AR_KEYTABLE_TYPE_TKIP
;
1781 if (ATH9K_IS_MIC_ENABLED(ah
)
1782 && entry
+ 64 >= pCap
->keycache_size
) {
1783 ath_print(common
, ATH_DBG_ANY
,
1784 "entry %u inappropriate for TKIP\n", entry
);
1788 case ATH9K_CIPHER_WEP
:
1789 if (k
->kv_len
< WLAN_KEY_LEN_WEP40
) {
1790 ath_print(common
, ATH_DBG_ANY
,
1791 "WEP key length %u too small\n", k
->kv_len
);
1794 if (k
->kv_len
<= WLAN_KEY_LEN_WEP40
)
1795 keyType
= AR_KEYTABLE_TYPE_40
;
1796 else if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
1797 keyType
= AR_KEYTABLE_TYPE_104
;
1799 keyType
= AR_KEYTABLE_TYPE_128
;
1801 case ATH9K_CIPHER_CLR
:
1802 keyType
= AR_KEYTABLE_TYPE_CLR
;
1805 ath_print(common
, ATH_DBG_FATAL
,
1806 "cipher %u not supported\n", k
->kv_type
);
1810 key0
= get_unaligned_le32(k
->kv_val
+ 0);
1811 key1
= get_unaligned_le16(k
->kv_val
+ 4);
1812 key2
= get_unaligned_le32(k
->kv_val
+ 6);
1813 key3
= get_unaligned_le16(k
->kv_val
+ 10);
1814 key4
= get_unaligned_le32(k
->kv_val
+ 12);
1815 if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
1819 * Note: Key cache registers access special memory area that requires
1820 * two 32-bit writes to actually update the values in the internal
1821 * memory. Consequently, the exact order and pairs used here must be
1825 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
1826 u16 micentry
= entry
+ 64;
1829 * Write inverted key[47:0] first to avoid Michael MIC errors
1830 * on frames that could be sent or received at the same time.
1831 * The correct key will be written in the end once everything
1834 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), ~key0
);
1835 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), ~key1
);
1837 /* Write key[95:48] */
1838 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
1839 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
1841 /* Write key[127:96] and key type */
1842 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
1843 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
1845 /* Write MAC address for the entry */
1846 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
1848 if (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) {
1850 * TKIP uses two key cache entries:
1851 * Michael MIC TX/RX keys in the same key cache entry
1852 * (idx = main index + 64):
1853 * key0 [31:0] = RX key [31:0]
1854 * key1 [15:0] = TX key [31:16]
1855 * key1 [31:16] = reserved
1856 * key2 [31:0] = RX key [63:32]
1857 * key3 [15:0] = TX key [15:0]
1858 * key3 [31:16] = reserved
1859 * key4 [31:0] = TX key [63:32]
1861 u32 mic0
, mic1
, mic2
, mic3
, mic4
;
1863 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
1864 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
1865 mic1
= get_unaligned_le16(k
->kv_txmic
+ 2) & 0xffff;
1866 mic3
= get_unaligned_le16(k
->kv_txmic
+ 0) & 0xffff;
1867 mic4
= get_unaligned_le32(k
->kv_txmic
+ 4);
1869 /* Write RX[31:0] and TX[31:16] */
1870 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
1871 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), mic1
);
1873 /* Write RX[63:32] and TX[15:0] */
1874 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
1875 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), mic3
);
1877 /* Write TX[63:32] and keyType(reserved) */
1878 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), mic4
);
1879 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
1880 AR_KEYTABLE_TYPE_CLR
);
1884 * TKIP uses four key cache entries (two for group
1886 * Michael MIC TX/RX keys are in different key cache
1887 * entries (idx = main index + 64 for TX and
1888 * main index + 32 + 96 for RX):
1889 * key0 [31:0] = TX/RX MIC key [31:0]
1890 * key1 [31:0] = reserved
1891 * key2 [31:0] = TX/RX MIC key [63:32]
1892 * key3 [31:0] = reserved
1893 * key4 [31:0] = reserved
1895 * Upper layer code will call this function separately
1896 * for TX and RX keys when these registers offsets are
1901 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
1902 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
1904 /* Write MIC key[31:0] */
1905 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
1906 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
1908 /* Write MIC key[63:32] */
1909 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
1910 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
1912 /* Write TX[63:32] and keyType(reserved) */
1913 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), 0);
1914 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
1915 AR_KEYTABLE_TYPE_CLR
);
1918 /* MAC address registers are reserved for the MIC entry */
1919 REG_WRITE(ah
, AR_KEYTABLE_MAC0(micentry
), 0);
1920 REG_WRITE(ah
, AR_KEYTABLE_MAC1(micentry
), 0);
1923 * Write the correct (un-inverted) key[47:0] last to enable
1924 * TKIP now that all other registers are set with correct
1927 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
1928 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
1930 /* Write key[47:0] */
1931 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
1932 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
1934 /* Write key[95:48] */
1935 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
1936 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
1938 /* Write key[127:96] and key type */
1939 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
1940 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
1942 /* Write MAC address for the entry */
1943 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
1948 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry
);
1950 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
)
1952 if (entry
< ah
->caps
.keycache_size
) {
1953 u32 val
= REG_READ(ah
, AR_KEYTABLE_MAC1(entry
));
1954 if (val
& AR_KEYTABLE_VALID
)
1959 EXPORT_SYMBOL(ath9k_hw_keyisvalid
);
1961 /******************************/
1962 /* Power Management (Chipset) */
1963 /******************************/
1966 * Notify Power Mgt is disabled in self-generated frames.
1967 * If requested, force chip to sleep.
1969 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
1971 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1974 * Clear the RTC force wake bit to allow the
1975 * mac to go to sleep.
1977 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
1978 AR_RTC_FORCE_WAKE_EN
);
1979 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1980 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1982 /* Shutdown chip. Active low */
1983 if (!AR_SREV_5416(ah
) && !AR_SREV_9271(ah
))
1984 REG_CLR_BIT(ah
, (AR_RTC_RESET
),
1990 * Notify Power Management is enabled in self-generating
1991 * frames. If request, set power mode of chip to
1992 * auto/normal. Duration in units of 128us (1/8 TU).
1994 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
1996 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1998 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2000 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2001 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2002 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
2003 AR_RTC_FORCE_WAKE_ON_INT
);
2006 * Clear the RTC force wake bit to allow the
2007 * mac to go to sleep.
2009 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2010 AR_RTC_FORCE_WAKE_EN
);
2015 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
2021 if ((REG_READ(ah
, AR_RTC_STATUS
) &
2022 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
2023 if (ath9k_hw_set_reset_reg(ah
,
2024 ATH9K_RESET_POWER_ON
) != true) {
2027 if (!AR_SREV_9300_20_OR_LATER(ah
))
2028 ath9k_hw_init_pll(ah
, NULL
);
2030 if (AR_SREV_9100(ah
))
2031 REG_SET_BIT(ah
, AR_RTC_RESET
,
2034 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2035 AR_RTC_FORCE_WAKE_EN
);
2038 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
2039 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
2040 if (val
== AR_RTC_STATUS_ON
)
2043 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2044 AR_RTC_FORCE_WAKE_EN
);
2047 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2048 "Failed to wakeup in %uus\n",
2049 POWER_UP_TIME
/ 20);
2054 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2059 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
2061 struct ath_common
*common
= ath9k_hw_common(ah
);
2062 int status
= true, setChip
= true;
2063 static const char *modes
[] = {
2070 if (ah
->power_mode
== mode
)
2073 ath_print(common
, ATH_DBG_RESET
, "%s -> %s\n",
2074 modes
[ah
->power_mode
], modes
[mode
]);
2077 case ATH9K_PM_AWAKE
:
2078 status
= ath9k_hw_set_power_awake(ah
, setChip
);
2080 case ATH9K_PM_FULL_SLEEP
:
2081 ath9k_set_power_sleep(ah
, setChip
);
2082 ah
->chip_fullsleep
= true;
2084 case ATH9K_PM_NETWORK_SLEEP
:
2085 ath9k_set_power_network_sleep(ah
, setChip
);
2088 ath_print(common
, ATH_DBG_FATAL
,
2089 "Unknown power mode %u\n", mode
);
2092 ah
->power_mode
= mode
;
2096 EXPORT_SYMBOL(ath9k_hw_setpower
);
2099 * Helper for ASPM support.
2101 * Disable PLL when in L0s as well as receiver clock when in L1.
2102 * This power saving option must be enabled through the SerDes.
2104 * Programming the SerDes must go through the same 288 bit serial shift
2105 * register as the other analog registers. Hence the 9 writes.
2107 static void ar9002_hw_configpcipowersave(struct ath_hw
*ah
,
2114 if (ah
->is_pciexpress
!= true)
2117 /* Do not touch SerDes registers */
2118 if (ah
->config
.pcie_powersave_enable
== 2)
2121 /* Nothing to do on restore for 11N */
2123 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2125 * AR9280 2.0 or later chips use SerDes values from the
2126 * initvals.h initialized depending on chipset during
2129 for (i
= 0; i
< ah
->iniPcieSerdes
.ia_rows
; i
++) {
2130 REG_WRITE(ah
, INI_RA(&ah
->iniPcieSerdes
, i
, 0),
2131 INI_RA(&ah
->iniPcieSerdes
, i
, 1));
2133 } else if (AR_SREV_9280(ah
) &&
2134 (ah
->hw_version
.macRev
== AR_SREV_REVISION_9280_10
)) {
2135 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fd00);
2136 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2138 /* RX shut off when elecidle is asserted */
2139 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xa8000019);
2140 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x13160820);
2141 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980560);
2143 /* Shut off CLKREQ active in L1 */
2144 if (ah
->config
.pcie_clock_req
)
2145 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffc);
2147 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffd);
2149 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2150 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2151 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00043007);
2153 /* Load the new settings */
2154 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2157 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
2158 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2160 /* RX shut off when elecidle is asserted */
2161 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000039);
2162 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x53160824);
2163 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980579);
2166 * Ignore ah->ah_config.pcie_clock_req setting for
2169 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x001defff);
2171 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2172 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2173 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e3007);
2175 /* Load the new settings */
2176 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2181 /* set bit 19 to allow forcing of pcie core into L1 state */
2182 REG_SET_BIT(ah
, AR_PCIE_PM_CTRL
, AR_PCIE_PM_CTRL_ENA
);
2184 /* Several PCIe massages to ensure proper behaviour */
2185 if (ah
->config
.pcie_waen
) {
2186 val
= ah
->config
.pcie_waen
;
2188 val
&= (~AR_WA_D3_L1_DISABLE
);
2190 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
) ||
2192 val
= AR9285_WA_DEFAULT
;
2194 val
&= (~AR_WA_D3_L1_DISABLE
);
2195 } else if (AR_SREV_9280(ah
)) {
2197 * On AR9280 chips bit 22 of 0x4004 needs to be
2198 * set otherwise card may disappear.
2200 val
= AR9280_WA_DEFAULT
;
2202 val
&= (~AR_WA_D3_L1_DISABLE
);
2204 val
= AR_WA_DEFAULT
;
2207 REG_WRITE(ah
, AR_WA
, val
);
2212 * Set PCIe workaround bits
2213 * bit 14 in WA register (disable L1) should only
2214 * be set when device enters D3 and be cleared
2215 * when device comes back to D0.
2217 if (ah
->config
.pcie_waen
) {
2218 if (ah
->config
.pcie_waen
& AR_WA_D3_L1_DISABLE
)
2219 REG_SET_BIT(ah
, AR_WA
, AR_WA_D3_L1_DISABLE
);
2221 if (((AR_SREV_9285(ah
) || AR_SREV_9271(ah
) ||
2222 AR_SREV_9287(ah
)) &&
2223 (AR9285_WA_DEFAULT
& AR_WA_D3_L1_DISABLE
)) ||
2224 (AR_SREV_9280(ah
) &&
2225 (AR9280_WA_DEFAULT
& AR_WA_D3_L1_DISABLE
))) {
2226 REG_SET_BIT(ah
, AR_WA
, AR_WA_D3_L1_DISABLE
);
2232 /**********************/
2233 /* Interrupt Handling */
2234 /**********************/
2236 bool ath9k_hw_intrpend(struct ath_hw
*ah
)
2240 if (AR_SREV_9100(ah
))
2243 host_isr
= REG_READ(ah
, AR_INTR_ASYNC_CAUSE
);
2244 if ((host_isr
& AR_INTR_MAC_IRQ
) && (host_isr
!= AR_INTR_SPURIOUS
))
2247 host_isr
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
2248 if ((host_isr
& AR_INTR_SYNC_DEFAULT
)
2249 && (host_isr
!= AR_INTR_SPURIOUS
))
2254 EXPORT_SYMBOL(ath9k_hw_intrpend
);
2256 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
)
2260 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2262 bool fatal_int
= false;
2263 struct ath_common
*common
= ath9k_hw_common(ah
);
2265 if (!AR_SREV_9100(ah
)) {
2266 if (REG_READ(ah
, AR_INTR_ASYNC_CAUSE
) & AR_INTR_MAC_IRQ
) {
2267 if ((REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
)
2268 == AR_RTC_STATUS_ON
) {
2269 isr
= REG_READ(ah
, AR_ISR
);
2273 sync_cause
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
) &
2274 AR_INTR_SYNC_DEFAULT
;
2278 if (!isr
&& !sync_cause
)
2282 isr
= REG_READ(ah
, AR_ISR
);
2286 if (isr
& AR_ISR_BCNMISC
) {
2288 isr2
= REG_READ(ah
, AR_ISR_S2
);
2289 if (isr2
& AR_ISR_S2_TIM
)
2290 mask2
|= ATH9K_INT_TIM
;
2291 if (isr2
& AR_ISR_S2_DTIM
)
2292 mask2
|= ATH9K_INT_DTIM
;
2293 if (isr2
& AR_ISR_S2_DTIMSYNC
)
2294 mask2
|= ATH9K_INT_DTIMSYNC
;
2295 if (isr2
& (AR_ISR_S2_CABEND
))
2296 mask2
|= ATH9K_INT_CABEND
;
2297 if (isr2
& AR_ISR_S2_GTT
)
2298 mask2
|= ATH9K_INT_GTT
;
2299 if (isr2
& AR_ISR_S2_CST
)
2300 mask2
|= ATH9K_INT_CST
;
2301 if (isr2
& AR_ISR_S2_TSFOOR
)
2302 mask2
|= ATH9K_INT_TSFOOR
;
2305 isr
= REG_READ(ah
, AR_ISR_RAC
);
2306 if (isr
== 0xffffffff) {
2311 *masked
= isr
& ATH9K_INT_COMMON
;
2313 if (ah
->config
.rx_intr_mitigation
) {
2314 if (isr
& (AR_ISR_RXMINTR
| AR_ISR_RXINTM
))
2315 *masked
|= ATH9K_INT_RX
;
2318 if (isr
& (AR_ISR_RXOK
| AR_ISR_RXERR
))
2319 *masked
|= ATH9K_INT_RX
;
2321 (AR_ISR_TXOK
| AR_ISR_TXDESC
| AR_ISR_TXERR
|
2325 *masked
|= ATH9K_INT_TX
;
2327 s0_s
= REG_READ(ah
, AR_ISR_S0_S
);
2328 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXOK
);
2329 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXDESC
);
2331 s1_s
= REG_READ(ah
, AR_ISR_S1_S
);
2332 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXERR
);
2333 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXEOL
);
2336 if (isr
& AR_ISR_RXORN
) {
2337 ath_print(common
, ATH_DBG_INTERRUPT
,
2338 "receive FIFO overrun interrupt\n");
2341 if (!AR_SREV_9100(ah
)) {
2342 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2343 u32 isr5
= REG_READ(ah
, AR_ISR_S5_S
);
2344 if (isr5
& AR_ISR_S5_TIM_TIMER
)
2345 *masked
|= ATH9K_INT_TIM_TIMER
;
2352 if (AR_SREV_9100(ah
))
2355 if (isr
& AR_ISR_GENTMR
) {
2358 s5_s
= REG_READ(ah
, AR_ISR_S5_S
);
2359 if (isr
& AR_ISR_GENTMR
) {
2360 ah
->intr_gen_timer_trigger
=
2361 MS(s5_s
, AR_ISR_S5_GENTIMER_TRIG
);
2363 ah
->intr_gen_timer_thresh
=
2364 MS(s5_s
, AR_ISR_S5_GENTIMER_THRESH
);
2366 if (ah
->intr_gen_timer_trigger
)
2367 *masked
|= ATH9K_INT_GENTIMER
;
2375 (AR_INTR_SYNC_HOST1_FATAL
| AR_INTR_SYNC_HOST1_PERR
))
2379 if (sync_cause
& AR_INTR_SYNC_HOST1_FATAL
) {
2380 ath_print(common
, ATH_DBG_ANY
,
2381 "received PCI FATAL interrupt\n");
2383 if (sync_cause
& AR_INTR_SYNC_HOST1_PERR
) {
2384 ath_print(common
, ATH_DBG_ANY
,
2385 "received PCI PERR interrupt\n");
2387 *masked
|= ATH9K_INT_FATAL
;
2389 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TIMEOUT
) {
2390 ath_print(common
, ATH_DBG_INTERRUPT
,
2391 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2392 REG_WRITE(ah
, AR_RC
, AR_RC_HOSTIF
);
2393 REG_WRITE(ah
, AR_RC
, 0);
2394 *masked
|= ATH9K_INT_FATAL
;
2396 if (sync_cause
& AR_INTR_SYNC_LOCAL_TIMEOUT
) {
2397 ath_print(common
, ATH_DBG_INTERRUPT
,
2398 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2401 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE_CLR
, sync_cause
);
2402 (void) REG_READ(ah
, AR_INTR_SYNC_CAUSE_CLR
);
2407 EXPORT_SYMBOL(ath9k_hw_getisr
);
2409 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
)
2411 enum ath9k_int omask
= ah
->imask
;
2413 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2414 struct ath_common
*common
= ath9k_hw_common(ah
);
2416 ath_print(common
, ATH_DBG_INTERRUPT
, "0x%x => 0x%x\n", omask
, ints
);
2418 if (omask
& ATH9K_INT_GLOBAL
) {
2419 ath_print(common
, ATH_DBG_INTERRUPT
, "disable IER\n");
2420 REG_WRITE(ah
, AR_IER
, AR_IER_DISABLE
);
2421 (void) REG_READ(ah
, AR_IER
);
2422 if (!AR_SREV_9100(ah
)) {
2423 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
, 0);
2424 (void) REG_READ(ah
, AR_INTR_ASYNC_ENABLE
);
2426 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
2427 (void) REG_READ(ah
, AR_INTR_SYNC_ENABLE
);
2431 mask
= ints
& ATH9K_INT_COMMON
;
2434 if (ints
& ATH9K_INT_TX
) {
2435 if (ah
->txok_interrupt_mask
)
2436 mask
|= AR_IMR_TXOK
;
2437 if (ah
->txdesc_interrupt_mask
)
2438 mask
|= AR_IMR_TXDESC
;
2439 if (ah
->txerr_interrupt_mask
)
2440 mask
|= AR_IMR_TXERR
;
2441 if (ah
->txeol_interrupt_mask
)
2442 mask
|= AR_IMR_TXEOL
;
2444 if (ints
& ATH9K_INT_RX
) {
2445 mask
|= AR_IMR_RXERR
;
2446 if (ah
->config
.rx_intr_mitigation
)
2447 mask
|= AR_IMR_RXMINTR
| AR_IMR_RXINTM
;
2449 mask
|= AR_IMR_RXOK
| AR_IMR_RXDESC
;
2450 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
2451 mask
|= AR_IMR_GENTMR
;
2454 if (ints
& (ATH9K_INT_BMISC
)) {
2455 mask
|= AR_IMR_BCNMISC
;
2456 if (ints
& ATH9K_INT_TIM
)
2457 mask2
|= AR_IMR_S2_TIM
;
2458 if (ints
& ATH9K_INT_DTIM
)
2459 mask2
|= AR_IMR_S2_DTIM
;
2460 if (ints
& ATH9K_INT_DTIMSYNC
)
2461 mask2
|= AR_IMR_S2_DTIMSYNC
;
2462 if (ints
& ATH9K_INT_CABEND
)
2463 mask2
|= AR_IMR_S2_CABEND
;
2464 if (ints
& ATH9K_INT_TSFOOR
)
2465 mask2
|= AR_IMR_S2_TSFOOR
;
2468 if (ints
& (ATH9K_INT_GTT
| ATH9K_INT_CST
)) {
2469 mask
|= AR_IMR_BCNMISC
;
2470 if (ints
& ATH9K_INT_GTT
)
2471 mask2
|= AR_IMR_S2_GTT
;
2472 if (ints
& ATH9K_INT_CST
)
2473 mask2
|= AR_IMR_S2_CST
;
2476 ath_print(common
, ATH_DBG_INTERRUPT
, "new IMR 0x%x\n", mask
);
2477 REG_WRITE(ah
, AR_IMR
, mask
);
2478 ah
->imrs2_reg
&= ~(AR_IMR_S2_TIM
| AR_IMR_S2_DTIM
| AR_IMR_S2_DTIMSYNC
|
2479 AR_IMR_S2_CABEND
| AR_IMR_S2_CABTO
|
2480 AR_IMR_S2_TSFOOR
| AR_IMR_S2_GTT
| AR_IMR_S2_CST
);
2481 ah
->imrs2_reg
|= mask2
;
2482 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
2484 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2485 if (ints
& ATH9K_INT_TIM_TIMER
)
2486 REG_SET_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
2488 REG_CLR_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
2491 if (ints
& ATH9K_INT_GLOBAL
) {
2492 ath_print(common
, ATH_DBG_INTERRUPT
, "enable IER\n");
2493 REG_WRITE(ah
, AR_IER
, AR_IER_ENABLE
);
2494 if (!AR_SREV_9100(ah
)) {
2495 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
,
2497 REG_WRITE(ah
, AR_INTR_ASYNC_MASK
, AR_INTR_MAC_IRQ
);
2500 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
,
2501 AR_INTR_SYNC_DEFAULT
);
2502 REG_WRITE(ah
, AR_INTR_SYNC_MASK
,
2503 AR_INTR_SYNC_DEFAULT
);
2505 ath_print(common
, ATH_DBG_INTERRUPT
, "AR_IMR 0x%x IER 0x%x\n",
2506 REG_READ(ah
, AR_IMR
), REG_READ(ah
, AR_IER
));
2511 EXPORT_SYMBOL(ath9k_hw_set_interrupts
);
2513 /*******************/
2514 /* Beacon Handling */
2515 /*******************/
2517 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
2521 ah
->beacon_interval
= beacon_period
;
2523 switch (ah
->opmode
) {
2524 case NL80211_IFTYPE_STATION
:
2525 case NL80211_IFTYPE_MONITOR
:
2526 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
2527 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
2528 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
2529 flags
|= AR_TBTT_TIMER_EN
;
2531 case NL80211_IFTYPE_ADHOC
:
2532 case NL80211_IFTYPE_MESH_POINT
:
2533 REG_SET_BIT(ah
, AR_TXCFG
,
2534 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
2535 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
,
2536 TU_TO_USEC(next_beacon
+
2537 (ah
->atim_window
? ah
->
2539 flags
|= AR_NDP_TIMER_EN
;
2540 case NL80211_IFTYPE_AP
:
2541 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
2542 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
,
2543 TU_TO_USEC(next_beacon
-
2545 dma_beacon_response_time
));
2546 REG_WRITE(ah
, AR_NEXT_SWBA
,
2547 TU_TO_USEC(next_beacon
-
2549 sw_beacon_response_time
));
2551 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
2554 ath_print(ath9k_hw_common(ah
), ATH_DBG_BEACON
,
2555 "%s: unsupported opmode: %d\n",
2556 __func__
, ah
->opmode
);
2561 REG_WRITE(ah
, AR_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
2562 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
2563 REG_WRITE(ah
, AR_SWBA_PERIOD
, TU_TO_USEC(beacon_period
));
2564 REG_WRITE(ah
, AR_NDP_PERIOD
, TU_TO_USEC(beacon_period
));
2566 beacon_period
&= ~ATH9K_BEACON_ENA
;
2567 if (beacon_period
& ATH9K_BEACON_RESET_TSF
) {
2568 ath9k_hw_reset_tsf(ah
);
2571 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
2573 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
2575 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
2576 const struct ath9k_beacon_state
*bs
)
2578 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
2579 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2580 struct ath_common
*common
= ath9k_hw_common(ah
);
2582 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
2584 REG_WRITE(ah
, AR_BEACON_PERIOD
,
2585 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
2586 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
2587 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
2589 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
2590 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
2592 beaconintval
= bs
->bs_intval
& ATH9K_BEACON_PERIOD
;
2594 if (bs
->bs_sleepduration
> beaconintval
)
2595 beaconintval
= bs
->bs_sleepduration
;
2597 dtimperiod
= bs
->bs_dtimperiod
;
2598 if (bs
->bs_sleepduration
> dtimperiod
)
2599 dtimperiod
= bs
->bs_sleepduration
;
2601 if (beaconintval
== dtimperiod
)
2602 nextTbtt
= bs
->bs_nextdtim
;
2604 nextTbtt
= bs
->bs_nexttbtt
;
2606 ath_print(common
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
2607 ath_print(common
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
2608 ath_print(common
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
2609 ath_print(common
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
2611 REG_WRITE(ah
, AR_NEXT_DTIM
,
2612 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
2613 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
2615 REG_WRITE(ah
, AR_SLEEP1
,
2616 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
2617 | AR_SLEEP1_ASSUME_DTIM
);
2619 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
2620 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
2622 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
2624 REG_WRITE(ah
, AR_SLEEP2
,
2625 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
2627 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
2628 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
2630 REG_SET_BIT(ah
, AR_TIMER_MODE
,
2631 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
2634 /* TSF Out of Range Threshold */
2635 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
2637 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
2639 /*******************/
2640 /* HW Capabilities */
2641 /*******************/
2643 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
2645 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2646 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2647 struct ath_common
*common
= ath9k_hw_common(ah
);
2648 struct ath_btcoex_hw
*btcoex_hw
= &ah
->btcoex_hw
;
2650 u16 capField
= 0, eeval
;
2652 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
2653 regulatory
->current_rd
= eeval
;
2655 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_1
);
2656 if (AR_SREV_9285_10_OR_LATER(ah
))
2657 eeval
|= AR9285_RDEXT_DEFAULT
;
2658 regulatory
->current_rd_ext
= eeval
;
2660 capField
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_CAP
);
2662 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
2663 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
2664 if (regulatory
->current_rd
== 0x64 ||
2665 regulatory
->current_rd
== 0x65)
2666 regulatory
->current_rd
+= 5;
2667 else if (regulatory
->current_rd
== 0x41)
2668 regulatory
->current_rd
= 0x43;
2669 ath_print(common
, ATH_DBG_REGULATORY
,
2670 "regdomain mapped to 0x%x\n", regulatory
->current_rd
);
2673 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
2674 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
2675 ath_print(common
, ATH_DBG_FATAL
,
2676 "no band has been marked as supported in EEPROM.\n");
2680 bitmap_zero(pCap
->wireless_modes
, ATH9K_MODE_MAX
);
2682 if (eeval
& AR5416_OPFLAGS_11A
) {
2683 set_bit(ATH9K_MODE_11A
, pCap
->wireless_modes
);
2684 if (ah
->config
.ht_enable
) {
2685 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT20
))
2686 set_bit(ATH9K_MODE_11NA_HT20
,
2687 pCap
->wireless_modes
);
2688 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT40
)) {
2689 set_bit(ATH9K_MODE_11NA_HT40PLUS
,
2690 pCap
->wireless_modes
);
2691 set_bit(ATH9K_MODE_11NA_HT40MINUS
,
2692 pCap
->wireless_modes
);
2697 if (eeval
& AR5416_OPFLAGS_11G
) {
2698 set_bit(ATH9K_MODE_11G
, pCap
->wireless_modes
);
2699 if (ah
->config
.ht_enable
) {
2700 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT20
))
2701 set_bit(ATH9K_MODE_11NG_HT20
,
2702 pCap
->wireless_modes
);
2703 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT40
)) {
2704 set_bit(ATH9K_MODE_11NG_HT40PLUS
,
2705 pCap
->wireless_modes
);
2706 set_bit(ATH9K_MODE_11NG_HT40MINUS
,
2707 pCap
->wireless_modes
);
2712 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
2714 * For AR9271 we will temporarilly uses the rx chainmax as read from
2717 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
2718 !(eeval
& AR5416_OPFLAGS_11A
) &&
2719 !(AR_SREV_9271(ah
)))
2720 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2721 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
2723 /* Use rx_chainmask from EEPROM. */
2724 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
2726 if (!(AR_SREV_9280(ah
) && (ah
->hw_version
.macRev
== 0)))
2727 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
2729 pCap
->low_2ghz_chan
= 2312;
2730 pCap
->high_2ghz_chan
= 2732;
2732 pCap
->low_5ghz_chan
= 4920;
2733 pCap
->high_5ghz_chan
= 6100;
2735 pCap
->hw_caps
&= ~ATH9K_HW_CAP_CIPHER_CKIP
;
2736 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_TKIP
;
2737 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_AESCCM
;
2739 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MIC_CKIP
;
2740 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_TKIP
;
2741 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_AESCCM
;
2743 if (ah
->config
.ht_enable
)
2744 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
2746 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
2748 pCap
->hw_caps
|= ATH9K_HW_CAP_GTT
;
2749 pCap
->hw_caps
|= ATH9K_HW_CAP_VEOL
;
2750 pCap
->hw_caps
|= ATH9K_HW_CAP_BSSIDMASK
;
2751 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MCAST_KEYSEARCH
;
2753 if (capField
& AR_EEPROM_EEPCAP_MAXQCU
)
2754 pCap
->total_queues
=
2755 MS(capField
, AR_EEPROM_EEPCAP_MAXQCU
);
2757 pCap
->total_queues
= ATH9K_NUM_TX_QUEUES
;
2759 if (capField
& AR_EEPROM_EEPCAP_KC_ENTRIES
)
2760 pCap
->keycache_size
=
2761 1 << MS(capField
, AR_EEPROM_EEPCAP_KC_ENTRIES
);
2763 pCap
->keycache_size
= AR_KEYTABLE_SIZE
;
2765 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCC
;
2767 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
2768 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
>> 1;
2770 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
;
2772 if (AR_SREV_9271(ah
))
2773 pCap
->num_gpio_pins
= AR9271_NUM_GPIO
;
2774 else if (AR_SREV_9285_10_OR_LATER(ah
))
2775 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
2776 else if (AR_SREV_9280_10_OR_LATER(ah
))
2777 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
2779 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
2781 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
2782 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
2783 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
2785 pCap
->rts_aggr_limit
= (8 * 1024);
2788 pCap
->hw_caps
|= ATH9K_HW_CAP_ENHANCEDPM
;
2790 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2791 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
2792 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
2794 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
2795 ah
->rfkill_polarity
=
2796 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
2798 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
2801 if (AR_SREV_9271(ah
))
2802 pCap
->hw_caps
|= ATH9K_HW_CAP_AUTOSLEEP
;
2804 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
2806 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
2807 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
2809 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
2811 if (regulatory
->current_rd_ext
& (1 << REG_EXT_JAPAN_MIDBAND
)) {
2813 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
2814 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
|
2815 AR_EEPROM_EEREGCAP_EN_KK_U2
|
2816 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
;
2819 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
2820 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
;
2823 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2824 if (regulatory
->current_rd_ext
& (1 << REG_EXT_FCC_MIDBAND
) &&
2826 pCap
->reg_cap
|= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
;
2828 pCap
->num_antcfg_5ghz
=
2829 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_5GHZ
);
2830 pCap
->num_antcfg_2ghz
=
2831 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_2GHZ
);
2833 if (AR_SREV_9280_10_OR_LATER(ah
) &&
2834 ath9k_hw_btcoex_supported(ah
)) {
2835 btcoex_hw
->btactive_gpio
= ATH_BTACTIVE_GPIO
;
2836 btcoex_hw
->wlanactive_gpio
= ATH_WLANACTIVE_GPIO
;
2838 if (AR_SREV_9285(ah
)) {
2839 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_3WIRE
;
2840 btcoex_hw
->btpriority_gpio
= ATH_BTPRIORITY_GPIO
;
2842 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_2WIRE
;
2845 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_NONE
;
2851 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
2852 u32 capability
, u32
*result
)
2854 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2856 case ATH9K_CAP_CIPHER
:
2857 switch (capability
) {
2858 case ATH9K_CIPHER_AES_CCM
:
2859 case ATH9K_CIPHER_AES_OCB
:
2860 case ATH9K_CIPHER_TKIP
:
2861 case ATH9K_CIPHER_WEP
:
2862 case ATH9K_CIPHER_MIC
:
2863 case ATH9K_CIPHER_CLR
:
2868 case ATH9K_CAP_TKIP_MIC
:
2869 switch (capability
) {
2873 return (ah
->sta_id1_defaults
&
2874 AR_STA_ID1_CRPT_MIC_ENABLE
) ? true :
2877 case ATH9K_CAP_TKIP_SPLIT
:
2878 return (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) ?
2880 case ATH9K_CAP_MCAST_KEYSRCH
:
2881 switch (capability
) {
2885 if (REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_ADHOC
) {
2888 return (ah
->sta_id1_defaults
&
2889 AR_STA_ID1_MCAST_KSRCH
) ? true :
2894 case ATH9K_CAP_TXPOW
:
2895 switch (capability
) {
2899 *result
= regulatory
->power_limit
;
2902 *result
= regulatory
->max_power_level
;
2905 *result
= regulatory
->tp_scale
;
2910 return (AR_SREV_9280_20_OR_LATER(ah
) &&
2911 (ah
->eep_ops
->get_eeprom(ah
, EEP_RC_CHAIN_MASK
) == 1))
2917 EXPORT_SYMBOL(ath9k_hw_getcapability
);
2919 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
2920 u32 capability
, u32 setting
, int *status
)
2923 case ATH9K_CAP_TKIP_MIC
:
2925 ah
->sta_id1_defaults
|=
2926 AR_STA_ID1_CRPT_MIC_ENABLE
;
2928 ah
->sta_id1_defaults
&=
2929 ~AR_STA_ID1_CRPT_MIC_ENABLE
;
2931 case ATH9K_CAP_MCAST_KEYSRCH
:
2933 ah
->sta_id1_defaults
|= AR_STA_ID1_MCAST_KSRCH
;
2935 ah
->sta_id1_defaults
&= ~AR_STA_ID1_MCAST_KSRCH
;
2941 EXPORT_SYMBOL(ath9k_hw_setcapability
);
2943 /****************************/
2944 /* GPIO / RFKILL / Antennae */
2945 /****************************/
2947 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
2951 u32 gpio_shift
, tmp
;
2954 addr
= AR_GPIO_OUTPUT_MUX3
;
2956 addr
= AR_GPIO_OUTPUT_MUX2
;
2958 addr
= AR_GPIO_OUTPUT_MUX1
;
2960 gpio_shift
= (gpio
% 6) * 5;
2962 if (AR_SREV_9280_20_OR_LATER(ah
)
2963 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
2964 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
2965 (0x1f << gpio_shift
));
2967 tmp
= REG_READ(ah
, addr
);
2968 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
2969 tmp
&= ~(0x1f << gpio_shift
);
2970 tmp
|= (type
<< gpio_shift
);
2971 REG_WRITE(ah
, addr
, tmp
);
2975 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
2979 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
2981 gpio_shift
= gpio
<< 1;
2985 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
2986 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2988 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
2990 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
2992 #define MS_REG_READ(x, y) \
2993 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2995 if (gpio
>= ah
->caps
.num_gpio_pins
)
2998 if (AR_SREV_9300_20_OR_LATER(ah
))
2999 return MS_REG_READ(AR9300
, gpio
) != 0;
3000 else if (AR_SREV_9271(ah
))
3001 return MS_REG_READ(AR9271
, gpio
) != 0;
3002 else if (AR_SREV_9287_10_OR_LATER(ah
))
3003 return MS_REG_READ(AR9287
, gpio
) != 0;
3004 else if (AR_SREV_9285_10_OR_LATER(ah
))
3005 return MS_REG_READ(AR9285
, gpio
) != 0;
3006 else if (AR_SREV_9280_10_OR_LATER(ah
))
3007 return MS_REG_READ(AR928X
, gpio
) != 0;
3009 return MS_REG_READ(AR
, gpio
) != 0;
3011 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
3013 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
3018 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
3020 gpio_shift
= 2 * gpio
;
3024 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
3025 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3027 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
3029 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
3031 if (AR_SREV_9271(ah
))
3034 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
3037 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
3039 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
3041 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
3043 EXPORT_SYMBOL(ath9k_hw_getdefantenna
);
3045 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
3047 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
3049 EXPORT_SYMBOL(ath9k_hw_setantenna
);
3051 /*********************/
3052 /* General Operation */
3053 /*********************/
3055 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
3057 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
3058 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
3060 if (phybits
& AR_PHY_ERR_RADAR
)
3061 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
3062 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
3063 bits
|= ATH9K_RX_FILTER_PHYERR
;
3067 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
3069 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
3073 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
3076 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
3077 phybits
|= AR_PHY_ERR_RADAR
;
3078 if (bits
& ATH9K_RX_FILTER_PHYERR
)
3079 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
3080 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
3083 REG_WRITE(ah
, AR_RXCFG
,
3084 REG_READ(ah
, AR_RXCFG
) | AR_RXCFG_ZLFDMA
);
3086 REG_WRITE(ah
, AR_RXCFG
,
3087 REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_ZLFDMA
);
3089 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
3091 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
3093 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
3096 ath9k_hw_init_pll(ah
, NULL
);
3099 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
3101 bool ath9k_hw_disable(struct ath_hw
*ah
)
3103 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
3106 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
3109 ath9k_hw_init_pll(ah
, NULL
);
3112 EXPORT_SYMBOL(ath9k_hw_disable
);
3114 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
)
3116 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3117 struct ath9k_channel
*chan
= ah
->curchan
;
3118 struct ieee80211_channel
*channel
= chan
->chan
;
3120 regulatory
->power_limit
= min(limit
, (u32
) MAX_RATE_POWER
);
3122 ah
->eep_ops
->set_txpower(ah
, chan
,
3123 ath9k_regd_get_ctl(regulatory
, chan
),
3124 channel
->max_antenna_gain
* 2,
3125 channel
->max_power
* 2,
3126 min((u32
) MAX_RATE_POWER
,
3127 (u32
) regulatory
->power_limit
));
3129 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
3131 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
)
3133 memcpy(ath9k_hw_common(ah
)->macaddr
, mac
, ETH_ALEN
);
3135 EXPORT_SYMBOL(ath9k_hw_setmac
);
3137 void ath9k_hw_setopmode(struct ath_hw
*ah
)
3139 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
3141 EXPORT_SYMBOL(ath9k_hw_setopmode
);
3143 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
3145 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
3146 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
3148 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
3150 void ath9k_hw_write_associd(struct ath_hw
*ah
)
3152 struct ath_common
*common
= ath9k_hw_common(ah
);
3154 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
3155 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
3156 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
3158 EXPORT_SYMBOL(ath9k_hw_write_associd
);
3160 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
3164 tsf
= REG_READ(ah
, AR_TSF_U32
);
3165 tsf
= (tsf
<< 32) | REG_READ(ah
, AR_TSF_L32
);
3169 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
3171 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
3173 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
3174 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
3176 EXPORT_SYMBOL(ath9k_hw_settsf64
);
3178 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
3180 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
3181 AH_TSF_WRITE_TIMEOUT
))
3182 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
3183 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3185 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
3187 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
3189 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
3192 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
3194 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
3196 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
3199 * Extend 15-bit time stamp from rx descriptor to
3200 * a full 64-bit TSF using the current h/w TSF.
3202 u64
ath9k_hw_extend_tsf(struct ath_hw
*ah
, u32 rstamp
)
3206 tsf
= ath9k_hw_gettsf64(ah
);
3207 if ((tsf
& 0x7fff) < rstamp
)
3209 return (tsf
& ~0x7fff) | rstamp
;
3211 EXPORT_SYMBOL(ath9k_hw_extend_tsf
);
3213 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
)
3215 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
3218 if (conf_is_ht40(conf
) && !ah
->config
.cwm_ignore_extcca
)
3219 macmode
= AR_2040_JOINED_RX_CLEAR
;
3223 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
3226 /* HW Generic timers configuration */
3228 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
3230 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3231 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3232 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3233 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3234 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3235 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3236 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3237 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3238 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
3239 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
3240 AR_NDP2_TIMER_MODE
, 0x0002},
3241 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
3242 AR_NDP2_TIMER_MODE
, 0x0004},
3243 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
3244 AR_NDP2_TIMER_MODE
, 0x0008},
3245 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
3246 AR_NDP2_TIMER_MODE
, 0x0010},
3247 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
3248 AR_NDP2_TIMER_MODE
, 0x0020},
3249 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
3250 AR_NDP2_TIMER_MODE
, 0x0040},
3251 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
3252 AR_NDP2_TIMER_MODE
, 0x0080}
3255 /* HW generic timer primitives */
3257 /* compute and clear index of rightmost 1 */
3258 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
3268 return timer_table
->gen_timer_index
[b
];
3271 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
3273 return REG_READ(ah
, AR_TSF_L32
);
3275 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
3277 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
3278 void (*trigger
)(void *),
3279 void (*overflow
)(void *),
3283 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3284 struct ath_gen_timer
*timer
;
3286 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
3288 if (timer
== NULL
) {
3289 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
3290 "Failed to allocate memory"
3291 "for hw timer[%d]\n", timer_index
);
3295 /* allocate a hardware generic timer slot */
3296 timer_table
->timers
[timer_index
] = timer
;
3297 timer
->index
= timer_index
;
3298 timer
->trigger
= trigger
;
3299 timer
->overflow
= overflow
;
3304 EXPORT_SYMBOL(ath_gen_timer_alloc
);
3306 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
3307 struct ath_gen_timer
*timer
,
3311 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3314 BUG_ON(!timer_period
);
3316 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3318 tsf
= ath9k_hw_gettsf32(ah
);
3320 ath_print(ath9k_hw_common(ah
), ATH_DBG_HWTIMER
,
3321 "curent tsf %x period %x"
3322 "timer_next %x\n", tsf
, timer_period
, timer_next
);
3325 * Pull timer_next forward if the current TSF already passed it
3326 * because of software latency
3328 if (timer_next
< tsf
)
3329 timer_next
= tsf
+ timer_period
;
3332 * Program generic timer registers
3334 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
3336 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
3338 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3339 gen_tmr_configuration
[timer
->index
].mode_mask
);
3341 /* Enable both trigger and thresh interrupt masks */
3342 REG_SET_BIT(ah
, AR_IMR_S5
,
3343 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3344 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3346 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
3348 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3350 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3352 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
3353 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
3357 /* Clear generic timer enable bits. */
3358 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3359 gen_tmr_configuration
[timer
->index
].mode_mask
);
3361 /* Disable both trigger and thresh interrupt masks */
3362 REG_CLR_BIT(ah
, AR_IMR_S5
,
3363 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3364 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3366 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3368 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
3370 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3372 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3374 /* free the hardware generic timer slot */
3375 timer_table
->timers
[timer
->index
] = NULL
;
3378 EXPORT_SYMBOL(ath_gen_timer_free
);
3381 * Generic Timer Interrupts handling
3383 void ath_gen_timer_isr(struct ath_hw
*ah
)
3385 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3386 struct ath_gen_timer
*timer
;
3387 struct ath_common
*common
= ath9k_hw_common(ah
);
3388 u32 trigger_mask
, thresh_mask
, index
;
3390 /* get hardware generic timer interrupt status */
3391 trigger_mask
= ah
->intr_gen_timer_trigger
;
3392 thresh_mask
= ah
->intr_gen_timer_thresh
;
3393 trigger_mask
&= timer_table
->timer_mask
.val
;
3394 thresh_mask
&= timer_table
->timer_mask
.val
;
3396 trigger_mask
&= ~thresh_mask
;
3398 while (thresh_mask
) {
3399 index
= rightmost_index(timer_table
, &thresh_mask
);
3400 timer
= timer_table
->timers
[index
];
3402 ath_print(common
, ATH_DBG_HWTIMER
,
3403 "TSF overflow for Gen timer %d\n", index
);
3404 timer
->overflow(timer
->arg
);
3407 while (trigger_mask
) {
3408 index
= rightmost_index(timer_table
, &trigger_mask
);
3409 timer
= timer_table
->timers
[index
];
3411 ath_print(common
, ATH_DBG_HWTIMER
,
3412 "Gen timer[%d] trigger\n", index
);
3413 timer
->trigger(timer
->arg
);
3416 EXPORT_SYMBOL(ath_gen_timer_isr
);
3422 void ath9k_hw_htc_resetinit(struct ath_hw
*ah
)
3424 ah
->htc_reset_init
= true;
3426 EXPORT_SYMBOL(ath9k_hw_htc_resetinit
);
3431 } ath_mac_bb_names
[] = {
3432 /* Devices with external radios */
3433 { AR_SREV_VERSION_5416_PCI
, "5416" },
3434 { AR_SREV_VERSION_5416_PCIE
, "5418" },
3435 { AR_SREV_VERSION_9100
, "9100" },
3436 { AR_SREV_VERSION_9160
, "9160" },
3437 /* Single-chip solutions */
3438 { AR_SREV_VERSION_9280
, "9280" },
3439 { AR_SREV_VERSION_9285
, "9285" },
3440 { AR_SREV_VERSION_9287
, "9287" },
3441 { AR_SREV_VERSION_9271
, "9271" },
3444 /* For devices with external radios */
3448 } ath_rf_names
[] = {
3450 { AR_RAD5133_SREV_MAJOR
, "5133" },
3451 { AR_RAD5122_SREV_MAJOR
, "5122" },
3452 { AR_RAD2133_SREV_MAJOR
, "2133" },
3453 { AR_RAD2122_SREV_MAJOR
, "2122" }
3457 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3459 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
3463 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
3464 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
3465 return ath_mac_bb_names
[i
].name
;
3473 * Return the RF name. "????" is returned if the RF is unknown.
3474 * Used for devices with external radios.
3476 static const char *ath9k_hw_rf_name(u16 rf_version
)
3480 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
3481 if (ath_rf_names
[i
].version
== rf_version
) {
3482 return ath_rf_names
[i
].name
;
3489 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
3493 /* chipsets >= AR9280 are single-chip */
3494 if (AR_SREV_9280_10_OR_LATER(ah
)) {
3495 used
= snprintf(hw_name
, len
,
3496 "Atheros AR%s Rev:%x",
3497 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3498 ah
->hw_version
.macRev
);
3501 used
= snprintf(hw_name
, len
,
3502 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3503 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3504 ah
->hw_version
.macRev
,
3505 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
&
3506 AR_RADIO_SREV_MAJOR
)),
3507 ah
->hw_version
.phyRev
);
3510 hw_name
[used
] = '\0';
3512 EXPORT_SYMBOL(ath9k_hw_name
);
3514 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
3515 static void ar9002_hw_attach_ops(struct ath_hw
*ah
)
3517 struct ath_hw_private_ops
*priv_ops
= ath9k_hw_private_ops(ah
);
3518 struct ath_hw_ops
*ops
= ath9k_hw_ops(ah
);
3520 priv_ops
->init_cal_settings
= ar9002_hw_init_cal_settings
;
3521 priv_ops
->init_mode_regs
= ar9002_hw_init_mode_regs
;
3522 priv_ops
->macversion_supported
= ar9002_hw_macversion_supported
;
3524 ops
->config_pci_powersave
= ar9002_hw_configpcipowersave
;
3526 if (AR_SREV_9280_10_OR_LATER(ah
))
3527 ar9002_hw_attach_phy_ops(ah
);
3529 ar5008_hw_attach_phy_ops(ah
);