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ath9k_hw: move clock definitions from hw.c to hw.h
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
58 {
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
60
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
62 }
63
64 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan)
66 {
67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
68 }
69
70 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
71 {
72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
73 return;
74
75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
76 }
77
78 /********************/
79 /* Helper Functions */
80 /********************/
81
82 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
83 {
84 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
85
86 if (!ah->curchan) /* should really check for CCK instead */
87 return usecs *ATH9K_CLOCK_RATE_CCK;
88 if (conf->channel->band == IEEE80211_BAND_2GHZ)
89 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
90
91 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
92 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
93 else
94 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
95 }
96
97 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
98 {
99 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
100
101 if (conf_is_ht40(conf))
102 return ath9k_hw_mac_clks(ah, usecs) * 2;
103 else
104 return ath9k_hw_mac_clks(ah, usecs);
105 }
106
107 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
108 {
109 int i;
110
111 BUG_ON(timeout < AH_TIME_QUANTUM);
112
113 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
114 if ((REG_READ(ah, reg) & mask) == val)
115 return true;
116
117 udelay(AH_TIME_QUANTUM);
118 }
119
120 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
121 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
122 timeout, reg, REG_READ(ah, reg), mask, val);
123
124 return false;
125 }
126 EXPORT_SYMBOL(ath9k_hw_wait);
127
128 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
129 {
130 u32 retval;
131 int i;
132
133 for (i = 0, retval = 0; i < n; i++) {
134 retval = (retval << 1) | (val & 1);
135 val >>= 1;
136 }
137 return retval;
138 }
139
140 bool ath9k_get_channel_edges(struct ath_hw *ah,
141 u16 flags, u16 *low,
142 u16 *high)
143 {
144 struct ath9k_hw_capabilities *pCap = &ah->caps;
145
146 if (flags & CHANNEL_5GHZ) {
147 *low = pCap->low_5ghz_chan;
148 *high = pCap->high_5ghz_chan;
149 return true;
150 }
151 if ((flags & CHANNEL_2GHZ)) {
152 *low = pCap->low_2ghz_chan;
153 *high = pCap->high_2ghz_chan;
154 return true;
155 }
156 return false;
157 }
158
159 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
160 u8 phy, int kbps,
161 u32 frameLen, u16 rateix,
162 bool shortPreamble)
163 {
164 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
165
166 if (kbps == 0)
167 return 0;
168
169 switch (phy) {
170 case WLAN_RC_PHY_CCK:
171 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
172 if (shortPreamble)
173 phyTime >>= 1;
174 numBits = frameLen << 3;
175 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
176 break;
177 case WLAN_RC_PHY_OFDM:
178 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
179 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
180 numBits = OFDM_PLCP_BITS + (frameLen << 3);
181 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
182 txTime = OFDM_SIFS_TIME_QUARTER
183 + OFDM_PREAMBLE_TIME_QUARTER
184 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
185 } else if (ah->curchan &&
186 IS_CHAN_HALF_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_HALF +
191 OFDM_PREAMBLE_TIME_HALF
192 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
193 } else {
194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
195 numBits = OFDM_PLCP_BITS + (frameLen << 3);
196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
197 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
198 + (numSymbols * OFDM_SYMBOL_TIME);
199 }
200 break;
201 default:
202 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
203 "Unknown phy %u (rate ix %u)\n", phy, rateix);
204 txTime = 0;
205 break;
206 }
207
208 return txTime;
209 }
210 EXPORT_SYMBOL(ath9k_hw_computetxtime);
211
212 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
213 struct ath9k_channel *chan,
214 struct chan_centers *centers)
215 {
216 int8_t extoff;
217
218 if (!IS_CHAN_HT40(chan)) {
219 centers->ctl_center = centers->ext_center =
220 centers->synth_center = chan->channel;
221 return;
222 }
223
224 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
225 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
226 centers->synth_center =
227 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
228 extoff = 1;
229 } else {
230 centers->synth_center =
231 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
232 extoff = -1;
233 }
234
235 centers->ctl_center =
236 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
237 /* 25 MHz spacing is supported by hw but not on upper layers */
238 centers->ext_center =
239 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
240 }
241
242 /******************/
243 /* Chip Revisions */
244 /******************/
245
246 static void ath9k_hw_read_revisions(struct ath_hw *ah)
247 {
248 u32 val;
249
250 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
251
252 if (val == 0xFF) {
253 val = REG_READ(ah, AR_SREV);
254 ah->hw_version.macVersion =
255 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
256 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
257 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
258 } else {
259 if (!AR_SREV_9100(ah))
260 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
261
262 ah->hw_version.macRev = val & AR_SREV_REVISION;
263
264 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
265 ah->is_pciexpress = true;
266 }
267 }
268
269 /************************************/
270 /* HW Attach, Detach, Init Routines */
271 /************************************/
272
273 static void ath9k_hw_disablepcie(struct ath_hw *ah)
274 {
275 if (AR_SREV_9100(ah))
276 return;
277
278 ENABLE_REGWRITE_BUFFER(ah);
279
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
289
290 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
291
292 REGWRITE_BUFFER_FLUSH(ah);
293 DISABLE_REGWRITE_BUFFER(ah);
294 }
295
296 /* This should work for all families including legacy */
297 static bool ath9k_hw_chip_test(struct ath_hw *ah)
298 {
299 struct ath_common *common = ath9k_hw_common(ah);
300 u32 regAddr[2] = { AR_STA_ID0 };
301 u32 regHold[2];
302 u32 patternData[4] = { 0x55555555,
303 0xaaaaaaaa,
304 0x66666666,
305 0x99999999 };
306 int i, j, loop_max;
307
308 if (!AR_SREV_9300_20_OR_LATER(ah)) {
309 loop_max = 2;
310 regAddr[1] = AR_PHY_BASE + (8 << 2);
311 } else
312 loop_max = 1;
313
314 for (i = 0; i < loop_max; i++) {
315 u32 addr = regAddr[i];
316 u32 wrData, rdData;
317
318 regHold[i] = REG_READ(ah, addr);
319 for (j = 0; j < 0x100; j++) {
320 wrData = (j << 16) | j;
321 REG_WRITE(ah, addr, wrData);
322 rdData = REG_READ(ah, addr);
323 if (rdData != wrData) {
324 ath_print(common, ATH_DBG_FATAL,
325 "address test failed "
326 "addr: 0x%08x - wr:0x%08x != "
327 "rd:0x%08x\n",
328 addr, wrData, rdData);
329 return false;
330 }
331 }
332 for (j = 0; j < 4; j++) {
333 wrData = patternData[j];
334 REG_WRITE(ah, addr, wrData);
335 rdData = REG_READ(ah, addr);
336 if (wrData != rdData) {
337 ath_print(common, ATH_DBG_FATAL,
338 "address test failed "
339 "addr: 0x%08x - wr:0x%08x != "
340 "rd:0x%08x\n",
341 addr, wrData, rdData);
342 return false;
343 }
344 }
345 REG_WRITE(ah, regAddr[i], regHold[i]);
346 }
347 udelay(100);
348
349 return true;
350 }
351
352 static void ath9k_hw_init_config(struct ath_hw *ah)
353 {
354 int i;
355
356 ah->config.dma_beacon_response_time = 2;
357 ah->config.sw_beacon_response_time = 10;
358 ah->config.additional_swba_backoff = 0;
359 ah->config.ack_6mb = 0x0;
360 ah->config.cwm_ignore_extcca = 0;
361 ah->config.pcie_powersave_enable = 0;
362 ah->config.pcie_clock_req = 0;
363 ah->config.pcie_waen = 0;
364 ah->config.analog_shiftreg = 1;
365 ah->config.ofdm_trig_low = 200;
366 ah->config.ofdm_trig_high = 500;
367 ah->config.cck_trig_high = 200;
368 ah->config.cck_trig_low = 100;
369
370 /*
371 * For now ANI is disabled for AR9003, it is still
372 * being tested.
373 */
374 if (!AR_SREV_9300_20_OR_LATER(ah))
375 ah->config.enable_ani = 1;
376
377 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
378 ah->config.spurchans[i][0] = AR_NO_SPUR;
379 ah->config.spurchans[i][1] = AR_NO_SPUR;
380 }
381
382 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
383 ah->config.ht_enable = 1;
384 else
385 ah->config.ht_enable = 0;
386
387 ah->config.rx_intr_mitigation = true;
388
389 /*
390 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
391 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
392 * This means we use it for all AR5416 devices, and the few
393 * minor PCI AR9280 devices out there.
394 *
395 * Serialization is required because these devices do not handle
396 * well the case of two concurrent reads/writes due to the latency
397 * involved. During one read/write another read/write can be issued
398 * on another CPU while the previous read/write may still be working
399 * on our hardware, if we hit this case the hardware poops in a loop.
400 * We prevent this by serializing reads and writes.
401 *
402 * This issue is not present on PCI-Express devices or pre-AR5416
403 * devices (legacy, 802.11abg).
404 */
405 if (num_possible_cpus() > 1)
406 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
407 }
408
409 static void ath9k_hw_init_defaults(struct ath_hw *ah)
410 {
411 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
412
413 regulatory->country_code = CTRY_DEFAULT;
414 regulatory->power_limit = MAX_RATE_POWER;
415 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
416
417 ah->hw_version.magic = AR5416_MAGIC;
418 ah->hw_version.subvendorid = 0;
419
420 ah->ah_flags = 0;
421 if (!AR_SREV_9100(ah))
422 ah->ah_flags = AH_USE_EEPROM;
423
424 ah->atim_window = 0;
425 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
426 ah->beacon_interval = 100;
427 ah->enable_32kHz_clock = DONT_USE_32KHZ;
428 ah->slottime = (u32) -1;
429 ah->globaltxtimeout = (u32) -1;
430 ah->power_mode = ATH9K_PM_UNDEFINED;
431 }
432
433 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
434 {
435 struct ath_common *common = ath9k_hw_common(ah);
436 u32 sum;
437 int i;
438 u16 eeval;
439 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
440
441 sum = 0;
442 for (i = 0; i < 3; i++) {
443 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
444 sum += eeval;
445 common->macaddr[2 * i] = eeval >> 8;
446 common->macaddr[2 * i + 1] = eeval & 0xff;
447 }
448 if (sum == 0 || sum == 0xffff * 3)
449 return -EADDRNOTAVAIL;
450
451 return 0;
452 }
453
454 static int ath9k_hw_post_init(struct ath_hw *ah)
455 {
456 int ecode;
457
458 if (!AR_SREV_9271(ah)) {
459 if (!ath9k_hw_chip_test(ah))
460 return -ENODEV;
461 }
462
463 if (!AR_SREV_9300_20_OR_LATER(ah)) {
464 ecode = ar9002_hw_rf_claim(ah);
465 if (ecode != 0)
466 return ecode;
467 }
468
469 ecode = ath9k_hw_eeprom_init(ah);
470 if (ecode != 0)
471 return ecode;
472
473 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
474 "Eeprom VER: %d, REV: %d\n",
475 ah->eep_ops->get_eeprom_ver(ah),
476 ah->eep_ops->get_eeprom_rev(ah));
477
478 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
479 if (ecode) {
480 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
481 "Failed allocating banks for "
482 "external radio\n");
483 return ecode;
484 }
485
486 if (!AR_SREV_9100(ah)) {
487 ath9k_hw_ani_setup(ah);
488 ath9k_hw_ani_init(ah);
489 }
490
491 return 0;
492 }
493
494 static void ath9k_hw_attach_ops(struct ath_hw *ah)
495 {
496 if (AR_SREV_9300_20_OR_LATER(ah))
497 ar9003_hw_attach_ops(ah);
498 else
499 ar9002_hw_attach_ops(ah);
500 }
501
502 /* Called for all hardware families */
503 static int __ath9k_hw_init(struct ath_hw *ah)
504 {
505 struct ath_common *common = ath9k_hw_common(ah);
506 int r = 0;
507
508 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
509 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
510
511 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
512 ath_print(common, ATH_DBG_FATAL,
513 "Couldn't reset chip\n");
514 return -EIO;
515 }
516
517 ath9k_hw_init_defaults(ah);
518 ath9k_hw_init_config(ah);
519
520 ath9k_hw_attach_ops(ah);
521
522 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
523 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
524 return -EIO;
525 }
526
527 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
528 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
529 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
530 ah->config.serialize_regmode =
531 SER_REG_MODE_ON;
532 } else {
533 ah->config.serialize_regmode =
534 SER_REG_MODE_OFF;
535 }
536 }
537
538 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
539 ah->config.serialize_regmode);
540
541 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
542 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
543 else
544 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
545
546 if (!ath9k_hw_macversion_supported(ah)) {
547 ath_print(common, ATH_DBG_FATAL,
548 "Mac Chip Rev 0x%02x.%x is not supported by "
549 "this driver\n", ah->hw_version.macVersion,
550 ah->hw_version.macRev);
551 return -EOPNOTSUPP;
552 }
553
554 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
555 ah->is_pciexpress = false;
556
557 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
558 ath9k_hw_init_cal_settings(ah);
559
560 ah->ani_function = ATH9K_ANI_ALL;
561 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
562 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
563
564 ath9k_hw_init_mode_regs(ah);
565
566 /*
567 * Configire PCIE after Ini init. SERDES values now come from ini file
568 * This enables PCIe low power mode.
569 */
570 if (AR_SREV_9300_20_OR_LATER(ah)) {
571 u32 regval;
572 unsigned int i;
573
574 /* Set Bits 16 and 17 in the AR_WA register. */
575 regval = REG_READ(ah, AR_WA);
576 regval |= 0x00030000;
577 REG_WRITE(ah, AR_WA, regval);
578
579 for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
580 REG_WRITE(ah,
581 INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
582 INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
583 }
584 }
585
586 if (ah->is_pciexpress)
587 ath9k_hw_configpcipowersave(ah, 0, 0);
588 else
589 ath9k_hw_disablepcie(ah);
590
591 if (!AR_SREV_9300_20_OR_LATER(ah))
592 ar9002_hw_cck_chan14_spread(ah);
593
594 r = ath9k_hw_post_init(ah);
595 if (r)
596 return r;
597
598 ath9k_hw_init_mode_gain_regs(ah);
599 r = ath9k_hw_fill_cap_info(ah);
600 if (r)
601 return r;
602
603 r = ath9k_hw_init_macaddr(ah);
604 if (r) {
605 ath_print(common, ATH_DBG_FATAL,
606 "Failed to initialize MAC address\n");
607 return r;
608 }
609
610 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
611 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
612 else
613 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
614
615 if (AR_SREV_9300_20_OR_LATER(ah))
616 ar9003_hw_set_nf_limits(ah);
617
618 ath9k_init_nfcal_hist_buffer(ah);
619 ah->bb_watchdog_timeout_ms = 25;
620
621 common->state = ATH_HW_INITIALIZED;
622
623 return 0;
624 }
625
626 int ath9k_hw_init(struct ath_hw *ah)
627 {
628 int ret;
629 struct ath_common *common = ath9k_hw_common(ah);
630
631 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
632 switch (ah->hw_version.devid) {
633 case AR5416_DEVID_PCI:
634 case AR5416_DEVID_PCIE:
635 case AR5416_AR9100_DEVID:
636 case AR9160_DEVID_PCI:
637 case AR9280_DEVID_PCI:
638 case AR9280_DEVID_PCIE:
639 case AR9285_DEVID_PCIE:
640 case AR9287_DEVID_PCI:
641 case AR9287_DEVID_PCIE:
642 case AR2427_DEVID_PCIE:
643 case AR9300_DEVID_PCIE:
644 break;
645 default:
646 if (common->bus_ops->ath_bus_type == ATH_USB)
647 break;
648 ath_print(common, ATH_DBG_FATAL,
649 "Hardware device ID 0x%04x not supported\n",
650 ah->hw_version.devid);
651 return -EOPNOTSUPP;
652 }
653
654 ret = __ath9k_hw_init(ah);
655 if (ret) {
656 ath_print(common, ATH_DBG_FATAL,
657 "Unable to initialize hardware; "
658 "initialization status: %d\n", ret);
659 return ret;
660 }
661
662 return 0;
663 }
664 EXPORT_SYMBOL(ath9k_hw_init);
665
666 static void ath9k_hw_init_qos(struct ath_hw *ah)
667 {
668 ENABLE_REGWRITE_BUFFER(ah);
669
670 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
671 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
672
673 REG_WRITE(ah, AR_QOS_NO_ACK,
674 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
675 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
676 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
677
678 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
679 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
680 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
681 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
682 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
683
684 REGWRITE_BUFFER_FLUSH(ah);
685 DISABLE_REGWRITE_BUFFER(ah);
686 }
687
688 static void ath9k_hw_init_pll(struct ath_hw *ah,
689 struct ath9k_channel *chan)
690 {
691 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
692
693 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
694
695 /* Switch the core clock for ar9271 to 117Mhz */
696 if (AR_SREV_9271(ah)) {
697 udelay(500);
698 REG_WRITE(ah, 0x50040, 0x304);
699 }
700
701 udelay(RTC_PLL_SETTLE_DELAY);
702
703 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
704 }
705
706 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
707 enum nl80211_iftype opmode)
708 {
709 u32 imr_reg = AR_IMR_TXERR |
710 AR_IMR_TXURN |
711 AR_IMR_RXERR |
712 AR_IMR_RXORN |
713 AR_IMR_BCNMISC;
714
715 if (AR_SREV_9300_20_OR_LATER(ah)) {
716 imr_reg |= AR_IMR_RXOK_HP;
717 if (ah->config.rx_intr_mitigation)
718 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
719 else
720 imr_reg |= AR_IMR_RXOK_LP;
721
722 } else {
723 if (ah->config.rx_intr_mitigation)
724 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
725 else
726 imr_reg |= AR_IMR_RXOK;
727 }
728
729 if (ah->config.tx_intr_mitigation)
730 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
731 else
732 imr_reg |= AR_IMR_TXOK;
733
734 if (opmode == NL80211_IFTYPE_AP)
735 imr_reg |= AR_IMR_MIB;
736
737 ENABLE_REGWRITE_BUFFER(ah);
738
739 REG_WRITE(ah, AR_IMR, imr_reg);
740 ah->imrs2_reg |= AR_IMR_S2_GTT;
741 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
742
743 if (!AR_SREV_9100(ah)) {
744 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
745 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
746 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
747 }
748
749 REGWRITE_BUFFER_FLUSH(ah);
750 DISABLE_REGWRITE_BUFFER(ah);
751
752 if (AR_SREV_9300_20_OR_LATER(ah)) {
753 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
754 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
755 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
756 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
757 }
758 }
759
760 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
761 {
762 u32 val = ath9k_hw_mac_to_clks(ah, us);
763 val = min(val, (u32) 0xFFFF);
764 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
765 }
766
767 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
768 {
769 u32 val = ath9k_hw_mac_to_clks(ah, us);
770 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
771 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
772 }
773
774 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
775 {
776 u32 val = ath9k_hw_mac_to_clks(ah, us);
777 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
778 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
779 }
780
781 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
782 {
783 if (tu > 0xFFFF) {
784 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
785 "bad global tx timeout %u\n", tu);
786 ah->globaltxtimeout = (u32) -1;
787 return false;
788 } else {
789 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
790 ah->globaltxtimeout = tu;
791 return true;
792 }
793 }
794
795 void ath9k_hw_init_global_settings(struct ath_hw *ah)
796 {
797 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
798 int acktimeout;
799 int slottime;
800 int sifstime;
801
802 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
803 ah->misc_mode);
804
805 if (ah->misc_mode != 0)
806 REG_WRITE(ah, AR_PCU_MISC,
807 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
808
809 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
810 sifstime = 16;
811 else
812 sifstime = 10;
813
814 /* As defined by IEEE 802.11-2007 17.3.8.6 */
815 slottime = ah->slottime + 3 * ah->coverage_class;
816 acktimeout = slottime + sifstime;
817
818 /*
819 * Workaround for early ACK timeouts, add an offset to match the
820 * initval's 64us ack timeout value.
821 * This was initially only meant to work around an issue with delayed
822 * BA frames in some implementations, but it has been found to fix ACK
823 * timeout issues in other cases as well.
824 */
825 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
826 acktimeout += 64 - sifstime - ah->slottime;
827
828 ath9k_hw_setslottime(ah, slottime);
829 ath9k_hw_set_ack_timeout(ah, acktimeout);
830 ath9k_hw_set_cts_timeout(ah, acktimeout);
831 if (ah->globaltxtimeout != (u32) -1)
832 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
833 }
834 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
835
836 void ath9k_hw_deinit(struct ath_hw *ah)
837 {
838 struct ath_common *common = ath9k_hw_common(ah);
839
840 if (common->state < ATH_HW_INITIALIZED)
841 goto free_hw;
842
843 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
844
845 free_hw:
846 ath9k_hw_rf_free_ext_banks(ah);
847 }
848 EXPORT_SYMBOL(ath9k_hw_deinit);
849
850 /*******/
851 /* INI */
852 /*******/
853
854 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
855 {
856 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
857
858 if (IS_CHAN_B(chan))
859 ctl |= CTL_11B;
860 else if (IS_CHAN_G(chan))
861 ctl |= CTL_11G;
862 else
863 ctl |= CTL_11A;
864
865 return ctl;
866 }
867
868 /****************************************/
869 /* Reset and Channel Switching Routines */
870 /****************************************/
871
872 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
873 {
874 struct ath_common *common = ath9k_hw_common(ah);
875 u32 regval;
876
877 ENABLE_REGWRITE_BUFFER(ah);
878
879 /*
880 * set AHB_MODE not to do cacheline prefetches
881 */
882 if (!AR_SREV_9300_20_OR_LATER(ah)) {
883 regval = REG_READ(ah, AR_AHB_MODE);
884 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
885 }
886
887 /*
888 * let mac dma reads be in 128 byte chunks
889 */
890 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
891 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
892
893 REGWRITE_BUFFER_FLUSH(ah);
894 DISABLE_REGWRITE_BUFFER(ah);
895
896 /*
897 * Restore TX Trigger Level to its pre-reset value.
898 * The initial value depends on whether aggregation is enabled, and is
899 * adjusted whenever underruns are detected.
900 */
901 if (!AR_SREV_9300_20_OR_LATER(ah))
902 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
903
904 ENABLE_REGWRITE_BUFFER(ah);
905
906 /*
907 * let mac dma writes be in 128 byte chunks
908 */
909 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
910 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
911
912 /*
913 * Setup receive FIFO threshold to hold off TX activities
914 */
915 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
916
917 if (AR_SREV_9300_20_OR_LATER(ah)) {
918 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
919 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
920
921 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
922 ah->caps.rx_status_len);
923 }
924
925 /*
926 * reduce the number of usable entries in PCU TXBUF to avoid
927 * wrap around issues.
928 */
929 if (AR_SREV_9285(ah)) {
930 /* For AR9285 the number of Fifos are reduced to half.
931 * So set the usable tx buf size also to half to
932 * avoid data/delimiter underruns
933 */
934 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
935 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
936 } else if (!AR_SREV_9271(ah)) {
937 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
938 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
939 }
940
941 REGWRITE_BUFFER_FLUSH(ah);
942 DISABLE_REGWRITE_BUFFER(ah);
943
944 if (AR_SREV_9300_20_OR_LATER(ah))
945 ath9k_hw_reset_txstatus_ring(ah);
946 }
947
948 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
949 {
950 u32 val;
951
952 val = REG_READ(ah, AR_STA_ID1);
953 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
954 switch (opmode) {
955 case NL80211_IFTYPE_AP:
956 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
957 | AR_STA_ID1_KSRCH_MODE);
958 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
959 break;
960 case NL80211_IFTYPE_ADHOC:
961 case NL80211_IFTYPE_MESH_POINT:
962 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
963 | AR_STA_ID1_KSRCH_MODE);
964 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
965 break;
966 case NL80211_IFTYPE_STATION:
967 case NL80211_IFTYPE_MONITOR:
968 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
969 break;
970 }
971 }
972
973 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
974 u32 *coef_mantissa, u32 *coef_exponent)
975 {
976 u32 coef_exp, coef_man;
977
978 for (coef_exp = 31; coef_exp > 0; coef_exp--)
979 if ((coef_scaled >> coef_exp) & 0x1)
980 break;
981
982 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
983
984 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
985
986 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
987 *coef_exponent = coef_exp - 16;
988 }
989
990 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
991 {
992 u32 rst_flags;
993 u32 tmpReg;
994
995 if (AR_SREV_9100(ah)) {
996 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
997 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
998 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
999 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1000 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1001 }
1002
1003 ENABLE_REGWRITE_BUFFER(ah);
1004
1005 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1006 AR_RTC_FORCE_WAKE_ON_INT);
1007
1008 if (AR_SREV_9100(ah)) {
1009 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1010 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1011 } else {
1012 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1013 if (tmpReg &
1014 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1015 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1016 u32 val;
1017 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1018
1019 val = AR_RC_HOSTIF;
1020 if (!AR_SREV_9300_20_OR_LATER(ah))
1021 val |= AR_RC_AHB;
1022 REG_WRITE(ah, AR_RC, val);
1023
1024 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1025 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1026
1027 rst_flags = AR_RTC_RC_MAC_WARM;
1028 if (type == ATH9K_RESET_COLD)
1029 rst_flags |= AR_RTC_RC_MAC_COLD;
1030 }
1031
1032 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1033
1034 REGWRITE_BUFFER_FLUSH(ah);
1035 DISABLE_REGWRITE_BUFFER(ah);
1036
1037 udelay(50);
1038
1039 REG_WRITE(ah, AR_RTC_RC, 0);
1040 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1041 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1042 "RTC stuck in MAC reset\n");
1043 return false;
1044 }
1045
1046 if (!AR_SREV_9100(ah))
1047 REG_WRITE(ah, AR_RC, 0);
1048
1049 if (AR_SREV_9100(ah))
1050 udelay(50);
1051
1052 return true;
1053 }
1054
1055 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1056 {
1057 ENABLE_REGWRITE_BUFFER(ah);
1058
1059 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1060 AR_RTC_FORCE_WAKE_ON_INT);
1061
1062 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1063 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1064
1065 REG_WRITE(ah, AR_RTC_RESET, 0);
1066
1067 REGWRITE_BUFFER_FLUSH(ah);
1068 DISABLE_REGWRITE_BUFFER(ah);
1069
1070 if (!AR_SREV_9300_20_OR_LATER(ah))
1071 udelay(2);
1072
1073 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1074 REG_WRITE(ah, AR_RC, 0);
1075
1076 REG_WRITE(ah, AR_RTC_RESET, 1);
1077
1078 if (!ath9k_hw_wait(ah,
1079 AR_RTC_STATUS,
1080 AR_RTC_STATUS_M,
1081 AR_RTC_STATUS_ON,
1082 AH_WAIT_TIMEOUT)) {
1083 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1084 "RTC not waking up\n");
1085 return false;
1086 }
1087
1088 ath9k_hw_read_revisions(ah);
1089
1090 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1091 }
1092
1093 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1094 {
1095 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1096 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1097
1098 switch (type) {
1099 case ATH9K_RESET_POWER_ON:
1100 return ath9k_hw_set_reset_power_on(ah);
1101 case ATH9K_RESET_WARM:
1102 case ATH9K_RESET_COLD:
1103 return ath9k_hw_set_reset(ah, type);
1104 default:
1105 return false;
1106 }
1107 }
1108
1109 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1110 struct ath9k_channel *chan)
1111 {
1112 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1113 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1114 return false;
1115 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1116 return false;
1117
1118 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1119 return false;
1120
1121 ah->chip_fullsleep = false;
1122 ath9k_hw_init_pll(ah, chan);
1123 ath9k_hw_set_rfmode(ah, chan);
1124
1125 return true;
1126 }
1127
1128 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1129 struct ath9k_channel *chan)
1130 {
1131 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1132 struct ath_common *common = ath9k_hw_common(ah);
1133 struct ieee80211_channel *channel = chan->chan;
1134 u32 qnum;
1135 int r;
1136
1137 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1138 if (ath9k_hw_numtxpending(ah, qnum)) {
1139 ath_print(common, ATH_DBG_QUEUE,
1140 "Transmit frames pending on "
1141 "queue %d\n", qnum);
1142 return false;
1143 }
1144 }
1145
1146 if (!ath9k_hw_rfbus_req(ah)) {
1147 ath_print(common, ATH_DBG_FATAL,
1148 "Could not kill baseband RX\n");
1149 return false;
1150 }
1151
1152 ath9k_hw_set_channel_regs(ah, chan);
1153
1154 r = ath9k_hw_rf_set_freq(ah, chan);
1155 if (r) {
1156 ath_print(common, ATH_DBG_FATAL,
1157 "Failed to set channel\n");
1158 return false;
1159 }
1160
1161 ah->eep_ops->set_txpower(ah, chan,
1162 ath9k_regd_get_ctl(regulatory, chan),
1163 channel->max_antenna_gain * 2,
1164 channel->max_power * 2,
1165 min((u32) MAX_RATE_POWER,
1166 (u32) regulatory->power_limit));
1167
1168 ath9k_hw_rfbus_done(ah);
1169
1170 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1171 ath9k_hw_set_delta_slope(ah, chan);
1172
1173 ath9k_hw_spur_mitigate_freq(ah, chan);
1174
1175 if (!chan->oneTimeCalsDone)
1176 chan->oneTimeCalsDone = true;
1177
1178 return true;
1179 }
1180
1181 bool ath9k_hw_check_alive(struct ath_hw *ah)
1182 {
1183 int count = 50;
1184 u32 reg;
1185
1186 if (AR_SREV_9285_10_OR_LATER(ah))
1187 return true;
1188
1189 do {
1190 reg = REG_READ(ah, AR_OBS_BUS_1);
1191
1192 if ((reg & 0x7E7FFFEF) == 0x00702400)
1193 continue;
1194
1195 switch (reg & 0x7E000B00) {
1196 case 0x1E000000:
1197 case 0x52000B00:
1198 case 0x18000B00:
1199 continue;
1200 default:
1201 return true;
1202 }
1203 } while (count-- > 0);
1204
1205 return false;
1206 }
1207 EXPORT_SYMBOL(ath9k_hw_check_alive);
1208
1209 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1210 bool bChannelChange)
1211 {
1212 struct ath_common *common = ath9k_hw_common(ah);
1213 u32 saveLedState;
1214 struct ath9k_channel *curchan = ah->curchan;
1215 u32 saveDefAntenna;
1216 u32 macStaId1;
1217 u64 tsf = 0;
1218 int i, r;
1219
1220 ah->txchainmask = common->tx_chainmask;
1221 ah->rxchainmask = common->rx_chainmask;
1222
1223 if (!ah->chip_fullsleep) {
1224 ath9k_hw_abortpcurecv(ah);
1225 if (!ath9k_hw_stopdmarecv(ah))
1226 ath_print(common, ATH_DBG_XMIT,
1227 "Failed to stop receive dma\n");
1228 }
1229
1230 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1231 return -EIO;
1232
1233 if (curchan && !ah->chip_fullsleep)
1234 ath9k_hw_getnf(ah, curchan);
1235
1236 if (bChannelChange &&
1237 (ah->chip_fullsleep != true) &&
1238 (ah->curchan != NULL) &&
1239 (chan->channel != ah->curchan->channel) &&
1240 ((chan->channelFlags & CHANNEL_ALL) ==
1241 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1242 !AR_SREV_9280(ah)) {
1243
1244 if (ath9k_hw_channel_change(ah, chan)) {
1245 ath9k_hw_loadnf(ah, ah->curchan);
1246 ath9k_hw_start_nfcal(ah);
1247 return 0;
1248 }
1249 }
1250
1251 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1252 if (saveDefAntenna == 0)
1253 saveDefAntenna = 1;
1254
1255 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1256
1257 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1258 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1259 tsf = ath9k_hw_gettsf64(ah);
1260
1261 saveLedState = REG_READ(ah, AR_CFG_LED) &
1262 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1263 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1264
1265 ath9k_hw_mark_phy_inactive(ah);
1266
1267 /* Only required on the first reset */
1268 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1269 REG_WRITE(ah,
1270 AR9271_RESET_POWER_DOWN_CONTROL,
1271 AR9271_RADIO_RF_RST);
1272 udelay(50);
1273 }
1274
1275 if (!ath9k_hw_chip_reset(ah, chan)) {
1276 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1277 return -EINVAL;
1278 }
1279
1280 /* Only required on the first reset */
1281 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1282 ah->htc_reset_init = false;
1283 REG_WRITE(ah,
1284 AR9271_RESET_POWER_DOWN_CONTROL,
1285 AR9271_GATE_MAC_CTL);
1286 udelay(50);
1287 }
1288
1289 /* Restore TSF */
1290 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1291 ath9k_hw_settsf64(ah, tsf);
1292
1293 if (AR_SREV_9280_10_OR_LATER(ah))
1294 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1295
1296 if (!AR_SREV_9300_20_OR_LATER(ah))
1297 ar9002_hw_enable_async_fifo(ah);
1298
1299 r = ath9k_hw_process_ini(ah, chan);
1300 if (r)
1301 return r;
1302
1303 /* Setup MFP options for CCMP */
1304 if (AR_SREV_9280_20_OR_LATER(ah)) {
1305 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1306 * frames when constructing CCMP AAD. */
1307 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1308 0xc7ff);
1309 ah->sw_mgmt_crypto = false;
1310 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1311 /* Disable hardware crypto for management frames */
1312 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1313 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1314 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1315 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1316 ah->sw_mgmt_crypto = true;
1317 } else
1318 ah->sw_mgmt_crypto = true;
1319
1320 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1321 ath9k_hw_set_delta_slope(ah, chan);
1322
1323 ath9k_hw_spur_mitigate_freq(ah, chan);
1324 ah->eep_ops->set_board_values(ah, chan);
1325
1326 ath9k_hw_set_operating_mode(ah, ah->opmode);
1327
1328 ENABLE_REGWRITE_BUFFER(ah);
1329
1330 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1331 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1332 | macStaId1
1333 | AR_STA_ID1_RTS_USE_DEF
1334 | (ah->config.
1335 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1336 | ah->sta_id1_defaults);
1337 ath_hw_setbssidmask(common);
1338 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1339 ath9k_hw_write_associd(ah);
1340 REG_WRITE(ah, AR_ISR, ~0);
1341 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1342
1343 REGWRITE_BUFFER_FLUSH(ah);
1344 DISABLE_REGWRITE_BUFFER(ah);
1345
1346 r = ath9k_hw_rf_set_freq(ah, chan);
1347 if (r)
1348 return r;
1349
1350 ENABLE_REGWRITE_BUFFER(ah);
1351
1352 for (i = 0; i < AR_NUM_DCU; i++)
1353 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1354
1355 REGWRITE_BUFFER_FLUSH(ah);
1356 DISABLE_REGWRITE_BUFFER(ah);
1357
1358 ah->intr_txqs = 0;
1359 for (i = 0; i < ah->caps.total_queues; i++)
1360 ath9k_hw_resettxqueue(ah, i);
1361
1362 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1363 ath9k_hw_init_qos(ah);
1364
1365 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1366 ath9k_enable_rfkill(ah);
1367
1368 ath9k_hw_init_global_settings(ah);
1369
1370 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1371 ar9002_hw_update_async_fifo(ah);
1372 ar9002_hw_enable_wep_aggregation(ah);
1373 }
1374
1375 REG_WRITE(ah, AR_STA_ID1,
1376 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1377
1378 ath9k_hw_set_dma(ah);
1379
1380 REG_WRITE(ah, AR_OBS, 8);
1381
1382 if (ah->config.rx_intr_mitigation) {
1383 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1384 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1385 }
1386
1387 if (ah->config.tx_intr_mitigation) {
1388 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1389 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1390 }
1391
1392 ath9k_hw_init_bb(ah, chan);
1393
1394 if (!ath9k_hw_init_cal(ah, chan))
1395 return -EIO;
1396
1397 ENABLE_REGWRITE_BUFFER(ah);
1398
1399 ath9k_hw_restore_chainmask(ah);
1400 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1401
1402 REGWRITE_BUFFER_FLUSH(ah);
1403 DISABLE_REGWRITE_BUFFER(ah);
1404
1405 /*
1406 * For big endian systems turn on swapping for descriptors
1407 */
1408 if (AR_SREV_9100(ah)) {
1409 u32 mask;
1410 mask = REG_READ(ah, AR_CFG);
1411 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1412 ath_print(common, ATH_DBG_RESET,
1413 "CFG Byte Swap Set 0x%x\n", mask);
1414 } else {
1415 mask =
1416 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1417 REG_WRITE(ah, AR_CFG, mask);
1418 ath_print(common, ATH_DBG_RESET,
1419 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1420 }
1421 } else {
1422 if (common->bus_ops->ath_bus_type == ATH_USB) {
1423 /* Configure AR9271 target WLAN */
1424 if (AR_SREV_9271(ah))
1425 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1426 else
1427 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1428 }
1429 #ifdef __BIG_ENDIAN
1430 else
1431 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1432 #endif
1433 }
1434
1435 if (ah->btcoex_hw.enabled)
1436 ath9k_hw_btcoex_enable(ah);
1437
1438 if (AR_SREV_9300_20_OR_LATER(ah)) {
1439 ath9k_hw_loadnf(ah, curchan);
1440 ath9k_hw_start_nfcal(ah);
1441 ar9003_hw_bb_watchdog_config(ah);
1442 }
1443
1444 return 0;
1445 }
1446 EXPORT_SYMBOL(ath9k_hw_reset);
1447
1448 /************************/
1449 /* Key Cache Management */
1450 /************************/
1451
1452 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1453 {
1454 u32 keyType;
1455
1456 if (entry >= ah->caps.keycache_size) {
1457 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1458 "keychache entry %u out of range\n", entry);
1459 return false;
1460 }
1461
1462 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1463
1464 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1465 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1466 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1467 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1468 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1469 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1470 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1471 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1472
1473 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1474 u16 micentry = entry + 64;
1475
1476 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1477 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1478 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1479 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1480
1481 }
1482
1483 return true;
1484 }
1485 EXPORT_SYMBOL(ath9k_hw_keyreset);
1486
1487 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1488 {
1489 u32 macHi, macLo;
1490 u32 unicast_flag = AR_KEYTABLE_VALID;
1491
1492 if (entry >= ah->caps.keycache_size) {
1493 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1494 "keychache entry %u out of range\n", entry);
1495 return false;
1496 }
1497
1498 if (mac != NULL) {
1499 /*
1500 * AR_KEYTABLE_VALID indicates that the address is a unicast
1501 * address, which must match the transmitter address for
1502 * decrypting frames.
1503 * Not setting this bit allows the hardware to use the key
1504 * for multicast frame decryption.
1505 */
1506 if (mac[0] & 0x01)
1507 unicast_flag = 0;
1508
1509 macHi = (mac[5] << 8) | mac[4];
1510 macLo = (mac[3] << 24) |
1511 (mac[2] << 16) |
1512 (mac[1] << 8) |
1513 mac[0];
1514 macLo >>= 1;
1515 macLo |= (macHi & 1) << 31;
1516 macHi >>= 1;
1517 } else {
1518 macLo = macHi = 0;
1519 }
1520 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1521 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
1522
1523 return true;
1524 }
1525 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1526
1527 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1528 const struct ath9k_keyval *k,
1529 const u8 *mac)
1530 {
1531 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1532 struct ath_common *common = ath9k_hw_common(ah);
1533 u32 key0, key1, key2, key3, key4;
1534 u32 keyType;
1535
1536 if (entry >= pCap->keycache_size) {
1537 ath_print(common, ATH_DBG_FATAL,
1538 "keycache entry %u out of range\n", entry);
1539 return false;
1540 }
1541
1542 switch (k->kv_type) {
1543 case ATH9K_CIPHER_AES_OCB:
1544 keyType = AR_KEYTABLE_TYPE_AES;
1545 break;
1546 case ATH9K_CIPHER_AES_CCM:
1547 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1548 ath_print(common, ATH_DBG_ANY,
1549 "AES-CCM not supported by mac rev 0x%x\n",
1550 ah->hw_version.macRev);
1551 return false;
1552 }
1553 keyType = AR_KEYTABLE_TYPE_CCM;
1554 break;
1555 case ATH9K_CIPHER_TKIP:
1556 keyType = AR_KEYTABLE_TYPE_TKIP;
1557 if (ATH9K_IS_MIC_ENABLED(ah)
1558 && entry + 64 >= pCap->keycache_size) {
1559 ath_print(common, ATH_DBG_ANY,
1560 "entry %u inappropriate for TKIP\n", entry);
1561 return false;
1562 }
1563 break;
1564 case ATH9K_CIPHER_WEP:
1565 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1566 ath_print(common, ATH_DBG_ANY,
1567 "WEP key length %u too small\n", k->kv_len);
1568 return false;
1569 }
1570 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1571 keyType = AR_KEYTABLE_TYPE_40;
1572 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1573 keyType = AR_KEYTABLE_TYPE_104;
1574 else
1575 keyType = AR_KEYTABLE_TYPE_128;
1576 break;
1577 case ATH9K_CIPHER_CLR:
1578 keyType = AR_KEYTABLE_TYPE_CLR;
1579 break;
1580 default:
1581 ath_print(common, ATH_DBG_FATAL,
1582 "cipher %u not supported\n", k->kv_type);
1583 return false;
1584 }
1585
1586 key0 = get_unaligned_le32(k->kv_val + 0);
1587 key1 = get_unaligned_le16(k->kv_val + 4);
1588 key2 = get_unaligned_le32(k->kv_val + 6);
1589 key3 = get_unaligned_le16(k->kv_val + 10);
1590 key4 = get_unaligned_le32(k->kv_val + 12);
1591 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1592 key4 &= 0xff;
1593
1594 /*
1595 * Note: Key cache registers access special memory area that requires
1596 * two 32-bit writes to actually update the values in the internal
1597 * memory. Consequently, the exact order and pairs used here must be
1598 * maintained.
1599 */
1600
1601 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1602 u16 micentry = entry + 64;
1603
1604 /*
1605 * Write inverted key[47:0] first to avoid Michael MIC errors
1606 * on frames that could be sent or received at the same time.
1607 * The correct key will be written in the end once everything
1608 * else is ready.
1609 */
1610 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1611 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1612
1613 /* Write key[95:48] */
1614 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1615 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1616
1617 /* Write key[127:96] and key type */
1618 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1619 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1620
1621 /* Write MAC address for the entry */
1622 (void) ath9k_hw_keysetmac(ah, entry, mac);
1623
1624 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1625 /*
1626 * TKIP uses two key cache entries:
1627 * Michael MIC TX/RX keys in the same key cache entry
1628 * (idx = main index + 64):
1629 * key0 [31:0] = RX key [31:0]
1630 * key1 [15:0] = TX key [31:16]
1631 * key1 [31:16] = reserved
1632 * key2 [31:0] = RX key [63:32]
1633 * key3 [15:0] = TX key [15:0]
1634 * key3 [31:16] = reserved
1635 * key4 [31:0] = TX key [63:32]
1636 */
1637 u32 mic0, mic1, mic2, mic3, mic4;
1638
1639 mic0 = get_unaligned_le32(k->kv_mic + 0);
1640 mic2 = get_unaligned_le32(k->kv_mic + 4);
1641 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1642 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1643 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1644
1645 /* Write RX[31:0] and TX[31:16] */
1646 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1647 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1648
1649 /* Write RX[63:32] and TX[15:0] */
1650 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1651 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1652
1653 /* Write TX[63:32] and keyType(reserved) */
1654 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1655 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1656 AR_KEYTABLE_TYPE_CLR);
1657
1658 } else {
1659 /*
1660 * TKIP uses four key cache entries (two for group
1661 * keys):
1662 * Michael MIC TX/RX keys are in different key cache
1663 * entries (idx = main index + 64 for TX and
1664 * main index + 32 + 96 for RX):
1665 * key0 [31:0] = TX/RX MIC key [31:0]
1666 * key1 [31:0] = reserved
1667 * key2 [31:0] = TX/RX MIC key [63:32]
1668 * key3 [31:0] = reserved
1669 * key4 [31:0] = reserved
1670 *
1671 * Upper layer code will call this function separately
1672 * for TX and RX keys when these registers offsets are
1673 * used.
1674 */
1675 u32 mic0, mic2;
1676
1677 mic0 = get_unaligned_le32(k->kv_mic + 0);
1678 mic2 = get_unaligned_le32(k->kv_mic + 4);
1679
1680 /* Write MIC key[31:0] */
1681 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1682 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1683
1684 /* Write MIC key[63:32] */
1685 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1686 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1687
1688 /* Write TX[63:32] and keyType(reserved) */
1689 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1690 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1691 AR_KEYTABLE_TYPE_CLR);
1692 }
1693
1694 /* MAC address registers are reserved for the MIC entry */
1695 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1696 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1697
1698 /*
1699 * Write the correct (un-inverted) key[47:0] last to enable
1700 * TKIP now that all other registers are set with correct
1701 * values.
1702 */
1703 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1704 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1705 } else {
1706 /* Write key[47:0] */
1707 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1708 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1709
1710 /* Write key[95:48] */
1711 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1712 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1713
1714 /* Write key[127:96] and key type */
1715 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1716 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1717
1718 /* Write MAC address for the entry */
1719 (void) ath9k_hw_keysetmac(ah, entry, mac);
1720 }
1721
1722 return true;
1723 }
1724 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1725
1726 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1727 {
1728 if (entry < ah->caps.keycache_size) {
1729 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1730 if (val & AR_KEYTABLE_VALID)
1731 return true;
1732 }
1733 return false;
1734 }
1735 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1736
1737 /******************************/
1738 /* Power Management (Chipset) */
1739 /******************************/
1740
1741 /*
1742 * Notify Power Mgt is disabled in self-generated frames.
1743 * If requested, force chip to sleep.
1744 */
1745 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1746 {
1747 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1748 if (setChip) {
1749 /*
1750 * Clear the RTC force wake bit to allow the
1751 * mac to go to sleep.
1752 */
1753 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1754 AR_RTC_FORCE_WAKE_EN);
1755 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1756 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1757
1758 /* Shutdown chip. Active low */
1759 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1760 REG_CLR_BIT(ah, (AR_RTC_RESET),
1761 AR_RTC_RESET_EN);
1762 }
1763 }
1764
1765 /*
1766 * Notify Power Management is enabled in self-generating
1767 * frames. If request, set power mode of chip to
1768 * auto/normal. Duration in units of 128us (1/8 TU).
1769 */
1770 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1771 {
1772 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1773 if (setChip) {
1774 struct ath9k_hw_capabilities *pCap = &ah->caps;
1775
1776 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1777 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1778 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1779 AR_RTC_FORCE_WAKE_ON_INT);
1780 } else {
1781 /*
1782 * Clear the RTC force wake bit to allow the
1783 * mac to go to sleep.
1784 */
1785 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1786 AR_RTC_FORCE_WAKE_EN);
1787 }
1788 }
1789 }
1790
1791 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1792 {
1793 u32 val;
1794 int i;
1795
1796 if (setChip) {
1797 if ((REG_READ(ah, AR_RTC_STATUS) &
1798 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1799 if (ath9k_hw_set_reset_reg(ah,
1800 ATH9K_RESET_POWER_ON) != true) {
1801 return false;
1802 }
1803 if (!AR_SREV_9300_20_OR_LATER(ah))
1804 ath9k_hw_init_pll(ah, NULL);
1805 }
1806 if (AR_SREV_9100(ah))
1807 REG_SET_BIT(ah, AR_RTC_RESET,
1808 AR_RTC_RESET_EN);
1809
1810 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1811 AR_RTC_FORCE_WAKE_EN);
1812 udelay(50);
1813
1814 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1815 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1816 if (val == AR_RTC_STATUS_ON)
1817 break;
1818 udelay(50);
1819 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1820 AR_RTC_FORCE_WAKE_EN);
1821 }
1822 if (i == 0) {
1823 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1824 "Failed to wakeup in %uus\n",
1825 POWER_UP_TIME / 20);
1826 return false;
1827 }
1828 }
1829
1830 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1831
1832 return true;
1833 }
1834
1835 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1836 {
1837 struct ath_common *common = ath9k_hw_common(ah);
1838 int status = true, setChip = true;
1839 static const char *modes[] = {
1840 "AWAKE",
1841 "FULL-SLEEP",
1842 "NETWORK SLEEP",
1843 "UNDEFINED"
1844 };
1845
1846 if (ah->power_mode == mode)
1847 return status;
1848
1849 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1850 modes[ah->power_mode], modes[mode]);
1851
1852 switch (mode) {
1853 case ATH9K_PM_AWAKE:
1854 status = ath9k_hw_set_power_awake(ah, setChip);
1855 break;
1856 case ATH9K_PM_FULL_SLEEP:
1857 ath9k_set_power_sleep(ah, setChip);
1858 ah->chip_fullsleep = true;
1859 break;
1860 case ATH9K_PM_NETWORK_SLEEP:
1861 ath9k_set_power_network_sleep(ah, setChip);
1862 break;
1863 default:
1864 ath_print(common, ATH_DBG_FATAL,
1865 "Unknown power mode %u\n", mode);
1866 return false;
1867 }
1868 ah->power_mode = mode;
1869
1870 return status;
1871 }
1872 EXPORT_SYMBOL(ath9k_hw_setpower);
1873
1874 /*******************/
1875 /* Beacon Handling */
1876 /*******************/
1877
1878 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1879 {
1880 int flags = 0;
1881
1882 ah->beacon_interval = beacon_period;
1883
1884 ENABLE_REGWRITE_BUFFER(ah);
1885
1886 switch (ah->opmode) {
1887 case NL80211_IFTYPE_STATION:
1888 case NL80211_IFTYPE_MONITOR:
1889 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1890 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1891 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1892 flags |= AR_TBTT_TIMER_EN;
1893 break;
1894 case NL80211_IFTYPE_ADHOC:
1895 case NL80211_IFTYPE_MESH_POINT:
1896 REG_SET_BIT(ah, AR_TXCFG,
1897 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1898 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1899 TU_TO_USEC(next_beacon +
1900 (ah->atim_window ? ah->
1901 atim_window : 1)));
1902 flags |= AR_NDP_TIMER_EN;
1903 case NL80211_IFTYPE_AP:
1904 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1905 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1906 TU_TO_USEC(next_beacon -
1907 ah->config.
1908 dma_beacon_response_time));
1909 REG_WRITE(ah, AR_NEXT_SWBA,
1910 TU_TO_USEC(next_beacon -
1911 ah->config.
1912 sw_beacon_response_time));
1913 flags |=
1914 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1915 break;
1916 default:
1917 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1918 "%s: unsupported opmode: %d\n",
1919 __func__, ah->opmode);
1920 return;
1921 break;
1922 }
1923
1924 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1925 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1926 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1927 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1928
1929 REGWRITE_BUFFER_FLUSH(ah);
1930 DISABLE_REGWRITE_BUFFER(ah);
1931
1932 beacon_period &= ~ATH9K_BEACON_ENA;
1933 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1934 ath9k_hw_reset_tsf(ah);
1935 }
1936
1937 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1938 }
1939 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1940
1941 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1942 const struct ath9k_beacon_state *bs)
1943 {
1944 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1945 struct ath9k_hw_capabilities *pCap = &ah->caps;
1946 struct ath_common *common = ath9k_hw_common(ah);
1947
1948 ENABLE_REGWRITE_BUFFER(ah);
1949
1950 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1951
1952 REG_WRITE(ah, AR_BEACON_PERIOD,
1953 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1954 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1955 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1956
1957 REGWRITE_BUFFER_FLUSH(ah);
1958 DISABLE_REGWRITE_BUFFER(ah);
1959
1960 REG_RMW_FIELD(ah, AR_RSSI_THR,
1961 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1962
1963 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1964
1965 if (bs->bs_sleepduration > beaconintval)
1966 beaconintval = bs->bs_sleepduration;
1967
1968 dtimperiod = bs->bs_dtimperiod;
1969 if (bs->bs_sleepduration > dtimperiod)
1970 dtimperiod = bs->bs_sleepduration;
1971
1972 if (beaconintval == dtimperiod)
1973 nextTbtt = bs->bs_nextdtim;
1974 else
1975 nextTbtt = bs->bs_nexttbtt;
1976
1977 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1978 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1979 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1980 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1981
1982 ENABLE_REGWRITE_BUFFER(ah);
1983
1984 REG_WRITE(ah, AR_NEXT_DTIM,
1985 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1986 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1987
1988 REG_WRITE(ah, AR_SLEEP1,
1989 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1990 | AR_SLEEP1_ASSUME_DTIM);
1991
1992 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1993 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1994 else
1995 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1996
1997 REG_WRITE(ah, AR_SLEEP2,
1998 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1999
2000 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2001 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2002
2003 REGWRITE_BUFFER_FLUSH(ah);
2004 DISABLE_REGWRITE_BUFFER(ah);
2005
2006 REG_SET_BIT(ah, AR_TIMER_MODE,
2007 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2008 AR_DTIM_TIMER_EN);
2009
2010 /* TSF Out of Range Threshold */
2011 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2012 }
2013 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2014
2015 /*******************/
2016 /* HW Capabilities */
2017 /*******************/
2018
2019 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2020 {
2021 struct ath9k_hw_capabilities *pCap = &ah->caps;
2022 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2023 struct ath_common *common = ath9k_hw_common(ah);
2024 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2025
2026 u16 capField = 0, eeval;
2027
2028 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2029 regulatory->current_rd = eeval;
2030
2031 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2032 if (AR_SREV_9285_10_OR_LATER(ah))
2033 eeval |= AR9285_RDEXT_DEFAULT;
2034 regulatory->current_rd_ext = eeval;
2035
2036 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2037
2038 if (ah->opmode != NL80211_IFTYPE_AP &&
2039 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2040 if (regulatory->current_rd == 0x64 ||
2041 regulatory->current_rd == 0x65)
2042 regulatory->current_rd += 5;
2043 else if (regulatory->current_rd == 0x41)
2044 regulatory->current_rd = 0x43;
2045 ath_print(common, ATH_DBG_REGULATORY,
2046 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2047 }
2048
2049 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2050 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2051 ath_print(common, ATH_DBG_FATAL,
2052 "no band has been marked as supported in EEPROM.\n");
2053 return -EINVAL;
2054 }
2055
2056 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2057
2058 if (eeval & AR5416_OPFLAGS_11A) {
2059 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2060 if (ah->config.ht_enable) {
2061 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2062 set_bit(ATH9K_MODE_11NA_HT20,
2063 pCap->wireless_modes);
2064 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2065 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2066 pCap->wireless_modes);
2067 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2068 pCap->wireless_modes);
2069 }
2070 }
2071 }
2072
2073 if (eeval & AR5416_OPFLAGS_11G) {
2074 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2075 if (ah->config.ht_enable) {
2076 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2077 set_bit(ATH9K_MODE_11NG_HT20,
2078 pCap->wireless_modes);
2079 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2080 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2081 pCap->wireless_modes);
2082 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2083 pCap->wireless_modes);
2084 }
2085 }
2086 }
2087
2088 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2089 /*
2090 * For AR9271 we will temporarilly uses the rx chainmax as read from
2091 * the EEPROM.
2092 */
2093 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2094 !(eeval & AR5416_OPFLAGS_11A) &&
2095 !(AR_SREV_9271(ah)))
2096 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2097 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2098 else
2099 /* Use rx_chainmask from EEPROM. */
2100 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2101
2102 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2103 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2104
2105 pCap->low_2ghz_chan = 2312;
2106 pCap->high_2ghz_chan = 2732;
2107
2108 pCap->low_5ghz_chan = 4920;
2109 pCap->high_5ghz_chan = 6100;
2110
2111 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2112 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2113 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2114
2115 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2116 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2117 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2118
2119 if (ah->config.ht_enable)
2120 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2121 else
2122 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2123
2124 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2125 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2126 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2127 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2128
2129 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2130 pCap->total_queues =
2131 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2132 else
2133 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2134
2135 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2136 pCap->keycache_size =
2137 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2138 else
2139 pCap->keycache_size = AR_KEYTABLE_SIZE;
2140
2141 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2142
2143 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2144 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2145 else
2146 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2147
2148 if (AR_SREV_9271(ah))
2149 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2150 else if (AR_SREV_9285_10_OR_LATER(ah))
2151 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2152 else if (AR_SREV_9280_10_OR_LATER(ah))
2153 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2154 else
2155 pCap->num_gpio_pins = AR_NUM_GPIO;
2156
2157 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2158 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2159 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2160 } else {
2161 pCap->rts_aggr_limit = (8 * 1024);
2162 }
2163
2164 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2165
2166 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2167 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2168 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2169 ah->rfkill_gpio =
2170 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2171 ah->rfkill_polarity =
2172 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2173
2174 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2175 }
2176 #endif
2177 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2178 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2179 else
2180 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2181
2182 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2183 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2184 else
2185 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2186
2187 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2188 pCap->reg_cap =
2189 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2190 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2191 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2192 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2193 } else {
2194 pCap->reg_cap =
2195 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2196 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2197 }
2198
2199 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2200 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2201 AR_SREV_5416(ah))
2202 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2203
2204 pCap->num_antcfg_5ghz =
2205 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2206 pCap->num_antcfg_2ghz =
2207 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2208
2209 if (AR_SREV_9280_10_OR_LATER(ah) &&
2210 ath9k_hw_btcoex_supported(ah)) {
2211 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2212 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2213
2214 if (AR_SREV_9285(ah)) {
2215 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2216 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2217 } else {
2218 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2219 }
2220 } else {
2221 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2222 }
2223
2224 if (AR_SREV_9300_20_OR_LATER(ah)) {
2225 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2226 ATH9K_HW_CAP_FASTCLOCK;
2227 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2228 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2229 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2230 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2231 pCap->txs_len = sizeof(struct ar9003_txs);
2232 } else {
2233 pCap->tx_desc_len = sizeof(struct ath_desc);
2234 if (AR_SREV_9280_20(ah) &&
2235 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2236 AR5416_EEP_MINOR_VER_16) ||
2237 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2238 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2239 }
2240
2241 if (AR_SREV_9300_20_OR_LATER(ah))
2242 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2243
2244 if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
2245 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2246
2247 return 0;
2248 }
2249
2250 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2251 u32 capability, u32 *result)
2252 {
2253 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2254 switch (type) {
2255 case ATH9K_CAP_CIPHER:
2256 switch (capability) {
2257 case ATH9K_CIPHER_AES_CCM:
2258 case ATH9K_CIPHER_AES_OCB:
2259 case ATH9K_CIPHER_TKIP:
2260 case ATH9K_CIPHER_WEP:
2261 case ATH9K_CIPHER_MIC:
2262 case ATH9K_CIPHER_CLR:
2263 return true;
2264 default:
2265 return false;
2266 }
2267 case ATH9K_CAP_TKIP_MIC:
2268 switch (capability) {
2269 case 0:
2270 return true;
2271 case 1:
2272 return (ah->sta_id1_defaults &
2273 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2274 false;
2275 }
2276 case ATH9K_CAP_TKIP_SPLIT:
2277 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2278 false : true;
2279 case ATH9K_CAP_MCAST_KEYSRCH:
2280 switch (capability) {
2281 case 0:
2282 return true;
2283 case 1:
2284 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2285 return false;
2286 } else {
2287 return (ah->sta_id1_defaults &
2288 AR_STA_ID1_MCAST_KSRCH) ? true :
2289 false;
2290 }
2291 }
2292 return false;
2293 case ATH9K_CAP_TXPOW:
2294 switch (capability) {
2295 case 0:
2296 return 0;
2297 case 1:
2298 *result = regulatory->power_limit;
2299 return 0;
2300 case 2:
2301 *result = regulatory->max_power_level;
2302 return 0;
2303 case 3:
2304 *result = regulatory->tp_scale;
2305 return 0;
2306 }
2307 return false;
2308 case ATH9K_CAP_DS:
2309 return (AR_SREV_9280_20_OR_LATER(ah) &&
2310 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2311 ? false : true;
2312 default:
2313 return false;
2314 }
2315 }
2316 EXPORT_SYMBOL(ath9k_hw_getcapability);
2317
2318 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2319 u32 capability, u32 setting, int *status)
2320 {
2321 switch (type) {
2322 case ATH9K_CAP_TKIP_MIC:
2323 if (setting)
2324 ah->sta_id1_defaults |=
2325 AR_STA_ID1_CRPT_MIC_ENABLE;
2326 else
2327 ah->sta_id1_defaults &=
2328 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2329 return true;
2330 case ATH9K_CAP_MCAST_KEYSRCH:
2331 if (setting)
2332 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2333 else
2334 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2335 return true;
2336 default:
2337 return false;
2338 }
2339 }
2340 EXPORT_SYMBOL(ath9k_hw_setcapability);
2341
2342 /****************************/
2343 /* GPIO / RFKILL / Antennae */
2344 /****************************/
2345
2346 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2347 u32 gpio, u32 type)
2348 {
2349 int addr;
2350 u32 gpio_shift, tmp;
2351
2352 if (gpio > 11)
2353 addr = AR_GPIO_OUTPUT_MUX3;
2354 else if (gpio > 5)
2355 addr = AR_GPIO_OUTPUT_MUX2;
2356 else
2357 addr = AR_GPIO_OUTPUT_MUX1;
2358
2359 gpio_shift = (gpio % 6) * 5;
2360
2361 if (AR_SREV_9280_20_OR_LATER(ah)
2362 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2363 REG_RMW(ah, addr, (type << gpio_shift),
2364 (0x1f << gpio_shift));
2365 } else {
2366 tmp = REG_READ(ah, addr);
2367 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2368 tmp &= ~(0x1f << gpio_shift);
2369 tmp |= (type << gpio_shift);
2370 REG_WRITE(ah, addr, tmp);
2371 }
2372 }
2373
2374 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2375 {
2376 u32 gpio_shift;
2377
2378 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2379
2380 gpio_shift = gpio << 1;
2381
2382 REG_RMW(ah,
2383 AR_GPIO_OE_OUT,
2384 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2385 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2386 }
2387 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2388
2389 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2390 {
2391 #define MS_REG_READ(x, y) \
2392 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2393
2394 if (gpio >= ah->caps.num_gpio_pins)
2395 return 0xffffffff;
2396
2397 if (AR_SREV_9300_20_OR_LATER(ah))
2398 return MS_REG_READ(AR9300, gpio) != 0;
2399 else if (AR_SREV_9271(ah))
2400 return MS_REG_READ(AR9271, gpio) != 0;
2401 else if (AR_SREV_9287_10_OR_LATER(ah))
2402 return MS_REG_READ(AR9287, gpio) != 0;
2403 else if (AR_SREV_9285_10_OR_LATER(ah))
2404 return MS_REG_READ(AR9285, gpio) != 0;
2405 else if (AR_SREV_9280_10_OR_LATER(ah))
2406 return MS_REG_READ(AR928X, gpio) != 0;
2407 else
2408 return MS_REG_READ(AR, gpio) != 0;
2409 }
2410 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2411
2412 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2413 u32 ah_signal_type)
2414 {
2415 u32 gpio_shift;
2416
2417 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2418
2419 gpio_shift = 2 * gpio;
2420
2421 REG_RMW(ah,
2422 AR_GPIO_OE_OUT,
2423 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2424 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2425 }
2426 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2427
2428 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2429 {
2430 if (AR_SREV_9271(ah))
2431 val = ~val;
2432
2433 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2434 AR_GPIO_BIT(gpio));
2435 }
2436 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2437
2438 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2439 {
2440 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2441 }
2442 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2443
2444 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2445 {
2446 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2447 }
2448 EXPORT_SYMBOL(ath9k_hw_setantenna);
2449
2450 /*********************/
2451 /* General Operation */
2452 /*********************/
2453
2454 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2455 {
2456 u32 bits = REG_READ(ah, AR_RX_FILTER);
2457 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2458
2459 if (phybits & AR_PHY_ERR_RADAR)
2460 bits |= ATH9K_RX_FILTER_PHYRADAR;
2461 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2462 bits |= ATH9K_RX_FILTER_PHYERR;
2463
2464 return bits;
2465 }
2466 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2467
2468 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2469 {
2470 u32 phybits;
2471
2472 ENABLE_REGWRITE_BUFFER(ah);
2473
2474 REG_WRITE(ah, AR_RX_FILTER, bits);
2475
2476 phybits = 0;
2477 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2478 phybits |= AR_PHY_ERR_RADAR;
2479 if (bits & ATH9K_RX_FILTER_PHYERR)
2480 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2481 REG_WRITE(ah, AR_PHY_ERR, phybits);
2482
2483 if (phybits)
2484 REG_WRITE(ah, AR_RXCFG,
2485 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2486 else
2487 REG_WRITE(ah, AR_RXCFG,
2488 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2489
2490 REGWRITE_BUFFER_FLUSH(ah);
2491 DISABLE_REGWRITE_BUFFER(ah);
2492 }
2493 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2494
2495 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2496 {
2497 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2498 return false;
2499
2500 ath9k_hw_init_pll(ah, NULL);
2501 return true;
2502 }
2503 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2504
2505 bool ath9k_hw_disable(struct ath_hw *ah)
2506 {
2507 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2508 return false;
2509
2510 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2511 return false;
2512
2513 ath9k_hw_init_pll(ah, NULL);
2514 return true;
2515 }
2516 EXPORT_SYMBOL(ath9k_hw_disable);
2517
2518 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2519 {
2520 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2521 struct ath9k_channel *chan = ah->curchan;
2522 struct ieee80211_channel *channel = chan->chan;
2523
2524 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2525
2526 ah->eep_ops->set_txpower(ah, chan,
2527 ath9k_regd_get_ctl(regulatory, chan),
2528 channel->max_antenna_gain * 2,
2529 channel->max_power * 2,
2530 min((u32) MAX_RATE_POWER,
2531 (u32) regulatory->power_limit));
2532 }
2533 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2534
2535 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2536 {
2537 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2538 }
2539 EXPORT_SYMBOL(ath9k_hw_setmac);
2540
2541 void ath9k_hw_setopmode(struct ath_hw *ah)
2542 {
2543 ath9k_hw_set_operating_mode(ah, ah->opmode);
2544 }
2545 EXPORT_SYMBOL(ath9k_hw_setopmode);
2546
2547 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2548 {
2549 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2550 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2551 }
2552 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2553
2554 void ath9k_hw_write_associd(struct ath_hw *ah)
2555 {
2556 struct ath_common *common = ath9k_hw_common(ah);
2557
2558 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2559 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2560 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2561 }
2562 EXPORT_SYMBOL(ath9k_hw_write_associd);
2563
2564 #define ATH9K_MAX_TSF_READ 10
2565
2566 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2567 {
2568 u32 tsf_lower, tsf_upper1, tsf_upper2;
2569 int i;
2570
2571 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2572 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2573 tsf_lower = REG_READ(ah, AR_TSF_L32);
2574 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2575 if (tsf_upper2 == tsf_upper1)
2576 break;
2577 tsf_upper1 = tsf_upper2;
2578 }
2579
2580 WARN_ON( i == ATH9K_MAX_TSF_READ );
2581
2582 return (((u64)tsf_upper1 << 32) | tsf_lower);
2583 }
2584 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2585
2586 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2587 {
2588 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2589 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2590 }
2591 EXPORT_SYMBOL(ath9k_hw_settsf64);
2592
2593 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2594 {
2595 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2596 AH_TSF_WRITE_TIMEOUT))
2597 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2598 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2599
2600 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2601 }
2602 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2603
2604 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2605 {
2606 if (setting)
2607 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2608 else
2609 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2610 }
2611 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2612
2613 /*
2614 * Extend 15-bit time stamp from rx descriptor to
2615 * a full 64-bit TSF using the current h/w TSF.
2616 */
2617 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2618 {
2619 u64 tsf;
2620
2621 tsf = ath9k_hw_gettsf64(ah);
2622 if ((tsf & 0x7fff) < rstamp)
2623 tsf -= 0x8000;
2624 return (tsf & ~0x7fff) | rstamp;
2625 }
2626 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2627
2628 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2629 {
2630 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2631 u32 macmode;
2632
2633 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2634 macmode = AR_2040_JOINED_RX_CLEAR;
2635 else
2636 macmode = 0;
2637
2638 REG_WRITE(ah, AR_2040_MODE, macmode);
2639 }
2640
2641 /* HW Generic timers configuration */
2642
2643 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2644 {
2645 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2646 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2647 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2648 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2649 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2650 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2651 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2652 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2653 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2654 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2655 AR_NDP2_TIMER_MODE, 0x0002},
2656 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2657 AR_NDP2_TIMER_MODE, 0x0004},
2658 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2659 AR_NDP2_TIMER_MODE, 0x0008},
2660 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2661 AR_NDP2_TIMER_MODE, 0x0010},
2662 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2663 AR_NDP2_TIMER_MODE, 0x0020},
2664 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2665 AR_NDP2_TIMER_MODE, 0x0040},
2666 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2667 AR_NDP2_TIMER_MODE, 0x0080}
2668 };
2669
2670 /* HW generic timer primitives */
2671
2672 /* compute and clear index of rightmost 1 */
2673 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2674 {
2675 u32 b;
2676
2677 b = *mask;
2678 b &= (0-b);
2679 *mask &= ~b;
2680 b *= debruijn32;
2681 b >>= 27;
2682
2683 return timer_table->gen_timer_index[b];
2684 }
2685
2686 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2687 {
2688 return REG_READ(ah, AR_TSF_L32);
2689 }
2690 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2691
2692 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2693 void (*trigger)(void *),
2694 void (*overflow)(void *),
2695 void *arg,
2696 u8 timer_index)
2697 {
2698 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2699 struct ath_gen_timer *timer;
2700
2701 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2702
2703 if (timer == NULL) {
2704 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2705 "Failed to allocate memory"
2706 "for hw timer[%d]\n", timer_index);
2707 return NULL;
2708 }
2709
2710 /* allocate a hardware generic timer slot */
2711 timer_table->timers[timer_index] = timer;
2712 timer->index = timer_index;
2713 timer->trigger = trigger;
2714 timer->overflow = overflow;
2715 timer->arg = arg;
2716
2717 return timer;
2718 }
2719 EXPORT_SYMBOL(ath_gen_timer_alloc);
2720
2721 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2722 struct ath_gen_timer *timer,
2723 u32 timer_next,
2724 u32 timer_period)
2725 {
2726 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2727 u32 tsf;
2728
2729 BUG_ON(!timer_period);
2730
2731 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2732
2733 tsf = ath9k_hw_gettsf32(ah);
2734
2735 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2736 "curent tsf %x period %x"
2737 "timer_next %x\n", tsf, timer_period, timer_next);
2738
2739 /*
2740 * Pull timer_next forward if the current TSF already passed it
2741 * because of software latency
2742 */
2743 if (timer_next < tsf)
2744 timer_next = tsf + timer_period;
2745
2746 /*
2747 * Program generic timer registers
2748 */
2749 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2750 timer_next);
2751 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2752 timer_period);
2753 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2754 gen_tmr_configuration[timer->index].mode_mask);
2755
2756 /* Enable both trigger and thresh interrupt masks */
2757 REG_SET_BIT(ah, AR_IMR_S5,
2758 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2759 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2760 }
2761 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2762
2763 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2764 {
2765 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2766
2767 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2768 (timer->index >= ATH_MAX_GEN_TIMER)) {
2769 return;
2770 }
2771
2772 /* Clear generic timer enable bits. */
2773 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2774 gen_tmr_configuration[timer->index].mode_mask);
2775
2776 /* Disable both trigger and thresh interrupt masks */
2777 REG_CLR_BIT(ah, AR_IMR_S5,
2778 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2779 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2780
2781 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2782 }
2783 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2784
2785 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2786 {
2787 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2788
2789 /* free the hardware generic timer slot */
2790 timer_table->timers[timer->index] = NULL;
2791 kfree(timer);
2792 }
2793 EXPORT_SYMBOL(ath_gen_timer_free);
2794
2795 /*
2796 * Generic Timer Interrupts handling
2797 */
2798 void ath_gen_timer_isr(struct ath_hw *ah)
2799 {
2800 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2801 struct ath_gen_timer *timer;
2802 struct ath_common *common = ath9k_hw_common(ah);
2803 u32 trigger_mask, thresh_mask, index;
2804
2805 /* get hardware generic timer interrupt status */
2806 trigger_mask = ah->intr_gen_timer_trigger;
2807 thresh_mask = ah->intr_gen_timer_thresh;
2808 trigger_mask &= timer_table->timer_mask.val;
2809 thresh_mask &= timer_table->timer_mask.val;
2810
2811 trigger_mask &= ~thresh_mask;
2812
2813 while (thresh_mask) {
2814 index = rightmost_index(timer_table, &thresh_mask);
2815 timer = timer_table->timers[index];
2816 BUG_ON(!timer);
2817 ath_print(common, ATH_DBG_HWTIMER,
2818 "TSF overflow for Gen timer %d\n", index);
2819 timer->overflow(timer->arg);
2820 }
2821
2822 while (trigger_mask) {
2823 index = rightmost_index(timer_table, &trigger_mask);
2824 timer = timer_table->timers[index];
2825 BUG_ON(!timer);
2826 ath_print(common, ATH_DBG_HWTIMER,
2827 "Gen timer[%d] trigger\n", index);
2828 timer->trigger(timer->arg);
2829 }
2830 }
2831 EXPORT_SYMBOL(ath_gen_timer_isr);
2832
2833 /********/
2834 /* HTC */
2835 /********/
2836
2837 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2838 {
2839 ah->htc_reset_init = true;
2840 }
2841 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2842
2843 static struct {
2844 u32 version;
2845 const char * name;
2846 } ath_mac_bb_names[] = {
2847 /* Devices with external radios */
2848 { AR_SREV_VERSION_5416_PCI, "5416" },
2849 { AR_SREV_VERSION_5416_PCIE, "5418" },
2850 { AR_SREV_VERSION_9100, "9100" },
2851 { AR_SREV_VERSION_9160, "9160" },
2852 /* Single-chip solutions */
2853 { AR_SREV_VERSION_9280, "9280" },
2854 { AR_SREV_VERSION_9285, "9285" },
2855 { AR_SREV_VERSION_9287, "9287" },
2856 { AR_SREV_VERSION_9271, "9271" },
2857 { AR_SREV_VERSION_9300, "9300" },
2858 };
2859
2860 /* For devices with external radios */
2861 static struct {
2862 u16 version;
2863 const char * name;
2864 } ath_rf_names[] = {
2865 { 0, "5133" },
2866 { AR_RAD5133_SREV_MAJOR, "5133" },
2867 { AR_RAD5122_SREV_MAJOR, "5122" },
2868 { AR_RAD2133_SREV_MAJOR, "2133" },
2869 { AR_RAD2122_SREV_MAJOR, "2122" }
2870 };
2871
2872 /*
2873 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2874 */
2875 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2876 {
2877 int i;
2878
2879 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2880 if (ath_mac_bb_names[i].version == mac_bb_version) {
2881 return ath_mac_bb_names[i].name;
2882 }
2883 }
2884
2885 return "????";
2886 }
2887
2888 /*
2889 * Return the RF name. "????" is returned if the RF is unknown.
2890 * Used for devices with external radios.
2891 */
2892 static const char *ath9k_hw_rf_name(u16 rf_version)
2893 {
2894 int i;
2895
2896 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2897 if (ath_rf_names[i].version == rf_version) {
2898 return ath_rf_names[i].name;
2899 }
2900 }
2901
2902 return "????";
2903 }
2904
2905 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2906 {
2907 int used;
2908
2909 /* chipsets >= AR9280 are single-chip */
2910 if (AR_SREV_9280_10_OR_LATER(ah)) {
2911 used = snprintf(hw_name, len,
2912 "Atheros AR%s Rev:%x",
2913 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2914 ah->hw_version.macRev);
2915 }
2916 else {
2917 used = snprintf(hw_name, len,
2918 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2919 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2920 ah->hw_version.macRev,
2921 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2922 AR_RADIO_SREV_MAJOR)),
2923 ah->hw_version.phyRev);
2924 }
2925
2926 hw_name[used] = '\0';
2927 }
2928 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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