2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
24 #include "ar9003_mac.h"
26 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
33 static int __init
ath9k_init(void)
37 module_init(ath9k_init
);
39 static void __exit
ath9k_exit(void)
43 module_exit(ath9k_exit
);
45 /* Private hardware callbacks */
47 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
49 ath9k_hw_private_ops(ah
)->init_cal_settings(ah
);
52 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
54 ath9k_hw_private_ops(ah
)->init_mode_regs(ah
);
57 static bool ath9k_hw_macversion_supported(struct ath_hw
*ah
)
59 struct ath_hw_private_ops
*priv_ops
= ath9k_hw_private_ops(ah
);
61 return priv_ops
->macversion_supported(ah
->hw_version
.macVersion
);
64 static u32
ath9k_hw_compute_pll_control(struct ath_hw
*ah
,
65 struct ath9k_channel
*chan
)
67 return ath9k_hw_private_ops(ah
)->compute_pll_control(ah
, chan
);
70 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
72 if (!ath9k_hw_private_ops(ah
)->init_mode_gain_regs
)
75 ath9k_hw_private_ops(ah
)->init_mode_gain_regs(ah
);
78 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw
*ah
)
80 /* You will not have this callback if using the old ANI */
81 if (!ath9k_hw_private_ops(ah
)->ani_cache_ini_regs
)
84 ath9k_hw_private_ops(ah
)->ani_cache_ini_regs(ah
);
87 /********************/
88 /* Helper Functions */
89 /********************/
91 static void ath9k_hw_set_clockrate(struct ath_hw
*ah
)
93 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
94 struct ath_common
*common
= ath9k_hw_common(ah
);
95 unsigned int clockrate
;
97 if (!ah
->curchan
) /* should really check for CCK instead */
98 clockrate
= ATH9K_CLOCK_RATE_CCK
;
99 else if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
100 clockrate
= ATH9K_CLOCK_RATE_2GHZ_OFDM
;
101 else if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_FASTCLOCK
)
102 clockrate
= ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM
;
104 clockrate
= ATH9K_CLOCK_RATE_5GHZ_OFDM
;
106 if (conf_is_ht40(conf
))
109 common
->clockrate
= clockrate
;
112 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
114 struct ath_common
*common
= ath9k_hw_common(ah
);
116 return usecs
* common
->clockrate
;
119 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
123 BUG_ON(timeout
< AH_TIME_QUANTUM
);
125 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
126 if ((REG_READ(ah
, reg
) & mask
) == val
)
129 udelay(AH_TIME_QUANTUM
);
132 ath_print(ath9k_hw_common(ah
), ATH_DBG_ANY
,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
138 EXPORT_SYMBOL(ath9k_hw_wait
);
140 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
145 for (i
= 0, retval
= 0; i
< n
; i
++) {
146 retval
= (retval
<< 1) | (val
& 1);
152 bool ath9k_get_channel_edges(struct ath_hw
*ah
,
156 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
158 if (flags
& CHANNEL_5GHZ
) {
159 *low
= pCap
->low_5ghz_chan
;
160 *high
= pCap
->high_5ghz_chan
;
163 if ((flags
& CHANNEL_2GHZ
)) {
164 *low
= pCap
->low_2ghz_chan
;
165 *high
= pCap
->high_2ghz_chan
;
171 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
173 u32 frameLen
, u16 rateix
,
176 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
182 case WLAN_RC_PHY_CCK
:
183 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
186 numBits
= frameLen
<< 3;
187 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
189 case WLAN_RC_PHY_OFDM
:
190 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
191 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
192 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
193 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
194 txTime
= OFDM_SIFS_TIME_QUARTER
195 + OFDM_PREAMBLE_TIME_QUARTER
196 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
197 } else if (ah
->curchan
&&
198 IS_CHAN_HALF_RATE(ah
->curchan
)) {
199 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
200 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
201 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
202 txTime
= OFDM_SIFS_TIME_HALF
+
203 OFDM_PREAMBLE_TIME_HALF
204 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
206 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
207 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
208 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
209 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
210 + (numSymbols
* OFDM_SYMBOL_TIME
);
214 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
215 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
222 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
224 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
225 struct ath9k_channel
*chan
,
226 struct chan_centers
*centers
)
230 if (!IS_CHAN_HT40(chan
)) {
231 centers
->ctl_center
= centers
->ext_center
=
232 centers
->synth_center
= chan
->channel
;
236 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
237 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
238 centers
->synth_center
=
239 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
242 centers
->synth_center
=
243 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
247 centers
->ctl_center
=
248 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
249 /* 25 MHz spacing is supported by hw but not on upper layers */
250 centers
->ext_center
=
251 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
258 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
262 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
265 val
= REG_READ(ah
, AR_SREV
);
266 ah
->hw_version
.macVersion
=
267 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
268 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
269 ah
->is_pciexpress
= (val
& AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
271 if (!AR_SREV_9100(ah
))
272 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
274 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
276 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
277 ah
->is_pciexpress
= true;
281 /************************************/
282 /* HW Attach, Detach, Init Routines */
283 /************************************/
285 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
287 if (AR_SREV_9100(ah
))
290 ENABLE_REGWRITE_BUFFER(ah
);
292 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
293 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
294 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
295 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
296 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
297 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
298 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
299 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
300 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
302 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
304 REGWRITE_BUFFER_FLUSH(ah
);
307 /* This should work for all families including legacy */
308 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
310 struct ath_common
*common
= ath9k_hw_common(ah
);
311 u32 regAddr
[2] = { AR_STA_ID0
};
313 u32 patternData
[4] = { 0x55555555,
319 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
321 regAddr
[1] = AR_PHY_BASE
+ (8 << 2);
325 for (i
= 0; i
< loop_max
; i
++) {
326 u32 addr
= regAddr
[i
];
329 regHold
[i
] = REG_READ(ah
, addr
);
330 for (j
= 0; j
< 0x100; j
++) {
331 wrData
= (j
<< 16) | j
;
332 REG_WRITE(ah
, addr
, wrData
);
333 rdData
= REG_READ(ah
, addr
);
334 if (rdData
!= wrData
) {
335 ath_print(common
, ATH_DBG_FATAL
,
336 "address test failed "
337 "addr: 0x%08x - wr:0x%08x != "
339 addr
, wrData
, rdData
);
343 for (j
= 0; j
< 4; j
++) {
344 wrData
= patternData
[j
];
345 REG_WRITE(ah
, addr
, wrData
);
346 rdData
= REG_READ(ah
, addr
);
347 if (wrData
!= rdData
) {
348 ath_print(common
, ATH_DBG_FATAL
,
349 "address test failed "
350 "addr: 0x%08x - wr:0x%08x != "
352 addr
, wrData
, rdData
);
356 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
363 static void ath9k_hw_init_config(struct ath_hw
*ah
)
367 ah
->config
.dma_beacon_response_time
= 2;
368 ah
->config
.sw_beacon_response_time
= 10;
369 ah
->config
.additional_swba_backoff
= 0;
370 ah
->config
.ack_6mb
= 0x0;
371 ah
->config
.cwm_ignore_extcca
= 0;
372 ah
->config
.pcie_powersave_enable
= 0;
373 ah
->config
.pcie_clock_req
= 0;
374 ah
->config
.pcie_waen
= 0;
375 ah
->config
.analog_shiftreg
= 1;
376 ah
->config
.enable_ani
= true;
378 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
379 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
380 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
383 if (ah
->hw_version
.devid
!= AR2427_DEVID_PCIE
)
384 ah
->config
.ht_enable
= 1;
386 ah
->config
.ht_enable
= 0;
388 ah
->config
.rx_intr_mitigation
= true;
389 ah
->config
.pcieSerDesWrite
= true;
392 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
393 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
394 * This means we use it for all AR5416 devices, and the few
395 * minor PCI AR9280 devices out there.
397 * Serialization is required because these devices do not handle
398 * well the case of two concurrent reads/writes due to the latency
399 * involved. During one read/write another read/write can be issued
400 * on another CPU while the previous read/write may still be working
401 * on our hardware, if we hit this case the hardware poops in a loop.
402 * We prevent this by serializing reads and writes.
404 * This issue is not present on PCI-Express devices or pre-AR5416
405 * devices (legacy, 802.11abg).
407 if (num_possible_cpus() > 1)
408 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
411 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
413 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
415 regulatory
->country_code
= CTRY_DEFAULT
;
416 regulatory
->power_limit
= MAX_RATE_POWER
;
417 regulatory
->tp_scale
= ATH9K_TP_SCALE_MAX
;
419 ah
->hw_version
.magic
= AR5416_MAGIC
;
420 ah
->hw_version
.subvendorid
= 0;
423 if (!AR_SREV_9100(ah
))
424 ah
->ah_flags
= AH_USE_EEPROM
;
427 ah
->sta_id1_defaults
=
428 AR_STA_ID1_CRPT_MIC_ENABLE
|
429 AR_STA_ID1_MCAST_KSRCH
;
430 ah
->beacon_interval
= 100;
431 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
432 ah
->slottime
= (u32
) -1;
433 ah
->globaltxtimeout
= (u32
) -1;
434 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
437 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
439 struct ath_common
*common
= ath9k_hw_common(ah
);
443 u32 EEP_MAC
[] = { EEP_MAC_LSW
, EEP_MAC_MID
, EEP_MAC_MSW
};
446 for (i
= 0; i
< 3; i
++) {
447 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_MAC
[i
]);
449 common
->macaddr
[2 * i
] = eeval
>> 8;
450 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
452 if (sum
== 0 || sum
== 0xffff * 3)
453 return -EADDRNOTAVAIL
;
458 static int ath9k_hw_post_init(struct ath_hw
*ah
)
462 if (!AR_SREV_9271(ah
)) {
463 if (!ath9k_hw_chip_test(ah
))
467 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
468 ecode
= ar9002_hw_rf_claim(ah
);
473 ecode
= ath9k_hw_eeprom_init(ah
);
477 ath_print(ath9k_hw_common(ah
), ATH_DBG_CONFIG
,
478 "Eeprom VER: %d, REV: %d\n",
479 ah
->eep_ops
->get_eeprom_ver(ah
),
480 ah
->eep_ops
->get_eeprom_rev(ah
));
482 ecode
= ath9k_hw_rf_alloc_ext_banks(ah
);
484 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
485 "Failed allocating banks for "
487 ath9k_hw_rf_free_ext_banks(ah
);
491 if (!AR_SREV_9100(ah
)) {
492 ath9k_hw_ani_setup(ah
);
493 ath9k_hw_ani_init(ah
);
499 static void ath9k_hw_attach_ops(struct ath_hw
*ah
)
501 if (AR_SREV_9300_20_OR_LATER(ah
))
502 ar9003_hw_attach_ops(ah
);
504 ar9002_hw_attach_ops(ah
);
507 /* Called for all hardware families */
508 static int __ath9k_hw_init(struct ath_hw
*ah
)
510 struct ath_common
*common
= ath9k_hw_common(ah
);
513 if (ah
->hw_version
.devid
== AR5416_AR9100_DEVID
)
514 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
516 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
517 ath_print(common
, ATH_DBG_FATAL
,
518 "Couldn't reset chip\n");
522 ath9k_hw_init_defaults(ah
);
523 ath9k_hw_init_config(ah
);
525 ath9k_hw_attach_ops(ah
);
527 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
528 ath_print(common
, ATH_DBG_FATAL
, "Couldn't wakeup chip\n");
532 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
533 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
534 ((AR_SREV_9160(ah
) || AR_SREV_9280(ah
)) &&
535 !ah
->is_pciexpress
)) {
536 ah
->config
.serialize_regmode
=
539 ah
->config
.serialize_regmode
=
544 ath_print(common
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
545 ah
->config
.serialize_regmode
);
547 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
548 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
550 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
552 if (!ath9k_hw_macversion_supported(ah
)) {
553 ath_print(common
, ATH_DBG_FATAL
,
554 "Mac Chip Rev 0x%02x.%x is not supported by "
555 "this driver\n", ah
->hw_version
.macVersion
,
556 ah
->hw_version
.macRev
);
560 if (AR_SREV_9271(ah
) || AR_SREV_9100(ah
))
561 ah
->is_pciexpress
= false;
563 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
564 ath9k_hw_init_cal_settings(ah
);
566 ah
->ani_function
= ATH9K_ANI_ALL
;
567 if (AR_SREV_9280_20_OR_LATER(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
568 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
569 if (!AR_SREV_9300_20_OR_LATER(ah
))
570 ah
->ani_function
&= ~ATH9K_ANI_MRC_CCK
;
572 ath9k_hw_init_mode_regs(ah
);
575 * Read back AR_WA into a permanent copy and set bits 14 and 17.
576 * We need to do this to avoid RMW of this register. We cannot
577 * read the reg when chip is asleep.
579 ah
->WARegVal
= REG_READ(ah
, AR_WA
);
580 ah
->WARegVal
|= (AR_WA_D3_L1_DISABLE
|
581 AR_WA_ASPM_TIMER_BASED_DISABLE
);
583 if (ah
->is_pciexpress
)
584 ath9k_hw_configpcipowersave(ah
, 0, 0);
586 ath9k_hw_disablepcie(ah
);
588 if (!AR_SREV_9300_20_OR_LATER(ah
))
589 ar9002_hw_cck_chan14_spread(ah
);
591 r
= ath9k_hw_post_init(ah
);
595 ath9k_hw_init_mode_gain_regs(ah
);
596 r
= ath9k_hw_fill_cap_info(ah
);
600 r
= ath9k_hw_init_macaddr(ah
);
602 ath_print(common
, ATH_DBG_FATAL
,
603 "Failed to initialize MAC address\n");
607 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
608 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
610 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
612 ah
->bb_watchdog_timeout_ms
= 25;
614 common
->state
= ATH_HW_INITIALIZED
;
619 int ath9k_hw_init(struct ath_hw
*ah
)
622 struct ath_common
*common
= ath9k_hw_common(ah
);
624 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
625 switch (ah
->hw_version
.devid
) {
626 case AR5416_DEVID_PCI
:
627 case AR5416_DEVID_PCIE
:
628 case AR5416_AR9100_DEVID
:
629 case AR9160_DEVID_PCI
:
630 case AR9280_DEVID_PCI
:
631 case AR9280_DEVID_PCIE
:
632 case AR9285_DEVID_PCIE
:
633 case AR9287_DEVID_PCI
:
634 case AR9287_DEVID_PCIE
:
635 case AR2427_DEVID_PCIE
:
636 case AR9300_DEVID_PCIE
:
639 if (common
->bus_ops
->ath_bus_type
== ATH_USB
)
641 ath_print(common
, ATH_DBG_FATAL
,
642 "Hardware device ID 0x%04x not supported\n",
643 ah
->hw_version
.devid
);
647 ret
= __ath9k_hw_init(ah
);
649 ath_print(common
, ATH_DBG_FATAL
,
650 "Unable to initialize hardware; "
651 "initialization status: %d\n", ret
);
657 EXPORT_SYMBOL(ath9k_hw_init
);
659 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
661 ENABLE_REGWRITE_BUFFER(ah
);
663 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
664 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
666 REG_WRITE(ah
, AR_QOS_NO_ACK
,
667 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
668 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
669 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
671 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
672 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
673 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
674 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
675 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
677 REGWRITE_BUFFER_FLUSH(ah
);
680 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
681 struct ath9k_channel
*chan
)
683 u32 pll
= ath9k_hw_compute_pll_control(ah
, chan
);
685 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
687 /* Switch the core clock for ar9271 to 117Mhz */
688 if (AR_SREV_9271(ah
)) {
690 REG_WRITE(ah
, 0x50040, 0x304);
693 udelay(RTC_PLL_SETTLE_DELAY
);
695 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
698 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
699 enum nl80211_iftype opmode
)
701 u32 imr_reg
= AR_IMR_TXERR
|
707 if (AR_SREV_9300_20_OR_LATER(ah
)) {
708 imr_reg
|= AR_IMR_RXOK_HP
;
709 if (ah
->config
.rx_intr_mitigation
)
710 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
712 imr_reg
|= AR_IMR_RXOK_LP
;
715 if (ah
->config
.rx_intr_mitigation
)
716 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
718 imr_reg
|= AR_IMR_RXOK
;
721 if (ah
->config
.tx_intr_mitigation
)
722 imr_reg
|= AR_IMR_TXINTM
| AR_IMR_TXMINTR
;
724 imr_reg
|= AR_IMR_TXOK
;
726 if (opmode
== NL80211_IFTYPE_AP
)
727 imr_reg
|= AR_IMR_MIB
;
729 ENABLE_REGWRITE_BUFFER(ah
);
731 REG_WRITE(ah
, AR_IMR
, imr_reg
);
732 ah
->imrs2_reg
|= AR_IMR_S2_GTT
;
733 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
735 if (!AR_SREV_9100(ah
)) {
736 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
737 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, AR_INTR_SYNC_DEFAULT
);
738 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
741 REGWRITE_BUFFER_FLUSH(ah
);
743 if (AR_SREV_9300_20_OR_LATER(ah
)) {
744 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_ENABLE
, 0);
745 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_MASK
, 0);
746 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_ENABLE
, 0);
747 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_MASK
, 0);
751 static void ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
753 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
754 val
= min(val
, (u32
) 0xFFFF);
755 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, val
);
758 static void ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
760 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
761 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_ACK
));
762 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK
, val
);
765 static void ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
767 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
768 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_CTS
));
769 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_CTS
, val
);
772 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
775 ath_print(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
776 "bad global tx timeout %u\n", tu
);
777 ah
->globaltxtimeout
= (u32
) -1;
780 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
781 ah
->globaltxtimeout
= tu
;
786 void ath9k_hw_init_global_settings(struct ath_hw
*ah
)
788 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
793 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
796 if (ah
->misc_mode
!= 0)
797 REG_WRITE(ah
, AR_PCU_MISC
,
798 REG_READ(ah
, AR_PCU_MISC
) | ah
->misc_mode
);
800 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_5GHZ
)
805 /* As defined by IEEE 802.11-2007 17.3.8.6 */
806 slottime
= ah
->slottime
+ 3 * ah
->coverage_class
;
807 acktimeout
= slottime
+ sifstime
;
810 * Workaround for early ACK timeouts, add an offset to match the
811 * initval's 64us ack timeout value.
812 * This was initially only meant to work around an issue with delayed
813 * BA frames in some implementations, but it has been found to fix ACK
814 * timeout issues in other cases as well.
816 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
817 acktimeout
+= 64 - sifstime
- ah
->slottime
;
819 ath9k_hw_setslottime(ah
, slottime
);
820 ath9k_hw_set_ack_timeout(ah
, acktimeout
);
821 ath9k_hw_set_cts_timeout(ah
, acktimeout
);
822 if (ah
->globaltxtimeout
!= (u32
) -1)
823 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
825 EXPORT_SYMBOL(ath9k_hw_init_global_settings
);
827 void ath9k_hw_deinit(struct ath_hw
*ah
)
829 struct ath_common
*common
= ath9k_hw_common(ah
);
831 if (common
->state
< ATH_HW_INITIALIZED
)
834 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
837 ath9k_hw_rf_free_ext_banks(ah
);
839 EXPORT_SYMBOL(ath9k_hw_deinit
);
845 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
)
847 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
851 else if (IS_CHAN_G(chan
))
859 /****************************************/
860 /* Reset and Channel Switching Routines */
861 /****************************************/
863 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
865 struct ath_common
*common
= ath9k_hw_common(ah
);
868 ENABLE_REGWRITE_BUFFER(ah
);
871 * set AHB_MODE not to do cacheline prefetches
873 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
874 regval
= REG_READ(ah
, AR_AHB_MODE
);
875 REG_WRITE(ah
, AR_AHB_MODE
, regval
| AR_AHB_PREFETCH_RD_EN
);
879 * let mac dma reads be in 128 byte chunks
881 regval
= REG_READ(ah
, AR_TXCFG
) & ~AR_TXCFG_DMASZ_MASK
;
882 REG_WRITE(ah
, AR_TXCFG
, regval
| AR_TXCFG_DMASZ_128B
);
884 REGWRITE_BUFFER_FLUSH(ah
);
887 * Restore TX Trigger Level to its pre-reset value.
888 * The initial value depends on whether aggregation is enabled, and is
889 * adjusted whenever underruns are detected.
891 if (!AR_SREV_9300_20_OR_LATER(ah
))
892 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
894 ENABLE_REGWRITE_BUFFER(ah
);
897 * let mac dma writes be in 128 byte chunks
899 regval
= REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_DMASZ_MASK
;
900 REG_WRITE(ah
, AR_RXCFG
, regval
| AR_RXCFG_DMASZ_128B
);
903 * Setup receive FIFO threshold to hold off TX activities
905 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
907 if (AR_SREV_9300_20_OR_LATER(ah
)) {
908 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_HP
, 0x1);
909 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_LP
, 0x1);
911 ath9k_hw_set_rx_bufsize(ah
, common
->rx_bufsize
-
912 ah
->caps
.rx_status_len
);
916 * reduce the number of usable entries in PCU TXBUF to avoid
917 * wrap around issues.
919 if (AR_SREV_9285(ah
)) {
920 /* For AR9285 the number of Fifos are reduced to half.
921 * So set the usable tx buf size also to half to
922 * avoid data/delimiter underruns
924 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
925 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
926 } else if (!AR_SREV_9271(ah
)) {
927 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
928 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
931 REGWRITE_BUFFER_FLUSH(ah
);
933 if (AR_SREV_9300_20_OR_LATER(ah
))
934 ath9k_hw_reset_txstatus_ring(ah
);
937 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
941 val
= REG_READ(ah
, AR_STA_ID1
);
942 val
&= ~(AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
);
944 case NL80211_IFTYPE_AP
:
945 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_STA_AP
946 | AR_STA_ID1_KSRCH_MODE
);
947 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
949 case NL80211_IFTYPE_ADHOC
:
950 case NL80211_IFTYPE_MESH_POINT
:
951 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_ADHOC
952 | AR_STA_ID1_KSRCH_MODE
);
953 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
955 case NL80211_IFTYPE_STATION
:
956 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
959 if (ah
->is_monitoring
)
960 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
965 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
966 u32
*coef_mantissa
, u32
*coef_exponent
)
968 u32 coef_exp
, coef_man
;
970 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
971 if ((coef_scaled
>> coef_exp
) & 0x1)
974 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
976 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
978 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
979 *coef_exponent
= coef_exp
- 16;
982 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
987 if (AR_SREV_9100(ah
)) {
988 u32 val
= REG_READ(ah
, AR_RTC_DERIVED_CLK
);
989 val
&= ~AR_RTC_DERIVED_CLK_PERIOD
;
990 val
|= SM(1, AR_RTC_DERIVED_CLK_PERIOD
);
991 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, val
);
992 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
995 ENABLE_REGWRITE_BUFFER(ah
);
997 if (AR_SREV_9300_20_OR_LATER(ah
)) {
998 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1002 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1003 AR_RTC_FORCE_WAKE_ON_INT
);
1005 if (AR_SREV_9100(ah
)) {
1006 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1007 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1009 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1011 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1012 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1014 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1017 if (!AR_SREV_9300_20_OR_LATER(ah
))
1019 REG_WRITE(ah
, AR_RC
, val
);
1021 } else if (!AR_SREV_9300_20_OR_LATER(ah
))
1022 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1024 rst_flags
= AR_RTC_RC_MAC_WARM
;
1025 if (type
== ATH9K_RESET_COLD
)
1026 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1029 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1031 REGWRITE_BUFFER_FLUSH(ah
);
1035 REG_WRITE(ah
, AR_RTC_RC
, 0);
1036 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1037 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1038 "RTC stuck in MAC reset\n");
1042 if (!AR_SREV_9100(ah
))
1043 REG_WRITE(ah
, AR_RC
, 0);
1045 if (AR_SREV_9100(ah
))
1051 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1053 ENABLE_REGWRITE_BUFFER(ah
);
1055 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1056 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1060 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1061 AR_RTC_FORCE_WAKE_ON_INT
);
1063 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1064 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1066 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1069 REGWRITE_BUFFER_FLUSH(ah
);
1071 if (!AR_SREV_9300_20_OR_LATER(ah
))
1074 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1075 REG_WRITE(ah
, AR_RC
, 0);
1077 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1079 if (!ath9k_hw_wait(ah
,
1084 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1085 "RTC not waking up\n");
1089 ath9k_hw_read_revisions(ah
);
1091 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1094 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1096 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1097 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1101 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1102 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1105 case ATH9K_RESET_POWER_ON
:
1106 return ath9k_hw_set_reset_power_on(ah
);
1107 case ATH9K_RESET_WARM
:
1108 case ATH9K_RESET_COLD
:
1109 return ath9k_hw_set_reset(ah
, type
);
1115 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1116 struct ath9k_channel
*chan
)
1118 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
1119 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1121 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1124 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1127 ah
->chip_fullsleep
= false;
1128 ath9k_hw_init_pll(ah
, chan
);
1129 ath9k_hw_set_rfmode(ah
, chan
);
1134 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1135 struct ath9k_channel
*chan
)
1137 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1138 struct ath_common
*common
= ath9k_hw_common(ah
);
1139 struct ieee80211_channel
*channel
= chan
->chan
;
1143 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1144 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1145 ath_print(common
, ATH_DBG_QUEUE
,
1146 "Transmit frames pending on "
1147 "queue %d\n", qnum
);
1152 if (!ath9k_hw_rfbus_req(ah
)) {
1153 ath_print(common
, ATH_DBG_FATAL
,
1154 "Could not kill baseband RX\n");
1158 ath9k_hw_set_channel_regs(ah
, chan
);
1160 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1162 ath_print(common
, ATH_DBG_FATAL
,
1163 "Failed to set channel\n");
1166 ath9k_hw_set_clockrate(ah
);
1168 ah
->eep_ops
->set_txpower(ah
, chan
,
1169 ath9k_regd_get_ctl(regulatory
, chan
),
1170 channel
->max_antenna_gain
* 2,
1171 channel
->max_power
* 2,
1172 min((u32
) MAX_RATE_POWER
,
1173 (u32
) regulatory
->power_limit
));
1175 ath9k_hw_rfbus_done(ah
);
1177 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1178 ath9k_hw_set_delta_slope(ah
, chan
);
1180 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1185 bool ath9k_hw_check_alive(struct ath_hw
*ah
)
1190 if (AR_SREV_9285_12_OR_LATER(ah
))
1194 reg
= REG_READ(ah
, AR_OBS_BUS_1
);
1196 if ((reg
& 0x7E7FFFEF) == 0x00702400)
1199 switch (reg
& 0x7E000B00) {
1207 } while (count
-- > 0);
1211 EXPORT_SYMBOL(ath9k_hw_check_alive
);
1213 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1214 struct ath9k_hw_cal_data
*caldata
, bool bChannelChange
)
1216 struct ath_common
*common
= ath9k_hw_common(ah
);
1218 struct ath9k_channel
*curchan
= ah
->curchan
;
1224 ah
->txchainmask
= common
->tx_chainmask
;
1225 ah
->rxchainmask
= common
->rx_chainmask
;
1227 if (!ah
->chip_fullsleep
) {
1228 ath9k_hw_abortpcurecv(ah
);
1229 if (!ath9k_hw_stopdmarecv(ah
)) {
1230 ath_print(common
, ATH_DBG_XMIT
,
1231 "Failed to stop receive dma\n");
1232 bChannelChange
= false;
1236 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1239 if (curchan
&& !ah
->chip_fullsleep
)
1240 ath9k_hw_getnf(ah
, curchan
);
1242 ah
->caldata
= caldata
;
1244 (chan
->channel
!= caldata
->channel
||
1245 (chan
->channelFlags
& ~CHANNEL_CW_INT
) !=
1246 (caldata
->channelFlags
& ~CHANNEL_CW_INT
))) {
1247 /* Operating channel changed, reset channel calibration data */
1248 memset(caldata
, 0, sizeof(*caldata
));
1249 ath9k_init_nfcal_hist_buffer(ah
, chan
);
1252 if (bChannelChange
&&
1253 (ah
->chip_fullsleep
!= true) &&
1254 (ah
->curchan
!= NULL
) &&
1255 (chan
->channel
!= ah
->curchan
->channel
) &&
1256 ((chan
->channelFlags
& CHANNEL_ALL
) ==
1257 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)) &&
1258 (!AR_SREV_9280(ah
) || AR_DEVID_7010(ah
))) {
1260 if (ath9k_hw_channel_change(ah
, chan
)) {
1261 ath9k_hw_loadnf(ah
, ah
->curchan
);
1262 ath9k_hw_start_nfcal(ah
, true);
1263 if (AR_SREV_9271(ah
))
1264 ar9002_hw_load_ani_reg(ah
, chan
);
1269 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1270 if (saveDefAntenna
== 0)
1273 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1275 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1276 if (AR_SREV_9100(ah
) ||
1277 (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)))
1278 tsf
= ath9k_hw_gettsf64(ah
);
1280 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1281 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1282 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1284 ath9k_hw_mark_phy_inactive(ah
);
1286 /* Only required on the first reset */
1287 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1289 AR9271_RESET_POWER_DOWN_CONTROL
,
1290 AR9271_RADIO_RF_RST
);
1294 if (!ath9k_hw_chip_reset(ah
, chan
)) {
1295 ath_print(common
, ATH_DBG_FATAL
, "Chip reset failed\n");
1299 /* Only required on the first reset */
1300 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1301 ah
->htc_reset_init
= false;
1303 AR9271_RESET_POWER_DOWN_CONTROL
,
1304 AR9271_GATE_MAC_CTL
);
1310 ath9k_hw_settsf64(ah
, tsf
);
1312 if (AR_SREV_9280_20_OR_LATER(ah
))
1313 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
1315 if (!AR_SREV_9300_20_OR_LATER(ah
))
1316 ar9002_hw_enable_async_fifo(ah
);
1318 r
= ath9k_hw_process_ini(ah
, chan
);
1323 * Some AR91xx SoC devices frequently fail to accept TSF writes
1324 * right after the chip reset. When that happens, write a new
1325 * value after the initvals have been applied, with an offset
1326 * based on measured time difference
1328 if (AR_SREV_9100(ah
) && (ath9k_hw_gettsf64(ah
) < tsf
)) {
1330 ath9k_hw_settsf64(ah
, tsf
);
1333 /* Setup MFP options for CCMP */
1334 if (AR_SREV_9280_20_OR_LATER(ah
)) {
1335 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1336 * frames when constructing CCMP AAD. */
1337 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
1339 ah
->sw_mgmt_crypto
= false;
1340 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1341 /* Disable hardware crypto for management frames */
1342 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
1343 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
1344 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1345 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
1346 ah
->sw_mgmt_crypto
= true;
1348 ah
->sw_mgmt_crypto
= true;
1350 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1351 ath9k_hw_set_delta_slope(ah
, chan
);
1353 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1354 ah
->eep_ops
->set_board_values(ah
, chan
);
1356 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
1358 ENABLE_REGWRITE_BUFFER(ah
);
1360 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(common
->macaddr
));
1361 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(common
->macaddr
+ 4)
1363 | AR_STA_ID1_RTS_USE_DEF
1365 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
1366 | ah
->sta_id1_defaults
);
1367 ath_hw_setbssidmask(common
);
1368 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
1369 ath9k_hw_write_associd(ah
);
1370 REG_WRITE(ah
, AR_ISR
, ~0);
1371 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
1373 REGWRITE_BUFFER_FLUSH(ah
);
1375 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1379 ath9k_hw_set_clockrate(ah
);
1381 ENABLE_REGWRITE_BUFFER(ah
);
1383 for (i
= 0; i
< AR_NUM_DCU
; i
++)
1384 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
1386 REGWRITE_BUFFER_FLUSH(ah
);
1389 for (i
= 0; i
< ah
->caps
.total_queues
; i
++)
1390 ath9k_hw_resettxqueue(ah
, i
);
1392 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
1393 ath9k_hw_ani_cache_ini_regs(ah
);
1394 ath9k_hw_init_qos(ah
);
1396 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1397 ath9k_enable_rfkill(ah
);
1399 ath9k_hw_init_global_settings(ah
);
1401 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
1402 ar9002_hw_update_async_fifo(ah
);
1403 ar9002_hw_enable_wep_aggregation(ah
);
1406 REG_WRITE(ah
, AR_STA_ID1
,
1407 REG_READ(ah
, AR_STA_ID1
) | AR_STA_ID1_PRESERVE_SEQNUM
);
1409 ath9k_hw_set_dma(ah
);
1411 REG_WRITE(ah
, AR_OBS
, 8);
1413 if (ah
->config
.rx_intr_mitigation
) {
1414 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
1415 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
1418 if (ah
->config
.tx_intr_mitigation
) {
1419 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_LAST
, 300);
1420 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_FIRST
, 750);
1423 ath9k_hw_init_bb(ah
, chan
);
1425 if (!ath9k_hw_init_cal(ah
, chan
))
1428 ENABLE_REGWRITE_BUFFER(ah
);
1430 ath9k_hw_restore_chainmask(ah
);
1431 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
1433 REGWRITE_BUFFER_FLUSH(ah
);
1436 * For big endian systems turn on swapping for descriptors
1438 if (AR_SREV_9100(ah
)) {
1440 mask
= REG_READ(ah
, AR_CFG
);
1441 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
1442 ath_print(common
, ATH_DBG_RESET
,
1443 "CFG Byte Swap Set 0x%x\n", mask
);
1446 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
1447 REG_WRITE(ah
, AR_CFG
, mask
);
1448 ath_print(common
, ATH_DBG_RESET
,
1449 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
1452 if (common
->bus_ops
->ath_bus_type
== ATH_USB
) {
1453 /* Configure AR9271 target WLAN */
1454 if (AR_SREV_9271(ah
))
1455 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
1457 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1461 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1465 if (ah
->btcoex_hw
.enabled
)
1466 ath9k_hw_btcoex_enable(ah
);
1468 if (AR_SREV_9300_20_OR_LATER(ah
))
1469 ar9003_hw_bb_watchdog_config(ah
);
1473 EXPORT_SYMBOL(ath9k_hw_reset
);
1475 /******************************/
1476 /* Power Management (Chipset) */
1477 /******************************/
1480 * Notify Power Mgt is disabled in self-generated frames.
1481 * If requested, force chip to sleep.
1483 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
1485 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1488 * Clear the RTC force wake bit to allow the
1489 * mac to go to sleep.
1491 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
1492 AR_RTC_FORCE_WAKE_EN
);
1493 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1494 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1496 /* Shutdown chip. Active low */
1497 if (!AR_SREV_5416(ah
) && !AR_SREV_9271(ah
))
1498 REG_CLR_BIT(ah
, (AR_RTC_RESET
),
1502 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1503 if (AR_SREV_9300_20_OR_LATER(ah
))
1504 REG_WRITE(ah
, AR_WA
,
1505 ah
->WARegVal
& ~AR_WA_D3_L1_DISABLE
);
1509 * Notify Power Management is enabled in self-generating
1510 * frames. If request, set power mode of chip to
1511 * auto/normal. Duration in units of 128us (1/8 TU).
1513 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
1515 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1517 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1519 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
1520 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1521 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1522 AR_RTC_FORCE_WAKE_ON_INT
);
1525 * Clear the RTC force wake bit to allow the
1526 * mac to go to sleep.
1528 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
1529 AR_RTC_FORCE_WAKE_EN
);
1533 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1534 if (AR_SREV_9300_20_OR_LATER(ah
))
1535 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
& ~AR_WA_D3_L1_DISABLE
);
1538 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
1543 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1544 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1545 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1550 if ((REG_READ(ah
, AR_RTC_STATUS
) &
1551 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
1552 if (ath9k_hw_set_reset_reg(ah
,
1553 ATH9K_RESET_POWER_ON
) != true) {
1556 if (!AR_SREV_9300_20_OR_LATER(ah
))
1557 ath9k_hw_init_pll(ah
, NULL
);
1559 if (AR_SREV_9100(ah
))
1560 REG_SET_BIT(ah
, AR_RTC_RESET
,
1563 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
1564 AR_RTC_FORCE_WAKE_EN
);
1567 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
1568 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
1569 if (val
== AR_RTC_STATUS_ON
)
1572 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
1573 AR_RTC_FORCE_WAKE_EN
);
1576 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1577 "Failed to wakeup in %uus\n",
1578 POWER_UP_TIME
/ 20);
1583 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1588 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
1590 struct ath_common
*common
= ath9k_hw_common(ah
);
1591 int status
= true, setChip
= true;
1592 static const char *modes
[] = {
1599 if (ah
->power_mode
== mode
)
1602 ath_print(common
, ATH_DBG_RESET
, "%s -> %s\n",
1603 modes
[ah
->power_mode
], modes
[mode
]);
1606 case ATH9K_PM_AWAKE
:
1607 status
= ath9k_hw_set_power_awake(ah
, setChip
);
1609 case ATH9K_PM_FULL_SLEEP
:
1610 ath9k_set_power_sleep(ah
, setChip
);
1611 ah
->chip_fullsleep
= true;
1613 case ATH9K_PM_NETWORK_SLEEP
:
1614 ath9k_set_power_network_sleep(ah
, setChip
);
1617 ath_print(common
, ATH_DBG_FATAL
,
1618 "Unknown power mode %u\n", mode
);
1621 ah
->power_mode
= mode
;
1625 EXPORT_SYMBOL(ath9k_hw_setpower
);
1627 /*******************/
1628 /* Beacon Handling */
1629 /*******************/
1631 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
1635 ah
->beacon_interval
= beacon_period
;
1637 ENABLE_REGWRITE_BUFFER(ah
);
1639 switch (ah
->opmode
) {
1640 case NL80211_IFTYPE_STATION
:
1641 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
1642 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
1643 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
1644 flags
|= AR_TBTT_TIMER_EN
;
1646 case NL80211_IFTYPE_ADHOC
:
1647 case NL80211_IFTYPE_MESH_POINT
:
1648 REG_SET_BIT(ah
, AR_TXCFG
,
1649 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
1650 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
,
1651 TU_TO_USEC(next_beacon
+
1652 (ah
->atim_window
? ah
->
1654 flags
|= AR_NDP_TIMER_EN
;
1655 case NL80211_IFTYPE_AP
:
1656 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
1657 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
,
1658 TU_TO_USEC(next_beacon
-
1660 dma_beacon_response_time
));
1661 REG_WRITE(ah
, AR_NEXT_SWBA
,
1662 TU_TO_USEC(next_beacon
-
1664 sw_beacon_response_time
));
1666 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
1669 if (ah
->is_monitoring
) {
1670 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
,
1671 TU_TO_USEC(next_beacon
));
1672 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
1673 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
1674 flags
|= AR_TBTT_TIMER_EN
;
1677 ath_print(ath9k_hw_common(ah
), ATH_DBG_BEACON
,
1678 "%s: unsupported opmode: %d\n",
1679 __func__
, ah
->opmode
);
1684 REG_WRITE(ah
, AR_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
1685 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
1686 REG_WRITE(ah
, AR_SWBA_PERIOD
, TU_TO_USEC(beacon_period
));
1687 REG_WRITE(ah
, AR_NDP_PERIOD
, TU_TO_USEC(beacon_period
));
1689 REGWRITE_BUFFER_FLUSH(ah
);
1691 beacon_period
&= ~ATH9K_BEACON_ENA
;
1692 if (beacon_period
& ATH9K_BEACON_RESET_TSF
) {
1693 ath9k_hw_reset_tsf(ah
);
1696 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
1698 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
1700 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
1701 const struct ath9k_beacon_state
*bs
)
1703 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
1704 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1705 struct ath_common
*common
= ath9k_hw_common(ah
);
1707 ENABLE_REGWRITE_BUFFER(ah
);
1709 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
1711 REG_WRITE(ah
, AR_BEACON_PERIOD
,
1712 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
1713 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
1714 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
1716 REGWRITE_BUFFER_FLUSH(ah
);
1718 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
1719 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
1721 beaconintval
= bs
->bs_intval
& ATH9K_BEACON_PERIOD
;
1723 if (bs
->bs_sleepduration
> beaconintval
)
1724 beaconintval
= bs
->bs_sleepduration
;
1726 dtimperiod
= bs
->bs_dtimperiod
;
1727 if (bs
->bs_sleepduration
> dtimperiod
)
1728 dtimperiod
= bs
->bs_sleepduration
;
1730 if (beaconintval
== dtimperiod
)
1731 nextTbtt
= bs
->bs_nextdtim
;
1733 nextTbtt
= bs
->bs_nexttbtt
;
1735 ath_print(common
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
1736 ath_print(common
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
1737 ath_print(common
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
1738 ath_print(common
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
1740 ENABLE_REGWRITE_BUFFER(ah
);
1742 REG_WRITE(ah
, AR_NEXT_DTIM
,
1743 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
1744 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
1746 REG_WRITE(ah
, AR_SLEEP1
,
1747 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
1748 | AR_SLEEP1_ASSUME_DTIM
);
1750 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
1751 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
1753 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
1755 REG_WRITE(ah
, AR_SLEEP2
,
1756 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
1758 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
1759 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
1761 REGWRITE_BUFFER_FLUSH(ah
);
1763 REG_SET_BIT(ah
, AR_TIMER_MODE
,
1764 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
1767 /* TSF Out of Range Threshold */
1768 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
1770 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
1772 /*******************/
1773 /* HW Capabilities */
1774 /*******************/
1776 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
1778 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1779 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1780 struct ath_common
*common
= ath9k_hw_common(ah
);
1781 struct ath_btcoex_hw
*btcoex_hw
= &ah
->btcoex_hw
;
1783 u16 capField
= 0, eeval
;
1786 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
1787 regulatory
->current_rd
= eeval
;
1789 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_1
);
1790 if (AR_SREV_9285_12_OR_LATER(ah
))
1791 eeval
|= AR9285_RDEXT_DEFAULT
;
1792 regulatory
->current_rd_ext
= eeval
;
1794 capField
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_CAP
);
1796 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
1797 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
1798 if (regulatory
->current_rd
== 0x64 ||
1799 regulatory
->current_rd
== 0x65)
1800 regulatory
->current_rd
+= 5;
1801 else if (regulatory
->current_rd
== 0x41)
1802 regulatory
->current_rd
= 0x43;
1803 ath_print(common
, ATH_DBG_REGULATORY
,
1804 "regdomain mapped to 0x%x\n", regulatory
->current_rd
);
1807 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
1808 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
1809 ath_print(common
, ATH_DBG_FATAL
,
1810 "no band has been marked as supported in EEPROM.\n");
1814 if (eeval
& AR5416_OPFLAGS_11A
)
1815 pCap
->hw_caps
|= ATH9K_HW_CAP_5GHZ
;
1817 if (eeval
& AR5416_OPFLAGS_11G
)
1818 pCap
->hw_caps
|= ATH9K_HW_CAP_2GHZ
;
1820 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
1822 * For AR9271 we will temporarilly uses the rx chainmax as read from
1825 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
1826 !(eeval
& AR5416_OPFLAGS_11A
) &&
1827 !(AR_SREV_9271(ah
)))
1828 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1829 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
1831 /* Use rx_chainmask from EEPROM. */
1832 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
1834 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
1836 pCap
->low_2ghz_chan
= 2312;
1837 pCap
->high_2ghz_chan
= 2732;
1839 pCap
->low_5ghz_chan
= 4920;
1840 pCap
->high_5ghz_chan
= 6100;
1842 common
->crypt_caps
|= ATH_CRYPT_CAP_CIPHER_AESCCM
;
1844 if (ah
->config
.ht_enable
)
1845 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
1847 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
1849 if (capField
& AR_EEPROM_EEPCAP_MAXQCU
)
1850 pCap
->total_queues
=
1851 MS(capField
, AR_EEPROM_EEPCAP_MAXQCU
);
1853 pCap
->total_queues
= ATH9K_NUM_TX_QUEUES
;
1855 if (capField
& AR_EEPROM_EEPCAP_KC_ENTRIES
)
1856 pCap
->keycache_size
=
1857 1 << MS(capField
, AR_EEPROM_EEPCAP_KC_ENTRIES
);
1859 pCap
->keycache_size
= AR_KEYTABLE_SIZE
;
1861 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
1862 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
>> 1;
1864 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
;
1866 if (AR_SREV_9271(ah
))
1867 pCap
->num_gpio_pins
= AR9271_NUM_GPIO
;
1868 else if (AR_DEVID_7010(ah
))
1869 pCap
->num_gpio_pins
= AR7010_NUM_GPIO
;
1870 else if (AR_SREV_9285_12_OR_LATER(ah
))
1871 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
1872 else if (AR_SREV_9280_20_OR_LATER(ah
))
1873 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
1875 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
1877 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
1878 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
1879 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
1881 pCap
->rts_aggr_limit
= (8 * 1024);
1884 pCap
->hw_caps
|= ATH9K_HW_CAP_ENHANCEDPM
;
1886 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1887 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
1888 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
1890 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
1891 ah
->rfkill_polarity
=
1892 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
1894 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
1897 if (AR_SREV_9271(ah
) || AR_SREV_9300_20_OR_LATER(ah
))
1898 pCap
->hw_caps
|= ATH9K_HW_CAP_AUTOSLEEP
;
1900 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
1902 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
1903 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
1905 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
1907 if (regulatory
->current_rd_ext
& (1 << REG_EXT_JAPAN_MIDBAND
)) {
1909 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
1910 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
|
1911 AR_EEPROM_EEREGCAP_EN_KK_U2
|
1912 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
;
1915 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
1916 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
;
1919 /* Advertise midband for AR5416 with FCC midband set in eeprom */
1920 if (regulatory
->current_rd_ext
& (1 << REG_EXT_FCC_MIDBAND
) &&
1922 pCap
->reg_cap
|= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
;
1924 pCap
->num_antcfg_5ghz
=
1925 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_5GHZ
);
1926 pCap
->num_antcfg_2ghz
=
1927 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_2GHZ
);
1929 if (AR_SREV_9280_20_OR_LATER(ah
) &&
1930 ath9k_hw_btcoex_supported(ah
)) {
1931 btcoex_hw
->btactive_gpio
= ATH_BTACTIVE_GPIO
;
1932 btcoex_hw
->wlanactive_gpio
= ATH_WLANACTIVE_GPIO
;
1934 if (AR_SREV_9285(ah
)) {
1935 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_3WIRE
;
1936 btcoex_hw
->btpriority_gpio
= ATH_BTPRIORITY_GPIO
;
1938 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_2WIRE
;
1941 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_NONE
;
1944 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1945 pCap
->hw_caps
|= ATH9K_HW_CAP_EDMA
| ATH9K_HW_CAP_LDPC
|
1946 ATH9K_HW_CAP_FASTCLOCK
;
1947 pCap
->rx_hp_qdepth
= ATH9K_HW_RX_HP_QDEPTH
;
1948 pCap
->rx_lp_qdepth
= ATH9K_HW_RX_LP_QDEPTH
;
1949 pCap
->rx_status_len
= sizeof(struct ar9003_rxs
);
1950 pCap
->tx_desc_len
= sizeof(struct ar9003_txc
);
1951 pCap
->txs_len
= sizeof(struct ar9003_txs
);
1952 if (ah
->eep_ops
->get_eeprom(ah
, EEP_PAPRD
))
1953 pCap
->hw_caps
|= ATH9K_HW_CAP_PAPRD
;
1955 pCap
->tx_desc_len
= sizeof(struct ath_desc
);
1956 if (AR_SREV_9280_20(ah
) &&
1957 ((ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) <=
1958 AR5416_EEP_MINOR_VER_16
) ||
1959 ah
->eep_ops
->get_eeprom(ah
, EEP_FSTCLK_5G
)))
1960 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCLOCK
;
1963 if (AR_SREV_9300_20_OR_LATER(ah
))
1964 pCap
->hw_caps
|= ATH9K_HW_CAP_RAC_SUPPORTED
;
1966 if (AR_SREV_9287_11_OR_LATER(ah
) || AR_SREV_9271(ah
))
1967 pCap
->hw_caps
|= ATH9K_HW_CAP_SGI_20
;
1969 if (AR_SREV_9285(ah
))
1970 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MODAL_VER
) >= 3) {
1972 ah
->eep_ops
->get_eeprom(ah
, EEP_ANT_DIV_CTL1
);
1973 if ((ant_div_ctl1
& 0x1) && ((ant_div_ctl1
>> 3) & 0x1))
1974 pCap
->hw_caps
|= ATH9K_HW_CAP_ANT_DIV_COMB
;
1980 /****************************/
1981 /* GPIO / RFKILL / Antennae */
1982 /****************************/
1984 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
1988 u32 gpio_shift
, tmp
;
1991 addr
= AR_GPIO_OUTPUT_MUX3
;
1993 addr
= AR_GPIO_OUTPUT_MUX2
;
1995 addr
= AR_GPIO_OUTPUT_MUX1
;
1997 gpio_shift
= (gpio
% 6) * 5;
1999 if (AR_SREV_9280_20_OR_LATER(ah
)
2000 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
2001 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
2002 (0x1f << gpio_shift
));
2004 tmp
= REG_READ(ah
, addr
);
2005 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
2006 tmp
&= ~(0x1f << gpio_shift
);
2007 tmp
|= (type
<< gpio_shift
);
2008 REG_WRITE(ah
, addr
, tmp
);
2012 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
2016 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
2018 if (AR_DEVID_7010(ah
)) {
2020 REG_RMW(ah
, AR7010_GPIO_OE
,
2021 (AR7010_GPIO_OE_AS_INPUT
<< gpio_shift
),
2022 (AR7010_GPIO_OE_MASK
<< gpio_shift
));
2026 gpio_shift
= gpio
<< 1;
2029 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
2030 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2032 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
2034 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
2036 #define MS_REG_READ(x, y) \
2037 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2039 if (gpio
>= ah
->caps
.num_gpio_pins
)
2042 if (AR_DEVID_7010(ah
)) {
2044 val
= REG_READ(ah
, AR7010_GPIO_IN
);
2045 return (MS(val
, AR7010_GPIO_IN_VAL
) & AR_GPIO_BIT(gpio
)) == 0;
2046 } else if (AR_SREV_9300_20_OR_LATER(ah
))
2047 return MS_REG_READ(AR9300
, gpio
) != 0;
2048 else if (AR_SREV_9271(ah
))
2049 return MS_REG_READ(AR9271
, gpio
) != 0;
2050 else if (AR_SREV_9287_11_OR_LATER(ah
))
2051 return MS_REG_READ(AR9287
, gpio
) != 0;
2052 else if (AR_SREV_9285_12_OR_LATER(ah
))
2053 return MS_REG_READ(AR9285
, gpio
) != 0;
2054 else if (AR_SREV_9280_20_OR_LATER(ah
))
2055 return MS_REG_READ(AR928X
, gpio
) != 0;
2057 return MS_REG_READ(AR
, gpio
) != 0;
2059 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
2061 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
2066 if (AR_DEVID_7010(ah
)) {
2068 REG_RMW(ah
, AR7010_GPIO_OE
,
2069 (AR7010_GPIO_OE_AS_OUTPUT
<< gpio_shift
),
2070 (AR7010_GPIO_OE_MASK
<< gpio_shift
));
2074 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
2075 gpio_shift
= 2 * gpio
;
2078 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
2079 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2081 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
2083 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
2085 if (AR_DEVID_7010(ah
)) {
2087 REG_RMW(ah
, AR7010_GPIO_OUT
, ((val
&1) << gpio
),
2092 if (AR_SREV_9271(ah
))
2095 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
2098 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
2100 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
2102 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
2104 EXPORT_SYMBOL(ath9k_hw_getdefantenna
);
2106 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
2108 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
2110 EXPORT_SYMBOL(ath9k_hw_setantenna
);
2112 /*********************/
2113 /* General Operation */
2114 /*********************/
2116 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
2118 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
2119 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
2121 if (phybits
& AR_PHY_ERR_RADAR
)
2122 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
2123 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
2124 bits
|= ATH9K_RX_FILTER_PHYERR
;
2128 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
2130 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
2134 ENABLE_REGWRITE_BUFFER(ah
);
2136 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
2139 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
2140 phybits
|= AR_PHY_ERR_RADAR
;
2141 if (bits
& ATH9K_RX_FILTER_PHYERR
)
2142 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
2143 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
2146 REG_WRITE(ah
, AR_RXCFG
,
2147 REG_READ(ah
, AR_RXCFG
) | AR_RXCFG_ZLFDMA
);
2149 REG_WRITE(ah
, AR_RXCFG
,
2150 REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_ZLFDMA
);
2152 REGWRITE_BUFFER_FLUSH(ah
);
2154 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
2156 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
2158 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
2161 ath9k_hw_init_pll(ah
, NULL
);
2164 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
2166 bool ath9k_hw_disable(struct ath_hw
*ah
)
2168 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
2171 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
2174 ath9k_hw_init_pll(ah
, NULL
);
2177 EXPORT_SYMBOL(ath9k_hw_disable
);
2179 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
)
2181 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2182 struct ath9k_channel
*chan
= ah
->curchan
;
2183 struct ieee80211_channel
*channel
= chan
->chan
;
2185 regulatory
->power_limit
= min(limit
, (u32
) MAX_RATE_POWER
);
2187 ah
->eep_ops
->set_txpower(ah
, chan
,
2188 ath9k_regd_get_ctl(regulatory
, chan
),
2189 channel
->max_antenna_gain
* 2,
2190 channel
->max_power
* 2,
2191 min((u32
) MAX_RATE_POWER
,
2192 (u32
) regulatory
->power_limit
));
2194 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
2196 void ath9k_hw_setopmode(struct ath_hw
*ah
)
2198 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2200 EXPORT_SYMBOL(ath9k_hw_setopmode
);
2202 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
2204 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
2205 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
2207 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
2209 void ath9k_hw_write_associd(struct ath_hw
*ah
)
2211 struct ath_common
*common
= ath9k_hw_common(ah
);
2213 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
2214 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
2215 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
2217 EXPORT_SYMBOL(ath9k_hw_write_associd
);
2219 #define ATH9K_MAX_TSF_READ 10
2221 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
2223 u32 tsf_lower
, tsf_upper1
, tsf_upper2
;
2226 tsf_upper1
= REG_READ(ah
, AR_TSF_U32
);
2227 for (i
= 0; i
< ATH9K_MAX_TSF_READ
; i
++) {
2228 tsf_lower
= REG_READ(ah
, AR_TSF_L32
);
2229 tsf_upper2
= REG_READ(ah
, AR_TSF_U32
);
2230 if (tsf_upper2
== tsf_upper1
)
2232 tsf_upper1
= tsf_upper2
;
2235 WARN_ON( i
== ATH9K_MAX_TSF_READ
);
2237 return (((u64
)tsf_upper1
<< 32) | tsf_lower
);
2239 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
2241 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
2243 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
2244 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
2246 EXPORT_SYMBOL(ath9k_hw_settsf64
);
2248 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
2250 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
2251 AH_TSF_WRITE_TIMEOUT
))
2252 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
2253 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2255 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
2257 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
2259 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
2262 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
2264 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
2266 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
2268 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
)
2270 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
2273 if (conf_is_ht40(conf
) && !ah
->config
.cwm_ignore_extcca
)
2274 macmode
= AR_2040_JOINED_RX_CLEAR
;
2278 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
2281 /* HW Generic timers configuration */
2283 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
2285 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2286 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2287 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2288 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2289 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2290 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2291 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2292 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2293 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
2294 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
2295 AR_NDP2_TIMER_MODE
, 0x0002},
2296 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
2297 AR_NDP2_TIMER_MODE
, 0x0004},
2298 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
2299 AR_NDP2_TIMER_MODE
, 0x0008},
2300 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
2301 AR_NDP2_TIMER_MODE
, 0x0010},
2302 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
2303 AR_NDP2_TIMER_MODE
, 0x0020},
2304 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
2305 AR_NDP2_TIMER_MODE
, 0x0040},
2306 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
2307 AR_NDP2_TIMER_MODE
, 0x0080}
2310 /* HW generic timer primitives */
2312 /* compute and clear index of rightmost 1 */
2313 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
2323 return timer_table
->gen_timer_index
[b
];
2326 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
2328 return REG_READ(ah
, AR_TSF_L32
);
2330 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
2332 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
2333 void (*trigger
)(void *),
2334 void (*overflow
)(void *),
2338 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2339 struct ath_gen_timer
*timer
;
2341 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
2343 if (timer
== NULL
) {
2344 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2345 "Failed to allocate memory"
2346 "for hw timer[%d]\n", timer_index
);
2350 /* allocate a hardware generic timer slot */
2351 timer_table
->timers
[timer_index
] = timer
;
2352 timer
->index
= timer_index
;
2353 timer
->trigger
= trigger
;
2354 timer
->overflow
= overflow
;
2359 EXPORT_SYMBOL(ath_gen_timer_alloc
);
2361 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
2362 struct ath_gen_timer
*timer
,
2366 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2369 BUG_ON(!timer_period
);
2371 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
2373 tsf
= ath9k_hw_gettsf32(ah
);
2375 ath_print(ath9k_hw_common(ah
), ATH_DBG_HWTIMER
,
2376 "curent tsf %x period %x"
2377 "timer_next %x\n", tsf
, timer_period
, timer_next
);
2380 * Pull timer_next forward if the current TSF already passed it
2381 * because of software latency
2383 if (timer_next
< tsf
)
2384 timer_next
= tsf
+ timer_period
;
2387 * Program generic timer registers
2389 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
2391 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
2393 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2394 gen_tmr_configuration
[timer
->index
].mode_mask
);
2396 /* Enable both trigger and thresh interrupt masks */
2397 REG_SET_BIT(ah
, AR_IMR_S5
,
2398 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
2399 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
2401 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
2403 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
2405 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2407 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
2408 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
2412 /* Clear generic timer enable bits. */
2413 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2414 gen_tmr_configuration
[timer
->index
].mode_mask
);
2416 /* Disable both trigger and thresh interrupt masks */
2417 REG_CLR_BIT(ah
, AR_IMR_S5
,
2418 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
2419 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
2421 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
2423 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
2425 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
2427 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2429 /* free the hardware generic timer slot */
2430 timer_table
->timers
[timer
->index
] = NULL
;
2433 EXPORT_SYMBOL(ath_gen_timer_free
);
2436 * Generic Timer Interrupts handling
2438 void ath_gen_timer_isr(struct ath_hw
*ah
)
2440 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2441 struct ath_gen_timer
*timer
;
2442 struct ath_common
*common
= ath9k_hw_common(ah
);
2443 u32 trigger_mask
, thresh_mask
, index
;
2445 /* get hardware generic timer interrupt status */
2446 trigger_mask
= ah
->intr_gen_timer_trigger
;
2447 thresh_mask
= ah
->intr_gen_timer_thresh
;
2448 trigger_mask
&= timer_table
->timer_mask
.val
;
2449 thresh_mask
&= timer_table
->timer_mask
.val
;
2451 trigger_mask
&= ~thresh_mask
;
2453 while (thresh_mask
) {
2454 index
= rightmost_index(timer_table
, &thresh_mask
);
2455 timer
= timer_table
->timers
[index
];
2457 ath_print(common
, ATH_DBG_HWTIMER
,
2458 "TSF overflow for Gen timer %d\n", index
);
2459 timer
->overflow(timer
->arg
);
2462 while (trigger_mask
) {
2463 index
= rightmost_index(timer_table
, &trigger_mask
);
2464 timer
= timer_table
->timers
[index
];
2466 ath_print(common
, ATH_DBG_HWTIMER
,
2467 "Gen timer[%d] trigger\n", index
);
2468 timer
->trigger(timer
->arg
);
2471 EXPORT_SYMBOL(ath_gen_timer_isr
);
2477 void ath9k_hw_htc_resetinit(struct ath_hw
*ah
)
2479 ah
->htc_reset_init
= true;
2481 EXPORT_SYMBOL(ath9k_hw_htc_resetinit
);
2486 } ath_mac_bb_names
[] = {
2487 /* Devices with external radios */
2488 { AR_SREV_VERSION_5416_PCI
, "5416" },
2489 { AR_SREV_VERSION_5416_PCIE
, "5418" },
2490 { AR_SREV_VERSION_9100
, "9100" },
2491 { AR_SREV_VERSION_9160
, "9160" },
2492 /* Single-chip solutions */
2493 { AR_SREV_VERSION_9280
, "9280" },
2494 { AR_SREV_VERSION_9285
, "9285" },
2495 { AR_SREV_VERSION_9287
, "9287" },
2496 { AR_SREV_VERSION_9271
, "9271" },
2497 { AR_SREV_VERSION_9300
, "9300" },
2500 /* For devices with external radios */
2504 } ath_rf_names
[] = {
2506 { AR_RAD5133_SREV_MAJOR
, "5133" },
2507 { AR_RAD5122_SREV_MAJOR
, "5122" },
2508 { AR_RAD2133_SREV_MAJOR
, "2133" },
2509 { AR_RAD2122_SREV_MAJOR
, "2122" }
2513 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2515 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
2519 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
2520 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
2521 return ath_mac_bb_names
[i
].name
;
2529 * Return the RF name. "????" is returned if the RF is unknown.
2530 * Used for devices with external radios.
2532 static const char *ath9k_hw_rf_name(u16 rf_version
)
2536 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
2537 if (ath_rf_names
[i
].version
== rf_version
) {
2538 return ath_rf_names
[i
].name
;
2545 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
2549 /* chipsets >= AR9280 are single-chip */
2550 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2551 used
= snprintf(hw_name
, len
,
2552 "Atheros AR%s Rev:%x",
2553 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
2554 ah
->hw_version
.macRev
);
2557 used
= snprintf(hw_name
, len
,
2558 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2559 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
2560 ah
->hw_version
.macRev
,
2561 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
&
2562 AR_RADIO_SREV_MAJOR
)),
2563 ah
->hw_version
.phyRev
);
2566 hw_name
[used
] = '\0';
2568 EXPORT_SYMBOL(ath9k_hw_name
);