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ath9k: Reintroduce modparam to enable btcoex
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
58 {
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
60
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
62 }
63
64 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan)
66 {
67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
68 }
69
70 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
71 {
72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
73 return;
74
75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
76 }
77
78 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
79 {
80 /* You will not have this callback if using the old ANI */
81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
82 return;
83
84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
85 }
86
87 /********************/
88 /* Helper Functions */
89 /********************/
90
91 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
92 {
93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
94 struct ath_common *common = ath9k_hw_common(ah);
95 unsigned int clockrate;
96
97 if (!ah->curchan) /* should really check for CCK instead */
98 clockrate = ATH9K_CLOCK_RATE_CCK;
99 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
100 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
101 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
102 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
103 else
104 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
105
106 if (conf_is_ht40(conf))
107 clockrate *= 2;
108
109 common->clockrate = clockrate;
110 }
111
112 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
113 {
114 struct ath_common *common = ath9k_hw_common(ah);
115
116 return usecs * common->clockrate;
117 }
118
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
120 {
121 int i;
122
123 BUG_ON(timeout < AH_TIME_QUANTUM);
124
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126 if ((REG_READ(ah, reg) & mask) == val)
127 return true;
128
129 udelay(AH_TIME_QUANTUM);
130 }
131
132 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
135
136 return false;
137 }
138 EXPORT_SYMBOL(ath9k_hw_wait);
139
140 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
141 {
142 u32 retval;
143 int i;
144
145 for (i = 0, retval = 0; i < n; i++) {
146 retval = (retval << 1) | (val & 1);
147 val >>= 1;
148 }
149 return retval;
150 }
151
152 bool ath9k_get_channel_edges(struct ath_hw *ah,
153 u16 flags, u16 *low,
154 u16 *high)
155 {
156 struct ath9k_hw_capabilities *pCap = &ah->caps;
157
158 if (flags & CHANNEL_5GHZ) {
159 *low = pCap->low_5ghz_chan;
160 *high = pCap->high_5ghz_chan;
161 return true;
162 }
163 if ((flags & CHANNEL_2GHZ)) {
164 *low = pCap->low_2ghz_chan;
165 *high = pCap->high_2ghz_chan;
166 return true;
167 }
168 return false;
169 }
170
171 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
172 u8 phy, int kbps,
173 u32 frameLen, u16 rateix,
174 bool shortPreamble)
175 {
176 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
177
178 if (kbps == 0)
179 return 0;
180
181 switch (phy) {
182 case WLAN_RC_PHY_CCK:
183 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
184 if (shortPreamble)
185 phyTime >>= 1;
186 numBits = frameLen << 3;
187 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
188 break;
189 case WLAN_RC_PHY_OFDM:
190 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
192 numBits = OFDM_PLCP_BITS + (frameLen << 3);
193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
194 txTime = OFDM_SIFS_TIME_QUARTER
195 + OFDM_PREAMBLE_TIME_QUARTER
196 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
197 } else if (ah->curchan &&
198 IS_CHAN_HALF_RATE(ah->curchan)) {
199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME_HALF +
203 OFDM_PREAMBLE_TIME_HALF
204 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
205 } else {
206 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
207 numBits = OFDM_PLCP_BITS + (frameLen << 3);
208 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
209 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
210 + (numSymbols * OFDM_SYMBOL_TIME);
211 }
212 break;
213 default:
214 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
215 "Unknown phy %u (rate ix %u)\n", phy, rateix);
216 txTime = 0;
217 break;
218 }
219
220 return txTime;
221 }
222 EXPORT_SYMBOL(ath9k_hw_computetxtime);
223
224 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
225 struct ath9k_channel *chan,
226 struct chan_centers *centers)
227 {
228 int8_t extoff;
229
230 if (!IS_CHAN_HT40(chan)) {
231 centers->ctl_center = centers->ext_center =
232 centers->synth_center = chan->channel;
233 return;
234 }
235
236 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
237 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
238 centers->synth_center =
239 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
240 extoff = 1;
241 } else {
242 centers->synth_center =
243 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
244 extoff = -1;
245 }
246
247 centers->ctl_center =
248 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
249 /* 25 MHz spacing is supported by hw but not on upper layers */
250 centers->ext_center =
251 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
252 }
253
254 /******************/
255 /* Chip Revisions */
256 /******************/
257
258 static void ath9k_hw_read_revisions(struct ath_hw *ah)
259 {
260 u32 val;
261
262 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
263
264 if (val == 0xFF) {
265 val = REG_READ(ah, AR_SREV);
266 ah->hw_version.macVersion =
267 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
269 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
270 } else {
271 if (!AR_SREV_9100(ah))
272 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
273
274 ah->hw_version.macRev = val & AR_SREV_REVISION;
275
276 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
277 ah->is_pciexpress = true;
278 }
279 }
280
281 /************************************/
282 /* HW Attach, Detach, Init Routines */
283 /************************************/
284
285 static void ath9k_hw_disablepcie(struct ath_hw *ah)
286 {
287 if (AR_SREV_9100(ah))
288 return;
289
290 ENABLE_REGWRITE_BUFFER(ah);
291
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
300 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
301
302 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
303
304 REGWRITE_BUFFER_FLUSH(ah);
305 }
306
307 /* This should work for all families including legacy */
308 static bool ath9k_hw_chip_test(struct ath_hw *ah)
309 {
310 struct ath_common *common = ath9k_hw_common(ah);
311 u32 regAddr[2] = { AR_STA_ID0 };
312 u32 regHold[2];
313 static const u32 patternData[4] = {
314 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
315 };
316 int i, j, loop_max;
317
318 if (!AR_SREV_9300_20_OR_LATER(ah)) {
319 loop_max = 2;
320 regAddr[1] = AR_PHY_BASE + (8 << 2);
321 } else
322 loop_max = 1;
323
324 for (i = 0; i < loop_max; i++) {
325 u32 addr = regAddr[i];
326 u32 wrData, rdData;
327
328 regHold[i] = REG_READ(ah, addr);
329 for (j = 0; j < 0x100; j++) {
330 wrData = (j << 16) | j;
331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr);
333 if (rdData != wrData) {
334 ath_print(common, ATH_DBG_FATAL,
335 "address test failed "
336 "addr: 0x%08x - wr:0x%08x != "
337 "rd:0x%08x\n",
338 addr, wrData, rdData);
339 return false;
340 }
341 }
342 for (j = 0; j < 4; j++) {
343 wrData = patternData[j];
344 REG_WRITE(ah, addr, wrData);
345 rdData = REG_READ(ah, addr);
346 if (wrData != rdData) {
347 ath_print(common, ATH_DBG_FATAL,
348 "address test failed "
349 "addr: 0x%08x - wr:0x%08x != "
350 "rd:0x%08x\n",
351 addr, wrData, rdData);
352 return false;
353 }
354 }
355 REG_WRITE(ah, regAddr[i], regHold[i]);
356 }
357 udelay(100);
358
359 return true;
360 }
361
362 static void ath9k_hw_init_config(struct ath_hw *ah)
363 {
364 int i;
365
366 ah->config.dma_beacon_response_time = 2;
367 ah->config.sw_beacon_response_time = 10;
368 ah->config.additional_swba_backoff = 0;
369 ah->config.ack_6mb = 0x0;
370 ah->config.cwm_ignore_extcca = 0;
371 ah->config.pcie_powersave_enable = 0;
372 ah->config.pcie_clock_req = 0;
373 ah->config.pcie_waen = 0;
374 ah->config.analog_shiftreg = 1;
375 ah->config.enable_ani = true;
376
377 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
378 ah->config.spurchans[i][0] = AR_NO_SPUR;
379 ah->config.spurchans[i][1] = AR_NO_SPUR;
380 }
381
382 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
383 ah->config.ht_enable = 1;
384 else
385 ah->config.ht_enable = 0;
386
387 ah->config.rx_intr_mitigation = true;
388 ah->config.pcieSerDesWrite = true;
389
390 /*
391 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
392 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
393 * This means we use it for all AR5416 devices, and the few
394 * minor PCI AR9280 devices out there.
395 *
396 * Serialization is required because these devices do not handle
397 * well the case of two concurrent reads/writes due to the latency
398 * involved. During one read/write another read/write can be issued
399 * on another CPU while the previous read/write may still be working
400 * on our hardware, if we hit this case the hardware poops in a loop.
401 * We prevent this by serializing reads and writes.
402 *
403 * This issue is not present on PCI-Express devices or pre-AR5416
404 * devices (legacy, 802.11abg).
405 */
406 if (num_possible_cpus() > 1)
407 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
408 }
409
410 static void ath9k_hw_init_defaults(struct ath_hw *ah)
411 {
412 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
413
414 regulatory->country_code = CTRY_DEFAULT;
415 regulatory->power_limit = MAX_RATE_POWER;
416 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
417
418 ah->hw_version.magic = AR5416_MAGIC;
419 ah->hw_version.subvendorid = 0;
420
421 ah->atim_window = 0;
422 ah->sta_id1_defaults =
423 AR_STA_ID1_CRPT_MIC_ENABLE |
424 AR_STA_ID1_MCAST_KSRCH;
425 ah->beacon_interval = 100;
426 ah->enable_32kHz_clock = DONT_USE_32KHZ;
427 ah->slottime = (u32) -1;
428 ah->globaltxtimeout = (u32) -1;
429 ah->power_mode = ATH9K_PM_UNDEFINED;
430 }
431
432 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
433 {
434 struct ath_common *common = ath9k_hw_common(ah);
435 u32 sum;
436 int i;
437 u16 eeval;
438 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
439
440 sum = 0;
441 for (i = 0; i < 3; i++) {
442 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
443 sum += eeval;
444 common->macaddr[2 * i] = eeval >> 8;
445 common->macaddr[2 * i + 1] = eeval & 0xff;
446 }
447 if (sum == 0 || sum == 0xffff * 3)
448 return -EADDRNOTAVAIL;
449
450 return 0;
451 }
452
453 static int ath9k_hw_post_init(struct ath_hw *ah)
454 {
455 int ecode;
456
457 if (!AR_SREV_9271(ah)) {
458 if (!ath9k_hw_chip_test(ah))
459 return -ENODEV;
460 }
461
462 if (!AR_SREV_9300_20_OR_LATER(ah)) {
463 ecode = ar9002_hw_rf_claim(ah);
464 if (ecode != 0)
465 return ecode;
466 }
467
468 ecode = ath9k_hw_eeprom_init(ah);
469 if (ecode != 0)
470 return ecode;
471
472 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
473 "Eeprom VER: %d, REV: %d\n",
474 ah->eep_ops->get_eeprom_ver(ah),
475 ah->eep_ops->get_eeprom_rev(ah));
476
477 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
478 if (ecode) {
479 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
480 "Failed allocating banks for "
481 "external radio\n");
482 ath9k_hw_rf_free_ext_banks(ah);
483 return ecode;
484 }
485
486 if (!AR_SREV_9100(ah)) {
487 ath9k_hw_ani_setup(ah);
488 ath9k_hw_ani_init(ah);
489 }
490
491 return 0;
492 }
493
494 static void ath9k_hw_attach_ops(struct ath_hw *ah)
495 {
496 if (AR_SREV_9300_20_OR_LATER(ah))
497 ar9003_hw_attach_ops(ah);
498 else
499 ar9002_hw_attach_ops(ah);
500 }
501
502 /* Called for all hardware families */
503 static int __ath9k_hw_init(struct ath_hw *ah)
504 {
505 struct ath_common *common = ath9k_hw_common(ah);
506 int r = 0;
507
508 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
509 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
510
511 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
512 ath_print(common, ATH_DBG_FATAL,
513 "Couldn't reset chip\n");
514 return -EIO;
515 }
516
517 ath9k_hw_init_defaults(ah);
518 ath9k_hw_init_config(ah);
519
520 ath9k_hw_attach_ops(ah);
521
522 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
523 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
524 return -EIO;
525 }
526
527 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
528 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
529 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
530 !ah->is_pciexpress)) {
531 ah->config.serialize_regmode =
532 SER_REG_MODE_ON;
533 } else {
534 ah->config.serialize_regmode =
535 SER_REG_MODE_OFF;
536 }
537 }
538
539 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
540 ah->config.serialize_regmode);
541
542 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
543 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
544 else
545 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
546
547 if (!ath9k_hw_macversion_supported(ah)) {
548 ath_print(common, ATH_DBG_FATAL,
549 "Mac Chip Rev 0x%02x.%x is not supported by "
550 "this driver\n", ah->hw_version.macVersion,
551 ah->hw_version.macRev);
552 return -EOPNOTSUPP;
553 }
554
555 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
556 ah->is_pciexpress = false;
557
558 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
559 ath9k_hw_init_cal_settings(ah);
560
561 ah->ani_function = ATH9K_ANI_ALL;
562 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
563 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
564 if (!AR_SREV_9300_20_OR_LATER(ah))
565 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
566
567 ath9k_hw_init_mode_regs(ah);
568
569 /*
570 * Read back AR_WA into a permanent copy and set bits 14 and 17.
571 * We need to do this to avoid RMW of this register. We cannot
572 * read the reg when chip is asleep.
573 */
574 ah->WARegVal = REG_READ(ah, AR_WA);
575 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
576 AR_WA_ASPM_TIMER_BASED_DISABLE);
577
578 if (ah->is_pciexpress)
579 ath9k_hw_configpcipowersave(ah, 0, 0);
580 else
581 ath9k_hw_disablepcie(ah);
582
583 if (!AR_SREV_9300_20_OR_LATER(ah))
584 ar9002_hw_cck_chan14_spread(ah);
585
586 r = ath9k_hw_post_init(ah);
587 if (r)
588 return r;
589
590 ath9k_hw_init_mode_gain_regs(ah);
591 r = ath9k_hw_fill_cap_info(ah);
592 if (r)
593 return r;
594
595 r = ath9k_hw_init_macaddr(ah);
596 if (r) {
597 ath_print(common, ATH_DBG_FATAL,
598 "Failed to initialize MAC address\n");
599 return r;
600 }
601
602 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
603 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
604 else
605 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
606
607 ah->bb_watchdog_timeout_ms = 25;
608
609 common->state = ATH_HW_INITIALIZED;
610
611 return 0;
612 }
613
614 int ath9k_hw_init(struct ath_hw *ah)
615 {
616 int ret;
617 struct ath_common *common = ath9k_hw_common(ah);
618
619 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
620 switch (ah->hw_version.devid) {
621 case AR5416_DEVID_PCI:
622 case AR5416_DEVID_PCIE:
623 case AR5416_AR9100_DEVID:
624 case AR9160_DEVID_PCI:
625 case AR9280_DEVID_PCI:
626 case AR9280_DEVID_PCIE:
627 case AR9285_DEVID_PCIE:
628 case AR9287_DEVID_PCI:
629 case AR9287_DEVID_PCIE:
630 case AR2427_DEVID_PCIE:
631 case AR9300_DEVID_PCIE:
632 break;
633 default:
634 if (common->bus_ops->ath_bus_type == ATH_USB)
635 break;
636 ath_print(common, ATH_DBG_FATAL,
637 "Hardware device ID 0x%04x not supported\n",
638 ah->hw_version.devid);
639 return -EOPNOTSUPP;
640 }
641
642 ret = __ath9k_hw_init(ah);
643 if (ret) {
644 ath_print(common, ATH_DBG_FATAL,
645 "Unable to initialize hardware; "
646 "initialization status: %d\n", ret);
647 return ret;
648 }
649
650 return 0;
651 }
652 EXPORT_SYMBOL(ath9k_hw_init);
653
654 static void ath9k_hw_init_qos(struct ath_hw *ah)
655 {
656 ENABLE_REGWRITE_BUFFER(ah);
657
658 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
659 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
660
661 REG_WRITE(ah, AR_QOS_NO_ACK,
662 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
663 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
664 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
665
666 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
667 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
668 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
670 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
671
672 REGWRITE_BUFFER_FLUSH(ah);
673 }
674
675 static void ath9k_hw_init_pll(struct ath_hw *ah,
676 struct ath9k_channel *chan)
677 {
678 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
679
680 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
681
682 /* Switch the core clock for ar9271 to 117Mhz */
683 if (AR_SREV_9271(ah)) {
684 udelay(500);
685 REG_WRITE(ah, 0x50040, 0x304);
686 }
687
688 udelay(RTC_PLL_SETTLE_DELAY);
689
690 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
691 }
692
693 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
694 enum nl80211_iftype opmode)
695 {
696 u32 imr_reg = AR_IMR_TXERR |
697 AR_IMR_TXURN |
698 AR_IMR_RXERR |
699 AR_IMR_RXORN |
700 AR_IMR_BCNMISC;
701
702 if (AR_SREV_9300_20_OR_LATER(ah)) {
703 imr_reg |= AR_IMR_RXOK_HP;
704 if (ah->config.rx_intr_mitigation)
705 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
706 else
707 imr_reg |= AR_IMR_RXOK_LP;
708
709 } else {
710 if (ah->config.rx_intr_mitigation)
711 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
712 else
713 imr_reg |= AR_IMR_RXOK;
714 }
715
716 if (ah->config.tx_intr_mitigation)
717 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
718 else
719 imr_reg |= AR_IMR_TXOK;
720
721 if (opmode == NL80211_IFTYPE_AP)
722 imr_reg |= AR_IMR_MIB;
723
724 ENABLE_REGWRITE_BUFFER(ah);
725
726 REG_WRITE(ah, AR_IMR, imr_reg);
727 ah->imrs2_reg |= AR_IMR_S2_GTT;
728 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
729
730 if (!AR_SREV_9100(ah)) {
731 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
732 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
733 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
734 }
735
736 REGWRITE_BUFFER_FLUSH(ah);
737
738 if (AR_SREV_9300_20_OR_LATER(ah)) {
739 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
740 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
741 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
742 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
743 }
744 }
745
746 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
747 {
748 u32 val = ath9k_hw_mac_to_clks(ah, us);
749 val = min(val, (u32) 0xFFFF);
750 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
751 }
752
753 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
754 {
755 u32 val = ath9k_hw_mac_to_clks(ah, us);
756 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
757 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
758 }
759
760 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
761 {
762 u32 val = ath9k_hw_mac_to_clks(ah, us);
763 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
764 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
765 }
766
767 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
768 {
769 if (tu > 0xFFFF) {
770 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
771 "bad global tx timeout %u\n", tu);
772 ah->globaltxtimeout = (u32) -1;
773 return false;
774 } else {
775 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
776 ah->globaltxtimeout = tu;
777 return true;
778 }
779 }
780
781 void ath9k_hw_init_global_settings(struct ath_hw *ah)
782 {
783 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
784 int acktimeout;
785 int slottime;
786 int sifstime;
787
788 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
789 ah->misc_mode);
790
791 if (ah->misc_mode != 0)
792 REG_WRITE(ah, AR_PCU_MISC,
793 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
794
795 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
796 sifstime = 16;
797 else
798 sifstime = 10;
799
800 /* As defined by IEEE 802.11-2007 17.3.8.6 */
801 slottime = ah->slottime + 3 * ah->coverage_class;
802 acktimeout = slottime + sifstime;
803
804 /*
805 * Workaround for early ACK timeouts, add an offset to match the
806 * initval's 64us ack timeout value.
807 * This was initially only meant to work around an issue with delayed
808 * BA frames in some implementations, but it has been found to fix ACK
809 * timeout issues in other cases as well.
810 */
811 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
812 acktimeout += 64 - sifstime - ah->slottime;
813
814 ath9k_hw_setslottime(ah, slottime);
815 ath9k_hw_set_ack_timeout(ah, acktimeout);
816 ath9k_hw_set_cts_timeout(ah, acktimeout);
817 if (ah->globaltxtimeout != (u32) -1)
818 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
819 }
820 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
821
822 void ath9k_hw_deinit(struct ath_hw *ah)
823 {
824 struct ath_common *common = ath9k_hw_common(ah);
825
826 if (common->state < ATH_HW_INITIALIZED)
827 goto free_hw;
828
829 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
830
831 free_hw:
832 ath9k_hw_rf_free_ext_banks(ah);
833 }
834 EXPORT_SYMBOL(ath9k_hw_deinit);
835
836 /*******/
837 /* INI */
838 /*******/
839
840 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
841 {
842 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
843
844 if (IS_CHAN_B(chan))
845 ctl |= CTL_11B;
846 else if (IS_CHAN_G(chan))
847 ctl |= CTL_11G;
848 else
849 ctl |= CTL_11A;
850
851 return ctl;
852 }
853
854 /****************************************/
855 /* Reset and Channel Switching Routines */
856 /****************************************/
857
858 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
859 {
860 struct ath_common *common = ath9k_hw_common(ah);
861 u32 regval;
862
863 ENABLE_REGWRITE_BUFFER(ah);
864
865 /*
866 * set AHB_MODE not to do cacheline prefetches
867 */
868 if (!AR_SREV_9300_20_OR_LATER(ah)) {
869 regval = REG_READ(ah, AR_AHB_MODE);
870 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
871 }
872
873 /*
874 * let mac dma reads be in 128 byte chunks
875 */
876 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
877 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
878
879 REGWRITE_BUFFER_FLUSH(ah);
880
881 /*
882 * Restore TX Trigger Level to its pre-reset value.
883 * The initial value depends on whether aggregation is enabled, and is
884 * adjusted whenever underruns are detected.
885 */
886 if (!AR_SREV_9300_20_OR_LATER(ah))
887 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
888
889 ENABLE_REGWRITE_BUFFER(ah);
890
891 /*
892 * let mac dma writes be in 128 byte chunks
893 */
894 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
895 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
896
897 /*
898 * Setup receive FIFO threshold to hold off TX activities
899 */
900 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
901
902 if (AR_SREV_9300_20_OR_LATER(ah)) {
903 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
904 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
905
906 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
907 ah->caps.rx_status_len);
908 }
909
910 /*
911 * reduce the number of usable entries in PCU TXBUF to avoid
912 * wrap around issues.
913 */
914 if (AR_SREV_9285(ah)) {
915 /* For AR9285 the number of Fifos are reduced to half.
916 * So set the usable tx buf size also to half to
917 * avoid data/delimiter underruns
918 */
919 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
920 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
921 } else if (!AR_SREV_9271(ah)) {
922 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
923 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
924 }
925
926 REGWRITE_BUFFER_FLUSH(ah);
927
928 if (AR_SREV_9300_20_OR_LATER(ah))
929 ath9k_hw_reset_txstatus_ring(ah);
930 }
931
932 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
933 {
934 u32 val;
935
936 val = REG_READ(ah, AR_STA_ID1);
937 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
938 switch (opmode) {
939 case NL80211_IFTYPE_AP:
940 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
941 | AR_STA_ID1_KSRCH_MODE);
942 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
943 break;
944 case NL80211_IFTYPE_ADHOC:
945 case NL80211_IFTYPE_MESH_POINT:
946 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
947 | AR_STA_ID1_KSRCH_MODE);
948 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
949 break;
950 case NL80211_IFTYPE_STATION:
951 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
952 break;
953 default:
954 if (ah->is_monitoring)
955 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
956 break;
957 }
958 }
959
960 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
961 u32 *coef_mantissa, u32 *coef_exponent)
962 {
963 u32 coef_exp, coef_man;
964
965 for (coef_exp = 31; coef_exp > 0; coef_exp--)
966 if ((coef_scaled >> coef_exp) & 0x1)
967 break;
968
969 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
970
971 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
972
973 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
974 *coef_exponent = coef_exp - 16;
975 }
976
977 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
978 {
979 u32 rst_flags;
980 u32 tmpReg;
981
982 if (AR_SREV_9100(ah)) {
983 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
984 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
985 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
986 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
987 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
988 }
989
990 ENABLE_REGWRITE_BUFFER(ah);
991
992 if (AR_SREV_9300_20_OR_LATER(ah)) {
993 REG_WRITE(ah, AR_WA, ah->WARegVal);
994 udelay(10);
995 }
996
997 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
998 AR_RTC_FORCE_WAKE_ON_INT);
999
1000 if (AR_SREV_9100(ah)) {
1001 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1002 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1003 } else {
1004 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1005 if (tmpReg &
1006 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1007 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1008 u32 val;
1009 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1010
1011 val = AR_RC_HOSTIF;
1012 if (!AR_SREV_9300_20_OR_LATER(ah))
1013 val |= AR_RC_AHB;
1014 REG_WRITE(ah, AR_RC, val);
1015
1016 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1017 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1018
1019 rst_flags = AR_RTC_RC_MAC_WARM;
1020 if (type == ATH9K_RESET_COLD)
1021 rst_flags |= AR_RTC_RC_MAC_COLD;
1022 }
1023
1024 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1025
1026 REGWRITE_BUFFER_FLUSH(ah);
1027
1028 udelay(50);
1029
1030 REG_WRITE(ah, AR_RTC_RC, 0);
1031 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1032 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1033 "RTC stuck in MAC reset\n");
1034 return false;
1035 }
1036
1037 if (!AR_SREV_9100(ah))
1038 REG_WRITE(ah, AR_RC, 0);
1039
1040 if (AR_SREV_9100(ah))
1041 udelay(50);
1042
1043 return true;
1044 }
1045
1046 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1047 {
1048 ENABLE_REGWRITE_BUFFER(ah);
1049
1050 if (AR_SREV_9300_20_OR_LATER(ah)) {
1051 REG_WRITE(ah, AR_WA, ah->WARegVal);
1052 udelay(10);
1053 }
1054
1055 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1056 AR_RTC_FORCE_WAKE_ON_INT);
1057
1058 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1059 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1060
1061 REG_WRITE(ah, AR_RTC_RESET, 0);
1062 udelay(2);
1063
1064 REGWRITE_BUFFER_FLUSH(ah);
1065
1066 if (!AR_SREV_9300_20_OR_LATER(ah))
1067 udelay(2);
1068
1069 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1070 REG_WRITE(ah, AR_RC, 0);
1071
1072 REG_WRITE(ah, AR_RTC_RESET, 1);
1073
1074 if (!ath9k_hw_wait(ah,
1075 AR_RTC_STATUS,
1076 AR_RTC_STATUS_M,
1077 AR_RTC_STATUS_ON,
1078 AH_WAIT_TIMEOUT)) {
1079 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1080 "RTC not waking up\n");
1081 return false;
1082 }
1083
1084 ath9k_hw_read_revisions(ah);
1085
1086 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1087 }
1088
1089 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1090 {
1091 if (AR_SREV_9300_20_OR_LATER(ah)) {
1092 REG_WRITE(ah, AR_WA, ah->WARegVal);
1093 udelay(10);
1094 }
1095
1096 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1097 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1098
1099 switch (type) {
1100 case ATH9K_RESET_POWER_ON:
1101 return ath9k_hw_set_reset_power_on(ah);
1102 case ATH9K_RESET_WARM:
1103 case ATH9K_RESET_COLD:
1104 return ath9k_hw_set_reset(ah, type);
1105 default:
1106 return false;
1107 }
1108 }
1109
1110 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1111 struct ath9k_channel *chan)
1112 {
1113 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1114 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1115 return false;
1116 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1117 return false;
1118
1119 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1120 return false;
1121
1122 ah->chip_fullsleep = false;
1123 ath9k_hw_init_pll(ah, chan);
1124 ath9k_hw_set_rfmode(ah, chan);
1125
1126 return true;
1127 }
1128
1129 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1130 struct ath9k_channel *chan)
1131 {
1132 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1133 struct ath_common *common = ath9k_hw_common(ah);
1134 struct ieee80211_channel *channel = chan->chan;
1135 u32 qnum;
1136 int r;
1137
1138 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1139 if (ath9k_hw_numtxpending(ah, qnum)) {
1140 ath_print(common, ATH_DBG_QUEUE,
1141 "Transmit frames pending on "
1142 "queue %d\n", qnum);
1143 return false;
1144 }
1145 }
1146
1147 if (!ath9k_hw_rfbus_req(ah)) {
1148 ath_print(common, ATH_DBG_FATAL,
1149 "Could not kill baseband RX\n");
1150 return false;
1151 }
1152
1153 ath9k_hw_set_channel_regs(ah, chan);
1154
1155 r = ath9k_hw_rf_set_freq(ah, chan);
1156 if (r) {
1157 ath_print(common, ATH_DBG_FATAL,
1158 "Failed to set channel\n");
1159 return false;
1160 }
1161 ath9k_hw_set_clockrate(ah);
1162
1163 ah->eep_ops->set_txpower(ah, chan,
1164 ath9k_regd_get_ctl(regulatory, chan),
1165 channel->max_antenna_gain * 2,
1166 channel->max_power * 2,
1167 min((u32) MAX_RATE_POWER,
1168 (u32) regulatory->power_limit), false);
1169
1170 ath9k_hw_rfbus_done(ah);
1171
1172 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1173 ath9k_hw_set_delta_slope(ah, chan);
1174
1175 ath9k_hw_spur_mitigate_freq(ah, chan);
1176
1177 return true;
1178 }
1179
1180 bool ath9k_hw_check_alive(struct ath_hw *ah)
1181 {
1182 int count = 50;
1183 u32 reg;
1184
1185 if (AR_SREV_9285_12_OR_LATER(ah))
1186 return true;
1187
1188 do {
1189 reg = REG_READ(ah, AR_OBS_BUS_1);
1190
1191 if ((reg & 0x7E7FFFEF) == 0x00702400)
1192 continue;
1193
1194 switch (reg & 0x7E000B00) {
1195 case 0x1E000000:
1196 case 0x52000B00:
1197 case 0x18000B00:
1198 continue;
1199 default:
1200 return true;
1201 }
1202 } while (count-- > 0);
1203
1204 return false;
1205 }
1206 EXPORT_SYMBOL(ath9k_hw_check_alive);
1207
1208 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1209 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1210 {
1211 struct ath_common *common = ath9k_hw_common(ah);
1212 u32 saveLedState;
1213 struct ath9k_channel *curchan = ah->curchan;
1214 u32 saveDefAntenna;
1215 u32 macStaId1;
1216 u64 tsf = 0;
1217 int i, r;
1218
1219 ah->txchainmask = common->tx_chainmask;
1220 ah->rxchainmask = common->rx_chainmask;
1221
1222 if (!ah->chip_fullsleep) {
1223 ath9k_hw_abortpcurecv(ah);
1224 if (!ath9k_hw_stopdmarecv(ah)) {
1225 ath_print(common, ATH_DBG_XMIT,
1226 "Failed to stop receive dma\n");
1227 bChannelChange = false;
1228 }
1229 }
1230
1231 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1232 return -EIO;
1233
1234 if (curchan && !ah->chip_fullsleep)
1235 ath9k_hw_getnf(ah, curchan);
1236
1237 ah->caldata = caldata;
1238 if (caldata &&
1239 (chan->channel != caldata->channel ||
1240 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1241 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1242 /* Operating channel changed, reset channel calibration data */
1243 memset(caldata, 0, sizeof(*caldata));
1244 ath9k_init_nfcal_hist_buffer(ah, chan);
1245 }
1246
1247 if (bChannelChange &&
1248 (ah->chip_fullsleep != true) &&
1249 (ah->curchan != NULL) &&
1250 (chan->channel != ah->curchan->channel) &&
1251 ((chan->channelFlags & CHANNEL_ALL) ==
1252 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1253 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1254
1255 if (ath9k_hw_channel_change(ah, chan)) {
1256 ath9k_hw_loadnf(ah, ah->curchan);
1257 ath9k_hw_start_nfcal(ah, true);
1258 if (AR_SREV_9271(ah))
1259 ar9002_hw_load_ani_reg(ah, chan);
1260 return 0;
1261 }
1262 }
1263
1264 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1265 if (saveDefAntenna == 0)
1266 saveDefAntenna = 1;
1267
1268 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1269
1270 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1271 if (AR_SREV_9100(ah) ||
1272 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1273 tsf = ath9k_hw_gettsf64(ah);
1274
1275 saveLedState = REG_READ(ah, AR_CFG_LED) &
1276 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1277 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1278
1279 ath9k_hw_mark_phy_inactive(ah);
1280
1281 /* Only required on the first reset */
1282 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1283 REG_WRITE(ah,
1284 AR9271_RESET_POWER_DOWN_CONTROL,
1285 AR9271_RADIO_RF_RST);
1286 udelay(50);
1287 }
1288
1289 if (!ath9k_hw_chip_reset(ah, chan)) {
1290 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1291 return -EINVAL;
1292 }
1293
1294 /* Only required on the first reset */
1295 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1296 ah->htc_reset_init = false;
1297 REG_WRITE(ah,
1298 AR9271_RESET_POWER_DOWN_CONTROL,
1299 AR9271_GATE_MAC_CTL);
1300 udelay(50);
1301 }
1302
1303 /* Restore TSF */
1304 if (tsf)
1305 ath9k_hw_settsf64(ah, tsf);
1306
1307 if (AR_SREV_9280_20_OR_LATER(ah))
1308 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1309
1310 if (!AR_SREV_9300_20_OR_LATER(ah))
1311 ar9002_hw_enable_async_fifo(ah);
1312
1313 r = ath9k_hw_process_ini(ah, chan);
1314 if (r)
1315 return r;
1316
1317 /*
1318 * Some AR91xx SoC devices frequently fail to accept TSF writes
1319 * right after the chip reset. When that happens, write a new
1320 * value after the initvals have been applied, with an offset
1321 * based on measured time difference
1322 */
1323 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1324 tsf += 1500;
1325 ath9k_hw_settsf64(ah, tsf);
1326 }
1327
1328 /* Setup MFP options for CCMP */
1329 if (AR_SREV_9280_20_OR_LATER(ah)) {
1330 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1331 * frames when constructing CCMP AAD. */
1332 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1333 0xc7ff);
1334 ah->sw_mgmt_crypto = false;
1335 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1336 /* Disable hardware crypto for management frames */
1337 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1338 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1339 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1340 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1341 ah->sw_mgmt_crypto = true;
1342 } else
1343 ah->sw_mgmt_crypto = true;
1344
1345 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1346 ath9k_hw_set_delta_slope(ah, chan);
1347
1348 ath9k_hw_spur_mitigate_freq(ah, chan);
1349 ah->eep_ops->set_board_values(ah, chan);
1350
1351 ath9k_hw_set_operating_mode(ah, ah->opmode);
1352
1353 ENABLE_REGWRITE_BUFFER(ah);
1354
1355 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1356 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1357 | macStaId1
1358 | AR_STA_ID1_RTS_USE_DEF
1359 | (ah->config.
1360 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1361 | ah->sta_id1_defaults);
1362 ath_hw_setbssidmask(common);
1363 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1364 ath9k_hw_write_associd(ah);
1365 REG_WRITE(ah, AR_ISR, ~0);
1366 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1367
1368 REGWRITE_BUFFER_FLUSH(ah);
1369
1370 r = ath9k_hw_rf_set_freq(ah, chan);
1371 if (r)
1372 return r;
1373
1374 ath9k_hw_set_clockrate(ah);
1375
1376 ENABLE_REGWRITE_BUFFER(ah);
1377
1378 for (i = 0; i < AR_NUM_DCU; i++)
1379 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1380
1381 REGWRITE_BUFFER_FLUSH(ah);
1382
1383 ah->intr_txqs = 0;
1384 for (i = 0; i < ah->caps.total_queues; i++)
1385 ath9k_hw_resettxqueue(ah, i);
1386
1387 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1388 ath9k_hw_ani_cache_ini_regs(ah);
1389 ath9k_hw_init_qos(ah);
1390
1391 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1392 ath9k_enable_rfkill(ah);
1393
1394 ath9k_hw_init_global_settings(ah);
1395
1396 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1397 ar9002_hw_update_async_fifo(ah);
1398 ar9002_hw_enable_wep_aggregation(ah);
1399 }
1400
1401 REG_WRITE(ah, AR_STA_ID1,
1402 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1403
1404 ath9k_hw_set_dma(ah);
1405
1406 REG_WRITE(ah, AR_OBS, 8);
1407
1408 if (ah->config.rx_intr_mitigation) {
1409 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1410 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1411 }
1412
1413 if (ah->config.tx_intr_mitigation) {
1414 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1415 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1416 }
1417
1418 ath9k_hw_init_bb(ah, chan);
1419
1420 if (!ath9k_hw_init_cal(ah, chan))
1421 return -EIO;
1422
1423 ENABLE_REGWRITE_BUFFER(ah);
1424
1425 ath9k_hw_restore_chainmask(ah);
1426 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1427
1428 REGWRITE_BUFFER_FLUSH(ah);
1429
1430 /*
1431 * For big endian systems turn on swapping for descriptors
1432 */
1433 if (AR_SREV_9100(ah)) {
1434 u32 mask;
1435 mask = REG_READ(ah, AR_CFG);
1436 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1437 ath_print(common, ATH_DBG_RESET,
1438 "CFG Byte Swap Set 0x%x\n", mask);
1439 } else {
1440 mask =
1441 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1442 REG_WRITE(ah, AR_CFG, mask);
1443 ath_print(common, ATH_DBG_RESET,
1444 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1445 }
1446 } else {
1447 if (common->bus_ops->ath_bus_type == ATH_USB) {
1448 /* Configure AR9271 target WLAN */
1449 if (AR_SREV_9271(ah))
1450 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1451 else
1452 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1453 }
1454 #ifdef __BIG_ENDIAN
1455 else
1456 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1457 #endif
1458 }
1459
1460 if (ah->btcoex_hw.enabled)
1461 ath9k_hw_btcoex_enable(ah);
1462
1463 if (AR_SREV_9300_20_OR_LATER(ah))
1464 ar9003_hw_bb_watchdog_config(ah);
1465
1466 return 0;
1467 }
1468 EXPORT_SYMBOL(ath9k_hw_reset);
1469
1470 /******************************/
1471 /* Power Management (Chipset) */
1472 /******************************/
1473
1474 /*
1475 * Notify Power Mgt is disabled in self-generated frames.
1476 * If requested, force chip to sleep.
1477 */
1478 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1479 {
1480 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1481 if (setChip) {
1482 /*
1483 * Clear the RTC force wake bit to allow the
1484 * mac to go to sleep.
1485 */
1486 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1487 AR_RTC_FORCE_WAKE_EN);
1488 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1489 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1490
1491 /* Shutdown chip. Active low */
1492 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1493 REG_CLR_BIT(ah, (AR_RTC_RESET),
1494 AR_RTC_RESET_EN);
1495 }
1496
1497 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1498 if (AR_SREV_9300_20_OR_LATER(ah))
1499 REG_WRITE(ah, AR_WA,
1500 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1501 }
1502
1503 /*
1504 * Notify Power Management is enabled in self-generating
1505 * frames. If request, set power mode of chip to
1506 * auto/normal. Duration in units of 128us (1/8 TU).
1507 */
1508 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1509 {
1510 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1511 if (setChip) {
1512 struct ath9k_hw_capabilities *pCap = &ah->caps;
1513
1514 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1515 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1516 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1517 AR_RTC_FORCE_WAKE_ON_INT);
1518 } else {
1519 /*
1520 * Clear the RTC force wake bit to allow the
1521 * mac to go to sleep.
1522 */
1523 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1524 AR_RTC_FORCE_WAKE_EN);
1525 }
1526 }
1527
1528 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1529 if (AR_SREV_9300_20_OR_LATER(ah))
1530 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1531 }
1532
1533 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1534 {
1535 u32 val;
1536 int i;
1537
1538 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1539 if (AR_SREV_9300_20_OR_LATER(ah)) {
1540 REG_WRITE(ah, AR_WA, ah->WARegVal);
1541 udelay(10);
1542 }
1543
1544 if (setChip) {
1545 if ((REG_READ(ah, AR_RTC_STATUS) &
1546 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1547 if (ath9k_hw_set_reset_reg(ah,
1548 ATH9K_RESET_POWER_ON) != true) {
1549 return false;
1550 }
1551 if (!AR_SREV_9300_20_OR_LATER(ah))
1552 ath9k_hw_init_pll(ah, NULL);
1553 }
1554 if (AR_SREV_9100(ah))
1555 REG_SET_BIT(ah, AR_RTC_RESET,
1556 AR_RTC_RESET_EN);
1557
1558 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1559 AR_RTC_FORCE_WAKE_EN);
1560 udelay(50);
1561
1562 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1563 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1564 if (val == AR_RTC_STATUS_ON)
1565 break;
1566 udelay(50);
1567 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1568 AR_RTC_FORCE_WAKE_EN);
1569 }
1570 if (i == 0) {
1571 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1572 "Failed to wakeup in %uus\n",
1573 POWER_UP_TIME / 20);
1574 return false;
1575 }
1576 }
1577
1578 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1579
1580 return true;
1581 }
1582
1583 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1584 {
1585 struct ath_common *common = ath9k_hw_common(ah);
1586 int status = true, setChip = true;
1587 static const char *modes[] = {
1588 "AWAKE",
1589 "FULL-SLEEP",
1590 "NETWORK SLEEP",
1591 "UNDEFINED"
1592 };
1593
1594 if (ah->power_mode == mode)
1595 return status;
1596
1597 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1598 modes[ah->power_mode], modes[mode]);
1599
1600 switch (mode) {
1601 case ATH9K_PM_AWAKE:
1602 status = ath9k_hw_set_power_awake(ah, setChip);
1603 break;
1604 case ATH9K_PM_FULL_SLEEP:
1605 ath9k_set_power_sleep(ah, setChip);
1606 ah->chip_fullsleep = true;
1607 break;
1608 case ATH9K_PM_NETWORK_SLEEP:
1609 ath9k_set_power_network_sleep(ah, setChip);
1610 break;
1611 default:
1612 ath_print(common, ATH_DBG_FATAL,
1613 "Unknown power mode %u\n", mode);
1614 return false;
1615 }
1616 ah->power_mode = mode;
1617
1618 return status;
1619 }
1620 EXPORT_SYMBOL(ath9k_hw_setpower);
1621
1622 /*******************/
1623 /* Beacon Handling */
1624 /*******************/
1625
1626 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1627 {
1628 int flags = 0;
1629
1630 ah->beacon_interval = beacon_period;
1631
1632 ENABLE_REGWRITE_BUFFER(ah);
1633
1634 switch (ah->opmode) {
1635 case NL80211_IFTYPE_STATION:
1636 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1637 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1638 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1639 flags |= AR_TBTT_TIMER_EN;
1640 break;
1641 case NL80211_IFTYPE_ADHOC:
1642 case NL80211_IFTYPE_MESH_POINT:
1643 REG_SET_BIT(ah, AR_TXCFG,
1644 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1645 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1646 TU_TO_USEC(next_beacon +
1647 (ah->atim_window ? ah->
1648 atim_window : 1)));
1649 flags |= AR_NDP_TIMER_EN;
1650 case NL80211_IFTYPE_AP:
1651 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1652 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1653 TU_TO_USEC(next_beacon -
1654 ah->config.
1655 dma_beacon_response_time));
1656 REG_WRITE(ah, AR_NEXT_SWBA,
1657 TU_TO_USEC(next_beacon -
1658 ah->config.
1659 sw_beacon_response_time));
1660 flags |=
1661 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1662 break;
1663 default:
1664 if (ah->is_monitoring) {
1665 REG_WRITE(ah, AR_NEXT_TBTT_TIMER,
1666 TU_TO_USEC(next_beacon));
1667 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1668 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1669 flags |= AR_TBTT_TIMER_EN;
1670 break;
1671 }
1672 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1673 "%s: unsupported opmode: %d\n",
1674 __func__, ah->opmode);
1675 return;
1676 break;
1677 }
1678
1679 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1680 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1681 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1682 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1683
1684 REGWRITE_BUFFER_FLUSH(ah);
1685
1686 beacon_period &= ~ATH9K_BEACON_ENA;
1687 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1688 ath9k_hw_reset_tsf(ah);
1689 }
1690
1691 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1692 }
1693 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1694
1695 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1696 const struct ath9k_beacon_state *bs)
1697 {
1698 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1699 struct ath9k_hw_capabilities *pCap = &ah->caps;
1700 struct ath_common *common = ath9k_hw_common(ah);
1701
1702 ENABLE_REGWRITE_BUFFER(ah);
1703
1704 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1705
1706 REG_WRITE(ah, AR_BEACON_PERIOD,
1707 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1708 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1709 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1710
1711 REGWRITE_BUFFER_FLUSH(ah);
1712
1713 REG_RMW_FIELD(ah, AR_RSSI_THR,
1714 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1715
1716 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1717
1718 if (bs->bs_sleepduration > beaconintval)
1719 beaconintval = bs->bs_sleepduration;
1720
1721 dtimperiod = bs->bs_dtimperiod;
1722 if (bs->bs_sleepduration > dtimperiod)
1723 dtimperiod = bs->bs_sleepduration;
1724
1725 if (beaconintval == dtimperiod)
1726 nextTbtt = bs->bs_nextdtim;
1727 else
1728 nextTbtt = bs->bs_nexttbtt;
1729
1730 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1731 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1732 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1733 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1734
1735 ENABLE_REGWRITE_BUFFER(ah);
1736
1737 REG_WRITE(ah, AR_NEXT_DTIM,
1738 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1739 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1740
1741 REG_WRITE(ah, AR_SLEEP1,
1742 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1743 | AR_SLEEP1_ASSUME_DTIM);
1744
1745 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1746 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1747 else
1748 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1749
1750 REG_WRITE(ah, AR_SLEEP2,
1751 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1752
1753 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1754 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1755
1756 REGWRITE_BUFFER_FLUSH(ah);
1757
1758 REG_SET_BIT(ah, AR_TIMER_MODE,
1759 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1760 AR_DTIM_TIMER_EN);
1761
1762 /* TSF Out of Range Threshold */
1763 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1764 }
1765 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1766
1767 /*******************/
1768 /* HW Capabilities */
1769 /*******************/
1770
1771 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1772 {
1773 struct ath9k_hw_capabilities *pCap = &ah->caps;
1774 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1775 struct ath_common *common = ath9k_hw_common(ah);
1776 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1777
1778 u16 capField = 0, eeval;
1779 u8 ant_div_ctl1;
1780
1781 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1782 regulatory->current_rd = eeval;
1783
1784 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1785 if (AR_SREV_9285_12_OR_LATER(ah))
1786 eeval |= AR9285_RDEXT_DEFAULT;
1787 regulatory->current_rd_ext = eeval;
1788
1789 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1790
1791 if (ah->opmode != NL80211_IFTYPE_AP &&
1792 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1793 if (regulatory->current_rd == 0x64 ||
1794 regulatory->current_rd == 0x65)
1795 regulatory->current_rd += 5;
1796 else if (regulatory->current_rd == 0x41)
1797 regulatory->current_rd = 0x43;
1798 ath_print(common, ATH_DBG_REGULATORY,
1799 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1800 }
1801
1802 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1803 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1804 ath_print(common, ATH_DBG_FATAL,
1805 "no band has been marked as supported in EEPROM.\n");
1806 return -EINVAL;
1807 }
1808
1809 if (eeval & AR5416_OPFLAGS_11A)
1810 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1811
1812 if (eeval & AR5416_OPFLAGS_11G)
1813 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1814
1815 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1816 /*
1817 * For AR9271 we will temporarilly uses the rx chainmax as read from
1818 * the EEPROM.
1819 */
1820 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1821 !(eeval & AR5416_OPFLAGS_11A) &&
1822 !(AR_SREV_9271(ah)))
1823 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1824 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1825 else
1826 /* Use rx_chainmask from EEPROM. */
1827 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1828
1829 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1830
1831 /* enable key search for every frame in an aggregate */
1832 if (AR_SREV_9300_20_OR_LATER(ah))
1833 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1834
1835 pCap->low_2ghz_chan = 2312;
1836 pCap->high_2ghz_chan = 2732;
1837
1838 pCap->low_5ghz_chan = 4920;
1839 pCap->high_5ghz_chan = 6100;
1840
1841 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1842
1843 if (ah->config.ht_enable)
1844 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1845 else
1846 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1847
1848 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1849 pCap->total_queues =
1850 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1851 else
1852 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1853
1854 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1855 pCap->keycache_size =
1856 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1857 else
1858 pCap->keycache_size = AR_KEYTABLE_SIZE;
1859
1860 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1861 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
1862 else
1863 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
1864
1865 if (AR_SREV_9271(ah))
1866 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1867 else if (AR_DEVID_7010(ah))
1868 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1869 else if (AR_SREV_9285_12_OR_LATER(ah))
1870 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1871 else if (AR_SREV_9280_20_OR_LATER(ah))
1872 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1873 else
1874 pCap->num_gpio_pins = AR_NUM_GPIO;
1875
1876 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1877 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1878 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1879 } else {
1880 pCap->rts_aggr_limit = (8 * 1024);
1881 }
1882
1883 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
1884
1885 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1886 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1887 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1888 ah->rfkill_gpio =
1889 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1890 ah->rfkill_polarity =
1891 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1892
1893 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1894 }
1895 #endif
1896 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1897 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1898 else
1899 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1900
1901 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1902 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1903 else
1904 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1905
1906 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
1907 pCap->reg_cap =
1908 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1909 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
1910 AR_EEPROM_EEREGCAP_EN_KK_U2 |
1911 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
1912 } else {
1913 pCap->reg_cap =
1914 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1915 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
1916 }
1917
1918 /* Advertise midband for AR5416 with FCC midband set in eeprom */
1919 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
1920 AR_SREV_5416(ah))
1921 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
1922
1923 pCap->num_antcfg_5ghz =
1924 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
1925 pCap->num_antcfg_2ghz =
1926 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
1927
1928 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1929 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1930 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1931
1932 if (AR_SREV_9285(ah)) {
1933 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1934 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1935 } else {
1936 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1937 }
1938 } else {
1939 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1940 }
1941
1942 if (AR_SREV_9300_20_OR_LATER(ah)) {
1943 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
1944 ATH9K_HW_CAP_FASTCLOCK;
1945 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1946 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1947 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1948 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1949 pCap->txs_len = sizeof(struct ar9003_txs);
1950 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1951 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1952 } else {
1953 pCap->tx_desc_len = sizeof(struct ath_desc);
1954 if (AR_SREV_9280_20(ah) &&
1955 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1956 AR5416_EEP_MINOR_VER_16) ||
1957 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1958 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1959 }
1960
1961 if (AR_SREV_9300_20_OR_LATER(ah))
1962 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1963
1964 if (AR_SREV_9300_20_OR_LATER(ah))
1965 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1966
1967 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1968 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1969
1970 if (AR_SREV_9285(ah))
1971 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1972 ant_div_ctl1 =
1973 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1974 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1975 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1976 }
1977
1978 return 0;
1979 }
1980
1981 /****************************/
1982 /* GPIO / RFKILL / Antennae */
1983 /****************************/
1984
1985 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
1986 u32 gpio, u32 type)
1987 {
1988 int addr;
1989 u32 gpio_shift, tmp;
1990
1991 if (gpio > 11)
1992 addr = AR_GPIO_OUTPUT_MUX3;
1993 else if (gpio > 5)
1994 addr = AR_GPIO_OUTPUT_MUX2;
1995 else
1996 addr = AR_GPIO_OUTPUT_MUX1;
1997
1998 gpio_shift = (gpio % 6) * 5;
1999
2000 if (AR_SREV_9280_20_OR_LATER(ah)
2001 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2002 REG_RMW(ah, addr, (type << gpio_shift),
2003 (0x1f << gpio_shift));
2004 } else {
2005 tmp = REG_READ(ah, addr);
2006 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2007 tmp &= ~(0x1f << gpio_shift);
2008 tmp |= (type << gpio_shift);
2009 REG_WRITE(ah, addr, tmp);
2010 }
2011 }
2012
2013 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2014 {
2015 u32 gpio_shift;
2016
2017 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2018
2019 if (AR_DEVID_7010(ah)) {
2020 gpio_shift = gpio;
2021 REG_RMW(ah, AR7010_GPIO_OE,
2022 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2023 (AR7010_GPIO_OE_MASK << gpio_shift));
2024 return;
2025 }
2026
2027 gpio_shift = gpio << 1;
2028 REG_RMW(ah,
2029 AR_GPIO_OE_OUT,
2030 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2031 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2032 }
2033 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2034
2035 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2036 {
2037 #define MS_REG_READ(x, y) \
2038 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2039
2040 if (gpio >= ah->caps.num_gpio_pins)
2041 return 0xffffffff;
2042
2043 if (AR_DEVID_7010(ah)) {
2044 u32 val;
2045 val = REG_READ(ah, AR7010_GPIO_IN);
2046 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2047 } else if (AR_SREV_9300_20_OR_LATER(ah))
2048 return MS_REG_READ(AR9300, gpio) != 0;
2049 else if (AR_SREV_9271(ah))
2050 return MS_REG_READ(AR9271, gpio) != 0;
2051 else if (AR_SREV_9287_11_OR_LATER(ah))
2052 return MS_REG_READ(AR9287, gpio) != 0;
2053 else if (AR_SREV_9285_12_OR_LATER(ah))
2054 return MS_REG_READ(AR9285, gpio) != 0;
2055 else if (AR_SREV_9280_20_OR_LATER(ah))
2056 return MS_REG_READ(AR928X, gpio) != 0;
2057 else
2058 return MS_REG_READ(AR, gpio) != 0;
2059 }
2060 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2061
2062 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2063 u32 ah_signal_type)
2064 {
2065 u32 gpio_shift;
2066
2067 if (AR_DEVID_7010(ah)) {
2068 gpio_shift = gpio;
2069 REG_RMW(ah, AR7010_GPIO_OE,
2070 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2071 (AR7010_GPIO_OE_MASK << gpio_shift));
2072 return;
2073 }
2074
2075 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2076 gpio_shift = 2 * gpio;
2077 REG_RMW(ah,
2078 AR_GPIO_OE_OUT,
2079 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2080 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2081 }
2082 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2083
2084 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2085 {
2086 if (AR_DEVID_7010(ah)) {
2087 val = val ? 0 : 1;
2088 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2089 AR_GPIO_BIT(gpio));
2090 return;
2091 }
2092
2093 if (AR_SREV_9271(ah))
2094 val = ~val;
2095
2096 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2097 AR_GPIO_BIT(gpio));
2098 }
2099 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2100
2101 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2102 {
2103 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2104 }
2105 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2106
2107 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2108 {
2109 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2110 }
2111 EXPORT_SYMBOL(ath9k_hw_setantenna);
2112
2113 /*********************/
2114 /* General Operation */
2115 /*********************/
2116
2117 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2118 {
2119 u32 bits = REG_READ(ah, AR_RX_FILTER);
2120 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2121
2122 if (phybits & AR_PHY_ERR_RADAR)
2123 bits |= ATH9K_RX_FILTER_PHYRADAR;
2124 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2125 bits |= ATH9K_RX_FILTER_PHYERR;
2126
2127 return bits;
2128 }
2129 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2130
2131 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2132 {
2133 u32 phybits;
2134
2135 ENABLE_REGWRITE_BUFFER(ah);
2136
2137 REG_WRITE(ah, AR_RX_FILTER, bits);
2138
2139 phybits = 0;
2140 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2141 phybits |= AR_PHY_ERR_RADAR;
2142 if (bits & ATH9K_RX_FILTER_PHYERR)
2143 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2144 REG_WRITE(ah, AR_PHY_ERR, phybits);
2145
2146 if (phybits)
2147 REG_WRITE(ah, AR_RXCFG,
2148 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2149 else
2150 REG_WRITE(ah, AR_RXCFG,
2151 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2152
2153 REGWRITE_BUFFER_FLUSH(ah);
2154 }
2155 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2156
2157 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2158 {
2159 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2160 return false;
2161
2162 ath9k_hw_init_pll(ah, NULL);
2163 return true;
2164 }
2165 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2166
2167 bool ath9k_hw_disable(struct ath_hw *ah)
2168 {
2169 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2170 return false;
2171
2172 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2173 return false;
2174
2175 ath9k_hw_init_pll(ah, NULL);
2176 return true;
2177 }
2178 EXPORT_SYMBOL(ath9k_hw_disable);
2179
2180 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2181 {
2182 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2183 struct ath9k_channel *chan = ah->curchan;
2184 struct ieee80211_channel *channel = chan->chan;
2185
2186 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2187
2188 ah->eep_ops->set_txpower(ah, chan,
2189 ath9k_regd_get_ctl(regulatory, chan),
2190 channel->max_antenna_gain * 2,
2191 channel->max_power * 2,
2192 min((u32) MAX_RATE_POWER,
2193 (u32) regulatory->power_limit), test);
2194 }
2195 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2196
2197 void ath9k_hw_setopmode(struct ath_hw *ah)
2198 {
2199 ath9k_hw_set_operating_mode(ah, ah->opmode);
2200 }
2201 EXPORT_SYMBOL(ath9k_hw_setopmode);
2202
2203 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2204 {
2205 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2206 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2207 }
2208 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2209
2210 void ath9k_hw_write_associd(struct ath_hw *ah)
2211 {
2212 struct ath_common *common = ath9k_hw_common(ah);
2213
2214 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2215 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2216 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2217 }
2218 EXPORT_SYMBOL(ath9k_hw_write_associd);
2219
2220 #define ATH9K_MAX_TSF_READ 10
2221
2222 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2223 {
2224 u32 tsf_lower, tsf_upper1, tsf_upper2;
2225 int i;
2226
2227 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2228 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2229 tsf_lower = REG_READ(ah, AR_TSF_L32);
2230 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2231 if (tsf_upper2 == tsf_upper1)
2232 break;
2233 tsf_upper1 = tsf_upper2;
2234 }
2235
2236 WARN_ON( i == ATH9K_MAX_TSF_READ );
2237
2238 return (((u64)tsf_upper1 << 32) | tsf_lower);
2239 }
2240 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2241
2242 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2243 {
2244 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2245 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2246 }
2247 EXPORT_SYMBOL(ath9k_hw_settsf64);
2248
2249 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2250 {
2251 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2252 AH_TSF_WRITE_TIMEOUT))
2253 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2254 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2255
2256 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2257 }
2258 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2259
2260 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2261 {
2262 if (setting)
2263 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2264 else
2265 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2266 }
2267 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2268
2269 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2270 {
2271 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2272 u32 macmode;
2273
2274 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2275 macmode = AR_2040_JOINED_RX_CLEAR;
2276 else
2277 macmode = 0;
2278
2279 REG_WRITE(ah, AR_2040_MODE, macmode);
2280 }
2281
2282 /* HW Generic timers configuration */
2283
2284 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2285 {
2286 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2287 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2288 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2289 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2290 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2291 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2292 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2293 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2294 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2295 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2296 AR_NDP2_TIMER_MODE, 0x0002},
2297 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2298 AR_NDP2_TIMER_MODE, 0x0004},
2299 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2300 AR_NDP2_TIMER_MODE, 0x0008},
2301 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2302 AR_NDP2_TIMER_MODE, 0x0010},
2303 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2304 AR_NDP2_TIMER_MODE, 0x0020},
2305 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2306 AR_NDP2_TIMER_MODE, 0x0040},
2307 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2308 AR_NDP2_TIMER_MODE, 0x0080}
2309 };
2310
2311 /* HW generic timer primitives */
2312
2313 /* compute and clear index of rightmost 1 */
2314 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2315 {
2316 u32 b;
2317
2318 b = *mask;
2319 b &= (0-b);
2320 *mask &= ~b;
2321 b *= debruijn32;
2322 b >>= 27;
2323
2324 return timer_table->gen_timer_index[b];
2325 }
2326
2327 static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2328 {
2329 return REG_READ(ah, AR_TSF_L32);
2330 }
2331
2332 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2333 void (*trigger)(void *),
2334 void (*overflow)(void *),
2335 void *arg,
2336 u8 timer_index)
2337 {
2338 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2339 struct ath_gen_timer *timer;
2340
2341 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2342
2343 if (timer == NULL) {
2344 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2345 "Failed to allocate memory"
2346 "for hw timer[%d]\n", timer_index);
2347 return NULL;
2348 }
2349
2350 /* allocate a hardware generic timer slot */
2351 timer_table->timers[timer_index] = timer;
2352 timer->index = timer_index;
2353 timer->trigger = trigger;
2354 timer->overflow = overflow;
2355 timer->arg = arg;
2356
2357 return timer;
2358 }
2359 EXPORT_SYMBOL(ath_gen_timer_alloc);
2360
2361 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2362 struct ath_gen_timer *timer,
2363 u32 timer_next,
2364 u32 timer_period)
2365 {
2366 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2367 u32 tsf;
2368
2369 BUG_ON(!timer_period);
2370
2371 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2372
2373 tsf = ath9k_hw_gettsf32(ah);
2374
2375 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2376 "curent tsf %x period %x"
2377 "timer_next %x\n", tsf, timer_period, timer_next);
2378
2379 /*
2380 * Pull timer_next forward if the current TSF already passed it
2381 * because of software latency
2382 */
2383 if (timer_next < tsf)
2384 timer_next = tsf + timer_period;
2385
2386 /*
2387 * Program generic timer registers
2388 */
2389 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2390 timer_next);
2391 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2392 timer_period);
2393 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2394 gen_tmr_configuration[timer->index].mode_mask);
2395
2396 /* Enable both trigger and thresh interrupt masks */
2397 REG_SET_BIT(ah, AR_IMR_S5,
2398 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2399 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2400 }
2401 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2402
2403 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2404 {
2405 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2406
2407 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2408 (timer->index >= ATH_MAX_GEN_TIMER)) {
2409 return;
2410 }
2411
2412 /* Clear generic timer enable bits. */
2413 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2414 gen_tmr_configuration[timer->index].mode_mask);
2415
2416 /* Disable both trigger and thresh interrupt masks */
2417 REG_CLR_BIT(ah, AR_IMR_S5,
2418 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2419 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2420
2421 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2422 }
2423 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2424
2425 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2426 {
2427 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2428
2429 /* free the hardware generic timer slot */
2430 timer_table->timers[timer->index] = NULL;
2431 kfree(timer);
2432 }
2433 EXPORT_SYMBOL(ath_gen_timer_free);
2434
2435 /*
2436 * Generic Timer Interrupts handling
2437 */
2438 void ath_gen_timer_isr(struct ath_hw *ah)
2439 {
2440 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2441 struct ath_gen_timer *timer;
2442 struct ath_common *common = ath9k_hw_common(ah);
2443 u32 trigger_mask, thresh_mask, index;
2444
2445 /* get hardware generic timer interrupt status */
2446 trigger_mask = ah->intr_gen_timer_trigger;
2447 thresh_mask = ah->intr_gen_timer_thresh;
2448 trigger_mask &= timer_table->timer_mask.val;
2449 thresh_mask &= timer_table->timer_mask.val;
2450
2451 trigger_mask &= ~thresh_mask;
2452
2453 while (thresh_mask) {
2454 index = rightmost_index(timer_table, &thresh_mask);
2455 timer = timer_table->timers[index];
2456 BUG_ON(!timer);
2457 ath_print(common, ATH_DBG_HWTIMER,
2458 "TSF overflow for Gen timer %d\n", index);
2459 timer->overflow(timer->arg);
2460 }
2461
2462 while (trigger_mask) {
2463 index = rightmost_index(timer_table, &trigger_mask);
2464 timer = timer_table->timers[index];
2465 BUG_ON(!timer);
2466 ath_print(common, ATH_DBG_HWTIMER,
2467 "Gen timer[%d] trigger\n", index);
2468 timer->trigger(timer->arg);
2469 }
2470 }
2471 EXPORT_SYMBOL(ath_gen_timer_isr);
2472
2473 /********/
2474 /* HTC */
2475 /********/
2476
2477 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2478 {
2479 ah->htc_reset_init = true;
2480 }
2481 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2482
2483 static struct {
2484 u32 version;
2485 const char * name;
2486 } ath_mac_bb_names[] = {
2487 /* Devices with external radios */
2488 { AR_SREV_VERSION_5416_PCI, "5416" },
2489 { AR_SREV_VERSION_5416_PCIE, "5418" },
2490 { AR_SREV_VERSION_9100, "9100" },
2491 { AR_SREV_VERSION_9160, "9160" },
2492 /* Single-chip solutions */
2493 { AR_SREV_VERSION_9280, "9280" },
2494 { AR_SREV_VERSION_9285, "9285" },
2495 { AR_SREV_VERSION_9287, "9287" },
2496 { AR_SREV_VERSION_9271, "9271" },
2497 { AR_SREV_VERSION_9300, "9300" },
2498 };
2499
2500 /* For devices with external radios */
2501 static struct {
2502 u16 version;
2503 const char * name;
2504 } ath_rf_names[] = {
2505 { 0, "5133" },
2506 { AR_RAD5133_SREV_MAJOR, "5133" },
2507 { AR_RAD5122_SREV_MAJOR, "5122" },
2508 { AR_RAD2133_SREV_MAJOR, "2133" },
2509 { AR_RAD2122_SREV_MAJOR, "2122" }
2510 };
2511
2512 /*
2513 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2514 */
2515 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2516 {
2517 int i;
2518
2519 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2520 if (ath_mac_bb_names[i].version == mac_bb_version) {
2521 return ath_mac_bb_names[i].name;
2522 }
2523 }
2524
2525 return "????";
2526 }
2527
2528 /*
2529 * Return the RF name. "????" is returned if the RF is unknown.
2530 * Used for devices with external radios.
2531 */
2532 static const char *ath9k_hw_rf_name(u16 rf_version)
2533 {
2534 int i;
2535
2536 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2537 if (ath_rf_names[i].version == rf_version) {
2538 return ath_rf_names[i].name;
2539 }
2540 }
2541
2542 return "????";
2543 }
2544
2545 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2546 {
2547 int used;
2548
2549 /* chipsets >= AR9280 are single-chip */
2550 if (AR_SREV_9280_20_OR_LATER(ah)) {
2551 used = snprintf(hw_name, len,
2552 "Atheros AR%s Rev:%x",
2553 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2554 ah->hw_version.macRev);
2555 }
2556 else {
2557 used = snprintf(hw_name, len,
2558 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2559 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2560 ah->hw_version.macRev,
2561 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2562 AR_RADIO_SREV_MAJOR)),
2563 ah->hw_version.phyRev);
2564 }
2565
2566 hw_name[used] = '\0';
2567 }
2568 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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