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[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "ath9k.h"
22 #include "initvals.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
30 enum ath9k_ht_macmode macmode);
31 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
32 struct ar5416_eeprom_def *pEepData,
33 u32 reg, u32 value);
34 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
36
37 /********************/
38 /* Helper Functions */
39 /********************/
40
41 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
42 {
43 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
44
45 if (!ah->curchan) /* should really check for CCK instead */
46 return clks / ATH9K_CLOCK_RATE_CCK;
47 if (conf->channel->band == IEEE80211_BAND_2GHZ)
48 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
49
50 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
51 }
52
53 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
54 {
55 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
56
57 if (conf_is_ht40(conf))
58 return ath9k_hw_mac_usec(ah, clks) / 2;
59 else
60 return ath9k_hw_mac_usec(ah, clks);
61 }
62
63 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
64 {
65 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
66
67 if (!ah->curchan) /* should really check for CCK instead */
68 return usecs *ATH9K_CLOCK_RATE_CCK;
69 if (conf->channel->band == IEEE80211_BAND_2GHZ)
70 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
71 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
72 }
73
74 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
75 {
76 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
77
78 if (conf_is_ht40(conf))
79 return ath9k_hw_mac_clks(ah, usecs) * 2;
80 else
81 return ath9k_hw_mac_clks(ah, usecs);
82 }
83
84 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
85 {
86 int i;
87
88 BUG_ON(timeout < AH_TIME_QUANTUM);
89
90 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
91 if ((REG_READ(ah, reg) & mask) == val)
92 return true;
93
94 udelay(AH_TIME_QUANTUM);
95 }
96
97 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
98 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
99 timeout, reg, REG_READ(ah, reg), mask, val);
100
101 return false;
102 }
103
104 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
105 {
106 u32 retval;
107 int i;
108
109 for (i = 0, retval = 0; i < n; i++) {
110 retval = (retval << 1) | (val & 1);
111 val >>= 1;
112 }
113 return retval;
114 }
115
116 bool ath9k_get_channel_edges(struct ath_hw *ah,
117 u16 flags, u16 *low,
118 u16 *high)
119 {
120 struct ath9k_hw_capabilities *pCap = &ah->caps;
121
122 if (flags & CHANNEL_5GHZ) {
123 *low = pCap->low_5ghz_chan;
124 *high = pCap->high_5ghz_chan;
125 return true;
126 }
127 if ((flags & CHANNEL_2GHZ)) {
128 *low = pCap->low_2ghz_chan;
129 *high = pCap->high_2ghz_chan;
130 return true;
131 }
132 return false;
133 }
134
135 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
136 const struct ath_rate_table *rates,
137 u32 frameLen, u16 rateix,
138 bool shortPreamble)
139 {
140 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
141 u32 kbps;
142
143 kbps = rates->info[rateix].ratekbps;
144
145 if (kbps == 0)
146 return 0;
147
148 switch (rates->info[rateix].phy) {
149 case WLAN_RC_PHY_CCK:
150 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
151 if (shortPreamble && rates->info[rateix].short_preamble)
152 phyTime >>= 1;
153 numBits = frameLen << 3;
154 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
155 break;
156 case WLAN_RC_PHY_OFDM:
157 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
158 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
159 numBits = OFDM_PLCP_BITS + (frameLen << 3);
160 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
161 txTime = OFDM_SIFS_TIME_QUARTER
162 + OFDM_PREAMBLE_TIME_QUARTER
163 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
164 } else if (ah->curchan &&
165 IS_CHAN_HALF_RATE(ah->curchan)) {
166 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
167 numBits = OFDM_PLCP_BITS + (frameLen << 3);
168 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
169 txTime = OFDM_SIFS_TIME_HALF +
170 OFDM_PREAMBLE_TIME_HALF
171 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
172 } else {
173 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
174 numBits = OFDM_PLCP_BITS + (frameLen << 3);
175 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
176 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
177 + (numSymbols * OFDM_SYMBOL_TIME);
178 }
179 break;
180 default:
181 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
182 "Unknown phy %u (rate ix %u)\n",
183 rates->info[rateix].phy, rateix);
184 txTime = 0;
185 break;
186 }
187
188 return txTime;
189 }
190
191 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
192 struct ath9k_channel *chan,
193 struct chan_centers *centers)
194 {
195 int8_t extoff;
196
197 if (!IS_CHAN_HT40(chan)) {
198 centers->ctl_center = centers->ext_center =
199 centers->synth_center = chan->channel;
200 return;
201 }
202
203 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
204 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
205 centers->synth_center =
206 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
207 extoff = 1;
208 } else {
209 centers->synth_center =
210 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
211 extoff = -1;
212 }
213
214 centers->ctl_center =
215 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
216 centers->ext_center =
217 centers->synth_center + (extoff *
218 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
219 HT40_CHANNEL_CENTER_SHIFT : 15));
220 }
221
222 /******************/
223 /* Chip Revisions */
224 /******************/
225
226 static void ath9k_hw_read_revisions(struct ath_hw *ah)
227 {
228 u32 val;
229
230 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
231
232 if (val == 0xFF) {
233 val = REG_READ(ah, AR_SREV);
234 ah->hw_version.macVersion =
235 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
236 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
237 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
238 } else {
239 if (!AR_SREV_9100(ah))
240 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
241
242 ah->hw_version.macRev = val & AR_SREV_REVISION;
243
244 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
245 ah->is_pciexpress = true;
246 }
247 }
248
249 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
250 {
251 u32 val;
252 int i;
253
254 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
255
256 for (i = 0; i < 8; i++)
257 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
258 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
259 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
260
261 return ath9k_hw_reverse_bits(val, 8);
262 }
263
264 /************************************/
265 /* HW Attach, Detach, Init Routines */
266 /************************************/
267
268 static void ath9k_hw_disablepcie(struct ath_hw *ah)
269 {
270 if (AR_SREV_9100(ah))
271 return;
272
273 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
274 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
275 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
282
283 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
284 }
285
286 static bool ath9k_hw_chip_test(struct ath_hw *ah)
287 {
288 struct ath_common *common = ath9k_hw_common(ah);
289 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
290 u32 regHold[2];
291 u32 patternData[4] = { 0x55555555,
292 0xaaaaaaaa,
293 0x66666666,
294 0x99999999 };
295 int i, j;
296
297 for (i = 0; i < 2; i++) {
298 u32 addr = regAddr[i];
299 u32 wrData, rdData;
300
301 regHold[i] = REG_READ(ah, addr);
302 for (j = 0; j < 0x100; j++) {
303 wrData = (j << 16) | j;
304 REG_WRITE(ah, addr, wrData);
305 rdData = REG_READ(ah, addr);
306 if (rdData != wrData) {
307 ath_print(common, ATH_DBG_FATAL,
308 "address test failed "
309 "addr: 0x%08x - wr:0x%08x != "
310 "rd:0x%08x\n",
311 addr, wrData, rdData);
312 return false;
313 }
314 }
315 for (j = 0; j < 4; j++) {
316 wrData = patternData[j];
317 REG_WRITE(ah, addr, wrData);
318 rdData = REG_READ(ah, addr);
319 if (wrData != rdData) {
320 ath_print(common, ATH_DBG_FATAL,
321 "address test failed "
322 "addr: 0x%08x - wr:0x%08x != "
323 "rd:0x%08x\n",
324 addr, wrData, rdData);
325 return false;
326 }
327 }
328 REG_WRITE(ah, regAddr[i], regHold[i]);
329 }
330 udelay(100);
331
332 return true;
333 }
334
335 static const char *ath9k_hw_devname(u16 devid)
336 {
337 switch (devid) {
338 case AR5416_DEVID_PCI:
339 return "Atheros 5416";
340 case AR5416_DEVID_PCIE:
341 return "Atheros 5418";
342 case AR9160_DEVID_PCI:
343 return "Atheros 9160";
344 case AR5416_AR9100_DEVID:
345 return "Atheros 9100";
346 case AR9280_DEVID_PCI:
347 case AR9280_DEVID_PCIE:
348 return "Atheros 9280";
349 case AR9285_DEVID_PCIE:
350 return "Atheros 9285";
351 case AR5416_DEVID_AR9287_PCI:
352 case AR5416_DEVID_AR9287_PCIE:
353 return "Atheros 9287";
354 }
355
356 return NULL;
357 }
358
359 static void ath9k_hw_init_config(struct ath_hw *ah)
360 {
361 int i;
362
363 ah->config.dma_beacon_response_time = 2;
364 ah->config.sw_beacon_response_time = 10;
365 ah->config.additional_swba_backoff = 0;
366 ah->config.ack_6mb = 0x0;
367 ah->config.cwm_ignore_extcca = 0;
368 ah->config.pcie_powersave_enable = 0;
369 ah->config.pcie_clock_req = 0;
370 ah->config.pcie_waen = 0;
371 ah->config.analog_shiftreg = 1;
372 ah->config.ht_enable = 1;
373 ah->config.ofdm_trig_low = 200;
374 ah->config.ofdm_trig_high = 500;
375 ah->config.cck_trig_high = 200;
376 ah->config.cck_trig_low = 100;
377 ah->config.enable_ani = 1;
378 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
379 ah->config.antenna_switch_swap = 0;
380
381 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
382 ah->config.spurchans[i][0] = AR_NO_SPUR;
383 ah->config.spurchans[i][1] = AR_NO_SPUR;
384 }
385
386 ah->config.intr_mitigation = true;
387
388 /*
389 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
390 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
391 * This means we use it for all AR5416 devices, and the few
392 * minor PCI AR9280 devices out there.
393 *
394 * Serialization is required because these devices do not handle
395 * well the case of two concurrent reads/writes due to the latency
396 * involved. During one read/write another read/write can be issued
397 * on another CPU while the previous read/write may still be working
398 * on our hardware, if we hit this case the hardware poops in a loop.
399 * We prevent this by serializing reads and writes.
400 *
401 * This issue is not present on PCI-Express devices or pre-AR5416
402 * devices (legacy, 802.11abg).
403 */
404 if (num_possible_cpus() > 1)
405 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
406 }
407
408 static void ath9k_hw_init_defaults(struct ath_hw *ah)
409 {
410 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
411
412 regulatory->country_code = CTRY_DEFAULT;
413 regulatory->power_limit = MAX_RATE_POWER;
414 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
415
416 ah->hw_version.magic = AR5416_MAGIC;
417 ah->hw_version.subvendorid = 0;
418
419 ah->ah_flags = 0;
420 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
421 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
422 if (!AR_SREV_9100(ah))
423 ah->ah_flags = AH_USE_EEPROM;
424
425 ah->atim_window = 0;
426 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
427 ah->beacon_interval = 100;
428 ah->enable_32kHz_clock = DONT_USE_32KHZ;
429 ah->slottime = (u32) -1;
430 ah->acktimeout = (u32) -1;
431 ah->ctstimeout = (u32) -1;
432 ah->globaltxtimeout = (u32) -1;
433
434 ah->gbeacon_rate = 0;
435
436 ah->power_mode = ATH9K_PM_UNDEFINED;
437 }
438
439 static int ath9k_hw_rfattach(struct ath_hw *ah)
440 {
441 bool rfStatus = false;
442 int ecode = 0;
443
444 rfStatus = ath9k_hw_init_rf(ah, &ecode);
445 if (!rfStatus) {
446 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
447 "RF setup failed, status: %u\n", ecode);
448 return ecode;
449 }
450
451 return 0;
452 }
453
454 static int ath9k_hw_rf_claim(struct ath_hw *ah)
455 {
456 u32 val;
457
458 REG_WRITE(ah, AR_PHY(0), 0x00000007);
459
460 val = ath9k_hw_get_radiorev(ah);
461 switch (val & AR_RADIO_SREV_MAJOR) {
462 case 0:
463 val = AR_RAD5133_SREV_MAJOR;
464 break;
465 case AR_RAD5133_SREV_MAJOR:
466 case AR_RAD5122_SREV_MAJOR:
467 case AR_RAD2133_SREV_MAJOR:
468 case AR_RAD2122_SREV_MAJOR:
469 break;
470 default:
471 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
472 "Radio Chip Rev 0x%02X not supported\n",
473 val & AR_RADIO_SREV_MAJOR);
474 return -EOPNOTSUPP;
475 }
476
477 ah->hw_version.analog5GhzRev = val;
478
479 return 0;
480 }
481
482 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
483 {
484 struct ath_common *common = ath9k_hw_common(ah);
485 u32 sum;
486 int i;
487 u16 eeval;
488
489 sum = 0;
490 for (i = 0; i < 3; i++) {
491 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
492 sum += eeval;
493 common->macaddr[2 * i] = eeval >> 8;
494 common->macaddr[2 * i + 1] = eeval & 0xff;
495 }
496 if (sum == 0 || sum == 0xffff * 3)
497 return -EADDRNOTAVAIL;
498
499 return 0;
500 }
501
502 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
503 {
504 u32 rxgain_type;
505
506 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
507 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
508
509 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
510 INIT_INI_ARRAY(&ah->iniModesRxGain,
511 ar9280Modes_backoff_13db_rxgain_9280_2,
512 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
513 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
514 INIT_INI_ARRAY(&ah->iniModesRxGain,
515 ar9280Modes_backoff_23db_rxgain_9280_2,
516 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
517 else
518 INIT_INI_ARRAY(&ah->iniModesRxGain,
519 ar9280Modes_original_rxgain_9280_2,
520 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
521 } else {
522 INIT_INI_ARRAY(&ah->iniModesRxGain,
523 ar9280Modes_original_rxgain_9280_2,
524 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
525 }
526 }
527
528 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
529 {
530 u32 txgain_type;
531
532 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
533 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
534
535 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
536 INIT_INI_ARRAY(&ah->iniModesTxGain,
537 ar9280Modes_high_power_tx_gain_9280_2,
538 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
539 else
540 INIT_INI_ARRAY(&ah->iniModesTxGain,
541 ar9280Modes_original_tx_gain_9280_2,
542 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
543 } else {
544 INIT_INI_ARRAY(&ah->iniModesTxGain,
545 ar9280Modes_original_tx_gain_9280_2,
546 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
547 }
548 }
549
550 static int ath9k_hw_post_init(struct ath_hw *ah)
551 {
552 int ecode;
553
554 if (!ath9k_hw_chip_test(ah))
555 return -ENODEV;
556
557 ecode = ath9k_hw_rf_claim(ah);
558 if (ecode != 0)
559 return ecode;
560
561 ecode = ath9k_hw_eeprom_init(ah);
562 if (ecode != 0)
563 return ecode;
564
565 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
566 "Eeprom VER: %d, REV: %d\n",
567 ah->eep_ops->get_eeprom_ver(ah),
568 ah->eep_ops->get_eeprom_rev(ah));
569
570 ecode = ath9k_hw_rfattach(ah);
571 if (ecode != 0)
572 return ecode;
573
574 if (!AR_SREV_9100(ah)) {
575 ath9k_hw_ani_setup(ah);
576 ath9k_hw_ani_init(ah);
577 }
578
579 return 0;
580 }
581
582 static bool ath9k_hw_devid_supported(u16 devid)
583 {
584 switch (devid) {
585 case AR5416_DEVID_PCI:
586 case AR5416_DEVID_PCIE:
587 case AR5416_AR9100_DEVID:
588 case AR9160_DEVID_PCI:
589 case AR9280_DEVID_PCI:
590 case AR9280_DEVID_PCIE:
591 case AR9285_DEVID_PCIE:
592 case AR5416_DEVID_AR9287_PCI:
593 case AR5416_DEVID_AR9287_PCIE:
594 return true;
595 default:
596 break;
597 }
598 return false;
599 }
600
601 static bool ath9k_hw_macversion_supported(u32 macversion)
602 {
603 switch (macversion) {
604 case AR_SREV_VERSION_5416_PCI:
605 case AR_SREV_VERSION_5416_PCIE:
606 case AR_SREV_VERSION_9160:
607 case AR_SREV_VERSION_9100:
608 case AR_SREV_VERSION_9280:
609 case AR_SREV_VERSION_9285:
610 case AR_SREV_VERSION_9287:
611 return true;
612 /* Not yet */
613 case AR_SREV_VERSION_9271:
614 default:
615 break;
616 }
617 return false;
618 }
619
620 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
621 {
622 if (AR_SREV_9160_10_OR_LATER(ah)) {
623 if (AR_SREV_9280_10_OR_LATER(ah)) {
624 ah->iq_caldata.calData = &iq_cal_single_sample;
625 ah->adcgain_caldata.calData =
626 &adc_gain_cal_single_sample;
627 ah->adcdc_caldata.calData =
628 &adc_dc_cal_single_sample;
629 ah->adcdc_calinitdata.calData =
630 &adc_init_dc_cal;
631 } else {
632 ah->iq_caldata.calData = &iq_cal_multi_sample;
633 ah->adcgain_caldata.calData =
634 &adc_gain_cal_multi_sample;
635 ah->adcdc_caldata.calData =
636 &adc_dc_cal_multi_sample;
637 ah->adcdc_calinitdata.calData =
638 &adc_init_dc_cal;
639 }
640 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
641 }
642 }
643
644 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
645 {
646 if (AR_SREV_9271(ah)) {
647 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
648 ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
649 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
650 ARRAY_SIZE(ar9271Common_9271_1_0), 2);
651 return;
652 }
653
654 if (AR_SREV_9287_11_OR_LATER(ah)) {
655 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
656 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
657 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
658 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
659 if (ah->config.pcie_clock_req)
660 INIT_INI_ARRAY(&ah->iniPcieSerdes,
661 ar9287PciePhy_clkreq_off_L1_9287_1_1,
662 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
663 else
664 INIT_INI_ARRAY(&ah->iniPcieSerdes,
665 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
666 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
667 2);
668 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
669 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
670 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
671 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
672 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
673
674 if (ah->config.pcie_clock_req)
675 INIT_INI_ARRAY(&ah->iniPcieSerdes,
676 ar9287PciePhy_clkreq_off_L1_9287_1_0,
677 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
678 else
679 INIT_INI_ARRAY(&ah->iniPcieSerdes,
680 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
681 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
682 2);
683 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
684
685
686 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
687 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
688 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
689 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
690
691 if (ah->config.pcie_clock_req) {
692 INIT_INI_ARRAY(&ah->iniPcieSerdes,
693 ar9285PciePhy_clkreq_off_L1_9285_1_2,
694 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
695 } else {
696 INIT_INI_ARRAY(&ah->iniPcieSerdes,
697 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
698 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
699 2);
700 }
701 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
702 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
703 ARRAY_SIZE(ar9285Modes_9285), 6);
704 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
705 ARRAY_SIZE(ar9285Common_9285), 2);
706
707 if (ah->config.pcie_clock_req) {
708 INIT_INI_ARRAY(&ah->iniPcieSerdes,
709 ar9285PciePhy_clkreq_off_L1_9285,
710 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
711 } else {
712 INIT_INI_ARRAY(&ah->iniPcieSerdes,
713 ar9285PciePhy_clkreq_always_on_L1_9285,
714 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
715 }
716 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
717 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
718 ARRAY_SIZE(ar9280Modes_9280_2), 6);
719 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
720 ARRAY_SIZE(ar9280Common_9280_2), 2);
721
722 if (ah->config.pcie_clock_req) {
723 INIT_INI_ARRAY(&ah->iniPcieSerdes,
724 ar9280PciePhy_clkreq_off_L1_9280,
725 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
726 } else {
727 INIT_INI_ARRAY(&ah->iniPcieSerdes,
728 ar9280PciePhy_clkreq_always_on_L1_9280,
729 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
730 }
731 INIT_INI_ARRAY(&ah->iniModesAdditional,
732 ar9280Modes_fast_clock_9280_2,
733 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
734 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
735 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
736 ARRAY_SIZE(ar9280Modes_9280), 6);
737 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
738 ARRAY_SIZE(ar9280Common_9280), 2);
739 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
740 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
741 ARRAY_SIZE(ar5416Modes_9160), 6);
742 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
743 ARRAY_SIZE(ar5416Common_9160), 2);
744 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
745 ARRAY_SIZE(ar5416Bank0_9160), 2);
746 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
747 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
748 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
749 ARRAY_SIZE(ar5416Bank1_9160), 2);
750 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
751 ARRAY_SIZE(ar5416Bank2_9160), 2);
752 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
753 ARRAY_SIZE(ar5416Bank3_9160), 3);
754 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
755 ARRAY_SIZE(ar5416Bank6_9160), 3);
756 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
757 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
758 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
759 ARRAY_SIZE(ar5416Bank7_9160), 2);
760 if (AR_SREV_9160_11(ah)) {
761 INIT_INI_ARRAY(&ah->iniAddac,
762 ar5416Addac_91601_1,
763 ARRAY_SIZE(ar5416Addac_91601_1), 2);
764 } else {
765 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
766 ARRAY_SIZE(ar5416Addac_9160), 2);
767 }
768 } else if (AR_SREV_9100_OR_LATER(ah)) {
769 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
770 ARRAY_SIZE(ar5416Modes_9100), 6);
771 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
772 ARRAY_SIZE(ar5416Common_9100), 2);
773 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
774 ARRAY_SIZE(ar5416Bank0_9100), 2);
775 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
776 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
777 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
778 ARRAY_SIZE(ar5416Bank1_9100), 2);
779 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
780 ARRAY_SIZE(ar5416Bank2_9100), 2);
781 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
782 ARRAY_SIZE(ar5416Bank3_9100), 3);
783 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
784 ARRAY_SIZE(ar5416Bank6_9100), 3);
785 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
786 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
787 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
788 ARRAY_SIZE(ar5416Bank7_9100), 2);
789 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
790 ARRAY_SIZE(ar5416Addac_9100), 2);
791 } else {
792 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
793 ARRAY_SIZE(ar5416Modes), 6);
794 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
795 ARRAY_SIZE(ar5416Common), 2);
796 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
797 ARRAY_SIZE(ar5416Bank0), 2);
798 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
799 ARRAY_SIZE(ar5416BB_RfGain), 3);
800 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
801 ARRAY_SIZE(ar5416Bank1), 2);
802 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
803 ARRAY_SIZE(ar5416Bank2), 2);
804 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
805 ARRAY_SIZE(ar5416Bank3), 3);
806 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
807 ARRAY_SIZE(ar5416Bank6), 3);
808 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
809 ARRAY_SIZE(ar5416Bank6TPC), 3);
810 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
811 ARRAY_SIZE(ar5416Bank7), 2);
812 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
813 ARRAY_SIZE(ar5416Addac), 2);
814 }
815 }
816
817 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
818 {
819 if (AR_SREV_9287_11_OR_LATER(ah))
820 INIT_INI_ARRAY(&ah->iniModesRxGain,
821 ar9287Modes_rx_gain_9287_1_1,
822 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
823 else if (AR_SREV_9287_10(ah))
824 INIT_INI_ARRAY(&ah->iniModesRxGain,
825 ar9287Modes_rx_gain_9287_1_0,
826 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
827 else if (AR_SREV_9280_20(ah))
828 ath9k_hw_init_rxgain_ini(ah);
829
830 if (AR_SREV_9287_11_OR_LATER(ah)) {
831 INIT_INI_ARRAY(&ah->iniModesTxGain,
832 ar9287Modes_tx_gain_9287_1_1,
833 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
834 } else if (AR_SREV_9287_10(ah)) {
835 INIT_INI_ARRAY(&ah->iniModesTxGain,
836 ar9287Modes_tx_gain_9287_1_0,
837 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
838 } else if (AR_SREV_9280_20(ah)) {
839 ath9k_hw_init_txgain_ini(ah);
840 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
841 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
842
843 /* txgain table */
844 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
845 INIT_INI_ARRAY(&ah->iniModesTxGain,
846 ar9285Modes_high_power_tx_gain_9285_1_2,
847 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
848 } else {
849 INIT_INI_ARRAY(&ah->iniModesTxGain,
850 ar9285Modes_original_tx_gain_9285_1_2,
851 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
852 }
853
854 }
855 }
856
857 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
858 {
859 u32 i, j;
860
861 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
862 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
863
864 /* EEPROM Fixup */
865 for (i = 0; i < ah->iniModes.ia_rows; i++) {
866 u32 reg = INI_RA(&ah->iniModes, i, 0);
867
868 for (j = 1; j < ah->iniModes.ia_columns; j++) {
869 u32 val = INI_RA(&ah->iniModes, i, j);
870
871 INI_RA(&ah->iniModes, i, j) =
872 ath9k_hw_ini_fixup(ah,
873 &ah->eeprom.def,
874 reg, val);
875 }
876 }
877 }
878 }
879
880 int ath9k_hw_init(struct ath_hw *ah)
881 {
882 struct ath_common *common = ath9k_hw_common(ah);
883 int r = 0;
884
885 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
886 return -EOPNOTSUPP;
887
888 ath9k_hw_init_defaults(ah);
889 ath9k_hw_init_config(ah);
890
891 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
892 ath_print(common, ATH_DBG_FATAL,
893 "Couldn't reset chip\n");
894 return -EIO;
895 }
896
897 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
898 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
899 return -EIO;
900 }
901
902 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
903 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
904 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
905 ah->config.serialize_regmode =
906 SER_REG_MODE_ON;
907 } else {
908 ah->config.serialize_regmode =
909 SER_REG_MODE_OFF;
910 }
911 }
912
913 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
914 ah->config.serialize_regmode);
915
916 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
917 ath_print(common, ATH_DBG_FATAL,
918 "Mac Chip Rev 0x%02x.%x is not supported by "
919 "this driver\n", ah->hw_version.macVersion,
920 ah->hw_version.macRev);
921 return -EOPNOTSUPP;
922 }
923
924 if (AR_SREV_9100(ah)) {
925 ah->iq_caldata.calData = &iq_cal_multi_sample;
926 ah->supp_cals = IQ_MISMATCH_CAL;
927 ah->is_pciexpress = false;
928 }
929
930 if (AR_SREV_9271(ah))
931 ah->is_pciexpress = false;
932
933 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
934
935 ath9k_hw_init_cal_settings(ah);
936
937 ah->ani_function = ATH9K_ANI_ALL;
938 if (AR_SREV_9280_10_OR_LATER(ah))
939 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
940
941 ath9k_hw_init_mode_regs(ah);
942
943 if (ah->is_pciexpress)
944 ath9k_hw_configpcipowersave(ah, 0, 0);
945 else
946 ath9k_hw_disablepcie(ah);
947
948 r = ath9k_hw_post_init(ah);
949 if (r)
950 return r;
951
952 ath9k_hw_init_mode_gain_regs(ah);
953 ath9k_hw_fill_cap_info(ah);
954 ath9k_hw_init_11a_eeprom_fix(ah);
955
956 r = ath9k_hw_init_macaddr(ah);
957 if (r) {
958 ath_print(common, ATH_DBG_FATAL,
959 "Failed to initialize MAC address\n");
960 return r;
961 }
962
963 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
964 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
965 else
966 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
967
968 ath9k_init_nfcal_hist_buffer(ah);
969
970 return 0;
971 }
972
973 static void ath9k_hw_init_bb(struct ath_hw *ah,
974 struct ath9k_channel *chan)
975 {
976 u32 synthDelay;
977
978 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
979 if (IS_CHAN_B(chan))
980 synthDelay = (4 * synthDelay) / 22;
981 else
982 synthDelay /= 10;
983
984 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
985
986 udelay(synthDelay + BASE_ACTIVATE_DELAY);
987 }
988
989 static void ath9k_hw_init_qos(struct ath_hw *ah)
990 {
991 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
992 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
993
994 REG_WRITE(ah, AR_QOS_NO_ACK,
995 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
996 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
997 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
998
999 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1000 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1001 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1002 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1003 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1004 }
1005
1006 static void ath9k_hw_init_pll(struct ath_hw *ah,
1007 struct ath9k_channel *chan)
1008 {
1009 u32 pll;
1010
1011 if (AR_SREV_9100(ah)) {
1012 if (chan && IS_CHAN_5GHZ(chan))
1013 pll = 0x1450;
1014 else
1015 pll = 0x1458;
1016 } else {
1017 if (AR_SREV_9280_10_OR_LATER(ah)) {
1018 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1019
1020 if (chan && IS_CHAN_HALF_RATE(chan))
1021 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1022 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1023 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1024
1025 if (chan && IS_CHAN_5GHZ(chan)) {
1026 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1027
1028
1029 if (AR_SREV_9280_20(ah)) {
1030 if (((chan->channel % 20) == 0)
1031 || ((chan->channel % 10) == 0))
1032 pll = 0x2850;
1033 else
1034 pll = 0x142c;
1035 }
1036 } else {
1037 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1038 }
1039
1040 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1041
1042 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1043
1044 if (chan && IS_CHAN_HALF_RATE(chan))
1045 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1046 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1047 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1048
1049 if (chan && IS_CHAN_5GHZ(chan))
1050 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1051 else
1052 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1053 } else {
1054 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1055
1056 if (chan && IS_CHAN_HALF_RATE(chan))
1057 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1058 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1059 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1060
1061 if (chan && IS_CHAN_5GHZ(chan))
1062 pll |= SM(0xa, AR_RTC_PLL_DIV);
1063 else
1064 pll |= SM(0xb, AR_RTC_PLL_DIV);
1065 }
1066 }
1067 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1068
1069 udelay(RTC_PLL_SETTLE_DELAY);
1070
1071 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1072 }
1073
1074 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1075 {
1076 int rx_chainmask, tx_chainmask;
1077
1078 rx_chainmask = ah->rxchainmask;
1079 tx_chainmask = ah->txchainmask;
1080
1081 switch (rx_chainmask) {
1082 case 0x5:
1083 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1084 AR_PHY_SWAP_ALT_CHAIN);
1085 case 0x3:
1086 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1087 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1088 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1089 break;
1090 }
1091 case 0x1:
1092 case 0x2:
1093 case 0x7:
1094 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1095 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1096 break;
1097 default:
1098 break;
1099 }
1100
1101 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1102 if (tx_chainmask == 0x5) {
1103 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1104 AR_PHY_SWAP_ALT_CHAIN);
1105 }
1106 if (AR_SREV_9100(ah))
1107 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1108 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1109 }
1110
1111 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1112 enum nl80211_iftype opmode)
1113 {
1114 ah->mask_reg = AR_IMR_TXERR |
1115 AR_IMR_TXURN |
1116 AR_IMR_RXERR |
1117 AR_IMR_RXORN |
1118 AR_IMR_BCNMISC;
1119
1120 if (ah->config.intr_mitigation)
1121 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1122 else
1123 ah->mask_reg |= AR_IMR_RXOK;
1124
1125 ah->mask_reg |= AR_IMR_TXOK;
1126
1127 if (opmode == NL80211_IFTYPE_AP)
1128 ah->mask_reg |= AR_IMR_MIB;
1129
1130 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1131 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1132
1133 if (!AR_SREV_9100(ah)) {
1134 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1135 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1136 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1137 }
1138 }
1139
1140 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1141 {
1142 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1143 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1144 "bad ack timeout %u\n", us);
1145 ah->acktimeout = (u32) -1;
1146 return false;
1147 } else {
1148 REG_RMW_FIELD(ah, AR_TIME_OUT,
1149 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1150 ah->acktimeout = us;
1151 return true;
1152 }
1153 }
1154
1155 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1156 {
1157 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1158 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1159 "bad cts timeout %u\n", us);
1160 ah->ctstimeout = (u32) -1;
1161 return false;
1162 } else {
1163 REG_RMW_FIELD(ah, AR_TIME_OUT,
1164 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1165 ah->ctstimeout = us;
1166 return true;
1167 }
1168 }
1169
1170 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1171 {
1172 if (tu > 0xFFFF) {
1173 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1174 "bad global tx timeout %u\n", tu);
1175 ah->globaltxtimeout = (u32) -1;
1176 return false;
1177 } else {
1178 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1179 ah->globaltxtimeout = tu;
1180 return true;
1181 }
1182 }
1183
1184 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1185 {
1186 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1187 ah->misc_mode);
1188
1189 if (ah->misc_mode != 0)
1190 REG_WRITE(ah, AR_PCU_MISC,
1191 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1192 if (ah->slottime != (u32) -1)
1193 ath9k_hw_setslottime(ah, ah->slottime);
1194 if (ah->acktimeout != (u32) -1)
1195 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1196 if (ah->ctstimeout != (u32) -1)
1197 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1198 if (ah->globaltxtimeout != (u32) -1)
1199 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1200 }
1201
1202 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1203 {
1204 return vendorid == ATHEROS_VENDOR_ID ?
1205 ath9k_hw_devname(devid) : NULL;
1206 }
1207
1208 void ath9k_hw_detach(struct ath_hw *ah)
1209 {
1210 if (!AR_SREV_9100(ah))
1211 ath9k_hw_ani_disable(ah);
1212
1213 ath9k_hw_rf_free(ah);
1214 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1215 kfree(ah);
1216 ah = NULL;
1217 }
1218
1219 /*******/
1220 /* INI */
1221 /*******/
1222
1223 static void ath9k_hw_override_ini(struct ath_hw *ah,
1224 struct ath9k_channel *chan)
1225 {
1226 u32 val;
1227
1228 if (AR_SREV_9271(ah)) {
1229 /*
1230 * Enable spectral scan to solution for issues with stuck
1231 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1232 * AR9271 1.1
1233 */
1234 if (AR_SREV_9271_10(ah)) {
1235 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1236 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1237 }
1238 else if (AR_SREV_9271_11(ah))
1239 /*
1240 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1241 * present on AR9271 1.1
1242 */
1243 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1244 return;
1245 }
1246
1247 /*
1248 * Set the RX_ABORT and RX_DIS and clear if off only after
1249 * RXE is set for MAC. This prevents frames with corrupted
1250 * descriptor status.
1251 */
1252 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1253
1254 if (AR_SREV_9280_10_OR_LATER(ah)) {
1255 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1256 (~AR_PCU_MISC_MODE2_HWWAR1);
1257
1258 if (AR_SREV_9287_10_OR_LATER(ah))
1259 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1260
1261 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1262 }
1263
1264 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1265 AR_SREV_9280_10_OR_LATER(ah))
1266 return;
1267 /*
1268 * Disable BB clock gating
1269 * Necessary to avoid issues on AR5416 2.0
1270 */
1271 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1272 }
1273
1274 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1275 struct ar5416_eeprom_def *pEepData,
1276 u32 reg, u32 value)
1277 {
1278 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1279 struct ath_common *common = ath9k_hw_common(ah);
1280
1281 switch (ah->hw_version.devid) {
1282 case AR9280_DEVID_PCI:
1283 if (reg == 0x7894) {
1284 ath_print(common, ATH_DBG_EEPROM,
1285 "ini VAL: %x EEPROM: %x\n", value,
1286 (pBase->version & 0xff));
1287
1288 if ((pBase->version & 0xff) > 0x0a) {
1289 ath_print(common, ATH_DBG_EEPROM,
1290 "PWDCLKIND: %d\n",
1291 pBase->pwdclkind);
1292 value &= ~AR_AN_TOP2_PWDCLKIND;
1293 value |= AR_AN_TOP2_PWDCLKIND &
1294 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1295 } else {
1296 ath_print(common, ATH_DBG_EEPROM,
1297 "PWDCLKIND Earlier Rev\n");
1298 }
1299
1300 ath_print(common, ATH_DBG_EEPROM,
1301 "final ini VAL: %x\n", value);
1302 }
1303 break;
1304 }
1305
1306 return value;
1307 }
1308
1309 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1310 struct ar5416_eeprom_def *pEepData,
1311 u32 reg, u32 value)
1312 {
1313 if (ah->eep_map == EEP_MAP_4KBITS)
1314 return value;
1315 else
1316 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1317 }
1318
1319 static void ath9k_olc_init(struct ath_hw *ah)
1320 {
1321 u32 i;
1322
1323 if (OLC_FOR_AR9287_10_LATER) {
1324 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1325 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1326 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1327 AR9287_AN_TXPC0_TXPCMODE,
1328 AR9287_AN_TXPC0_TXPCMODE_S,
1329 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1330 udelay(100);
1331 } else {
1332 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1333 ah->originalGain[i] =
1334 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1335 AR_PHY_TX_GAIN);
1336 ah->PDADCdelta = 0;
1337 }
1338 }
1339
1340 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1341 struct ath9k_channel *chan)
1342 {
1343 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1344
1345 if (IS_CHAN_B(chan))
1346 ctl |= CTL_11B;
1347 else if (IS_CHAN_G(chan))
1348 ctl |= CTL_11G;
1349 else
1350 ctl |= CTL_11A;
1351
1352 return ctl;
1353 }
1354
1355 static int ath9k_hw_process_ini(struct ath_hw *ah,
1356 struct ath9k_channel *chan,
1357 enum ath9k_ht_macmode macmode)
1358 {
1359 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1360 int i, regWrites = 0;
1361 struct ieee80211_channel *channel = chan->chan;
1362 u32 modesIndex, freqIndex;
1363
1364 switch (chan->chanmode) {
1365 case CHANNEL_A:
1366 case CHANNEL_A_HT20:
1367 modesIndex = 1;
1368 freqIndex = 1;
1369 break;
1370 case CHANNEL_A_HT40PLUS:
1371 case CHANNEL_A_HT40MINUS:
1372 modesIndex = 2;
1373 freqIndex = 1;
1374 break;
1375 case CHANNEL_G:
1376 case CHANNEL_G_HT20:
1377 case CHANNEL_B:
1378 modesIndex = 4;
1379 freqIndex = 2;
1380 break;
1381 case CHANNEL_G_HT40PLUS:
1382 case CHANNEL_G_HT40MINUS:
1383 modesIndex = 3;
1384 freqIndex = 2;
1385 break;
1386
1387 default:
1388 return -EINVAL;
1389 }
1390
1391 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1392 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1393 ah->eep_ops->set_addac(ah, chan);
1394
1395 if (AR_SREV_5416_22_OR_LATER(ah)) {
1396 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1397 } else {
1398 struct ar5416IniArray temp;
1399 u32 addacSize =
1400 sizeof(u32) * ah->iniAddac.ia_rows *
1401 ah->iniAddac.ia_columns;
1402
1403 memcpy(ah->addac5416_21,
1404 ah->iniAddac.ia_array, addacSize);
1405
1406 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1407
1408 temp.ia_array = ah->addac5416_21;
1409 temp.ia_columns = ah->iniAddac.ia_columns;
1410 temp.ia_rows = ah->iniAddac.ia_rows;
1411 REG_WRITE_ARRAY(&temp, 1, regWrites);
1412 }
1413
1414 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1415
1416 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1417 u32 reg = INI_RA(&ah->iniModes, i, 0);
1418 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1419
1420 REG_WRITE(ah, reg, val);
1421
1422 if (reg >= 0x7800 && reg < 0x78a0
1423 && ah->config.analog_shiftreg) {
1424 udelay(100);
1425 }
1426
1427 DO_DELAY(regWrites);
1428 }
1429
1430 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1431 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1432
1433 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1434 AR_SREV_9287_10_OR_LATER(ah))
1435 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1436
1437 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1438 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1439 u32 val = INI_RA(&ah->iniCommon, i, 1);
1440
1441 REG_WRITE(ah, reg, val);
1442
1443 if (reg >= 0x7800 && reg < 0x78a0
1444 && ah->config.analog_shiftreg) {
1445 udelay(100);
1446 }
1447
1448 DO_DELAY(regWrites);
1449 }
1450
1451 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1452
1453 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1454 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1455 regWrites);
1456 }
1457
1458 ath9k_hw_override_ini(ah, chan);
1459 ath9k_hw_set_regs(ah, chan, macmode);
1460 ath9k_hw_init_chain_masks(ah);
1461
1462 if (OLC_FOR_AR9280_20_LATER)
1463 ath9k_olc_init(ah);
1464
1465 ah->eep_ops->set_txpower(ah, chan,
1466 ath9k_regd_get_ctl(regulatory, chan),
1467 channel->max_antenna_gain * 2,
1468 channel->max_power * 2,
1469 min((u32) MAX_RATE_POWER,
1470 (u32) regulatory->power_limit));
1471
1472 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1473 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1474 "ar5416SetRfRegs failed\n");
1475 return -EIO;
1476 }
1477
1478 return 0;
1479 }
1480
1481 /****************************************/
1482 /* Reset and Channel Switching Routines */
1483 /****************************************/
1484
1485 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1486 {
1487 u32 rfMode = 0;
1488
1489 if (chan == NULL)
1490 return;
1491
1492 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1493 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1494
1495 if (!AR_SREV_9280_10_OR_LATER(ah))
1496 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1497 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1498
1499 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1500 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1501
1502 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1503 }
1504
1505 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1506 {
1507 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1508 }
1509
1510 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1511 {
1512 u32 regval;
1513
1514 /*
1515 * set AHB_MODE not to do cacheline prefetches
1516 */
1517 regval = REG_READ(ah, AR_AHB_MODE);
1518 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1519
1520 /*
1521 * let mac dma reads be in 128 byte chunks
1522 */
1523 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1524 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1525
1526 /*
1527 * Restore TX Trigger Level to its pre-reset value.
1528 * The initial value depends on whether aggregation is enabled, and is
1529 * adjusted whenever underruns are detected.
1530 */
1531 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1532
1533 /*
1534 * let mac dma writes be in 128 byte chunks
1535 */
1536 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1537 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1538
1539 /*
1540 * Setup receive FIFO threshold to hold off TX activities
1541 */
1542 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1543
1544 /*
1545 * reduce the number of usable entries in PCU TXBUF to avoid
1546 * wrap around issues.
1547 */
1548 if (AR_SREV_9285(ah)) {
1549 /* For AR9285 the number of Fifos are reduced to half.
1550 * So set the usable tx buf size also to half to
1551 * avoid data/delimiter underruns
1552 */
1553 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1554 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1555 } else if (!AR_SREV_9271(ah)) {
1556 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1557 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1558 }
1559 }
1560
1561 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1562 {
1563 u32 val;
1564
1565 val = REG_READ(ah, AR_STA_ID1);
1566 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1567 switch (opmode) {
1568 case NL80211_IFTYPE_AP:
1569 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1570 | AR_STA_ID1_KSRCH_MODE);
1571 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1572 break;
1573 case NL80211_IFTYPE_ADHOC:
1574 case NL80211_IFTYPE_MESH_POINT:
1575 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1576 | AR_STA_ID1_KSRCH_MODE);
1577 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1578 break;
1579 case NL80211_IFTYPE_STATION:
1580 case NL80211_IFTYPE_MONITOR:
1581 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1582 break;
1583 }
1584 }
1585
1586 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1587 u32 coef_scaled,
1588 u32 *coef_mantissa,
1589 u32 *coef_exponent)
1590 {
1591 u32 coef_exp, coef_man;
1592
1593 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1594 if ((coef_scaled >> coef_exp) & 0x1)
1595 break;
1596
1597 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1598
1599 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1600
1601 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1602 *coef_exponent = coef_exp - 16;
1603 }
1604
1605 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1606 struct ath9k_channel *chan)
1607 {
1608 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1609 u32 clockMhzScaled = 0x64000000;
1610 struct chan_centers centers;
1611
1612 if (IS_CHAN_HALF_RATE(chan))
1613 clockMhzScaled = clockMhzScaled >> 1;
1614 else if (IS_CHAN_QUARTER_RATE(chan))
1615 clockMhzScaled = clockMhzScaled >> 2;
1616
1617 ath9k_hw_get_channel_centers(ah, chan, &centers);
1618 coef_scaled = clockMhzScaled / centers.synth_center;
1619
1620 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1621 &ds_coef_exp);
1622
1623 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1624 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1625 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1626 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1627
1628 coef_scaled = (9 * coef_scaled) / 10;
1629
1630 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1631 &ds_coef_exp);
1632
1633 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1634 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1635 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1636 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1637 }
1638
1639 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1640 {
1641 u32 rst_flags;
1642 u32 tmpReg;
1643
1644 if (AR_SREV_9100(ah)) {
1645 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1646 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1647 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1648 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1649 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1650 }
1651
1652 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1653 AR_RTC_FORCE_WAKE_ON_INT);
1654
1655 if (AR_SREV_9100(ah)) {
1656 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1657 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1658 } else {
1659 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1660 if (tmpReg &
1661 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1662 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1663 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1664 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1665 } else {
1666 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1667 }
1668
1669 rst_flags = AR_RTC_RC_MAC_WARM;
1670 if (type == ATH9K_RESET_COLD)
1671 rst_flags |= AR_RTC_RC_MAC_COLD;
1672 }
1673
1674 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1675 udelay(50);
1676
1677 REG_WRITE(ah, AR_RTC_RC, 0);
1678 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1679 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1680 "RTC stuck in MAC reset\n");
1681 return false;
1682 }
1683
1684 if (!AR_SREV_9100(ah))
1685 REG_WRITE(ah, AR_RC, 0);
1686
1687 ath9k_hw_init_pll(ah, NULL);
1688
1689 if (AR_SREV_9100(ah))
1690 udelay(50);
1691
1692 return true;
1693 }
1694
1695 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1696 {
1697 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1698 AR_RTC_FORCE_WAKE_ON_INT);
1699
1700 if (!AR_SREV_9100(ah))
1701 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1702
1703 REG_WRITE(ah, AR_RTC_RESET, 0);
1704 udelay(2);
1705
1706 if (!AR_SREV_9100(ah))
1707 REG_WRITE(ah, AR_RC, 0);
1708
1709 REG_WRITE(ah, AR_RTC_RESET, 1);
1710
1711 if (!ath9k_hw_wait(ah,
1712 AR_RTC_STATUS,
1713 AR_RTC_STATUS_M,
1714 AR_RTC_STATUS_ON,
1715 AH_WAIT_TIMEOUT)) {
1716 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1717 "RTC not waking up\n");
1718 return false;
1719 }
1720
1721 ath9k_hw_read_revisions(ah);
1722
1723 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1724 }
1725
1726 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1727 {
1728 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1729 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1730
1731 switch (type) {
1732 case ATH9K_RESET_POWER_ON:
1733 return ath9k_hw_set_reset_power_on(ah);
1734 case ATH9K_RESET_WARM:
1735 case ATH9K_RESET_COLD:
1736 return ath9k_hw_set_reset(ah, type);
1737 default:
1738 return false;
1739 }
1740 }
1741
1742 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1743 enum ath9k_ht_macmode macmode)
1744 {
1745 u32 phymode;
1746 u32 enableDacFifo = 0;
1747
1748 if (AR_SREV_9285_10_OR_LATER(ah))
1749 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1750 AR_PHY_FC_ENABLE_DAC_FIFO);
1751
1752 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1753 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1754
1755 if (IS_CHAN_HT40(chan)) {
1756 phymode |= AR_PHY_FC_DYN2040_EN;
1757
1758 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1759 (chan->chanmode == CHANNEL_G_HT40PLUS))
1760 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1761
1762 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1763 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1764 }
1765 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1766
1767 ath9k_hw_set11nmac2040(ah, macmode);
1768
1769 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1770 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1771 }
1772
1773 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1774 struct ath9k_channel *chan)
1775 {
1776 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1777 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1778 return false;
1779 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1780 return false;
1781
1782 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1783 return false;
1784
1785 ah->chip_fullsleep = false;
1786 ath9k_hw_init_pll(ah, chan);
1787 ath9k_hw_set_rfmode(ah, chan);
1788
1789 return true;
1790 }
1791
1792 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1793 struct ath9k_channel *chan,
1794 enum ath9k_ht_macmode macmode)
1795 {
1796 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1797 struct ath_common *common = ath9k_hw_common(ah);
1798 struct ieee80211_channel *channel = chan->chan;
1799 u32 synthDelay, qnum;
1800
1801 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1802 if (ath9k_hw_numtxpending(ah, qnum)) {
1803 ath_print(common, ATH_DBG_QUEUE,
1804 "Transmit frames pending on "
1805 "queue %d\n", qnum);
1806 return false;
1807 }
1808 }
1809
1810 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1811 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1812 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1813 ath_print(common, ATH_DBG_FATAL,
1814 "Could not kill baseband RX\n");
1815 return false;
1816 }
1817
1818 ath9k_hw_set_regs(ah, chan, macmode);
1819
1820 if (AR_SREV_9280_10_OR_LATER(ah)) {
1821 ath9k_hw_ar9280_set_channel(ah, chan);
1822 } else {
1823 if (!(ath9k_hw_set_channel(ah, chan))) {
1824 ath_print(common, ATH_DBG_FATAL,
1825 "Failed to set channel\n");
1826 return false;
1827 }
1828 }
1829
1830 ah->eep_ops->set_txpower(ah, chan,
1831 ath9k_regd_get_ctl(regulatory, chan),
1832 channel->max_antenna_gain * 2,
1833 channel->max_power * 2,
1834 min((u32) MAX_RATE_POWER,
1835 (u32) regulatory->power_limit));
1836
1837 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1838 if (IS_CHAN_B(chan))
1839 synthDelay = (4 * synthDelay) / 22;
1840 else
1841 synthDelay /= 10;
1842
1843 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1844
1845 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1846
1847 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1848 ath9k_hw_set_delta_slope(ah, chan);
1849
1850 if (AR_SREV_9280_10_OR_LATER(ah))
1851 ath9k_hw_9280_spur_mitigate(ah, chan);
1852 else
1853 ath9k_hw_spur_mitigate(ah, chan);
1854
1855 if (!chan->oneTimeCalsDone)
1856 chan->oneTimeCalsDone = true;
1857
1858 return true;
1859 }
1860
1861 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1862 {
1863 int bb_spur = AR_NO_SPUR;
1864 int freq;
1865 int bin, cur_bin;
1866 int bb_spur_off, spur_subchannel_sd;
1867 int spur_freq_sd;
1868 int spur_delta_phase;
1869 int denominator;
1870 int upper, lower, cur_vit_mask;
1871 int tmp, newVal;
1872 int i;
1873 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1874 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1875 };
1876 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1877 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1878 };
1879 int inc[4] = { 0, 100, 0, 0 };
1880 struct chan_centers centers;
1881
1882 int8_t mask_m[123];
1883 int8_t mask_p[123];
1884 int8_t mask_amt;
1885 int tmp_mask;
1886 int cur_bb_spur;
1887 bool is2GHz = IS_CHAN_2GHZ(chan);
1888
1889 memset(&mask_m, 0, sizeof(int8_t) * 123);
1890 memset(&mask_p, 0, sizeof(int8_t) * 123);
1891
1892 ath9k_hw_get_channel_centers(ah, chan, &centers);
1893 freq = centers.synth_center;
1894
1895 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1896 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1897 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1898
1899 if (is2GHz)
1900 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1901 else
1902 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1903
1904 if (AR_NO_SPUR == cur_bb_spur)
1905 break;
1906 cur_bb_spur = cur_bb_spur - freq;
1907
1908 if (IS_CHAN_HT40(chan)) {
1909 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1910 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1911 bb_spur = cur_bb_spur;
1912 break;
1913 }
1914 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1915 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1916 bb_spur = cur_bb_spur;
1917 break;
1918 }
1919 }
1920
1921 if (AR_NO_SPUR == bb_spur) {
1922 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1923 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1924 return;
1925 } else {
1926 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1927 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1928 }
1929
1930 bin = bb_spur * 320;
1931
1932 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1933
1934 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1935 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1936 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1937 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1938 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1939
1940 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1941 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1942 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1943 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1944 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1945 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1946
1947 if (IS_CHAN_HT40(chan)) {
1948 if (bb_spur < 0) {
1949 spur_subchannel_sd = 1;
1950 bb_spur_off = bb_spur + 10;
1951 } else {
1952 spur_subchannel_sd = 0;
1953 bb_spur_off = bb_spur - 10;
1954 }
1955 } else {
1956 spur_subchannel_sd = 0;
1957 bb_spur_off = bb_spur;
1958 }
1959
1960 if (IS_CHAN_HT40(chan))
1961 spur_delta_phase =
1962 ((bb_spur * 262144) /
1963 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1964 else
1965 spur_delta_phase =
1966 ((bb_spur * 524288) /
1967 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1968
1969 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1970 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1971
1972 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1973 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1974 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1975 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1976
1977 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1978 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1979
1980 cur_bin = -6000;
1981 upper = bin + 100;
1982 lower = bin - 100;
1983
1984 for (i = 0; i < 4; i++) {
1985 int pilot_mask = 0;
1986 int chan_mask = 0;
1987 int bp = 0;
1988 for (bp = 0; bp < 30; bp++) {
1989 if ((cur_bin > lower) && (cur_bin < upper)) {
1990 pilot_mask = pilot_mask | 0x1 << bp;
1991 chan_mask = chan_mask | 0x1 << bp;
1992 }
1993 cur_bin += 100;
1994 }
1995 cur_bin += inc[i];
1996 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1997 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1998 }
1999
2000 cur_vit_mask = 6100;
2001 upper = bin + 120;
2002 lower = bin - 120;
2003
2004 for (i = 0; i < 123; i++) {
2005 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2006
2007 /* workaround for gcc bug #37014 */
2008 volatile int tmp_v = abs(cur_vit_mask - bin);
2009
2010 if (tmp_v < 75)
2011 mask_amt = 1;
2012 else
2013 mask_amt = 0;
2014 if (cur_vit_mask < 0)
2015 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2016 else
2017 mask_p[cur_vit_mask / 100] = mask_amt;
2018 }
2019 cur_vit_mask -= 100;
2020 }
2021
2022 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2023 | (mask_m[48] << 26) | (mask_m[49] << 24)
2024 | (mask_m[50] << 22) | (mask_m[51] << 20)
2025 | (mask_m[52] << 18) | (mask_m[53] << 16)
2026 | (mask_m[54] << 14) | (mask_m[55] << 12)
2027 | (mask_m[56] << 10) | (mask_m[57] << 8)
2028 | (mask_m[58] << 6) | (mask_m[59] << 4)
2029 | (mask_m[60] << 2) | (mask_m[61] << 0);
2030 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2031 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2032
2033 tmp_mask = (mask_m[31] << 28)
2034 | (mask_m[32] << 26) | (mask_m[33] << 24)
2035 | (mask_m[34] << 22) | (mask_m[35] << 20)
2036 | (mask_m[36] << 18) | (mask_m[37] << 16)
2037 | (mask_m[48] << 14) | (mask_m[39] << 12)
2038 | (mask_m[40] << 10) | (mask_m[41] << 8)
2039 | (mask_m[42] << 6) | (mask_m[43] << 4)
2040 | (mask_m[44] << 2) | (mask_m[45] << 0);
2041 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2042 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2043
2044 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2045 | (mask_m[18] << 26) | (mask_m[18] << 24)
2046 | (mask_m[20] << 22) | (mask_m[20] << 20)
2047 | (mask_m[22] << 18) | (mask_m[22] << 16)
2048 | (mask_m[24] << 14) | (mask_m[24] << 12)
2049 | (mask_m[25] << 10) | (mask_m[26] << 8)
2050 | (mask_m[27] << 6) | (mask_m[28] << 4)
2051 | (mask_m[29] << 2) | (mask_m[30] << 0);
2052 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2053 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2054
2055 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2056 | (mask_m[2] << 26) | (mask_m[3] << 24)
2057 | (mask_m[4] << 22) | (mask_m[5] << 20)
2058 | (mask_m[6] << 18) | (mask_m[7] << 16)
2059 | (mask_m[8] << 14) | (mask_m[9] << 12)
2060 | (mask_m[10] << 10) | (mask_m[11] << 8)
2061 | (mask_m[12] << 6) | (mask_m[13] << 4)
2062 | (mask_m[14] << 2) | (mask_m[15] << 0);
2063 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2064 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2065
2066 tmp_mask = (mask_p[15] << 28)
2067 | (mask_p[14] << 26) | (mask_p[13] << 24)
2068 | (mask_p[12] << 22) | (mask_p[11] << 20)
2069 | (mask_p[10] << 18) | (mask_p[9] << 16)
2070 | (mask_p[8] << 14) | (mask_p[7] << 12)
2071 | (mask_p[6] << 10) | (mask_p[5] << 8)
2072 | (mask_p[4] << 6) | (mask_p[3] << 4)
2073 | (mask_p[2] << 2) | (mask_p[1] << 0);
2074 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2075 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2076
2077 tmp_mask = (mask_p[30] << 28)
2078 | (mask_p[29] << 26) | (mask_p[28] << 24)
2079 | (mask_p[27] << 22) | (mask_p[26] << 20)
2080 | (mask_p[25] << 18) | (mask_p[24] << 16)
2081 | (mask_p[23] << 14) | (mask_p[22] << 12)
2082 | (mask_p[21] << 10) | (mask_p[20] << 8)
2083 | (mask_p[19] << 6) | (mask_p[18] << 4)
2084 | (mask_p[17] << 2) | (mask_p[16] << 0);
2085 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2086 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2087
2088 tmp_mask = (mask_p[45] << 28)
2089 | (mask_p[44] << 26) | (mask_p[43] << 24)
2090 | (mask_p[42] << 22) | (mask_p[41] << 20)
2091 | (mask_p[40] << 18) | (mask_p[39] << 16)
2092 | (mask_p[38] << 14) | (mask_p[37] << 12)
2093 | (mask_p[36] << 10) | (mask_p[35] << 8)
2094 | (mask_p[34] << 6) | (mask_p[33] << 4)
2095 | (mask_p[32] << 2) | (mask_p[31] << 0);
2096 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2097 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2098
2099 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2100 | (mask_p[59] << 26) | (mask_p[58] << 24)
2101 | (mask_p[57] << 22) | (mask_p[56] << 20)
2102 | (mask_p[55] << 18) | (mask_p[54] << 16)
2103 | (mask_p[53] << 14) | (mask_p[52] << 12)
2104 | (mask_p[51] << 10) | (mask_p[50] << 8)
2105 | (mask_p[49] << 6) | (mask_p[48] << 4)
2106 | (mask_p[47] << 2) | (mask_p[46] << 0);
2107 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2108 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2109 }
2110
2111 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2112 {
2113 int bb_spur = AR_NO_SPUR;
2114 int bin, cur_bin;
2115 int spur_freq_sd;
2116 int spur_delta_phase;
2117 int denominator;
2118 int upper, lower, cur_vit_mask;
2119 int tmp, new;
2120 int i;
2121 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2122 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2123 };
2124 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2125 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2126 };
2127 int inc[4] = { 0, 100, 0, 0 };
2128
2129 int8_t mask_m[123];
2130 int8_t mask_p[123];
2131 int8_t mask_amt;
2132 int tmp_mask;
2133 int cur_bb_spur;
2134 bool is2GHz = IS_CHAN_2GHZ(chan);
2135
2136 memset(&mask_m, 0, sizeof(int8_t) * 123);
2137 memset(&mask_p, 0, sizeof(int8_t) * 123);
2138
2139 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2140 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2141 if (AR_NO_SPUR == cur_bb_spur)
2142 break;
2143 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2144 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2145 bb_spur = cur_bb_spur;
2146 break;
2147 }
2148 }
2149
2150 if (AR_NO_SPUR == bb_spur)
2151 return;
2152
2153 bin = bb_spur * 32;
2154
2155 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2156 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2157 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2158 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2159 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2160
2161 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2162
2163 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2164 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2165 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2166 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2167 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2168 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2169
2170 spur_delta_phase = ((bb_spur * 524288) / 100) &
2171 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2172
2173 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2174 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2175
2176 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2177 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2178 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2179 REG_WRITE(ah, AR_PHY_TIMING11, new);
2180
2181 cur_bin = -6000;
2182 upper = bin + 100;
2183 lower = bin - 100;
2184
2185 for (i = 0; i < 4; i++) {
2186 int pilot_mask = 0;
2187 int chan_mask = 0;
2188 int bp = 0;
2189 for (bp = 0; bp < 30; bp++) {
2190 if ((cur_bin > lower) && (cur_bin < upper)) {
2191 pilot_mask = pilot_mask | 0x1 << bp;
2192 chan_mask = chan_mask | 0x1 << bp;
2193 }
2194 cur_bin += 100;
2195 }
2196 cur_bin += inc[i];
2197 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2198 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2199 }
2200
2201 cur_vit_mask = 6100;
2202 upper = bin + 120;
2203 lower = bin - 120;
2204
2205 for (i = 0; i < 123; i++) {
2206 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2207
2208 /* workaround for gcc bug #37014 */
2209 volatile int tmp_v = abs(cur_vit_mask - bin);
2210
2211 if (tmp_v < 75)
2212 mask_amt = 1;
2213 else
2214 mask_amt = 0;
2215 if (cur_vit_mask < 0)
2216 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2217 else
2218 mask_p[cur_vit_mask / 100] = mask_amt;
2219 }
2220 cur_vit_mask -= 100;
2221 }
2222
2223 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2224 | (mask_m[48] << 26) | (mask_m[49] << 24)
2225 | (mask_m[50] << 22) | (mask_m[51] << 20)
2226 | (mask_m[52] << 18) | (mask_m[53] << 16)
2227 | (mask_m[54] << 14) | (mask_m[55] << 12)
2228 | (mask_m[56] << 10) | (mask_m[57] << 8)
2229 | (mask_m[58] << 6) | (mask_m[59] << 4)
2230 | (mask_m[60] << 2) | (mask_m[61] << 0);
2231 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2232 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2233
2234 tmp_mask = (mask_m[31] << 28)
2235 | (mask_m[32] << 26) | (mask_m[33] << 24)
2236 | (mask_m[34] << 22) | (mask_m[35] << 20)
2237 | (mask_m[36] << 18) | (mask_m[37] << 16)
2238 | (mask_m[48] << 14) | (mask_m[39] << 12)
2239 | (mask_m[40] << 10) | (mask_m[41] << 8)
2240 | (mask_m[42] << 6) | (mask_m[43] << 4)
2241 | (mask_m[44] << 2) | (mask_m[45] << 0);
2242 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2243 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2244
2245 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2246 | (mask_m[18] << 26) | (mask_m[18] << 24)
2247 | (mask_m[20] << 22) | (mask_m[20] << 20)
2248 | (mask_m[22] << 18) | (mask_m[22] << 16)
2249 | (mask_m[24] << 14) | (mask_m[24] << 12)
2250 | (mask_m[25] << 10) | (mask_m[26] << 8)
2251 | (mask_m[27] << 6) | (mask_m[28] << 4)
2252 | (mask_m[29] << 2) | (mask_m[30] << 0);
2253 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2254 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2255
2256 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2257 | (mask_m[2] << 26) | (mask_m[3] << 24)
2258 | (mask_m[4] << 22) | (mask_m[5] << 20)
2259 | (mask_m[6] << 18) | (mask_m[7] << 16)
2260 | (mask_m[8] << 14) | (mask_m[9] << 12)
2261 | (mask_m[10] << 10) | (mask_m[11] << 8)
2262 | (mask_m[12] << 6) | (mask_m[13] << 4)
2263 | (mask_m[14] << 2) | (mask_m[15] << 0);
2264 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2265 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2266
2267 tmp_mask = (mask_p[15] << 28)
2268 | (mask_p[14] << 26) | (mask_p[13] << 24)
2269 | (mask_p[12] << 22) | (mask_p[11] << 20)
2270 | (mask_p[10] << 18) | (mask_p[9] << 16)
2271 | (mask_p[8] << 14) | (mask_p[7] << 12)
2272 | (mask_p[6] << 10) | (mask_p[5] << 8)
2273 | (mask_p[4] << 6) | (mask_p[3] << 4)
2274 | (mask_p[2] << 2) | (mask_p[1] << 0);
2275 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2276 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2277
2278 tmp_mask = (mask_p[30] << 28)
2279 | (mask_p[29] << 26) | (mask_p[28] << 24)
2280 | (mask_p[27] << 22) | (mask_p[26] << 20)
2281 | (mask_p[25] << 18) | (mask_p[24] << 16)
2282 | (mask_p[23] << 14) | (mask_p[22] << 12)
2283 | (mask_p[21] << 10) | (mask_p[20] << 8)
2284 | (mask_p[19] << 6) | (mask_p[18] << 4)
2285 | (mask_p[17] << 2) | (mask_p[16] << 0);
2286 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2287 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2288
2289 tmp_mask = (mask_p[45] << 28)
2290 | (mask_p[44] << 26) | (mask_p[43] << 24)
2291 | (mask_p[42] << 22) | (mask_p[41] << 20)
2292 | (mask_p[40] << 18) | (mask_p[39] << 16)
2293 | (mask_p[38] << 14) | (mask_p[37] << 12)
2294 | (mask_p[36] << 10) | (mask_p[35] << 8)
2295 | (mask_p[34] << 6) | (mask_p[33] << 4)
2296 | (mask_p[32] << 2) | (mask_p[31] << 0);
2297 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2298 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2299
2300 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2301 | (mask_p[59] << 26) | (mask_p[58] << 24)
2302 | (mask_p[57] << 22) | (mask_p[56] << 20)
2303 | (mask_p[55] << 18) | (mask_p[54] << 16)
2304 | (mask_p[53] << 14) | (mask_p[52] << 12)
2305 | (mask_p[51] << 10) | (mask_p[50] << 8)
2306 | (mask_p[49] << 6) | (mask_p[48] << 4)
2307 | (mask_p[47] << 2) | (mask_p[46] << 0);
2308 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2309 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2310 }
2311
2312 static void ath9k_enable_rfkill(struct ath_hw *ah)
2313 {
2314 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2315 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2316
2317 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2318 AR_GPIO_INPUT_MUX2_RFSILENT);
2319
2320 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2321 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2322 }
2323
2324 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2325 bool bChannelChange)
2326 {
2327 struct ath_common *common = ath9k_hw_common(ah);
2328 u32 saveLedState;
2329 struct ath_softc *sc = ah->ah_sc;
2330 struct ath9k_channel *curchan = ah->curchan;
2331 u32 saveDefAntenna;
2332 u32 macStaId1;
2333 u64 tsf = 0;
2334 int i, rx_chainmask, r;
2335
2336 ah->extprotspacing = sc->ht_extprotspacing;
2337 ah->txchainmask = sc->tx_chainmask;
2338 ah->rxchainmask = sc->rx_chainmask;
2339
2340 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2341 return -EIO;
2342
2343 if (curchan && !ah->chip_fullsleep)
2344 ath9k_hw_getnf(ah, curchan);
2345
2346 if (bChannelChange &&
2347 (ah->chip_fullsleep != true) &&
2348 (ah->curchan != NULL) &&
2349 (chan->channel != ah->curchan->channel) &&
2350 ((chan->channelFlags & CHANNEL_ALL) ==
2351 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2352 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2353 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2354
2355 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2356 ath9k_hw_loadnf(ah, ah->curchan);
2357 ath9k_hw_start_nfcal(ah);
2358 return 0;
2359 }
2360 }
2361
2362 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2363 if (saveDefAntenna == 0)
2364 saveDefAntenna = 1;
2365
2366 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2367
2368 /* For chips on which RTC reset is done, save TSF before it gets cleared */
2369 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2370 tsf = ath9k_hw_gettsf64(ah);
2371
2372 saveLedState = REG_READ(ah, AR_CFG_LED) &
2373 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2374 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2375
2376 ath9k_hw_mark_phy_inactive(ah);
2377
2378 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2379 REG_WRITE(ah,
2380 AR9271_RESET_POWER_DOWN_CONTROL,
2381 AR9271_RADIO_RF_RST);
2382 udelay(50);
2383 }
2384
2385 if (!ath9k_hw_chip_reset(ah, chan)) {
2386 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2387 return -EINVAL;
2388 }
2389
2390 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2391 ah->htc_reset_init = false;
2392 REG_WRITE(ah,
2393 AR9271_RESET_POWER_DOWN_CONTROL,
2394 AR9271_GATE_MAC_CTL);
2395 udelay(50);
2396 }
2397
2398 /* Restore TSF */
2399 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2400 ath9k_hw_settsf64(ah, tsf);
2401
2402 if (AR_SREV_9280_10_OR_LATER(ah))
2403 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2404
2405 if (AR_SREV_9287_12_OR_LATER(ah)) {
2406 /* Enable ASYNC FIFO */
2407 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2408 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2409 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2410 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2411 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2412 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2413 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2414 }
2415 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2416 if (r)
2417 return r;
2418
2419 /* Setup MFP options for CCMP */
2420 if (AR_SREV_9280_20_OR_LATER(ah)) {
2421 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2422 * frames when constructing CCMP AAD. */
2423 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2424 0xc7ff);
2425 ah->sw_mgmt_crypto = false;
2426 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2427 /* Disable hardware crypto for management frames */
2428 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2429 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2430 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2431 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2432 ah->sw_mgmt_crypto = true;
2433 } else
2434 ah->sw_mgmt_crypto = true;
2435
2436 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2437 ath9k_hw_set_delta_slope(ah, chan);
2438
2439 if (AR_SREV_9280_10_OR_LATER(ah))
2440 ath9k_hw_9280_spur_mitigate(ah, chan);
2441 else
2442 ath9k_hw_spur_mitigate(ah, chan);
2443
2444 ah->eep_ops->set_board_values(ah, chan);
2445
2446 ath9k_hw_decrease_chain_power(ah, chan);
2447
2448 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2449 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2450 | macStaId1
2451 | AR_STA_ID1_RTS_USE_DEF
2452 | (ah->config.
2453 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2454 | ah->sta_id1_defaults);
2455 ath9k_hw_set_operating_mode(ah, ah->opmode);
2456
2457 ath_hw_setbssidmask(common);
2458
2459 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2460
2461 ath9k_hw_write_associd(ah);
2462
2463 REG_WRITE(ah, AR_ISR, ~0);
2464
2465 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2466
2467 if (AR_SREV_9280_10_OR_LATER(ah))
2468 ath9k_hw_ar9280_set_channel(ah, chan);
2469 else
2470 if (!(ath9k_hw_set_channel(ah, chan)))
2471 return -EIO;
2472
2473 for (i = 0; i < AR_NUM_DCU; i++)
2474 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2475
2476 ah->intr_txqs = 0;
2477 for (i = 0; i < ah->caps.total_queues; i++)
2478 ath9k_hw_resettxqueue(ah, i);
2479
2480 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2481 ath9k_hw_init_qos(ah);
2482
2483 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2484 ath9k_enable_rfkill(ah);
2485
2486 ath9k_hw_init_user_settings(ah);
2487
2488 if (AR_SREV_9287_12_OR_LATER(ah)) {
2489 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2490 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2491 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2492 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2493 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2494 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2495
2496 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2497 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2498
2499 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2500 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2501 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2502 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2503 }
2504 if (AR_SREV_9287_12_OR_LATER(ah)) {
2505 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2506 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2507 }
2508
2509 REG_WRITE(ah, AR_STA_ID1,
2510 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2511
2512 ath9k_hw_set_dma(ah);
2513
2514 REG_WRITE(ah, AR_OBS, 8);
2515
2516 if (ah->config.intr_mitigation) {
2517 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2518 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2519 }
2520
2521 ath9k_hw_init_bb(ah, chan);
2522
2523 if (!ath9k_hw_init_cal(ah, chan))
2524 return -EIO;
2525
2526 rx_chainmask = ah->rxchainmask;
2527 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2528 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2529 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2530 }
2531
2532 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2533
2534 /*
2535 * For big endian systems turn on swapping for descriptors
2536 */
2537 if (AR_SREV_9100(ah)) {
2538 u32 mask;
2539 mask = REG_READ(ah, AR_CFG);
2540 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2541 ath_print(common, ATH_DBG_RESET,
2542 "CFG Byte Swap Set 0x%x\n", mask);
2543 } else {
2544 mask =
2545 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2546 REG_WRITE(ah, AR_CFG, mask);
2547 ath_print(common, ATH_DBG_RESET,
2548 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2549 }
2550 } else {
2551 /* Configure AR9271 target WLAN */
2552 if (AR_SREV_9271(ah))
2553 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2554 #ifdef __BIG_ENDIAN
2555 else
2556 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2557 #endif
2558 }
2559
2560 if (ah->btcoex_hw.enabled)
2561 ath9k_hw_btcoex_enable(ah);
2562
2563 return 0;
2564 }
2565
2566 /************************/
2567 /* Key Cache Management */
2568 /************************/
2569
2570 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2571 {
2572 u32 keyType;
2573
2574 if (entry >= ah->caps.keycache_size) {
2575 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2576 "keychache entry %u out of range\n", entry);
2577 return false;
2578 }
2579
2580 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2581
2582 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2583 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2584 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2585 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2586 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2587 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2588 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2589 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2590
2591 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2592 u16 micentry = entry + 64;
2593
2594 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2595 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2596 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2597 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2598
2599 }
2600
2601 return true;
2602 }
2603
2604 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2605 {
2606 u32 macHi, macLo;
2607
2608 if (entry >= ah->caps.keycache_size) {
2609 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2610 "keychache entry %u out of range\n", entry);
2611 return false;
2612 }
2613
2614 if (mac != NULL) {
2615 macHi = (mac[5] << 8) | mac[4];
2616 macLo = (mac[3] << 24) |
2617 (mac[2] << 16) |
2618 (mac[1] << 8) |
2619 mac[0];
2620 macLo >>= 1;
2621 macLo |= (macHi & 1) << 31;
2622 macHi >>= 1;
2623 } else {
2624 macLo = macHi = 0;
2625 }
2626 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2627 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2628
2629 return true;
2630 }
2631
2632 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2633 const struct ath9k_keyval *k,
2634 const u8 *mac)
2635 {
2636 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2637 struct ath_common *common = ath9k_hw_common(ah);
2638 u32 key0, key1, key2, key3, key4;
2639 u32 keyType;
2640
2641 if (entry >= pCap->keycache_size) {
2642 ath_print(common, ATH_DBG_FATAL,
2643 "keycache entry %u out of range\n", entry);
2644 return false;
2645 }
2646
2647 switch (k->kv_type) {
2648 case ATH9K_CIPHER_AES_OCB:
2649 keyType = AR_KEYTABLE_TYPE_AES;
2650 break;
2651 case ATH9K_CIPHER_AES_CCM:
2652 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2653 ath_print(common, ATH_DBG_ANY,
2654 "AES-CCM not supported by mac rev 0x%x\n",
2655 ah->hw_version.macRev);
2656 return false;
2657 }
2658 keyType = AR_KEYTABLE_TYPE_CCM;
2659 break;
2660 case ATH9K_CIPHER_TKIP:
2661 keyType = AR_KEYTABLE_TYPE_TKIP;
2662 if (ATH9K_IS_MIC_ENABLED(ah)
2663 && entry + 64 >= pCap->keycache_size) {
2664 ath_print(common, ATH_DBG_ANY,
2665 "entry %u inappropriate for TKIP\n", entry);
2666 return false;
2667 }
2668 break;
2669 case ATH9K_CIPHER_WEP:
2670 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2671 ath_print(common, ATH_DBG_ANY,
2672 "WEP key length %u too small\n", k->kv_len);
2673 return false;
2674 }
2675 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2676 keyType = AR_KEYTABLE_TYPE_40;
2677 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2678 keyType = AR_KEYTABLE_TYPE_104;
2679 else
2680 keyType = AR_KEYTABLE_TYPE_128;
2681 break;
2682 case ATH9K_CIPHER_CLR:
2683 keyType = AR_KEYTABLE_TYPE_CLR;
2684 break;
2685 default:
2686 ath_print(common, ATH_DBG_FATAL,
2687 "cipher %u not supported\n", k->kv_type);
2688 return false;
2689 }
2690
2691 key0 = get_unaligned_le32(k->kv_val + 0);
2692 key1 = get_unaligned_le16(k->kv_val + 4);
2693 key2 = get_unaligned_le32(k->kv_val + 6);
2694 key3 = get_unaligned_le16(k->kv_val + 10);
2695 key4 = get_unaligned_le32(k->kv_val + 12);
2696 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2697 key4 &= 0xff;
2698
2699 /*
2700 * Note: Key cache registers access special memory area that requires
2701 * two 32-bit writes to actually update the values in the internal
2702 * memory. Consequently, the exact order and pairs used here must be
2703 * maintained.
2704 */
2705
2706 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2707 u16 micentry = entry + 64;
2708
2709 /*
2710 * Write inverted key[47:0] first to avoid Michael MIC errors
2711 * on frames that could be sent or received at the same time.
2712 * The correct key will be written in the end once everything
2713 * else is ready.
2714 */
2715 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2716 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2717
2718 /* Write key[95:48] */
2719 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2720 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2721
2722 /* Write key[127:96] and key type */
2723 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2724 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2725
2726 /* Write MAC address for the entry */
2727 (void) ath9k_hw_keysetmac(ah, entry, mac);
2728
2729 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2730 /*
2731 * TKIP uses two key cache entries:
2732 * Michael MIC TX/RX keys in the same key cache entry
2733 * (idx = main index + 64):
2734 * key0 [31:0] = RX key [31:0]
2735 * key1 [15:0] = TX key [31:16]
2736 * key1 [31:16] = reserved
2737 * key2 [31:0] = RX key [63:32]
2738 * key3 [15:0] = TX key [15:0]
2739 * key3 [31:16] = reserved
2740 * key4 [31:0] = TX key [63:32]
2741 */
2742 u32 mic0, mic1, mic2, mic3, mic4;
2743
2744 mic0 = get_unaligned_le32(k->kv_mic + 0);
2745 mic2 = get_unaligned_le32(k->kv_mic + 4);
2746 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2747 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2748 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2749
2750 /* Write RX[31:0] and TX[31:16] */
2751 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2752 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2753
2754 /* Write RX[63:32] and TX[15:0] */
2755 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2756 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2757
2758 /* Write TX[63:32] and keyType(reserved) */
2759 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2760 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2761 AR_KEYTABLE_TYPE_CLR);
2762
2763 } else {
2764 /*
2765 * TKIP uses four key cache entries (two for group
2766 * keys):
2767 * Michael MIC TX/RX keys are in different key cache
2768 * entries (idx = main index + 64 for TX and
2769 * main index + 32 + 96 for RX):
2770 * key0 [31:0] = TX/RX MIC key [31:0]
2771 * key1 [31:0] = reserved
2772 * key2 [31:0] = TX/RX MIC key [63:32]
2773 * key3 [31:0] = reserved
2774 * key4 [31:0] = reserved
2775 *
2776 * Upper layer code will call this function separately
2777 * for TX and RX keys when these registers offsets are
2778 * used.
2779 */
2780 u32 mic0, mic2;
2781
2782 mic0 = get_unaligned_le32(k->kv_mic + 0);
2783 mic2 = get_unaligned_le32(k->kv_mic + 4);
2784
2785 /* Write MIC key[31:0] */
2786 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2787 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2788
2789 /* Write MIC key[63:32] */
2790 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2791 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2792
2793 /* Write TX[63:32] and keyType(reserved) */
2794 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2795 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2796 AR_KEYTABLE_TYPE_CLR);
2797 }
2798
2799 /* MAC address registers are reserved for the MIC entry */
2800 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2801 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2802
2803 /*
2804 * Write the correct (un-inverted) key[47:0] last to enable
2805 * TKIP now that all other registers are set with correct
2806 * values.
2807 */
2808 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2809 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2810 } else {
2811 /* Write key[47:0] */
2812 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2813 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2814
2815 /* Write key[95:48] */
2816 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2817 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2818
2819 /* Write key[127:96] and key type */
2820 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2821 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2822
2823 /* Write MAC address for the entry */
2824 (void) ath9k_hw_keysetmac(ah, entry, mac);
2825 }
2826
2827 return true;
2828 }
2829
2830 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2831 {
2832 if (entry < ah->caps.keycache_size) {
2833 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2834 if (val & AR_KEYTABLE_VALID)
2835 return true;
2836 }
2837 return false;
2838 }
2839
2840 /******************************/
2841 /* Power Management (Chipset) */
2842 /******************************/
2843
2844 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2845 {
2846 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2847 if (setChip) {
2848 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2849 AR_RTC_FORCE_WAKE_EN);
2850 if (!AR_SREV_9100(ah))
2851 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2852
2853 REG_CLR_BIT(ah, (AR_RTC_RESET),
2854 AR_RTC_RESET_EN);
2855 }
2856 }
2857
2858 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2859 {
2860 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2861 if (setChip) {
2862 struct ath9k_hw_capabilities *pCap = &ah->caps;
2863
2864 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2865 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2866 AR_RTC_FORCE_WAKE_ON_INT);
2867 } else {
2868 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2869 AR_RTC_FORCE_WAKE_EN);
2870 }
2871 }
2872 }
2873
2874 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2875 {
2876 u32 val;
2877 int i;
2878
2879 if (setChip) {
2880 if ((REG_READ(ah, AR_RTC_STATUS) &
2881 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2882 if (ath9k_hw_set_reset_reg(ah,
2883 ATH9K_RESET_POWER_ON) != true) {
2884 return false;
2885 }
2886 }
2887 if (AR_SREV_9100(ah))
2888 REG_SET_BIT(ah, AR_RTC_RESET,
2889 AR_RTC_RESET_EN);
2890
2891 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2892 AR_RTC_FORCE_WAKE_EN);
2893 udelay(50);
2894
2895 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2896 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2897 if (val == AR_RTC_STATUS_ON)
2898 break;
2899 udelay(50);
2900 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2901 AR_RTC_FORCE_WAKE_EN);
2902 }
2903 if (i == 0) {
2904 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2905 "Failed to wakeup in %uus\n",
2906 POWER_UP_TIME / 20);
2907 return false;
2908 }
2909 }
2910
2911 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2912
2913 return true;
2914 }
2915
2916 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2917 {
2918 struct ath_common *common = ath9k_hw_common(ah);
2919 int status = true, setChip = true;
2920 static const char *modes[] = {
2921 "AWAKE",
2922 "FULL-SLEEP",
2923 "NETWORK SLEEP",
2924 "UNDEFINED"
2925 };
2926
2927 if (ah->power_mode == mode)
2928 return status;
2929
2930 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2931 modes[ah->power_mode], modes[mode]);
2932
2933 switch (mode) {
2934 case ATH9K_PM_AWAKE:
2935 status = ath9k_hw_set_power_awake(ah, setChip);
2936 break;
2937 case ATH9K_PM_FULL_SLEEP:
2938 ath9k_set_power_sleep(ah, setChip);
2939 ah->chip_fullsleep = true;
2940 break;
2941 case ATH9K_PM_NETWORK_SLEEP:
2942 ath9k_set_power_network_sleep(ah, setChip);
2943 break;
2944 default:
2945 ath_print(common, ATH_DBG_FATAL,
2946 "Unknown power mode %u\n", mode);
2947 return false;
2948 }
2949 ah->power_mode = mode;
2950
2951 return status;
2952 }
2953
2954 /*
2955 * Helper for ASPM support.
2956 *
2957 * Disable PLL when in L0s as well as receiver clock when in L1.
2958 * This power saving option must be enabled through the SerDes.
2959 *
2960 * Programming the SerDes must go through the same 288 bit serial shift
2961 * register as the other analog registers. Hence the 9 writes.
2962 */
2963 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2964 {
2965 u8 i;
2966 u32 val;
2967
2968 if (ah->is_pciexpress != true)
2969 return;
2970
2971 /* Do not touch SerDes registers */
2972 if (ah->config.pcie_powersave_enable == 2)
2973 return;
2974
2975 /* Nothing to do on restore for 11N */
2976 if (!restore) {
2977 if (AR_SREV_9280_20_OR_LATER(ah)) {
2978 /*
2979 * AR9280 2.0 or later chips use SerDes values from the
2980 * initvals.h initialized depending on chipset during
2981 * ath9k_hw_init()
2982 */
2983 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2984 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2985 INI_RA(&ah->iniPcieSerdes, i, 1));
2986 }
2987 } else if (AR_SREV_9280(ah) &&
2988 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2989 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2990 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2991
2992 /* RX shut off when elecidle is asserted */
2993 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2994 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2995 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2996
2997 /* Shut off CLKREQ active in L1 */
2998 if (ah->config.pcie_clock_req)
2999 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3000 else
3001 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3002
3003 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3004 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3005 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3006
3007 /* Load the new settings */
3008 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3009
3010 } else {
3011 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3012 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3013
3014 /* RX shut off when elecidle is asserted */
3015 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3016 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3017 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3018
3019 /*
3020 * Ignore ah->ah_config.pcie_clock_req setting for
3021 * pre-AR9280 11n
3022 */
3023 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3024
3025 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3026 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3027 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3028
3029 /* Load the new settings */
3030 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3031 }
3032
3033 udelay(1000);
3034
3035 /* set bit 19 to allow forcing of pcie core into L1 state */
3036 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3037
3038 /* Several PCIe massages to ensure proper behaviour */
3039 if (ah->config.pcie_waen) {
3040 val = ah->config.pcie_waen;
3041 if (!power_off)
3042 val &= (~AR_WA_D3_L1_DISABLE);
3043 } else {
3044 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3045 AR_SREV_9287(ah)) {
3046 val = AR9285_WA_DEFAULT;
3047 if (!power_off)
3048 val &= (~AR_WA_D3_L1_DISABLE);
3049 } else if (AR_SREV_9280(ah)) {
3050 /*
3051 * On AR9280 chips bit 22 of 0x4004 needs to be
3052 * set otherwise card may disappear.
3053 */
3054 val = AR9280_WA_DEFAULT;
3055 if (!power_off)
3056 val &= (~AR_WA_D3_L1_DISABLE);
3057 } else
3058 val = AR_WA_DEFAULT;
3059 }
3060
3061 REG_WRITE(ah, AR_WA, val);
3062 }
3063
3064 if (power_off) {
3065 /*
3066 * Set PCIe workaround bits
3067 * bit 14 in WA register (disable L1) should only
3068 * be set when device enters D3 and be cleared
3069 * when device comes back to D0.
3070 */
3071 if (ah->config.pcie_waen) {
3072 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3073 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3074 } else {
3075 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3076 AR_SREV_9287(ah)) &&
3077 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3078 (AR_SREV_9280(ah) &&
3079 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3080 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3081 }
3082 }
3083 }
3084 }
3085
3086 /**********************/
3087 /* Interrupt Handling */
3088 /**********************/
3089
3090 bool ath9k_hw_intrpend(struct ath_hw *ah)
3091 {
3092 u32 host_isr;
3093
3094 if (AR_SREV_9100(ah))
3095 return true;
3096
3097 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3098 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3099 return true;
3100
3101 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3102 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3103 && (host_isr != AR_INTR_SPURIOUS))
3104 return true;
3105
3106 return false;
3107 }
3108
3109 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3110 {
3111 u32 isr = 0;
3112 u32 mask2 = 0;
3113 struct ath9k_hw_capabilities *pCap = &ah->caps;
3114 u32 sync_cause = 0;
3115 bool fatal_int = false;
3116 struct ath_common *common = ath9k_hw_common(ah);
3117
3118 if (!AR_SREV_9100(ah)) {
3119 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3120 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3121 == AR_RTC_STATUS_ON) {
3122 isr = REG_READ(ah, AR_ISR);
3123 }
3124 }
3125
3126 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3127 AR_INTR_SYNC_DEFAULT;
3128
3129 *masked = 0;
3130
3131 if (!isr && !sync_cause)
3132 return false;
3133 } else {
3134 *masked = 0;
3135 isr = REG_READ(ah, AR_ISR);
3136 }
3137
3138 if (isr) {
3139 if (isr & AR_ISR_BCNMISC) {
3140 u32 isr2;
3141 isr2 = REG_READ(ah, AR_ISR_S2);
3142 if (isr2 & AR_ISR_S2_TIM)
3143 mask2 |= ATH9K_INT_TIM;
3144 if (isr2 & AR_ISR_S2_DTIM)
3145 mask2 |= ATH9K_INT_DTIM;
3146 if (isr2 & AR_ISR_S2_DTIMSYNC)
3147 mask2 |= ATH9K_INT_DTIMSYNC;
3148 if (isr2 & (AR_ISR_S2_CABEND))
3149 mask2 |= ATH9K_INT_CABEND;
3150 if (isr2 & AR_ISR_S2_GTT)
3151 mask2 |= ATH9K_INT_GTT;
3152 if (isr2 & AR_ISR_S2_CST)
3153 mask2 |= ATH9K_INT_CST;
3154 if (isr2 & AR_ISR_S2_TSFOOR)
3155 mask2 |= ATH9K_INT_TSFOOR;
3156 }
3157
3158 isr = REG_READ(ah, AR_ISR_RAC);
3159 if (isr == 0xffffffff) {
3160 *masked = 0;
3161 return false;
3162 }
3163
3164 *masked = isr & ATH9K_INT_COMMON;
3165
3166 if (ah->config.intr_mitigation) {
3167 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3168 *masked |= ATH9K_INT_RX;
3169 }
3170
3171 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3172 *masked |= ATH9K_INT_RX;
3173 if (isr &
3174 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3175 AR_ISR_TXEOL)) {
3176 u32 s0_s, s1_s;
3177
3178 *masked |= ATH9K_INT_TX;
3179
3180 s0_s = REG_READ(ah, AR_ISR_S0_S);
3181 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3182 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3183
3184 s1_s = REG_READ(ah, AR_ISR_S1_S);
3185 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3186 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3187 }
3188
3189 if (isr & AR_ISR_RXORN) {
3190 ath_print(common, ATH_DBG_INTERRUPT,
3191 "receive FIFO overrun interrupt\n");
3192 }
3193
3194 if (!AR_SREV_9100(ah)) {
3195 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3196 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3197 if (isr5 & AR_ISR_S5_TIM_TIMER)
3198 *masked |= ATH9K_INT_TIM_TIMER;
3199 }
3200 }
3201
3202 *masked |= mask2;
3203 }
3204
3205 if (AR_SREV_9100(ah))
3206 return true;
3207
3208 if (isr & AR_ISR_GENTMR) {
3209 u32 s5_s;
3210
3211 s5_s = REG_READ(ah, AR_ISR_S5_S);
3212 if (isr & AR_ISR_GENTMR) {
3213 ah->intr_gen_timer_trigger =
3214 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3215
3216 ah->intr_gen_timer_thresh =
3217 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3218
3219 if (ah->intr_gen_timer_trigger)
3220 *masked |= ATH9K_INT_GENTIMER;
3221
3222 }
3223 }
3224
3225 if (sync_cause) {
3226 fatal_int =
3227 (sync_cause &
3228 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3229 ? true : false;
3230
3231 if (fatal_int) {
3232 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3233 ath_print(common, ATH_DBG_ANY,
3234 "received PCI FATAL interrupt\n");
3235 }
3236 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3237 ath_print(common, ATH_DBG_ANY,
3238 "received PCI PERR interrupt\n");
3239 }
3240 *masked |= ATH9K_INT_FATAL;
3241 }
3242 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3243 ath_print(common, ATH_DBG_INTERRUPT,
3244 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3245 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3246 REG_WRITE(ah, AR_RC, 0);
3247 *masked |= ATH9K_INT_FATAL;
3248 }
3249 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3250 ath_print(common, ATH_DBG_INTERRUPT,
3251 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3252 }
3253
3254 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3255 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3256 }
3257
3258 return true;
3259 }
3260
3261 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3262 {
3263 u32 omask = ah->mask_reg;
3264 u32 mask, mask2;
3265 struct ath9k_hw_capabilities *pCap = &ah->caps;
3266 struct ath_common *common = ath9k_hw_common(ah);
3267
3268 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3269
3270 if (omask & ATH9K_INT_GLOBAL) {
3271 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
3272 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3273 (void) REG_READ(ah, AR_IER);
3274 if (!AR_SREV_9100(ah)) {
3275 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3276 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3277
3278 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3279 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3280 }
3281 }
3282
3283 mask = ints & ATH9K_INT_COMMON;
3284 mask2 = 0;
3285
3286 if (ints & ATH9K_INT_TX) {
3287 if (ah->txok_interrupt_mask)
3288 mask |= AR_IMR_TXOK;
3289 if (ah->txdesc_interrupt_mask)
3290 mask |= AR_IMR_TXDESC;
3291 if (ah->txerr_interrupt_mask)
3292 mask |= AR_IMR_TXERR;
3293 if (ah->txeol_interrupt_mask)
3294 mask |= AR_IMR_TXEOL;
3295 }
3296 if (ints & ATH9K_INT_RX) {
3297 mask |= AR_IMR_RXERR;
3298 if (ah->config.intr_mitigation)
3299 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3300 else
3301 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3302 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3303 mask |= AR_IMR_GENTMR;
3304 }
3305
3306 if (ints & (ATH9K_INT_BMISC)) {
3307 mask |= AR_IMR_BCNMISC;
3308 if (ints & ATH9K_INT_TIM)
3309 mask2 |= AR_IMR_S2_TIM;
3310 if (ints & ATH9K_INT_DTIM)
3311 mask2 |= AR_IMR_S2_DTIM;
3312 if (ints & ATH9K_INT_DTIMSYNC)
3313 mask2 |= AR_IMR_S2_DTIMSYNC;
3314 if (ints & ATH9K_INT_CABEND)
3315 mask2 |= AR_IMR_S2_CABEND;
3316 if (ints & ATH9K_INT_TSFOOR)
3317 mask2 |= AR_IMR_S2_TSFOOR;
3318 }
3319
3320 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3321 mask |= AR_IMR_BCNMISC;
3322 if (ints & ATH9K_INT_GTT)
3323 mask2 |= AR_IMR_S2_GTT;
3324 if (ints & ATH9K_INT_CST)
3325 mask2 |= AR_IMR_S2_CST;
3326 }
3327
3328 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3329 REG_WRITE(ah, AR_IMR, mask);
3330 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3331 AR_IMR_S2_DTIM |
3332 AR_IMR_S2_DTIMSYNC |
3333 AR_IMR_S2_CABEND |
3334 AR_IMR_S2_CABTO |
3335 AR_IMR_S2_TSFOOR |
3336 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3337 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3338 ah->mask_reg = ints;
3339
3340 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3341 if (ints & ATH9K_INT_TIM_TIMER)
3342 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3343 else
3344 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3345 }
3346
3347 if (ints & ATH9K_INT_GLOBAL) {
3348 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
3349 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3350 if (!AR_SREV_9100(ah)) {
3351 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3352 AR_INTR_MAC_IRQ);
3353 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3354
3355
3356 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3357 AR_INTR_SYNC_DEFAULT);
3358 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3359 AR_INTR_SYNC_DEFAULT);
3360 }
3361 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3362 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3363 }
3364
3365 return omask;
3366 }
3367
3368 /*******************/
3369 /* Beacon Handling */
3370 /*******************/
3371
3372 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3373 {
3374 int flags = 0;
3375
3376 ah->beacon_interval = beacon_period;
3377
3378 switch (ah->opmode) {
3379 case NL80211_IFTYPE_STATION:
3380 case NL80211_IFTYPE_MONITOR:
3381 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3382 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3383 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3384 flags |= AR_TBTT_TIMER_EN;
3385 break;
3386 case NL80211_IFTYPE_ADHOC:
3387 case NL80211_IFTYPE_MESH_POINT:
3388 REG_SET_BIT(ah, AR_TXCFG,
3389 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3390 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3391 TU_TO_USEC(next_beacon +
3392 (ah->atim_window ? ah->
3393 atim_window : 1)));
3394 flags |= AR_NDP_TIMER_EN;
3395 case NL80211_IFTYPE_AP:
3396 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3397 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3398 TU_TO_USEC(next_beacon -
3399 ah->config.
3400 dma_beacon_response_time));
3401 REG_WRITE(ah, AR_NEXT_SWBA,
3402 TU_TO_USEC(next_beacon -
3403 ah->config.
3404 sw_beacon_response_time));
3405 flags |=
3406 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3407 break;
3408 default:
3409 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3410 "%s: unsupported opmode: %d\n",
3411 __func__, ah->opmode);
3412 return;
3413 break;
3414 }
3415
3416 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3417 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3418 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3419 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3420
3421 beacon_period &= ~ATH9K_BEACON_ENA;
3422 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3423 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3424 ath9k_hw_reset_tsf(ah);
3425 }
3426
3427 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3428 }
3429
3430 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3431 const struct ath9k_beacon_state *bs)
3432 {
3433 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3434 struct ath9k_hw_capabilities *pCap = &ah->caps;
3435 struct ath_common *common = ath9k_hw_common(ah);
3436
3437 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3438
3439 REG_WRITE(ah, AR_BEACON_PERIOD,
3440 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3441 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3442 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3443
3444 REG_RMW_FIELD(ah, AR_RSSI_THR,
3445 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3446
3447 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3448
3449 if (bs->bs_sleepduration > beaconintval)
3450 beaconintval = bs->bs_sleepduration;
3451
3452 dtimperiod = bs->bs_dtimperiod;
3453 if (bs->bs_sleepduration > dtimperiod)
3454 dtimperiod = bs->bs_sleepduration;
3455
3456 if (beaconintval == dtimperiod)
3457 nextTbtt = bs->bs_nextdtim;
3458 else
3459 nextTbtt = bs->bs_nexttbtt;
3460
3461 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3462 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3463 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3464 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3465
3466 REG_WRITE(ah, AR_NEXT_DTIM,
3467 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3468 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3469
3470 REG_WRITE(ah, AR_SLEEP1,
3471 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3472 | AR_SLEEP1_ASSUME_DTIM);
3473
3474 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3475 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3476 else
3477 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3478
3479 REG_WRITE(ah, AR_SLEEP2,
3480 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3481
3482 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3483 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3484
3485 REG_SET_BIT(ah, AR_TIMER_MODE,
3486 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3487 AR_DTIM_TIMER_EN);
3488
3489 /* TSF Out of Range Threshold */
3490 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3491 }
3492
3493 /*******************/
3494 /* HW Capabilities */
3495 /*******************/
3496
3497 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3498 {
3499 struct ath9k_hw_capabilities *pCap = &ah->caps;
3500 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3501 struct ath_common *common = ath9k_hw_common(ah);
3502 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3503
3504 u16 capField = 0, eeval;
3505
3506 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3507 regulatory->current_rd = eeval;
3508
3509 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3510 if (AR_SREV_9285_10_OR_LATER(ah))
3511 eeval |= AR9285_RDEXT_DEFAULT;
3512 regulatory->current_rd_ext = eeval;
3513
3514 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3515
3516 if (ah->opmode != NL80211_IFTYPE_AP &&
3517 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3518 if (regulatory->current_rd == 0x64 ||
3519 regulatory->current_rd == 0x65)
3520 regulatory->current_rd += 5;
3521 else if (regulatory->current_rd == 0x41)
3522 regulatory->current_rd = 0x43;
3523 ath_print(common, ATH_DBG_REGULATORY,
3524 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3525 }
3526
3527 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3528 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3529
3530 if (eeval & AR5416_OPFLAGS_11A) {
3531 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3532 if (ah->config.ht_enable) {
3533 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3534 set_bit(ATH9K_MODE_11NA_HT20,
3535 pCap->wireless_modes);
3536 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3537 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3538 pCap->wireless_modes);
3539 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3540 pCap->wireless_modes);
3541 }
3542 }
3543 }
3544
3545 if (eeval & AR5416_OPFLAGS_11G) {
3546 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3547 if (ah->config.ht_enable) {
3548 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3549 set_bit(ATH9K_MODE_11NG_HT20,
3550 pCap->wireless_modes);
3551 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3552 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3553 pCap->wireless_modes);
3554 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3555 pCap->wireless_modes);
3556 }
3557 }
3558 }
3559
3560 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3561 /*
3562 * For AR9271 we will temporarilly uses the rx chainmax as read from
3563 * the EEPROM.
3564 */
3565 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3566 !(eeval & AR5416_OPFLAGS_11A) &&
3567 !(AR_SREV_9271(ah)))
3568 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3569 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3570 else
3571 /* Use rx_chainmask from EEPROM. */
3572 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3573
3574 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3575 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3576
3577 pCap->low_2ghz_chan = 2312;
3578 pCap->high_2ghz_chan = 2732;
3579
3580 pCap->low_5ghz_chan = 4920;
3581 pCap->high_5ghz_chan = 6100;
3582
3583 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3584 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3585 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3586
3587 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3588 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3589 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3590
3591 if (ah->config.ht_enable)
3592 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3593 else
3594 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3595
3596 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3597 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3598 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3599 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3600
3601 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3602 pCap->total_queues =
3603 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3604 else
3605 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3606
3607 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3608 pCap->keycache_size =
3609 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3610 else
3611 pCap->keycache_size = AR_KEYTABLE_SIZE;
3612
3613 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3614 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3615
3616 if (AR_SREV_9285_10_OR_LATER(ah))
3617 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3618 else if (AR_SREV_9280_10_OR_LATER(ah))
3619 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3620 else
3621 pCap->num_gpio_pins = AR_NUM_GPIO;
3622
3623 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3624 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3625 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3626 } else {
3627 pCap->rts_aggr_limit = (8 * 1024);
3628 }
3629
3630 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3631
3632 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3633 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3634 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3635 ah->rfkill_gpio =
3636 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3637 ah->rfkill_polarity =
3638 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3639
3640 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3641 }
3642 #endif
3643
3644 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3645
3646 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3647 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3648 else
3649 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3650
3651 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3652 pCap->reg_cap =
3653 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3654 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3655 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3656 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3657 } else {
3658 pCap->reg_cap =
3659 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3660 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3661 }
3662
3663 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3664
3665 pCap->num_antcfg_5ghz =
3666 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3667 pCap->num_antcfg_2ghz =
3668 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3669
3670 if (AR_SREV_9280_10_OR_LATER(ah) &&
3671 ath9k_hw_btcoex_supported(ah)) {
3672 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3673 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3674
3675 if (AR_SREV_9285(ah)) {
3676 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3677 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3678 } else {
3679 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3680 }
3681 } else {
3682 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3683 }
3684 }
3685
3686 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3687 u32 capability, u32 *result)
3688 {
3689 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3690 switch (type) {
3691 case ATH9K_CAP_CIPHER:
3692 switch (capability) {
3693 case ATH9K_CIPHER_AES_CCM:
3694 case ATH9K_CIPHER_AES_OCB:
3695 case ATH9K_CIPHER_TKIP:
3696 case ATH9K_CIPHER_WEP:
3697 case ATH9K_CIPHER_MIC:
3698 case ATH9K_CIPHER_CLR:
3699 return true;
3700 default:
3701 return false;
3702 }
3703 case ATH9K_CAP_TKIP_MIC:
3704 switch (capability) {
3705 case 0:
3706 return true;
3707 case 1:
3708 return (ah->sta_id1_defaults &
3709 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3710 false;
3711 }
3712 case ATH9K_CAP_TKIP_SPLIT:
3713 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3714 false : true;
3715 case ATH9K_CAP_DIVERSITY:
3716 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3717 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3718 true : false;
3719 case ATH9K_CAP_MCAST_KEYSRCH:
3720 switch (capability) {
3721 case 0:
3722 return true;
3723 case 1:
3724 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3725 return false;
3726 } else {
3727 return (ah->sta_id1_defaults &
3728 AR_STA_ID1_MCAST_KSRCH) ? true :
3729 false;
3730 }
3731 }
3732 return false;
3733 case ATH9K_CAP_TXPOW:
3734 switch (capability) {
3735 case 0:
3736 return 0;
3737 case 1:
3738 *result = regulatory->power_limit;
3739 return 0;
3740 case 2:
3741 *result = regulatory->max_power_level;
3742 return 0;
3743 case 3:
3744 *result = regulatory->tp_scale;
3745 return 0;
3746 }
3747 return false;
3748 case ATH9K_CAP_DS:
3749 return (AR_SREV_9280_20_OR_LATER(ah) &&
3750 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3751 ? false : true;
3752 default:
3753 return false;
3754 }
3755 }
3756
3757 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3758 u32 capability, u32 setting, int *status)
3759 {
3760 u32 v;
3761
3762 switch (type) {
3763 case ATH9K_CAP_TKIP_MIC:
3764 if (setting)
3765 ah->sta_id1_defaults |=
3766 AR_STA_ID1_CRPT_MIC_ENABLE;
3767 else
3768 ah->sta_id1_defaults &=
3769 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3770 return true;
3771 case ATH9K_CAP_DIVERSITY:
3772 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3773 if (setting)
3774 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3775 else
3776 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3777 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3778 return true;
3779 case ATH9K_CAP_MCAST_KEYSRCH:
3780 if (setting)
3781 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3782 else
3783 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3784 return true;
3785 default:
3786 return false;
3787 }
3788 }
3789
3790 /****************************/
3791 /* GPIO / RFKILL / Antennae */
3792 /****************************/
3793
3794 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3795 u32 gpio, u32 type)
3796 {
3797 int addr;
3798 u32 gpio_shift, tmp;
3799
3800 if (gpio > 11)
3801 addr = AR_GPIO_OUTPUT_MUX3;
3802 else if (gpio > 5)
3803 addr = AR_GPIO_OUTPUT_MUX2;
3804 else
3805 addr = AR_GPIO_OUTPUT_MUX1;
3806
3807 gpio_shift = (gpio % 6) * 5;
3808
3809 if (AR_SREV_9280_20_OR_LATER(ah)
3810 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3811 REG_RMW(ah, addr, (type << gpio_shift),
3812 (0x1f << gpio_shift));
3813 } else {
3814 tmp = REG_READ(ah, addr);
3815 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3816 tmp &= ~(0x1f << gpio_shift);
3817 tmp |= (type << gpio_shift);
3818 REG_WRITE(ah, addr, tmp);
3819 }
3820 }
3821
3822 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3823 {
3824 u32 gpio_shift;
3825
3826 ASSERT(gpio < ah->caps.num_gpio_pins);
3827
3828 gpio_shift = gpio << 1;
3829
3830 REG_RMW(ah,
3831 AR_GPIO_OE_OUT,
3832 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3833 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3834 }
3835
3836 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3837 {
3838 #define MS_REG_READ(x, y) \
3839 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3840
3841 if (gpio >= ah->caps.num_gpio_pins)
3842 return 0xffffffff;
3843
3844 if (AR_SREV_9287_10_OR_LATER(ah))
3845 return MS_REG_READ(AR9287, gpio) != 0;
3846 else if (AR_SREV_9285_10_OR_LATER(ah))
3847 return MS_REG_READ(AR9285, gpio) != 0;
3848 else if (AR_SREV_9280_10_OR_LATER(ah))
3849 return MS_REG_READ(AR928X, gpio) != 0;
3850 else
3851 return MS_REG_READ(AR, gpio) != 0;
3852 }
3853
3854 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3855 u32 ah_signal_type)
3856 {
3857 u32 gpio_shift;
3858
3859 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3860
3861 gpio_shift = 2 * gpio;
3862
3863 REG_RMW(ah,
3864 AR_GPIO_OE_OUT,
3865 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3866 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3867 }
3868
3869 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3870 {
3871 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3872 AR_GPIO_BIT(gpio));
3873 }
3874
3875 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3876 {
3877 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3878 }
3879
3880 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3881 {
3882 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3883 }
3884
3885 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3886 enum ath9k_ant_setting settings,
3887 struct ath9k_channel *chan,
3888 u8 *tx_chainmask,
3889 u8 *rx_chainmask,
3890 u8 *antenna_cfgd)
3891 {
3892 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3893
3894 if (AR_SREV_9280(ah)) {
3895 if (!tx_chainmask_cfg) {
3896
3897 tx_chainmask_cfg = *tx_chainmask;
3898 rx_chainmask_cfg = *rx_chainmask;
3899 }
3900
3901 switch (settings) {
3902 case ATH9K_ANT_FIXED_A:
3903 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3904 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3905 *antenna_cfgd = true;
3906 break;
3907 case ATH9K_ANT_FIXED_B:
3908 if (ah->caps.tx_chainmask >
3909 ATH9K_ANTENNA1_CHAINMASK) {
3910 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3911 }
3912 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3913 *antenna_cfgd = true;
3914 break;
3915 case ATH9K_ANT_VARIABLE:
3916 *tx_chainmask = tx_chainmask_cfg;
3917 *rx_chainmask = rx_chainmask_cfg;
3918 *antenna_cfgd = true;
3919 break;
3920 default:
3921 break;
3922 }
3923 } else {
3924 ah->config.diversity_control = settings;
3925 }
3926
3927 return true;
3928 }
3929
3930 /*********************/
3931 /* General Operation */
3932 /*********************/
3933
3934 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3935 {
3936 u32 bits = REG_READ(ah, AR_RX_FILTER);
3937 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3938
3939 if (phybits & AR_PHY_ERR_RADAR)
3940 bits |= ATH9K_RX_FILTER_PHYRADAR;
3941 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3942 bits |= ATH9K_RX_FILTER_PHYERR;
3943
3944 return bits;
3945 }
3946
3947 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3948 {
3949 u32 phybits;
3950
3951 REG_WRITE(ah, AR_RX_FILTER, bits);
3952
3953 phybits = 0;
3954 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3955 phybits |= AR_PHY_ERR_RADAR;
3956 if (bits & ATH9K_RX_FILTER_PHYERR)
3957 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3958 REG_WRITE(ah, AR_PHY_ERR, phybits);
3959
3960 if (phybits)
3961 REG_WRITE(ah, AR_RXCFG,
3962 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3963 else
3964 REG_WRITE(ah, AR_RXCFG,
3965 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3966 }
3967
3968 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3969 {
3970 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3971 }
3972
3973 bool ath9k_hw_disable(struct ath_hw *ah)
3974 {
3975 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3976 return false;
3977
3978 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3979 }
3980
3981 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3982 {
3983 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3984 struct ath9k_channel *chan = ah->curchan;
3985 struct ieee80211_channel *channel = chan->chan;
3986
3987 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3988
3989 ah->eep_ops->set_txpower(ah, chan,
3990 ath9k_regd_get_ctl(regulatory, chan),
3991 channel->max_antenna_gain * 2,
3992 channel->max_power * 2,
3993 min((u32) MAX_RATE_POWER,
3994 (u32) regulatory->power_limit));
3995 }
3996
3997 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3998 {
3999 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
4000 }
4001
4002 void ath9k_hw_setopmode(struct ath_hw *ah)
4003 {
4004 ath9k_hw_set_operating_mode(ah, ah->opmode);
4005 }
4006
4007 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
4008 {
4009 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4010 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4011 }
4012
4013 void ath9k_hw_write_associd(struct ath_hw *ah)
4014 {
4015 struct ath_common *common = ath9k_hw_common(ah);
4016
4017 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
4018 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
4019 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4020 }
4021
4022 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4023 {
4024 u64 tsf;
4025
4026 tsf = REG_READ(ah, AR_TSF_U32);
4027 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4028
4029 return tsf;
4030 }
4031
4032 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4033 {
4034 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4035 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4036 }
4037
4038 void ath9k_hw_reset_tsf(struct ath_hw *ah)
4039 {
4040 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4041 AH_TSF_WRITE_TIMEOUT))
4042 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4043 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4044
4045 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4046 }
4047
4048 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4049 {
4050 if (setting)
4051 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
4052 else
4053 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4054 }
4055
4056 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4057 {
4058 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4059 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4060 "bad slot time %u\n", us);
4061 ah->slottime = (u32) -1;
4062 return false;
4063 } else {
4064 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4065 ah->slottime = us;
4066 return true;
4067 }
4068 }
4069
4070 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
4071 {
4072 u32 macmode;
4073
4074 if (mode == ATH9K_HT_MACMODE_2040 &&
4075 !ah->config.cwm_ignore_extcca)
4076 macmode = AR_2040_JOINED_RX_CLEAR;
4077 else
4078 macmode = 0;
4079
4080 REG_WRITE(ah, AR_2040_MODE, macmode);
4081 }
4082
4083 /* HW Generic timers configuration */
4084
4085 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4086 {
4087 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4088 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4089 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4090 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4091 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4092 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4093 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4094 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4095 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4096 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4097 AR_NDP2_TIMER_MODE, 0x0002},
4098 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4099 AR_NDP2_TIMER_MODE, 0x0004},
4100 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4101 AR_NDP2_TIMER_MODE, 0x0008},
4102 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4103 AR_NDP2_TIMER_MODE, 0x0010},
4104 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4105 AR_NDP2_TIMER_MODE, 0x0020},
4106 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4107 AR_NDP2_TIMER_MODE, 0x0040},
4108 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4109 AR_NDP2_TIMER_MODE, 0x0080}
4110 };
4111
4112 /* HW generic timer primitives */
4113
4114 /* compute and clear index of rightmost 1 */
4115 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4116 {
4117 u32 b;
4118
4119 b = *mask;
4120 b &= (0-b);
4121 *mask &= ~b;
4122 b *= debruijn32;
4123 b >>= 27;
4124
4125 return timer_table->gen_timer_index[b];
4126 }
4127
4128 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
4129 {
4130 return REG_READ(ah, AR_TSF_L32);
4131 }
4132
4133 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4134 void (*trigger)(void *),
4135 void (*overflow)(void *),
4136 void *arg,
4137 u8 timer_index)
4138 {
4139 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4140 struct ath_gen_timer *timer;
4141
4142 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4143
4144 if (timer == NULL) {
4145 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
4146 "Failed to allocate memory"
4147 "for hw timer[%d]\n", timer_index);
4148 return NULL;
4149 }
4150
4151 /* allocate a hardware generic timer slot */
4152 timer_table->timers[timer_index] = timer;
4153 timer->index = timer_index;
4154 timer->trigger = trigger;
4155 timer->overflow = overflow;
4156 timer->arg = arg;
4157
4158 return timer;
4159 }
4160
4161 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
4162 struct ath_gen_timer *timer,
4163 u32 timer_next,
4164 u32 timer_period)
4165 {
4166 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4167 u32 tsf;
4168
4169 BUG_ON(!timer_period);
4170
4171 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4172
4173 tsf = ath9k_hw_gettsf32(ah);
4174
4175 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
4176 "curent tsf %x period %x"
4177 "timer_next %x\n", tsf, timer_period, timer_next);
4178
4179 /*
4180 * Pull timer_next forward if the current TSF already passed it
4181 * because of software latency
4182 */
4183 if (timer_next < tsf)
4184 timer_next = tsf + timer_period;
4185
4186 /*
4187 * Program generic timer registers
4188 */
4189 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4190 timer_next);
4191 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4192 timer_period);
4193 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4194 gen_tmr_configuration[timer->index].mode_mask);
4195
4196 /* Enable both trigger and thresh interrupt masks */
4197 REG_SET_BIT(ah, AR_IMR_S5,
4198 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4199 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4200 }
4201
4202 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4203 {
4204 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4205
4206 if ((timer->index < AR_FIRST_NDP_TIMER) ||
4207 (timer->index >= ATH_MAX_GEN_TIMER)) {
4208 return;
4209 }
4210
4211 /* Clear generic timer enable bits. */
4212 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4213 gen_tmr_configuration[timer->index].mode_mask);
4214
4215 /* Disable both trigger and thresh interrupt masks */
4216 REG_CLR_BIT(ah, AR_IMR_S5,
4217 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4218 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4219
4220 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4221 }
4222
4223 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4224 {
4225 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4226
4227 /* free the hardware generic timer slot */
4228 timer_table->timers[timer->index] = NULL;
4229 kfree(timer);
4230 }
4231
4232 /*
4233 * Generic Timer Interrupts handling
4234 */
4235 void ath_gen_timer_isr(struct ath_hw *ah)
4236 {
4237 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4238 struct ath_gen_timer *timer;
4239 struct ath_common *common = ath9k_hw_common(ah);
4240 u32 trigger_mask, thresh_mask, index;
4241
4242 /* get hardware generic timer interrupt status */
4243 trigger_mask = ah->intr_gen_timer_trigger;
4244 thresh_mask = ah->intr_gen_timer_thresh;
4245 trigger_mask &= timer_table->timer_mask.val;
4246 thresh_mask &= timer_table->timer_mask.val;
4247
4248 trigger_mask &= ~thresh_mask;
4249
4250 while (thresh_mask) {
4251 index = rightmost_index(timer_table, &thresh_mask);
4252 timer = timer_table->timers[index];
4253 BUG_ON(!timer);
4254 ath_print(common, ATH_DBG_HWTIMER,
4255 "TSF overflow for Gen timer %d\n", index);
4256 timer->overflow(timer->arg);
4257 }
4258
4259 while (trigger_mask) {
4260 index = rightmost_index(timer_table, &trigger_mask);
4261 timer = timer_table->timers[index];
4262 BUG_ON(!timer);
4263 ath_print(common, ATH_DBG_HWTIMER,
4264 "Gen timer[%d] trigger\n", index);
4265 timer->trigger(timer->arg);
4266 }
4267 }
Linux kernel - Deliverables
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