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ath9k_hw: fix fast clock handling for 5GHz channels
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "hw-ops.h"
22 #include "rc.h"
23 #include "ar9003_mac.h"
24
25 #define ATH9K_CLOCK_RATE_CCK 22
26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
29
30 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
31
32 MODULE_AUTHOR("Atheros Communications");
33 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
34 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
35 MODULE_LICENSE("Dual BSD/GPL");
36
37 static int __init ath9k_init(void)
38 {
39 return 0;
40 }
41 module_init(ath9k_init);
42
43 static void __exit ath9k_exit(void)
44 {
45 return;
46 }
47 module_exit(ath9k_exit);
48
49 /* Private hardware callbacks */
50
51 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52 {
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54 }
55
56 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57 {
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59 }
60
61 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
62 {
63 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
64
65 return priv_ops->macversion_supported(ah->hw_version.macVersion);
66 }
67
68 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
69 struct ath9k_channel *chan)
70 {
71 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
72 }
73
74 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
75 {
76 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
77 return;
78
79 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
80 }
81
82 /********************/
83 /* Helper Functions */
84 /********************/
85
86 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
87 {
88 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
89
90 if (!ah->curchan) /* should really check for CCK instead */
91 return usecs *ATH9K_CLOCK_RATE_CCK;
92 if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
94
95 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
96 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
97 else
98 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
99 }
100
101 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
102 {
103 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
104
105 if (conf_is_ht40(conf))
106 return ath9k_hw_mac_clks(ah, usecs) * 2;
107 else
108 return ath9k_hw_mac_clks(ah, usecs);
109 }
110
111 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
112 {
113 int i;
114
115 BUG_ON(timeout < AH_TIME_QUANTUM);
116
117 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
118 if ((REG_READ(ah, reg) & mask) == val)
119 return true;
120
121 udelay(AH_TIME_QUANTUM);
122 }
123
124 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
125 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
126 timeout, reg, REG_READ(ah, reg), mask, val);
127
128 return false;
129 }
130 EXPORT_SYMBOL(ath9k_hw_wait);
131
132 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
133 {
134 u32 retval;
135 int i;
136
137 for (i = 0, retval = 0; i < n; i++) {
138 retval = (retval << 1) | (val & 1);
139 val >>= 1;
140 }
141 return retval;
142 }
143
144 bool ath9k_get_channel_edges(struct ath_hw *ah,
145 u16 flags, u16 *low,
146 u16 *high)
147 {
148 struct ath9k_hw_capabilities *pCap = &ah->caps;
149
150 if (flags & CHANNEL_5GHZ) {
151 *low = pCap->low_5ghz_chan;
152 *high = pCap->high_5ghz_chan;
153 return true;
154 }
155 if ((flags & CHANNEL_2GHZ)) {
156 *low = pCap->low_2ghz_chan;
157 *high = pCap->high_2ghz_chan;
158 return true;
159 }
160 return false;
161 }
162
163 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
164 u8 phy, int kbps,
165 u32 frameLen, u16 rateix,
166 bool shortPreamble)
167 {
168 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
169
170 if (kbps == 0)
171 return 0;
172
173 switch (phy) {
174 case WLAN_RC_PHY_CCK:
175 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
176 if (shortPreamble)
177 phyTime >>= 1;
178 numBits = frameLen << 3;
179 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
180 break;
181 case WLAN_RC_PHY_OFDM:
182 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
183 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
184 numBits = OFDM_PLCP_BITS + (frameLen << 3);
185 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
186 txTime = OFDM_SIFS_TIME_QUARTER
187 + OFDM_PREAMBLE_TIME_QUARTER
188 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
189 } else if (ah->curchan &&
190 IS_CHAN_HALF_RATE(ah->curchan)) {
191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
192 numBits = OFDM_PLCP_BITS + (frameLen << 3);
193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
194 txTime = OFDM_SIFS_TIME_HALF +
195 OFDM_PREAMBLE_TIME_HALF
196 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
197 } else {
198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
199 numBits = OFDM_PLCP_BITS + (frameLen << 3);
200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
201 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
202 + (numSymbols * OFDM_SYMBOL_TIME);
203 }
204 break;
205 default:
206 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
207 "Unknown phy %u (rate ix %u)\n", phy, rateix);
208 txTime = 0;
209 break;
210 }
211
212 return txTime;
213 }
214 EXPORT_SYMBOL(ath9k_hw_computetxtime);
215
216 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
217 struct ath9k_channel *chan,
218 struct chan_centers *centers)
219 {
220 int8_t extoff;
221
222 if (!IS_CHAN_HT40(chan)) {
223 centers->ctl_center = centers->ext_center =
224 centers->synth_center = chan->channel;
225 return;
226 }
227
228 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
229 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
230 centers->synth_center =
231 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
232 extoff = 1;
233 } else {
234 centers->synth_center =
235 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
236 extoff = -1;
237 }
238
239 centers->ctl_center =
240 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
241 /* 25 MHz spacing is supported by hw but not on upper layers */
242 centers->ext_center =
243 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
244 }
245
246 /******************/
247 /* Chip Revisions */
248 /******************/
249
250 static void ath9k_hw_read_revisions(struct ath_hw *ah)
251 {
252 u32 val;
253
254 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
255
256 if (val == 0xFF) {
257 val = REG_READ(ah, AR_SREV);
258 ah->hw_version.macVersion =
259 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
260 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
261 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
262 } else {
263 if (!AR_SREV_9100(ah))
264 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
265
266 ah->hw_version.macRev = val & AR_SREV_REVISION;
267
268 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
269 ah->is_pciexpress = true;
270 }
271 }
272
273 /************************************/
274 /* HW Attach, Detach, Init Routines */
275 /************************************/
276
277 static void ath9k_hw_disablepcie(struct ath_hw *ah)
278 {
279 if (AR_SREV_9100(ah))
280 return;
281
282 ENABLE_REGWRITE_BUFFER(ah);
283
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
293
294 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
295
296 REGWRITE_BUFFER_FLUSH(ah);
297 DISABLE_REGWRITE_BUFFER(ah);
298 }
299
300 /* This should work for all families including legacy */
301 static bool ath9k_hw_chip_test(struct ath_hw *ah)
302 {
303 struct ath_common *common = ath9k_hw_common(ah);
304 u32 regAddr[2] = { AR_STA_ID0 };
305 u32 regHold[2];
306 u32 patternData[4] = { 0x55555555,
307 0xaaaaaaaa,
308 0x66666666,
309 0x99999999 };
310 int i, j, loop_max;
311
312 if (!AR_SREV_9300_20_OR_LATER(ah)) {
313 loop_max = 2;
314 regAddr[1] = AR_PHY_BASE + (8 << 2);
315 } else
316 loop_max = 1;
317
318 for (i = 0; i < loop_max; i++) {
319 u32 addr = regAddr[i];
320 u32 wrData, rdData;
321
322 regHold[i] = REG_READ(ah, addr);
323 for (j = 0; j < 0x100; j++) {
324 wrData = (j << 16) | j;
325 REG_WRITE(ah, addr, wrData);
326 rdData = REG_READ(ah, addr);
327 if (rdData != wrData) {
328 ath_print(common, ATH_DBG_FATAL,
329 "address test failed "
330 "addr: 0x%08x - wr:0x%08x != "
331 "rd:0x%08x\n",
332 addr, wrData, rdData);
333 return false;
334 }
335 }
336 for (j = 0; j < 4; j++) {
337 wrData = patternData[j];
338 REG_WRITE(ah, addr, wrData);
339 rdData = REG_READ(ah, addr);
340 if (wrData != rdData) {
341 ath_print(common, ATH_DBG_FATAL,
342 "address test failed "
343 "addr: 0x%08x - wr:0x%08x != "
344 "rd:0x%08x\n",
345 addr, wrData, rdData);
346 return false;
347 }
348 }
349 REG_WRITE(ah, regAddr[i], regHold[i]);
350 }
351 udelay(100);
352
353 return true;
354 }
355
356 static void ath9k_hw_init_config(struct ath_hw *ah)
357 {
358 int i;
359
360 ah->config.dma_beacon_response_time = 2;
361 ah->config.sw_beacon_response_time = 10;
362 ah->config.additional_swba_backoff = 0;
363 ah->config.ack_6mb = 0x0;
364 ah->config.cwm_ignore_extcca = 0;
365 ah->config.pcie_powersave_enable = 0;
366 ah->config.pcie_clock_req = 0;
367 ah->config.pcie_waen = 0;
368 ah->config.analog_shiftreg = 1;
369 ah->config.ofdm_trig_low = 200;
370 ah->config.ofdm_trig_high = 500;
371 ah->config.cck_trig_high = 200;
372 ah->config.cck_trig_low = 100;
373
374 /*
375 * For now ANI is disabled for AR9003, it is still
376 * being tested.
377 */
378 if (!AR_SREV_9300_20_OR_LATER(ah))
379 ah->config.enable_ani = 1;
380
381 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
382 ah->config.spurchans[i][0] = AR_NO_SPUR;
383 ah->config.spurchans[i][1] = AR_NO_SPUR;
384 }
385
386 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
387 ah->config.ht_enable = 1;
388 else
389 ah->config.ht_enable = 0;
390
391 ah->config.rx_intr_mitigation = true;
392
393 /*
394 * Tx IQ Calibration (ah->config.tx_iq_calibration) is only
395 * used by AR9003, but it is showing reliability issues.
396 * It will take a while to fix so this is currently disabled.
397 */
398
399 /*
400 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
401 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
402 * This means we use it for all AR5416 devices, and the few
403 * minor PCI AR9280 devices out there.
404 *
405 * Serialization is required because these devices do not handle
406 * well the case of two concurrent reads/writes due to the latency
407 * involved. During one read/write another read/write can be issued
408 * on another CPU while the previous read/write may still be working
409 * on our hardware, if we hit this case the hardware poops in a loop.
410 * We prevent this by serializing reads and writes.
411 *
412 * This issue is not present on PCI-Express devices or pre-AR5416
413 * devices (legacy, 802.11abg).
414 */
415 if (num_possible_cpus() > 1)
416 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
417 }
418
419 static void ath9k_hw_init_defaults(struct ath_hw *ah)
420 {
421 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
422
423 regulatory->country_code = CTRY_DEFAULT;
424 regulatory->power_limit = MAX_RATE_POWER;
425 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
426
427 ah->hw_version.magic = AR5416_MAGIC;
428 ah->hw_version.subvendorid = 0;
429
430 ah->ah_flags = 0;
431 if (!AR_SREV_9100(ah))
432 ah->ah_flags = AH_USE_EEPROM;
433
434 ah->atim_window = 0;
435 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
436 ah->beacon_interval = 100;
437 ah->enable_32kHz_clock = DONT_USE_32KHZ;
438 ah->slottime = (u32) -1;
439 ah->globaltxtimeout = (u32) -1;
440 ah->power_mode = ATH9K_PM_UNDEFINED;
441 }
442
443 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
444 {
445 struct ath_common *common = ath9k_hw_common(ah);
446 u32 sum;
447 int i;
448 u16 eeval;
449 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
450
451 sum = 0;
452 for (i = 0; i < 3; i++) {
453 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
454 sum += eeval;
455 common->macaddr[2 * i] = eeval >> 8;
456 common->macaddr[2 * i + 1] = eeval & 0xff;
457 }
458 if (sum == 0 || sum == 0xffff * 3)
459 return -EADDRNOTAVAIL;
460
461 return 0;
462 }
463
464 static int ath9k_hw_post_init(struct ath_hw *ah)
465 {
466 int ecode;
467
468 if (!AR_SREV_9271(ah)) {
469 if (!ath9k_hw_chip_test(ah))
470 return -ENODEV;
471 }
472
473 if (!AR_SREV_9300_20_OR_LATER(ah)) {
474 ecode = ar9002_hw_rf_claim(ah);
475 if (ecode != 0)
476 return ecode;
477 }
478
479 ecode = ath9k_hw_eeprom_init(ah);
480 if (ecode != 0)
481 return ecode;
482
483 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
484 "Eeprom VER: %d, REV: %d\n",
485 ah->eep_ops->get_eeprom_ver(ah),
486 ah->eep_ops->get_eeprom_rev(ah));
487
488 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
489 if (ecode) {
490 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
491 "Failed allocating banks for "
492 "external radio\n");
493 return ecode;
494 }
495
496 if (!AR_SREV_9100(ah)) {
497 ath9k_hw_ani_setup(ah);
498 ath9k_hw_ani_init(ah);
499 }
500
501 return 0;
502 }
503
504 static void ath9k_hw_attach_ops(struct ath_hw *ah)
505 {
506 if (AR_SREV_9300_20_OR_LATER(ah))
507 ar9003_hw_attach_ops(ah);
508 else
509 ar9002_hw_attach_ops(ah);
510 }
511
512 /* Called for all hardware families */
513 static int __ath9k_hw_init(struct ath_hw *ah)
514 {
515 struct ath_common *common = ath9k_hw_common(ah);
516 int r = 0;
517
518 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
519 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
520
521 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
522 ath_print(common, ATH_DBG_FATAL,
523 "Couldn't reset chip\n");
524 return -EIO;
525 }
526
527 ath9k_hw_init_defaults(ah);
528 ath9k_hw_init_config(ah);
529
530 ath9k_hw_attach_ops(ah);
531
532 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
533 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
534 return -EIO;
535 }
536
537 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
538 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
539 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
540 ah->config.serialize_regmode =
541 SER_REG_MODE_ON;
542 } else {
543 ah->config.serialize_regmode =
544 SER_REG_MODE_OFF;
545 }
546 }
547
548 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
549 ah->config.serialize_regmode);
550
551 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
552 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
553 else
554 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
555
556 if (!ath9k_hw_macversion_supported(ah)) {
557 ath_print(common, ATH_DBG_FATAL,
558 "Mac Chip Rev 0x%02x.%x is not supported by "
559 "this driver\n", ah->hw_version.macVersion,
560 ah->hw_version.macRev);
561 return -EOPNOTSUPP;
562 }
563
564 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
565 ah->is_pciexpress = false;
566
567 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
568 ath9k_hw_init_cal_settings(ah);
569
570 ah->ani_function = ATH9K_ANI_ALL;
571 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
572 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
573
574 ath9k_hw_init_mode_regs(ah);
575
576 if (ah->is_pciexpress)
577 ath9k_hw_configpcipowersave(ah, 0, 0);
578 else
579 ath9k_hw_disablepcie(ah);
580
581 if (!AR_SREV_9300_20_OR_LATER(ah))
582 ar9002_hw_cck_chan14_spread(ah);
583
584 r = ath9k_hw_post_init(ah);
585 if (r)
586 return r;
587
588 ath9k_hw_init_mode_gain_regs(ah);
589 r = ath9k_hw_fill_cap_info(ah);
590 if (r)
591 return r;
592
593 r = ath9k_hw_init_macaddr(ah);
594 if (r) {
595 ath_print(common, ATH_DBG_FATAL,
596 "Failed to initialize MAC address\n");
597 return r;
598 }
599
600 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
601 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
602 else
603 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
604
605 if (AR_SREV_9300_20_OR_LATER(ah))
606 ar9003_hw_set_nf_limits(ah);
607
608 ath9k_init_nfcal_hist_buffer(ah);
609
610 common->state = ATH_HW_INITIALIZED;
611
612 return 0;
613 }
614
615 int ath9k_hw_init(struct ath_hw *ah)
616 {
617 int ret;
618 struct ath_common *common = ath9k_hw_common(ah);
619
620 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
621 switch (ah->hw_version.devid) {
622 case AR5416_DEVID_PCI:
623 case AR5416_DEVID_PCIE:
624 case AR5416_AR9100_DEVID:
625 case AR9160_DEVID_PCI:
626 case AR9280_DEVID_PCI:
627 case AR9280_DEVID_PCIE:
628 case AR9285_DEVID_PCIE:
629 case AR9287_DEVID_PCI:
630 case AR9287_DEVID_PCIE:
631 case AR2427_DEVID_PCIE:
632 case AR9300_DEVID_PCIE:
633 break;
634 default:
635 if (common->bus_ops->ath_bus_type == ATH_USB)
636 break;
637 ath_print(common, ATH_DBG_FATAL,
638 "Hardware device ID 0x%04x not supported\n",
639 ah->hw_version.devid);
640 return -EOPNOTSUPP;
641 }
642
643 ret = __ath9k_hw_init(ah);
644 if (ret) {
645 ath_print(common, ATH_DBG_FATAL,
646 "Unable to initialize hardware; "
647 "initialization status: %d\n", ret);
648 return ret;
649 }
650
651 return 0;
652 }
653 EXPORT_SYMBOL(ath9k_hw_init);
654
655 static void ath9k_hw_init_qos(struct ath_hw *ah)
656 {
657 ENABLE_REGWRITE_BUFFER(ah);
658
659 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
660 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
661
662 REG_WRITE(ah, AR_QOS_NO_ACK,
663 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
664 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
665 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
666
667 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
668 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
670 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
671 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
672
673 REGWRITE_BUFFER_FLUSH(ah);
674 DISABLE_REGWRITE_BUFFER(ah);
675 }
676
677 static void ath9k_hw_init_pll(struct ath_hw *ah,
678 struct ath9k_channel *chan)
679 {
680 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
681
682 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
683
684 /* Switch the core clock for ar9271 to 117Mhz */
685 if (AR_SREV_9271(ah)) {
686 udelay(500);
687 REG_WRITE(ah, 0x50040, 0x304);
688 }
689
690 udelay(RTC_PLL_SETTLE_DELAY);
691
692 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
693 }
694
695 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
696 enum nl80211_iftype opmode)
697 {
698 u32 imr_reg = AR_IMR_TXERR |
699 AR_IMR_TXURN |
700 AR_IMR_RXERR |
701 AR_IMR_RXORN |
702 AR_IMR_BCNMISC;
703
704 if (AR_SREV_9300_20_OR_LATER(ah)) {
705 imr_reg |= AR_IMR_RXOK_HP;
706 if (ah->config.rx_intr_mitigation)
707 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
708 else
709 imr_reg |= AR_IMR_RXOK_LP;
710
711 } else {
712 if (ah->config.rx_intr_mitigation)
713 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
714 else
715 imr_reg |= AR_IMR_RXOK;
716 }
717
718 if (ah->config.tx_intr_mitigation)
719 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
720 else
721 imr_reg |= AR_IMR_TXOK;
722
723 if (opmode == NL80211_IFTYPE_AP)
724 imr_reg |= AR_IMR_MIB;
725
726 ENABLE_REGWRITE_BUFFER(ah);
727
728 REG_WRITE(ah, AR_IMR, imr_reg);
729 ah->imrs2_reg |= AR_IMR_S2_GTT;
730 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
731
732 if (!AR_SREV_9100(ah)) {
733 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
734 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
735 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
736 }
737
738 REGWRITE_BUFFER_FLUSH(ah);
739 DISABLE_REGWRITE_BUFFER(ah);
740
741 if (AR_SREV_9300_20_OR_LATER(ah)) {
742 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
743 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
744 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
745 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
746 }
747 }
748
749 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
750 {
751 u32 val = ath9k_hw_mac_to_clks(ah, us);
752 val = min(val, (u32) 0xFFFF);
753 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
754 }
755
756 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
757 {
758 u32 val = ath9k_hw_mac_to_clks(ah, us);
759 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
760 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
761 }
762
763 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
764 {
765 u32 val = ath9k_hw_mac_to_clks(ah, us);
766 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
767 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
768 }
769
770 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
771 {
772 if (tu > 0xFFFF) {
773 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
774 "bad global tx timeout %u\n", tu);
775 ah->globaltxtimeout = (u32) -1;
776 return false;
777 } else {
778 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
779 ah->globaltxtimeout = tu;
780 return true;
781 }
782 }
783
784 void ath9k_hw_init_global_settings(struct ath_hw *ah)
785 {
786 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
787 int acktimeout;
788 int slottime;
789 int sifstime;
790
791 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
792 ah->misc_mode);
793
794 if (ah->misc_mode != 0)
795 REG_WRITE(ah, AR_PCU_MISC,
796 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
797
798 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
799 sifstime = 16;
800 else
801 sifstime = 10;
802
803 /* As defined by IEEE 802.11-2007 17.3.8.6 */
804 slottime = ah->slottime + 3 * ah->coverage_class;
805 acktimeout = slottime + sifstime;
806
807 /*
808 * Workaround for early ACK timeouts, add an offset to match the
809 * initval's 64us ack timeout value.
810 * This was initially only meant to work around an issue with delayed
811 * BA frames in some implementations, but it has been found to fix ACK
812 * timeout issues in other cases as well.
813 */
814 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
815 acktimeout += 64 - sifstime - ah->slottime;
816
817 ath9k_hw_setslottime(ah, slottime);
818 ath9k_hw_set_ack_timeout(ah, acktimeout);
819 ath9k_hw_set_cts_timeout(ah, acktimeout);
820 if (ah->globaltxtimeout != (u32) -1)
821 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
822 }
823 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
824
825 void ath9k_hw_deinit(struct ath_hw *ah)
826 {
827 struct ath_common *common = ath9k_hw_common(ah);
828
829 if (common->state < ATH_HW_INITIALIZED)
830 goto free_hw;
831
832 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
833
834 free_hw:
835 ath9k_hw_rf_free_ext_banks(ah);
836 }
837 EXPORT_SYMBOL(ath9k_hw_deinit);
838
839 /*******/
840 /* INI */
841 /*******/
842
843 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
844 {
845 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
846
847 if (IS_CHAN_B(chan))
848 ctl |= CTL_11B;
849 else if (IS_CHAN_G(chan))
850 ctl |= CTL_11G;
851 else
852 ctl |= CTL_11A;
853
854 return ctl;
855 }
856
857 /****************************************/
858 /* Reset and Channel Switching Routines */
859 /****************************************/
860
861 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
862 {
863 struct ath_common *common = ath9k_hw_common(ah);
864 u32 regval;
865
866 ENABLE_REGWRITE_BUFFER(ah);
867
868 /*
869 * set AHB_MODE not to do cacheline prefetches
870 */
871 if (!AR_SREV_9300_20_OR_LATER(ah)) {
872 regval = REG_READ(ah, AR_AHB_MODE);
873 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
874 }
875
876 /*
877 * let mac dma reads be in 128 byte chunks
878 */
879 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
880 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
881
882 REGWRITE_BUFFER_FLUSH(ah);
883 DISABLE_REGWRITE_BUFFER(ah);
884
885 /*
886 * Restore TX Trigger Level to its pre-reset value.
887 * The initial value depends on whether aggregation is enabled, and is
888 * adjusted whenever underruns are detected.
889 */
890 if (!AR_SREV_9300_20_OR_LATER(ah))
891 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
892
893 ENABLE_REGWRITE_BUFFER(ah);
894
895 /*
896 * let mac dma writes be in 128 byte chunks
897 */
898 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
899 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
900
901 /*
902 * Setup receive FIFO threshold to hold off TX activities
903 */
904 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
905
906 if (AR_SREV_9300_20_OR_LATER(ah)) {
907 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
908 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
909
910 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
911 ah->caps.rx_status_len);
912 }
913
914 /*
915 * reduce the number of usable entries in PCU TXBUF to avoid
916 * wrap around issues.
917 */
918 if (AR_SREV_9285(ah)) {
919 /* For AR9285 the number of Fifos are reduced to half.
920 * So set the usable tx buf size also to half to
921 * avoid data/delimiter underruns
922 */
923 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
924 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
925 } else if (!AR_SREV_9271(ah)) {
926 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
927 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
928 }
929
930 REGWRITE_BUFFER_FLUSH(ah);
931 DISABLE_REGWRITE_BUFFER(ah);
932
933 if (AR_SREV_9300_20_OR_LATER(ah))
934 ath9k_hw_reset_txstatus_ring(ah);
935 }
936
937 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
938 {
939 u32 val;
940
941 val = REG_READ(ah, AR_STA_ID1);
942 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
943 switch (opmode) {
944 case NL80211_IFTYPE_AP:
945 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
946 | AR_STA_ID1_KSRCH_MODE);
947 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
948 break;
949 case NL80211_IFTYPE_ADHOC:
950 case NL80211_IFTYPE_MESH_POINT:
951 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
952 | AR_STA_ID1_KSRCH_MODE);
953 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
954 break;
955 case NL80211_IFTYPE_STATION:
956 case NL80211_IFTYPE_MONITOR:
957 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
958 break;
959 }
960 }
961
962 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
963 u32 *coef_mantissa, u32 *coef_exponent)
964 {
965 u32 coef_exp, coef_man;
966
967 for (coef_exp = 31; coef_exp > 0; coef_exp--)
968 if ((coef_scaled >> coef_exp) & 0x1)
969 break;
970
971 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
972
973 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
974
975 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
976 *coef_exponent = coef_exp - 16;
977 }
978
979 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
980 {
981 u32 rst_flags;
982 u32 tmpReg;
983
984 if (AR_SREV_9100(ah)) {
985 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
986 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
987 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
988 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
989 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
990 }
991
992 ENABLE_REGWRITE_BUFFER(ah);
993
994 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
995 AR_RTC_FORCE_WAKE_ON_INT);
996
997 if (AR_SREV_9100(ah)) {
998 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
999 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1000 } else {
1001 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1002 if (tmpReg &
1003 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1004 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1005 u32 val;
1006 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1007
1008 val = AR_RC_HOSTIF;
1009 if (!AR_SREV_9300_20_OR_LATER(ah))
1010 val |= AR_RC_AHB;
1011 REG_WRITE(ah, AR_RC, val);
1012
1013 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1014 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1015
1016 rst_flags = AR_RTC_RC_MAC_WARM;
1017 if (type == ATH9K_RESET_COLD)
1018 rst_flags |= AR_RTC_RC_MAC_COLD;
1019 }
1020
1021 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1022
1023 REGWRITE_BUFFER_FLUSH(ah);
1024 DISABLE_REGWRITE_BUFFER(ah);
1025
1026 udelay(50);
1027
1028 REG_WRITE(ah, AR_RTC_RC, 0);
1029 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1030 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1031 "RTC stuck in MAC reset\n");
1032 return false;
1033 }
1034
1035 if (!AR_SREV_9100(ah))
1036 REG_WRITE(ah, AR_RC, 0);
1037
1038 if (AR_SREV_9100(ah))
1039 udelay(50);
1040
1041 return true;
1042 }
1043
1044 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1045 {
1046 ENABLE_REGWRITE_BUFFER(ah);
1047
1048 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1049 AR_RTC_FORCE_WAKE_ON_INT);
1050
1051 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1052 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1053
1054 REG_WRITE(ah, AR_RTC_RESET, 0);
1055
1056 REGWRITE_BUFFER_FLUSH(ah);
1057 DISABLE_REGWRITE_BUFFER(ah);
1058
1059 if (!AR_SREV_9300_20_OR_LATER(ah))
1060 udelay(2);
1061
1062 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1063 REG_WRITE(ah, AR_RC, 0);
1064
1065 REG_WRITE(ah, AR_RTC_RESET, 1);
1066
1067 if (!ath9k_hw_wait(ah,
1068 AR_RTC_STATUS,
1069 AR_RTC_STATUS_M,
1070 AR_RTC_STATUS_ON,
1071 AH_WAIT_TIMEOUT)) {
1072 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1073 "RTC not waking up\n");
1074 return false;
1075 }
1076
1077 ath9k_hw_read_revisions(ah);
1078
1079 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1080 }
1081
1082 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1083 {
1084 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1085 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1086
1087 switch (type) {
1088 case ATH9K_RESET_POWER_ON:
1089 return ath9k_hw_set_reset_power_on(ah);
1090 case ATH9K_RESET_WARM:
1091 case ATH9K_RESET_COLD:
1092 return ath9k_hw_set_reset(ah, type);
1093 default:
1094 return false;
1095 }
1096 }
1097
1098 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1099 struct ath9k_channel *chan)
1100 {
1101 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1102 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1103 return false;
1104 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1105 return false;
1106
1107 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1108 return false;
1109
1110 ah->chip_fullsleep = false;
1111 ath9k_hw_init_pll(ah, chan);
1112 ath9k_hw_set_rfmode(ah, chan);
1113
1114 return true;
1115 }
1116
1117 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1118 struct ath9k_channel *chan)
1119 {
1120 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1121 struct ath_common *common = ath9k_hw_common(ah);
1122 struct ieee80211_channel *channel = chan->chan;
1123 u32 qnum;
1124 int r;
1125
1126 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1127 if (ath9k_hw_numtxpending(ah, qnum)) {
1128 ath_print(common, ATH_DBG_QUEUE,
1129 "Transmit frames pending on "
1130 "queue %d\n", qnum);
1131 return false;
1132 }
1133 }
1134
1135 if (!ath9k_hw_rfbus_req(ah)) {
1136 ath_print(common, ATH_DBG_FATAL,
1137 "Could not kill baseband RX\n");
1138 return false;
1139 }
1140
1141 ath9k_hw_set_channel_regs(ah, chan);
1142
1143 r = ath9k_hw_rf_set_freq(ah, chan);
1144 if (r) {
1145 ath_print(common, ATH_DBG_FATAL,
1146 "Failed to set channel\n");
1147 return false;
1148 }
1149
1150 ah->eep_ops->set_txpower(ah, chan,
1151 ath9k_regd_get_ctl(regulatory, chan),
1152 channel->max_antenna_gain * 2,
1153 channel->max_power * 2,
1154 min((u32) MAX_RATE_POWER,
1155 (u32) regulatory->power_limit));
1156
1157 ath9k_hw_rfbus_done(ah);
1158
1159 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1160 ath9k_hw_set_delta_slope(ah, chan);
1161
1162 ath9k_hw_spur_mitigate_freq(ah, chan);
1163
1164 if (!chan->oneTimeCalsDone)
1165 chan->oneTimeCalsDone = true;
1166
1167 return true;
1168 }
1169
1170 bool ath9k_hw_check_alive(struct ath_hw *ah)
1171 {
1172 int count = 50;
1173 u32 reg;
1174
1175 if (AR_SREV_9285_10_OR_LATER(ah))
1176 return true;
1177
1178 do {
1179 reg = REG_READ(ah, AR_OBS_BUS_1);
1180
1181 if ((reg & 0x7E7FFFEF) == 0x00702400)
1182 continue;
1183
1184 switch (reg & 0x7E000B00) {
1185 case 0x1E000000:
1186 case 0x52000B00:
1187 case 0x18000B00:
1188 continue;
1189 default:
1190 return true;
1191 }
1192 } while (count-- > 0);
1193
1194 return false;
1195 }
1196 EXPORT_SYMBOL(ath9k_hw_check_alive);
1197
1198 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1199 bool bChannelChange)
1200 {
1201 struct ath_common *common = ath9k_hw_common(ah);
1202 u32 saveLedState;
1203 struct ath9k_channel *curchan = ah->curchan;
1204 u32 saveDefAntenna;
1205 u32 macStaId1;
1206 u64 tsf = 0;
1207 int i, r;
1208
1209 ah->txchainmask = common->tx_chainmask;
1210 ah->rxchainmask = common->rx_chainmask;
1211
1212 if (!ah->chip_fullsleep) {
1213 ath9k_hw_abortpcurecv(ah);
1214 if (!ath9k_hw_stopdmarecv(ah))
1215 ath_print(common, ATH_DBG_XMIT,
1216 "Failed to stop receive dma\n");
1217 }
1218
1219 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1220 return -EIO;
1221
1222 if (curchan && !ah->chip_fullsleep)
1223 ath9k_hw_getnf(ah, curchan);
1224
1225 if (bChannelChange &&
1226 (ah->chip_fullsleep != true) &&
1227 (ah->curchan != NULL) &&
1228 (chan->channel != ah->curchan->channel) &&
1229 ((chan->channelFlags & CHANNEL_ALL) ==
1230 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1231 !AR_SREV_9280(ah)) {
1232
1233 if (ath9k_hw_channel_change(ah, chan)) {
1234 ath9k_hw_loadnf(ah, ah->curchan);
1235 ath9k_hw_start_nfcal(ah);
1236 return 0;
1237 }
1238 }
1239
1240 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1241 if (saveDefAntenna == 0)
1242 saveDefAntenna = 1;
1243
1244 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1245
1246 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1247 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1248 tsf = ath9k_hw_gettsf64(ah);
1249
1250 saveLedState = REG_READ(ah, AR_CFG_LED) &
1251 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1252 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1253
1254 ath9k_hw_mark_phy_inactive(ah);
1255
1256 /* Only required on the first reset */
1257 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1258 REG_WRITE(ah,
1259 AR9271_RESET_POWER_DOWN_CONTROL,
1260 AR9271_RADIO_RF_RST);
1261 udelay(50);
1262 }
1263
1264 if (!ath9k_hw_chip_reset(ah, chan)) {
1265 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1266 return -EINVAL;
1267 }
1268
1269 /* Only required on the first reset */
1270 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1271 ah->htc_reset_init = false;
1272 REG_WRITE(ah,
1273 AR9271_RESET_POWER_DOWN_CONTROL,
1274 AR9271_GATE_MAC_CTL);
1275 udelay(50);
1276 }
1277
1278 /* Restore TSF */
1279 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1280 ath9k_hw_settsf64(ah, tsf);
1281
1282 if (AR_SREV_9280_10_OR_LATER(ah))
1283 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1284
1285 r = ath9k_hw_process_ini(ah, chan);
1286 if (r)
1287 return r;
1288
1289 /* Setup MFP options for CCMP */
1290 if (AR_SREV_9280_20_OR_LATER(ah)) {
1291 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1292 * frames when constructing CCMP AAD. */
1293 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1294 0xc7ff);
1295 ah->sw_mgmt_crypto = false;
1296 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1297 /* Disable hardware crypto for management frames */
1298 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1299 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1300 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1301 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1302 ah->sw_mgmt_crypto = true;
1303 } else
1304 ah->sw_mgmt_crypto = true;
1305
1306 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1307 ath9k_hw_set_delta_slope(ah, chan);
1308
1309 ath9k_hw_spur_mitigate_freq(ah, chan);
1310 ah->eep_ops->set_board_values(ah, chan);
1311
1312 ath9k_hw_set_operating_mode(ah, ah->opmode);
1313
1314 ENABLE_REGWRITE_BUFFER(ah);
1315
1316 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1317 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1318 | macStaId1
1319 | AR_STA_ID1_RTS_USE_DEF
1320 | (ah->config.
1321 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1322 | ah->sta_id1_defaults);
1323 ath_hw_setbssidmask(common);
1324 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1325 ath9k_hw_write_associd(ah);
1326 REG_WRITE(ah, AR_ISR, ~0);
1327 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1328
1329 REGWRITE_BUFFER_FLUSH(ah);
1330 DISABLE_REGWRITE_BUFFER(ah);
1331
1332 r = ath9k_hw_rf_set_freq(ah, chan);
1333 if (r)
1334 return r;
1335
1336 ENABLE_REGWRITE_BUFFER(ah);
1337
1338 for (i = 0; i < AR_NUM_DCU; i++)
1339 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1340
1341 REGWRITE_BUFFER_FLUSH(ah);
1342 DISABLE_REGWRITE_BUFFER(ah);
1343
1344 ah->intr_txqs = 0;
1345 for (i = 0; i < ah->caps.total_queues; i++)
1346 ath9k_hw_resettxqueue(ah, i);
1347
1348 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1349 ath9k_hw_init_qos(ah);
1350
1351 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1352 ath9k_enable_rfkill(ah);
1353
1354 ath9k_hw_init_global_settings(ah);
1355
1356 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1357 ar9002_hw_enable_async_fifo(ah);
1358 ar9002_hw_enable_wep_aggregation(ah);
1359 }
1360
1361 REG_WRITE(ah, AR_STA_ID1,
1362 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1363
1364 ath9k_hw_set_dma(ah);
1365
1366 REG_WRITE(ah, AR_OBS, 8);
1367
1368 if (ah->config.rx_intr_mitigation) {
1369 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1370 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1371 }
1372
1373 if (ah->config.tx_intr_mitigation) {
1374 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1375 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1376 }
1377
1378 ath9k_hw_init_bb(ah, chan);
1379
1380 if (!ath9k_hw_init_cal(ah, chan))
1381 return -EIO;
1382
1383 ENABLE_REGWRITE_BUFFER(ah);
1384
1385 ath9k_hw_restore_chainmask(ah);
1386 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1387
1388 REGWRITE_BUFFER_FLUSH(ah);
1389 DISABLE_REGWRITE_BUFFER(ah);
1390
1391 /*
1392 * For big endian systems turn on swapping for descriptors
1393 */
1394 if (AR_SREV_9100(ah)) {
1395 u32 mask;
1396 mask = REG_READ(ah, AR_CFG);
1397 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1398 ath_print(common, ATH_DBG_RESET,
1399 "CFG Byte Swap Set 0x%x\n", mask);
1400 } else {
1401 mask =
1402 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1403 REG_WRITE(ah, AR_CFG, mask);
1404 ath_print(common, ATH_DBG_RESET,
1405 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1406 }
1407 } else {
1408 /* Configure AR9271 target WLAN */
1409 if (AR_SREV_9271(ah))
1410 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1411 #ifdef __BIG_ENDIAN
1412 else
1413 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1414 #endif
1415 }
1416
1417 if (ah->btcoex_hw.enabled)
1418 ath9k_hw_btcoex_enable(ah);
1419
1420 if (AR_SREV_9300_20_OR_LATER(ah)) {
1421 ath9k_hw_loadnf(ah, curchan);
1422 ath9k_hw_start_nfcal(ah);
1423 }
1424
1425 return 0;
1426 }
1427 EXPORT_SYMBOL(ath9k_hw_reset);
1428
1429 /************************/
1430 /* Key Cache Management */
1431 /************************/
1432
1433 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1434 {
1435 u32 keyType;
1436
1437 if (entry >= ah->caps.keycache_size) {
1438 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1439 "keychache entry %u out of range\n", entry);
1440 return false;
1441 }
1442
1443 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1444
1445 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1446 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1447 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1448 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1449 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1450 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1451 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1452 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1453
1454 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1455 u16 micentry = entry + 64;
1456
1457 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1458 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1459 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1460 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1461
1462 }
1463
1464 return true;
1465 }
1466 EXPORT_SYMBOL(ath9k_hw_keyreset);
1467
1468 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1469 {
1470 u32 macHi, macLo;
1471
1472 if (entry >= ah->caps.keycache_size) {
1473 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1474 "keychache entry %u out of range\n", entry);
1475 return false;
1476 }
1477
1478 if (mac != NULL) {
1479 macHi = (mac[5] << 8) | mac[4];
1480 macLo = (mac[3] << 24) |
1481 (mac[2] << 16) |
1482 (mac[1] << 8) |
1483 mac[0];
1484 macLo >>= 1;
1485 macLo |= (macHi & 1) << 31;
1486 macHi >>= 1;
1487 } else {
1488 macLo = macHi = 0;
1489 }
1490 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1491 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1492
1493 return true;
1494 }
1495 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1496
1497 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1498 const struct ath9k_keyval *k,
1499 const u8 *mac)
1500 {
1501 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1502 struct ath_common *common = ath9k_hw_common(ah);
1503 u32 key0, key1, key2, key3, key4;
1504 u32 keyType;
1505
1506 if (entry >= pCap->keycache_size) {
1507 ath_print(common, ATH_DBG_FATAL,
1508 "keycache entry %u out of range\n", entry);
1509 return false;
1510 }
1511
1512 switch (k->kv_type) {
1513 case ATH9K_CIPHER_AES_OCB:
1514 keyType = AR_KEYTABLE_TYPE_AES;
1515 break;
1516 case ATH9K_CIPHER_AES_CCM:
1517 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1518 ath_print(common, ATH_DBG_ANY,
1519 "AES-CCM not supported by mac rev 0x%x\n",
1520 ah->hw_version.macRev);
1521 return false;
1522 }
1523 keyType = AR_KEYTABLE_TYPE_CCM;
1524 break;
1525 case ATH9K_CIPHER_TKIP:
1526 keyType = AR_KEYTABLE_TYPE_TKIP;
1527 if (ATH9K_IS_MIC_ENABLED(ah)
1528 && entry + 64 >= pCap->keycache_size) {
1529 ath_print(common, ATH_DBG_ANY,
1530 "entry %u inappropriate for TKIP\n", entry);
1531 return false;
1532 }
1533 break;
1534 case ATH9K_CIPHER_WEP:
1535 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1536 ath_print(common, ATH_DBG_ANY,
1537 "WEP key length %u too small\n", k->kv_len);
1538 return false;
1539 }
1540 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1541 keyType = AR_KEYTABLE_TYPE_40;
1542 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1543 keyType = AR_KEYTABLE_TYPE_104;
1544 else
1545 keyType = AR_KEYTABLE_TYPE_128;
1546 break;
1547 case ATH9K_CIPHER_CLR:
1548 keyType = AR_KEYTABLE_TYPE_CLR;
1549 break;
1550 default:
1551 ath_print(common, ATH_DBG_FATAL,
1552 "cipher %u not supported\n", k->kv_type);
1553 return false;
1554 }
1555
1556 key0 = get_unaligned_le32(k->kv_val + 0);
1557 key1 = get_unaligned_le16(k->kv_val + 4);
1558 key2 = get_unaligned_le32(k->kv_val + 6);
1559 key3 = get_unaligned_le16(k->kv_val + 10);
1560 key4 = get_unaligned_le32(k->kv_val + 12);
1561 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1562 key4 &= 0xff;
1563
1564 /*
1565 * Note: Key cache registers access special memory area that requires
1566 * two 32-bit writes to actually update the values in the internal
1567 * memory. Consequently, the exact order and pairs used here must be
1568 * maintained.
1569 */
1570
1571 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1572 u16 micentry = entry + 64;
1573
1574 /*
1575 * Write inverted key[47:0] first to avoid Michael MIC errors
1576 * on frames that could be sent or received at the same time.
1577 * The correct key will be written in the end once everything
1578 * else is ready.
1579 */
1580 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1581 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1582
1583 /* Write key[95:48] */
1584 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1585 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1586
1587 /* Write key[127:96] and key type */
1588 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1589 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1590
1591 /* Write MAC address for the entry */
1592 (void) ath9k_hw_keysetmac(ah, entry, mac);
1593
1594 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1595 /*
1596 * TKIP uses two key cache entries:
1597 * Michael MIC TX/RX keys in the same key cache entry
1598 * (idx = main index + 64):
1599 * key0 [31:0] = RX key [31:0]
1600 * key1 [15:0] = TX key [31:16]
1601 * key1 [31:16] = reserved
1602 * key2 [31:0] = RX key [63:32]
1603 * key3 [15:0] = TX key [15:0]
1604 * key3 [31:16] = reserved
1605 * key4 [31:0] = TX key [63:32]
1606 */
1607 u32 mic0, mic1, mic2, mic3, mic4;
1608
1609 mic0 = get_unaligned_le32(k->kv_mic + 0);
1610 mic2 = get_unaligned_le32(k->kv_mic + 4);
1611 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1612 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1613 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1614
1615 /* Write RX[31:0] and TX[31:16] */
1616 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1617 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1618
1619 /* Write RX[63:32] and TX[15:0] */
1620 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1621 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1622
1623 /* Write TX[63:32] and keyType(reserved) */
1624 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1625 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1626 AR_KEYTABLE_TYPE_CLR);
1627
1628 } else {
1629 /*
1630 * TKIP uses four key cache entries (two for group
1631 * keys):
1632 * Michael MIC TX/RX keys are in different key cache
1633 * entries (idx = main index + 64 for TX and
1634 * main index + 32 + 96 for RX):
1635 * key0 [31:0] = TX/RX MIC key [31:0]
1636 * key1 [31:0] = reserved
1637 * key2 [31:0] = TX/RX MIC key [63:32]
1638 * key3 [31:0] = reserved
1639 * key4 [31:0] = reserved
1640 *
1641 * Upper layer code will call this function separately
1642 * for TX and RX keys when these registers offsets are
1643 * used.
1644 */
1645 u32 mic0, mic2;
1646
1647 mic0 = get_unaligned_le32(k->kv_mic + 0);
1648 mic2 = get_unaligned_le32(k->kv_mic + 4);
1649
1650 /* Write MIC key[31:0] */
1651 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1652 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1653
1654 /* Write MIC key[63:32] */
1655 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1656 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1657
1658 /* Write TX[63:32] and keyType(reserved) */
1659 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1660 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1661 AR_KEYTABLE_TYPE_CLR);
1662 }
1663
1664 /* MAC address registers are reserved for the MIC entry */
1665 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1666 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1667
1668 /*
1669 * Write the correct (un-inverted) key[47:0] last to enable
1670 * TKIP now that all other registers are set with correct
1671 * values.
1672 */
1673 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1674 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1675 } else {
1676 /* Write key[47:0] */
1677 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1678 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1679
1680 /* Write key[95:48] */
1681 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1682 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1683
1684 /* Write key[127:96] and key type */
1685 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1686 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1687
1688 /* Write MAC address for the entry */
1689 (void) ath9k_hw_keysetmac(ah, entry, mac);
1690 }
1691
1692 return true;
1693 }
1694 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1695
1696 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1697 {
1698 if (entry < ah->caps.keycache_size) {
1699 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1700 if (val & AR_KEYTABLE_VALID)
1701 return true;
1702 }
1703 return false;
1704 }
1705 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1706
1707 /******************************/
1708 /* Power Management (Chipset) */
1709 /******************************/
1710
1711 /*
1712 * Notify Power Mgt is disabled in self-generated frames.
1713 * If requested, force chip to sleep.
1714 */
1715 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1716 {
1717 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1718 if (setChip) {
1719 /*
1720 * Clear the RTC force wake bit to allow the
1721 * mac to go to sleep.
1722 */
1723 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1724 AR_RTC_FORCE_WAKE_EN);
1725 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1726 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1727
1728 /* Shutdown chip. Active low */
1729 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1730 REG_CLR_BIT(ah, (AR_RTC_RESET),
1731 AR_RTC_RESET_EN);
1732 }
1733 }
1734
1735 /*
1736 * Notify Power Management is enabled in self-generating
1737 * frames. If request, set power mode of chip to
1738 * auto/normal. Duration in units of 128us (1/8 TU).
1739 */
1740 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1741 {
1742 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1743 if (setChip) {
1744 struct ath9k_hw_capabilities *pCap = &ah->caps;
1745
1746 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1747 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1748 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1749 AR_RTC_FORCE_WAKE_ON_INT);
1750 } else {
1751 /*
1752 * Clear the RTC force wake bit to allow the
1753 * mac to go to sleep.
1754 */
1755 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1756 AR_RTC_FORCE_WAKE_EN);
1757 }
1758 }
1759 }
1760
1761 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1762 {
1763 u32 val;
1764 int i;
1765
1766 if (setChip) {
1767 if ((REG_READ(ah, AR_RTC_STATUS) &
1768 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1769 if (ath9k_hw_set_reset_reg(ah,
1770 ATH9K_RESET_POWER_ON) != true) {
1771 return false;
1772 }
1773 if (!AR_SREV_9300_20_OR_LATER(ah))
1774 ath9k_hw_init_pll(ah, NULL);
1775 }
1776 if (AR_SREV_9100(ah))
1777 REG_SET_BIT(ah, AR_RTC_RESET,
1778 AR_RTC_RESET_EN);
1779
1780 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1781 AR_RTC_FORCE_WAKE_EN);
1782 udelay(50);
1783
1784 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1785 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1786 if (val == AR_RTC_STATUS_ON)
1787 break;
1788 udelay(50);
1789 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1790 AR_RTC_FORCE_WAKE_EN);
1791 }
1792 if (i == 0) {
1793 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1794 "Failed to wakeup in %uus\n",
1795 POWER_UP_TIME / 20);
1796 return false;
1797 }
1798 }
1799
1800 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1801
1802 return true;
1803 }
1804
1805 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1806 {
1807 struct ath_common *common = ath9k_hw_common(ah);
1808 int status = true, setChip = true;
1809 static const char *modes[] = {
1810 "AWAKE",
1811 "FULL-SLEEP",
1812 "NETWORK SLEEP",
1813 "UNDEFINED"
1814 };
1815
1816 if (ah->power_mode == mode)
1817 return status;
1818
1819 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1820 modes[ah->power_mode], modes[mode]);
1821
1822 switch (mode) {
1823 case ATH9K_PM_AWAKE:
1824 status = ath9k_hw_set_power_awake(ah, setChip);
1825 break;
1826 case ATH9K_PM_FULL_SLEEP:
1827 ath9k_set_power_sleep(ah, setChip);
1828 ah->chip_fullsleep = true;
1829 break;
1830 case ATH9K_PM_NETWORK_SLEEP:
1831 ath9k_set_power_network_sleep(ah, setChip);
1832 break;
1833 default:
1834 ath_print(common, ATH_DBG_FATAL,
1835 "Unknown power mode %u\n", mode);
1836 return false;
1837 }
1838 ah->power_mode = mode;
1839
1840 return status;
1841 }
1842 EXPORT_SYMBOL(ath9k_hw_setpower);
1843
1844 /*******************/
1845 /* Beacon Handling */
1846 /*******************/
1847
1848 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1849 {
1850 int flags = 0;
1851
1852 ah->beacon_interval = beacon_period;
1853
1854 ENABLE_REGWRITE_BUFFER(ah);
1855
1856 switch (ah->opmode) {
1857 case NL80211_IFTYPE_STATION:
1858 case NL80211_IFTYPE_MONITOR:
1859 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1860 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1861 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1862 flags |= AR_TBTT_TIMER_EN;
1863 break;
1864 case NL80211_IFTYPE_ADHOC:
1865 case NL80211_IFTYPE_MESH_POINT:
1866 REG_SET_BIT(ah, AR_TXCFG,
1867 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1868 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1869 TU_TO_USEC(next_beacon +
1870 (ah->atim_window ? ah->
1871 atim_window : 1)));
1872 flags |= AR_NDP_TIMER_EN;
1873 case NL80211_IFTYPE_AP:
1874 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1875 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1876 TU_TO_USEC(next_beacon -
1877 ah->config.
1878 dma_beacon_response_time));
1879 REG_WRITE(ah, AR_NEXT_SWBA,
1880 TU_TO_USEC(next_beacon -
1881 ah->config.
1882 sw_beacon_response_time));
1883 flags |=
1884 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1885 break;
1886 default:
1887 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1888 "%s: unsupported opmode: %d\n",
1889 __func__, ah->opmode);
1890 return;
1891 break;
1892 }
1893
1894 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1895 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1896 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1897 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1898
1899 REGWRITE_BUFFER_FLUSH(ah);
1900 DISABLE_REGWRITE_BUFFER(ah);
1901
1902 beacon_period &= ~ATH9K_BEACON_ENA;
1903 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1904 ath9k_hw_reset_tsf(ah);
1905 }
1906
1907 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1908 }
1909 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1910
1911 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1912 const struct ath9k_beacon_state *bs)
1913 {
1914 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1915 struct ath9k_hw_capabilities *pCap = &ah->caps;
1916 struct ath_common *common = ath9k_hw_common(ah);
1917
1918 ENABLE_REGWRITE_BUFFER(ah);
1919
1920 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1921
1922 REG_WRITE(ah, AR_BEACON_PERIOD,
1923 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1924 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1925 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1926
1927 REGWRITE_BUFFER_FLUSH(ah);
1928 DISABLE_REGWRITE_BUFFER(ah);
1929
1930 REG_RMW_FIELD(ah, AR_RSSI_THR,
1931 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1932
1933 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1934
1935 if (bs->bs_sleepduration > beaconintval)
1936 beaconintval = bs->bs_sleepduration;
1937
1938 dtimperiod = bs->bs_dtimperiod;
1939 if (bs->bs_sleepduration > dtimperiod)
1940 dtimperiod = bs->bs_sleepduration;
1941
1942 if (beaconintval == dtimperiod)
1943 nextTbtt = bs->bs_nextdtim;
1944 else
1945 nextTbtt = bs->bs_nexttbtt;
1946
1947 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1948 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1949 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1950 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1951
1952 ENABLE_REGWRITE_BUFFER(ah);
1953
1954 REG_WRITE(ah, AR_NEXT_DTIM,
1955 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1956 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1957
1958 REG_WRITE(ah, AR_SLEEP1,
1959 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1960 | AR_SLEEP1_ASSUME_DTIM);
1961
1962 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1963 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1964 else
1965 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1966
1967 REG_WRITE(ah, AR_SLEEP2,
1968 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1969
1970 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1971 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1972
1973 REGWRITE_BUFFER_FLUSH(ah);
1974 DISABLE_REGWRITE_BUFFER(ah);
1975
1976 REG_SET_BIT(ah, AR_TIMER_MODE,
1977 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1978 AR_DTIM_TIMER_EN);
1979
1980 /* TSF Out of Range Threshold */
1981 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1982 }
1983 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1984
1985 /*******************/
1986 /* HW Capabilities */
1987 /*******************/
1988
1989 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1990 {
1991 struct ath9k_hw_capabilities *pCap = &ah->caps;
1992 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1993 struct ath_common *common = ath9k_hw_common(ah);
1994 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1995
1996 u16 capField = 0, eeval;
1997
1998 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1999 regulatory->current_rd = eeval;
2000
2001 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2002 if (AR_SREV_9285_10_OR_LATER(ah))
2003 eeval |= AR9285_RDEXT_DEFAULT;
2004 regulatory->current_rd_ext = eeval;
2005
2006 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2007
2008 if (ah->opmode != NL80211_IFTYPE_AP &&
2009 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2010 if (regulatory->current_rd == 0x64 ||
2011 regulatory->current_rd == 0x65)
2012 regulatory->current_rd += 5;
2013 else if (regulatory->current_rd == 0x41)
2014 regulatory->current_rd = 0x43;
2015 ath_print(common, ATH_DBG_REGULATORY,
2016 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2017 }
2018
2019 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2020 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2021 ath_print(common, ATH_DBG_FATAL,
2022 "no band has been marked as supported in EEPROM.\n");
2023 return -EINVAL;
2024 }
2025
2026 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2027
2028 if (eeval & AR5416_OPFLAGS_11A) {
2029 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2030 if (ah->config.ht_enable) {
2031 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2032 set_bit(ATH9K_MODE_11NA_HT20,
2033 pCap->wireless_modes);
2034 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2035 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2036 pCap->wireless_modes);
2037 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2038 pCap->wireless_modes);
2039 }
2040 }
2041 }
2042
2043 if (eeval & AR5416_OPFLAGS_11G) {
2044 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2045 if (ah->config.ht_enable) {
2046 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2047 set_bit(ATH9K_MODE_11NG_HT20,
2048 pCap->wireless_modes);
2049 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2050 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2051 pCap->wireless_modes);
2052 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2053 pCap->wireless_modes);
2054 }
2055 }
2056 }
2057
2058 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2059 /*
2060 * For AR9271 we will temporarilly uses the rx chainmax as read from
2061 * the EEPROM.
2062 */
2063 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2064 !(eeval & AR5416_OPFLAGS_11A) &&
2065 !(AR_SREV_9271(ah)))
2066 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2067 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2068 else
2069 /* Use rx_chainmask from EEPROM. */
2070 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2071
2072 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2073 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2074
2075 pCap->low_2ghz_chan = 2312;
2076 pCap->high_2ghz_chan = 2732;
2077
2078 pCap->low_5ghz_chan = 4920;
2079 pCap->high_5ghz_chan = 6100;
2080
2081 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2082 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2083 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2084
2085 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2086 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2087 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2088
2089 if (ah->config.ht_enable)
2090 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2091 else
2092 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2093
2094 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2095 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2096 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2097 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2098
2099 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2100 pCap->total_queues =
2101 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2102 else
2103 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2104
2105 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2106 pCap->keycache_size =
2107 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2108 else
2109 pCap->keycache_size = AR_KEYTABLE_SIZE;
2110
2111 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2112
2113 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2114 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2115 else
2116 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2117
2118 if (AR_SREV_9271(ah))
2119 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2120 else if (AR_SREV_9285_10_OR_LATER(ah))
2121 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2122 else if (AR_SREV_9280_10_OR_LATER(ah))
2123 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2124 else
2125 pCap->num_gpio_pins = AR_NUM_GPIO;
2126
2127 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2128 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2129 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2130 } else {
2131 pCap->rts_aggr_limit = (8 * 1024);
2132 }
2133
2134 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2135
2136 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2137 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2138 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2139 ah->rfkill_gpio =
2140 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2141 ah->rfkill_polarity =
2142 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2143
2144 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2145 }
2146 #endif
2147 if (AR_SREV_9271(ah))
2148 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2149 else
2150 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2151
2152 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2153 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2154 else
2155 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2156
2157 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2158 pCap->reg_cap =
2159 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2160 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2161 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2162 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2163 } else {
2164 pCap->reg_cap =
2165 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2166 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2167 }
2168
2169 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2170 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2171 AR_SREV_5416(ah))
2172 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2173
2174 pCap->num_antcfg_5ghz =
2175 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2176 pCap->num_antcfg_2ghz =
2177 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2178
2179 if (AR_SREV_9280_10_OR_LATER(ah) &&
2180 ath9k_hw_btcoex_supported(ah)) {
2181 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2182 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2183
2184 if (AR_SREV_9285(ah)) {
2185 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2186 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2187 } else {
2188 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2189 }
2190 } else {
2191 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2192 }
2193
2194 if (AR_SREV_9300_20_OR_LATER(ah)) {
2195 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2196 ATH9K_HW_CAP_FASTCLOCK;
2197 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2198 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2199 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2200 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2201 pCap->txs_len = sizeof(struct ar9003_txs);
2202 } else {
2203 pCap->tx_desc_len = sizeof(struct ath_desc);
2204 if (AR_SREV_9280_20(ah) &&
2205 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2206 AR5416_EEP_MINOR_VER_16) ||
2207 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2208 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2209 }
2210
2211 if (AR_SREV_9300_20_OR_LATER(ah))
2212 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2213
2214 return 0;
2215 }
2216
2217 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2218 u32 capability, u32 *result)
2219 {
2220 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2221 switch (type) {
2222 case ATH9K_CAP_CIPHER:
2223 switch (capability) {
2224 case ATH9K_CIPHER_AES_CCM:
2225 case ATH9K_CIPHER_AES_OCB:
2226 case ATH9K_CIPHER_TKIP:
2227 case ATH9K_CIPHER_WEP:
2228 case ATH9K_CIPHER_MIC:
2229 case ATH9K_CIPHER_CLR:
2230 return true;
2231 default:
2232 return false;
2233 }
2234 case ATH9K_CAP_TKIP_MIC:
2235 switch (capability) {
2236 case 0:
2237 return true;
2238 case 1:
2239 return (ah->sta_id1_defaults &
2240 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2241 false;
2242 }
2243 case ATH9K_CAP_TKIP_SPLIT:
2244 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2245 false : true;
2246 case ATH9K_CAP_MCAST_KEYSRCH:
2247 switch (capability) {
2248 case 0:
2249 return true;
2250 case 1:
2251 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2252 return false;
2253 } else {
2254 return (ah->sta_id1_defaults &
2255 AR_STA_ID1_MCAST_KSRCH) ? true :
2256 false;
2257 }
2258 }
2259 return false;
2260 case ATH9K_CAP_TXPOW:
2261 switch (capability) {
2262 case 0:
2263 return 0;
2264 case 1:
2265 *result = regulatory->power_limit;
2266 return 0;
2267 case 2:
2268 *result = regulatory->max_power_level;
2269 return 0;
2270 case 3:
2271 *result = regulatory->tp_scale;
2272 return 0;
2273 }
2274 return false;
2275 case ATH9K_CAP_DS:
2276 return (AR_SREV_9280_20_OR_LATER(ah) &&
2277 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2278 ? false : true;
2279 default:
2280 return false;
2281 }
2282 }
2283 EXPORT_SYMBOL(ath9k_hw_getcapability);
2284
2285 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2286 u32 capability, u32 setting, int *status)
2287 {
2288 switch (type) {
2289 case ATH9K_CAP_TKIP_MIC:
2290 if (setting)
2291 ah->sta_id1_defaults |=
2292 AR_STA_ID1_CRPT_MIC_ENABLE;
2293 else
2294 ah->sta_id1_defaults &=
2295 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2296 return true;
2297 case ATH9K_CAP_MCAST_KEYSRCH:
2298 if (setting)
2299 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2300 else
2301 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2302 return true;
2303 default:
2304 return false;
2305 }
2306 }
2307 EXPORT_SYMBOL(ath9k_hw_setcapability);
2308
2309 /****************************/
2310 /* GPIO / RFKILL / Antennae */
2311 /****************************/
2312
2313 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2314 u32 gpio, u32 type)
2315 {
2316 int addr;
2317 u32 gpio_shift, tmp;
2318
2319 if (gpio > 11)
2320 addr = AR_GPIO_OUTPUT_MUX3;
2321 else if (gpio > 5)
2322 addr = AR_GPIO_OUTPUT_MUX2;
2323 else
2324 addr = AR_GPIO_OUTPUT_MUX1;
2325
2326 gpio_shift = (gpio % 6) * 5;
2327
2328 if (AR_SREV_9280_20_OR_LATER(ah)
2329 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2330 REG_RMW(ah, addr, (type << gpio_shift),
2331 (0x1f << gpio_shift));
2332 } else {
2333 tmp = REG_READ(ah, addr);
2334 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2335 tmp &= ~(0x1f << gpio_shift);
2336 tmp |= (type << gpio_shift);
2337 REG_WRITE(ah, addr, tmp);
2338 }
2339 }
2340
2341 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2342 {
2343 u32 gpio_shift;
2344
2345 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2346
2347 gpio_shift = gpio << 1;
2348
2349 REG_RMW(ah,
2350 AR_GPIO_OE_OUT,
2351 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2352 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2353 }
2354 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2355
2356 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2357 {
2358 #define MS_REG_READ(x, y) \
2359 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2360
2361 if (gpio >= ah->caps.num_gpio_pins)
2362 return 0xffffffff;
2363
2364 if (AR_SREV_9300_20_OR_LATER(ah))
2365 return MS_REG_READ(AR9300, gpio) != 0;
2366 else if (AR_SREV_9271(ah))
2367 return MS_REG_READ(AR9271, gpio) != 0;
2368 else if (AR_SREV_9287_10_OR_LATER(ah))
2369 return MS_REG_READ(AR9287, gpio) != 0;
2370 else if (AR_SREV_9285_10_OR_LATER(ah))
2371 return MS_REG_READ(AR9285, gpio) != 0;
2372 else if (AR_SREV_9280_10_OR_LATER(ah))
2373 return MS_REG_READ(AR928X, gpio) != 0;
2374 else
2375 return MS_REG_READ(AR, gpio) != 0;
2376 }
2377 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2378
2379 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2380 u32 ah_signal_type)
2381 {
2382 u32 gpio_shift;
2383
2384 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2385
2386 gpio_shift = 2 * gpio;
2387
2388 REG_RMW(ah,
2389 AR_GPIO_OE_OUT,
2390 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2391 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2392 }
2393 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2394
2395 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2396 {
2397 if (AR_SREV_9271(ah))
2398 val = ~val;
2399
2400 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2401 AR_GPIO_BIT(gpio));
2402 }
2403 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2404
2405 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2406 {
2407 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2408 }
2409 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2410
2411 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2412 {
2413 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2414 }
2415 EXPORT_SYMBOL(ath9k_hw_setantenna);
2416
2417 /*********************/
2418 /* General Operation */
2419 /*********************/
2420
2421 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2422 {
2423 u32 bits = REG_READ(ah, AR_RX_FILTER);
2424 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2425
2426 if (phybits & AR_PHY_ERR_RADAR)
2427 bits |= ATH9K_RX_FILTER_PHYRADAR;
2428 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2429 bits |= ATH9K_RX_FILTER_PHYERR;
2430
2431 return bits;
2432 }
2433 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2434
2435 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2436 {
2437 u32 phybits;
2438
2439 ENABLE_REGWRITE_BUFFER(ah);
2440
2441 REG_WRITE(ah, AR_RX_FILTER, bits);
2442
2443 phybits = 0;
2444 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2445 phybits |= AR_PHY_ERR_RADAR;
2446 if (bits & ATH9K_RX_FILTER_PHYERR)
2447 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2448 REG_WRITE(ah, AR_PHY_ERR, phybits);
2449
2450 if (phybits)
2451 REG_WRITE(ah, AR_RXCFG,
2452 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2453 else
2454 REG_WRITE(ah, AR_RXCFG,
2455 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2456
2457 REGWRITE_BUFFER_FLUSH(ah);
2458 DISABLE_REGWRITE_BUFFER(ah);
2459 }
2460 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2461
2462 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2463 {
2464 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2465 return false;
2466
2467 ath9k_hw_init_pll(ah, NULL);
2468 return true;
2469 }
2470 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2471
2472 bool ath9k_hw_disable(struct ath_hw *ah)
2473 {
2474 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2475 return false;
2476
2477 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2478 return false;
2479
2480 ath9k_hw_init_pll(ah, NULL);
2481 return true;
2482 }
2483 EXPORT_SYMBOL(ath9k_hw_disable);
2484
2485 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2486 {
2487 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2488 struct ath9k_channel *chan = ah->curchan;
2489 struct ieee80211_channel *channel = chan->chan;
2490
2491 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2492
2493 ah->eep_ops->set_txpower(ah, chan,
2494 ath9k_regd_get_ctl(regulatory, chan),
2495 channel->max_antenna_gain * 2,
2496 channel->max_power * 2,
2497 min((u32) MAX_RATE_POWER,
2498 (u32) regulatory->power_limit));
2499 }
2500 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2501
2502 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2503 {
2504 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2505 }
2506 EXPORT_SYMBOL(ath9k_hw_setmac);
2507
2508 void ath9k_hw_setopmode(struct ath_hw *ah)
2509 {
2510 ath9k_hw_set_operating_mode(ah, ah->opmode);
2511 }
2512 EXPORT_SYMBOL(ath9k_hw_setopmode);
2513
2514 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2515 {
2516 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2517 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2518 }
2519 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2520
2521 void ath9k_hw_write_associd(struct ath_hw *ah)
2522 {
2523 struct ath_common *common = ath9k_hw_common(ah);
2524
2525 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2526 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2527 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2528 }
2529 EXPORT_SYMBOL(ath9k_hw_write_associd);
2530
2531 #define ATH9K_MAX_TSF_READ 10
2532
2533 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2534 {
2535 u32 tsf_lower, tsf_upper1, tsf_upper2;
2536 int i;
2537
2538 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2539 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2540 tsf_lower = REG_READ(ah, AR_TSF_L32);
2541 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2542 if (tsf_upper2 == tsf_upper1)
2543 break;
2544 tsf_upper1 = tsf_upper2;
2545 }
2546
2547 WARN_ON( i == ATH9K_MAX_TSF_READ );
2548
2549 return (((u64)tsf_upper1 << 32) | tsf_lower);
2550 }
2551 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2552
2553 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2554 {
2555 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2556 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2557 }
2558 EXPORT_SYMBOL(ath9k_hw_settsf64);
2559
2560 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2561 {
2562 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2563 AH_TSF_WRITE_TIMEOUT))
2564 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2565 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2566
2567 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2568 }
2569 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2570
2571 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2572 {
2573 if (setting)
2574 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2575 else
2576 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2577 }
2578 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2579
2580 /*
2581 * Extend 15-bit time stamp from rx descriptor to
2582 * a full 64-bit TSF using the current h/w TSF.
2583 */
2584 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2585 {
2586 u64 tsf;
2587
2588 tsf = ath9k_hw_gettsf64(ah);
2589 if ((tsf & 0x7fff) < rstamp)
2590 tsf -= 0x8000;
2591 return (tsf & ~0x7fff) | rstamp;
2592 }
2593 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2594
2595 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2596 {
2597 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2598 u32 macmode;
2599
2600 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2601 macmode = AR_2040_JOINED_RX_CLEAR;
2602 else
2603 macmode = 0;
2604
2605 REG_WRITE(ah, AR_2040_MODE, macmode);
2606 }
2607
2608 /* HW Generic timers configuration */
2609
2610 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2611 {
2612 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2613 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2614 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2615 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2616 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2617 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2618 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2619 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2620 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2621 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2622 AR_NDP2_TIMER_MODE, 0x0002},
2623 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2624 AR_NDP2_TIMER_MODE, 0x0004},
2625 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2626 AR_NDP2_TIMER_MODE, 0x0008},
2627 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2628 AR_NDP2_TIMER_MODE, 0x0010},
2629 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2630 AR_NDP2_TIMER_MODE, 0x0020},
2631 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2632 AR_NDP2_TIMER_MODE, 0x0040},
2633 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2634 AR_NDP2_TIMER_MODE, 0x0080}
2635 };
2636
2637 /* HW generic timer primitives */
2638
2639 /* compute and clear index of rightmost 1 */
2640 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2641 {
2642 u32 b;
2643
2644 b = *mask;
2645 b &= (0-b);
2646 *mask &= ~b;
2647 b *= debruijn32;
2648 b >>= 27;
2649
2650 return timer_table->gen_timer_index[b];
2651 }
2652
2653 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2654 {
2655 return REG_READ(ah, AR_TSF_L32);
2656 }
2657 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2658
2659 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2660 void (*trigger)(void *),
2661 void (*overflow)(void *),
2662 void *arg,
2663 u8 timer_index)
2664 {
2665 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2666 struct ath_gen_timer *timer;
2667
2668 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2669
2670 if (timer == NULL) {
2671 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2672 "Failed to allocate memory"
2673 "for hw timer[%d]\n", timer_index);
2674 return NULL;
2675 }
2676
2677 /* allocate a hardware generic timer slot */
2678 timer_table->timers[timer_index] = timer;
2679 timer->index = timer_index;
2680 timer->trigger = trigger;
2681 timer->overflow = overflow;
2682 timer->arg = arg;
2683
2684 return timer;
2685 }
2686 EXPORT_SYMBOL(ath_gen_timer_alloc);
2687
2688 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2689 struct ath_gen_timer *timer,
2690 u32 timer_next,
2691 u32 timer_period)
2692 {
2693 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2694 u32 tsf;
2695
2696 BUG_ON(!timer_period);
2697
2698 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2699
2700 tsf = ath9k_hw_gettsf32(ah);
2701
2702 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2703 "curent tsf %x period %x"
2704 "timer_next %x\n", tsf, timer_period, timer_next);
2705
2706 /*
2707 * Pull timer_next forward if the current TSF already passed it
2708 * because of software latency
2709 */
2710 if (timer_next < tsf)
2711 timer_next = tsf + timer_period;
2712
2713 /*
2714 * Program generic timer registers
2715 */
2716 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2717 timer_next);
2718 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2719 timer_period);
2720 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2721 gen_tmr_configuration[timer->index].mode_mask);
2722
2723 /* Enable both trigger and thresh interrupt masks */
2724 REG_SET_BIT(ah, AR_IMR_S5,
2725 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2726 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2727 }
2728 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2729
2730 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2731 {
2732 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2733
2734 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2735 (timer->index >= ATH_MAX_GEN_TIMER)) {
2736 return;
2737 }
2738
2739 /* Clear generic timer enable bits. */
2740 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2741 gen_tmr_configuration[timer->index].mode_mask);
2742
2743 /* Disable both trigger and thresh interrupt masks */
2744 REG_CLR_BIT(ah, AR_IMR_S5,
2745 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2746 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2747
2748 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2749 }
2750 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2751
2752 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2753 {
2754 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2755
2756 /* free the hardware generic timer slot */
2757 timer_table->timers[timer->index] = NULL;
2758 kfree(timer);
2759 }
2760 EXPORT_SYMBOL(ath_gen_timer_free);
2761
2762 /*
2763 * Generic Timer Interrupts handling
2764 */
2765 void ath_gen_timer_isr(struct ath_hw *ah)
2766 {
2767 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2768 struct ath_gen_timer *timer;
2769 struct ath_common *common = ath9k_hw_common(ah);
2770 u32 trigger_mask, thresh_mask, index;
2771
2772 /* get hardware generic timer interrupt status */
2773 trigger_mask = ah->intr_gen_timer_trigger;
2774 thresh_mask = ah->intr_gen_timer_thresh;
2775 trigger_mask &= timer_table->timer_mask.val;
2776 thresh_mask &= timer_table->timer_mask.val;
2777
2778 trigger_mask &= ~thresh_mask;
2779
2780 while (thresh_mask) {
2781 index = rightmost_index(timer_table, &thresh_mask);
2782 timer = timer_table->timers[index];
2783 BUG_ON(!timer);
2784 ath_print(common, ATH_DBG_HWTIMER,
2785 "TSF overflow for Gen timer %d\n", index);
2786 timer->overflow(timer->arg);
2787 }
2788
2789 while (trigger_mask) {
2790 index = rightmost_index(timer_table, &trigger_mask);
2791 timer = timer_table->timers[index];
2792 BUG_ON(!timer);
2793 ath_print(common, ATH_DBG_HWTIMER,
2794 "Gen timer[%d] trigger\n", index);
2795 timer->trigger(timer->arg);
2796 }
2797 }
2798 EXPORT_SYMBOL(ath_gen_timer_isr);
2799
2800 /********/
2801 /* HTC */
2802 /********/
2803
2804 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2805 {
2806 ah->htc_reset_init = true;
2807 }
2808 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2809
2810 static struct {
2811 u32 version;
2812 const char * name;
2813 } ath_mac_bb_names[] = {
2814 /* Devices with external radios */
2815 { AR_SREV_VERSION_5416_PCI, "5416" },
2816 { AR_SREV_VERSION_5416_PCIE, "5418" },
2817 { AR_SREV_VERSION_9100, "9100" },
2818 { AR_SREV_VERSION_9160, "9160" },
2819 /* Single-chip solutions */
2820 { AR_SREV_VERSION_9280, "9280" },
2821 { AR_SREV_VERSION_9285, "9285" },
2822 { AR_SREV_VERSION_9287, "9287" },
2823 { AR_SREV_VERSION_9271, "9271" },
2824 { AR_SREV_VERSION_9300, "9300" },
2825 };
2826
2827 /* For devices with external radios */
2828 static struct {
2829 u16 version;
2830 const char * name;
2831 } ath_rf_names[] = {
2832 { 0, "5133" },
2833 { AR_RAD5133_SREV_MAJOR, "5133" },
2834 { AR_RAD5122_SREV_MAJOR, "5122" },
2835 { AR_RAD2133_SREV_MAJOR, "2133" },
2836 { AR_RAD2122_SREV_MAJOR, "2122" }
2837 };
2838
2839 /*
2840 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2841 */
2842 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2843 {
2844 int i;
2845
2846 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2847 if (ath_mac_bb_names[i].version == mac_bb_version) {
2848 return ath_mac_bb_names[i].name;
2849 }
2850 }
2851
2852 return "????";
2853 }
2854
2855 /*
2856 * Return the RF name. "????" is returned if the RF is unknown.
2857 * Used for devices with external radios.
2858 */
2859 static const char *ath9k_hw_rf_name(u16 rf_version)
2860 {
2861 int i;
2862
2863 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2864 if (ath_rf_names[i].version == rf_version) {
2865 return ath_rf_names[i].name;
2866 }
2867 }
2868
2869 return "????";
2870 }
2871
2872 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2873 {
2874 int used;
2875
2876 /* chipsets >= AR9280 are single-chip */
2877 if (AR_SREV_9280_10_OR_LATER(ah)) {
2878 used = snprintf(hw_name, len,
2879 "Atheros AR%s Rev:%x",
2880 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2881 ah->hw_version.macRev);
2882 }
2883 else {
2884 used = snprintf(hw_name, len,
2885 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2886 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2887 ah->hw_version.macRev,
2888 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2889 AR_RADIO_SREV_MAJOR)),
2890 ah->hw_version.phyRev);
2891 }
2892
2893 hw_name[used] = '\0';
2894 }
2895 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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