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ath9k_hw: Abstract the routine which returns interrupt status
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "hw-ops.h"
22 #include "rc.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29
30 MODULE_AUTHOR("Atheros Communications");
31 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33 MODULE_LICENSE("Dual BSD/GPL");
34
35 static int __init ath9k_init(void)
36 {
37 return 0;
38 }
39 module_init(ath9k_init);
40
41 static void __exit ath9k_exit(void)
42 {
43 return;
44 }
45 module_exit(ath9k_exit);
46
47 /* Private hardware callbacks */
48
49 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
50 {
51 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 }
53
54 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
55 {
56 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 }
58
59 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
60 {
61 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
62
63 return priv_ops->macversion_supported(ah->hw_version.macVersion);
64 }
65
66 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
67 struct ath9k_channel *chan)
68 {
69 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
70 }
71
72 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
73 {
74 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87
88 if (!ah->curchan) /* should really check for CCK instead */
89 return usecs *ATH9K_CLOCK_RATE_CCK;
90 if (conf->channel->band == IEEE80211_BAND_2GHZ)
91 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
92 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
93 }
94
95 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
96 {
97 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
98
99 if (conf_is_ht40(conf))
100 return ath9k_hw_mac_clks(ah, usecs) * 2;
101 else
102 return ath9k_hw_mac_clks(ah, usecs);
103 }
104
105 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
106 {
107 int i;
108
109 BUG_ON(timeout < AH_TIME_QUANTUM);
110
111 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
112 if ((REG_READ(ah, reg) & mask) == val)
113 return true;
114
115 udelay(AH_TIME_QUANTUM);
116 }
117
118 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
119 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
120 timeout, reg, REG_READ(ah, reg), mask, val);
121
122 return false;
123 }
124 EXPORT_SYMBOL(ath9k_hw_wait);
125
126 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
127 {
128 u32 retval;
129 int i;
130
131 for (i = 0, retval = 0; i < n; i++) {
132 retval = (retval << 1) | (val & 1);
133 val >>= 1;
134 }
135 return retval;
136 }
137
138 bool ath9k_get_channel_edges(struct ath_hw *ah,
139 u16 flags, u16 *low,
140 u16 *high)
141 {
142 struct ath9k_hw_capabilities *pCap = &ah->caps;
143
144 if (flags & CHANNEL_5GHZ) {
145 *low = pCap->low_5ghz_chan;
146 *high = pCap->high_5ghz_chan;
147 return true;
148 }
149 if ((flags & CHANNEL_2GHZ)) {
150 *low = pCap->low_2ghz_chan;
151 *high = pCap->high_2ghz_chan;
152 return true;
153 }
154 return false;
155 }
156
157 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
158 u8 phy, int kbps,
159 u32 frameLen, u16 rateix,
160 bool shortPreamble)
161 {
162 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
163
164 if (kbps == 0)
165 return 0;
166
167 switch (phy) {
168 case WLAN_RC_PHY_CCK:
169 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
170 if (shortPreamble)
171 phyTime >>= 1;
172 numBits = frameLen << 3;
173 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
174 break;
175 case WLAN_RC_PHY_OFDM:
176 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
180 txTime = OFDM_SIFS_TIME_QUARTER
181 + OFDM_PREAMBLE_TIME_QUARTER
182 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
183 } else if (ah->curchan &&
184 IS_CHAN_HALF_RATE(ah->curchan)) {
185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME_HALF +
189 OFDM_PREAMBLE_TIME_HALF
190 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
191 } else {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
196 + (numSymbols * OFDM_SYMBOL_TIME);
197 }
198 break;
199 default:
200 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
201 "Unknown phy %u (rate ix %u)\n", phy, rateix);
202 txTime = 0;
203 break;
204 }
205
206 return txTime;
207 }
208 EXPORT_SYMBOL(ath9k_hw_computetxtime);
209
210 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
211 struct ath9k_channel *chan,
212 struct chan_centers *centers)
213 {
214 int8_t extoff;
215
216 if (!IS_CHAN_HT40(chan)) {
217 centers->ctl_center = centers->ext_center =
218 centers->synth_center = chan->channel;
219 return;
220 }
221
222 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
223 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
224 centers->synth_center =
225 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
226 extoff = 1;
227 } else {
228 centers->synth_center =
229 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
230 extoff = -1;
231 }
232
233 centers->ctl_center =
234 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
235 /* 25 MHz spacing is supported by hw but not on upper layers */
236 centers->ext_center =
237 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
238 }
239
240 /******************/
241 /* Chip Revisions */
242 /******************/
243
244 static void ath9k_hw_read_revisions(struct ath_hw *ah)
245 {
246 u32 val;
247
248 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
249
250 if (val == 0xFF) {
251 val = REG_READ(ah, AR_SREV);
252 ah->hw_version.macVersion =
253 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
254 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
255 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
256 } else {
257 if (!AR_SREV_9100(ah))
258 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
259
260 ah->hw_version.macRev = val & AR_SREV_REVISION;
261
262 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
263 ah->is_pciexpress = true;
264 }
265 }
266
267 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
268 {
269 u32 val;
270 int i;
271
272 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
273
274 for (i = 0; i < 8; i++)
275 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
276 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
277 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
278
279 return ath9k_hw_reverse_bits(val, 8);
280 }
281
282 /************************************/
283 /* HW Attach, Detach, Init Routines */
284 /************************************/
285
286 static void ath9k_hw_disablepcie(struct ath_hw *ah)
287 {
288 if (AR_SREV_9100(ah))
289 return;
290
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
300
301 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
302 }
303
304 /* This should work for all families including legacy */
305 static bool ath9k_hw_chip_test(struct ath_hw *ah)
306 {
307 struct ath_common *common = ath9k_hw_common(ah);
308 u32 regAddr[2] = { AR_STA_ID0 };
309 u32 regHold[2];
310 u32 patternData[4] = { 0x55555555,
311 0xaaaaaaaa,
312 0x66666666,
313 0x99999999 };
314 int i, j, loop_max;
315
316 if (!AR_SREV_9300_20_OR_LATER(ah)) {
317 loop_max = 2;
318 regAddr[1] = AR_PHY_BASE + (8 << 2);
319 } else
320 loop_max = 1;
321
322 for (i = 0; i < loop_max; i++) {
323 u32 addr = regAddr[i];
324 u32 wrData, rdData;
325
326 regHold[i] = REG_READ(ah, addr);
327 for (j = 0; j < 0x100; j++) {
328 wrData = (j << 16) | j;
329 REG_WRITE(ah, addr, wrData);
330 rdData = REG_READ(ah, addr);
331 if (rdData != wrData) {
332 ath_print(common, ATH_DBG_FATAL,
333 "address test failed "
334 "addr: 0x%08x - wr:0x%08x != "
335 "rd:0x%08x\n",
336 addr, wrData, rdData);
337 return false;
338 }
339 }
340 for (j = 0; j < 4; j++) {
341 wrData = patternData[j];
342 REG_WRITE(ah, addr, wrData);
343 rdData = REG_READ(ah, addr);
344 if (wrData != rdData) {
345 ath_print(common, ATH_DBG_FATAL,
346 "address test failed "
347 "addr: 0x%08x - wr:0x%08x != "
348 "rd:0x%08x\n",
349 addr, wrData, rdData);
350 return false;
351 }
352 }
353 REG_WRITE(ah, regAddr[i], regHold[i]);
354 }
355 udelay(100);
356
357 return true;
358 }
359
360 static void ath9k_hw_init_config(struct ath_hw *ah)
361 {
362 int i;
363
364 ah->config.dma_beacon_response_time = 2;
365 ah->config.sw_beacon_response_time = 10;
366 ah->config.additional_swba_backoff = 0;
367 ah->config.ack_6mb = 0x0;
368 ah->config.cwm_ignore_extcca = 0;
369 ah->config.pcie_powersave_enable = 0;
370 ah->config.pcie_clock_req = 0;
371 ah->config.pcie_waen = 0;
372 ah->config.analog_shiftreg = 1;
373 ah->config.ofdm_trig_low = 200;
374 ah->config.ofdm_trig_high = 500;
375 ah->config.cck_trig_high = 200;
376 ah->config.cck_trig_low = 100;
377
378 /*
379 * For now ANI is disabled for AR9003, it is still
380 * being tested.
381 */
382 if (!AR_SREV_9300_20_OR_LATER(ah))
383 ah->config.enable_ani = 1;
384
385 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
386 ah->config.spurchans[i][0] = AR_NO_SPUR;
387 ah->config.spurchans[i][1] = AR_NO_SPUR;
388 }
389
390 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
391 ah->config.ht_enable = 1;
392 else
393 ah->config.ht_enable = 0;
394
395 ah->config.rx_intr_mitigation = true;
396
397 /*
398 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
399 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
400 * This means we use it for all AR5416 devices, and the few
401 * minor PCI AR9280 devices out there.
402 *
403 * Serialization is required because these devices do not handle
404 * well the case of two concurrent reads/writes due to the latency
405 * involved. During one read/write another read/write can be issued
406 * on another CPU while the previous read/write may still be working
407 * on our hardware, if we hit this case the hardware poops in a loop.
408 * We prevent this by serializing reads and writes.
409 *
410 * This issue is not present on PCI-Express devices or pre-AR5416
411 * devices (legacy, 802.11abg).
412 */
413 if (num_possible_cpus() > 1)
414 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
415 }
416
417 static void ath9k_hw_init_defaults(struct ath_hw *ah)
418 {
419 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
420
421 regulatory->country_code = CTRY_DEFAULT;
422 regulatory->power_limit = MAX_RATE_POWER;
423 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
424
425 ah->hw_version.magic = AR5416_MAGIC;
426 ah->hw_version.subvendorid = 0;
427
428 ah->ah_flags = 0;
429 if (!AR_SREV_9100(ah))
430 ah->ah_flags = AH_USE_EEPROM;
431
432 ah->atim_window = 0;
433 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
434 ah->beacon_interval = 100;
435 ah->enable_32kHz_clock = DONT_USE_32KHZ;
436 ah->slottime = (u32) -1;
437 ah->globaltxtimeout = (u32) -1;
438 ah->power_mode = ATH9K_PM_UNDEFINED;
439 }
440
441 static int ath9k_hw_rf_claim(struct ath_hw *ah)
442 {
443 u32 val;
444
445 REG_WRITE(ah, AR_PHY(0), 0x00000007);
446
447 val = ath9k_hw_get_radiorev(ah);
448 switch (val & AR_RADIO_SREV_MAJOR) {
449 case 0:
450 val = AR_RAD5133_SREV_MAJOR;
451 break;
452 case AR_RAD5133_SREV_MAJOR:
453 case AR_RAD5122_SREV_MAJOR:
454 case AR_RAD2133_SREV_MAJOR:
455 case AR_RAD2122_SREV_MAJOR:
456 break;
457 default:
458 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
459 "Radio Chip Rev 0x%02X not supported\n",
460 val & AR_RADIO_SREV_MAJOR);
461 return -EOPNOTSUPP;
462 }
463
464 ah->hw_version.analog5GhzRev = val;
465
466 return 0;
467 }
468
469 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
470 {
471 struct ath_common *common = ath9k_hw_common(ah);
472 u32 sum;
473 int i;
474 u16 eeval;
475
476 sum = 0;
477 for (i = 0; i < 3; i++) {
478 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
479 sum += eeval;
480 common->macaddr[2 * i] = eeval >> 8;
481 common->macaddr[2 * i + 1] = eeval & 0xff;
482 }
483 if (sum == 0 || sum == 0xffff * 3)
484 return -EADDRNOTAVAIL;
485
486 return 0;
487 }
488
489 static int ath9k_hw_post_init(struct ath_hw *ah)
490 {
491 int ecode;
492
493 if (!AR_SREV_9271(ah)) {
494 if (!ath9k_hw_chip_test(ah))
495 return -ENODEV;
496 }
497
498 ecode = ath9k_hw_rf_claim(ah);
499 if (ecode != 0)
500 return ecode;
501
502 ecode = ath9k_hw_eeprom_init(ah);
503 if (ecode != 0)
504 return ecode;
505
506 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
507 "Eeprom VER: %d, REV: %d\n",
508 ah->eep_ops->get_eeprom_ver(ah),
509 ah->eep_ops->get_eeprom_rev(ah));
510
511 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
512 if (ecode) {
513 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
514 "Failed allocating banks for "
515 "external radio\n");
516 return ecode;
517 }
518
519 if (!AR_SREV_9100(ah)) {
520 ath9k_hw_ani_setup(ah);
521 ath9k_hw_ani_init(ah);
522 }
523
524 return 0;
525 }
526
527 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
528 {
529 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
530 struct ath_common *common = ath9k_hw_common(ah);
531
532 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
533 !AR_SREV_9285(ah) && !AR_SREV_9271(ah) &&
534 ((pBase->version & 0xff) > 0x0a) &&
535 (pBase->pwdclkind == 0);
536
537 if (ah->need_an_top2_fixup)
538 ath_print(common, ATH_DBG_EEPROM,
539 "needs fixup for AR_AN_TOP2 register\n");
540 }
541
542 static void ath9k_hw_attach_ops(struct ath_hw *ah)
543 {
544 if (AR_SREV_9300_20_OR_LATER(ah))
545 ar9003_hw_attach_ops(ah);
546 else
547 ar9002_hw_attach_ops(ah);
548 }
549
550 /* Called for all hardware families */
551 static int __ath9k_hw_init(struct ath_hw *ah)
552 {
553 struct ath_common *common = ath9k_hw_common(ah);
554 int r = 0;
555
556 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
557 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
558
559 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
560 ath_print(common, ATH_DBG_FATAL,
561 "Couldn't reset chip\n");
562 return -EIO;
563 }
564
565 ath9k_hw_init_defaults(ah);
566 ath9k_hw_init_config(ah);
567
568 ath9k_hw_attach_ops(ah);
569
570 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
571 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
572 return -EIO;
573 }
574
575 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
576 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
577 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
578 ah->config.serialize_regmode =
579 SER_REG_MODE_ON;
580 } else {
581 ah->config.serialize_regmode =
582 SER_REG_MODE_OFF;
583 }
584 }
585
586 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
587 ah->config.serialize_regmode);
588
589 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
590 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
591 else
592 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
593
594 if (!ath9k_hw_macversion_supported(ah)) {
595 ath_print(common, ATH_DBG_FATAL,
596 "Mac Chip Rev 0x%02x.%x is not supported by "
597 "this driver\n", ah->hw_version.macVersion,
598 ah->hw_version.macRev);
599 return -EOPNOTSUPP;
600 }
601
602 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
603 ah->is_pciexpress = false;
604
605 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
606 ath9k_hw_init_cal_settings(ah);
607
608 ah->ani_function = ATH9K_ANI_ALL;
609 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
610 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
611
612 ath9k_hw_init_mode_regs(ah);
613
614 if (ah->is_pciexpress)
615 ath9k_hw_configpcipowersave(ah, 0, 0);
616 else
617 ath9k_hw_disablepcie(ah);
618
619 if (!AR_SREV_9300_20_OR_LATER(ah))
620 ar9002_hw_cck_chan14_spread(ah);
621
622 r = ath9k_hw_post_init(ah);
623 if (r)
624 return r;
625
626 ath9k_hw_init_mode_gain_regs(ah);
627 r = ath9k_hw_fill_cap_info(ah);
628 if (r)
629 return r;
630
631 ath9k_hw_init_eeprom_fix(ah);
632
633 r = ath9k_hw_init_macaddr(ah);
634 if (r) {
635 ath_print(common, ATH_DBG_FATAL,
636 "Failed to initialize MAC address\n");
637 return r;
638 }
639
640 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
641 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
642 else
643 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
644
645 if (AR_SREV_9300_20_OR_LATER(ah))
646 ar9003_hw_set_nf_limits(ah);
647
648 ath9k_init_nfcal_hist_buffer(ah);
649
650 common->state = ATH_HW_INITIALIZED;
651
652 return 0;
653 }
654
655 int ath9k_hw_init(struct ath_hw *ah)
656 {
657 int ret;
658 struct ath_common *common = ath9k_hw_common(ah);
659
660 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
661 switch (ah->hw_version.devid) {
662 case AR5416_DEVID_PCI:
663 case AR5416_DEVID_PCIE:
664 case AR5416_AR9100_DEVID:
665 case AR9160_DEVID_PCI:
666 case AR9280_DEVID_PCI:
667 case AR9280_DEVID_PCIE:
668 case AR9285_DEVID_PCIE:
669 case AR9287_DEVID_PCI:
670 case AR9287_DEVID_PCIE:
671 case AR2427_DEVID_PCIE:
672 case AR9300_DEVID_PCIE:
673 break;
674 default:
675 if (common->bus_ops->ath_bus_type == ATH_USB)
676 break;
677 ath_print(common, ATH_DBG_FATAL,
678 "Hardware device ID 0x%04x not supported\n",
679 ah->hw_version.devid);
680 return -EOPNOTSUPP;
681 }
682
683 ret = __ath9k_hw_init(ah);
684 if (ret) {
685 ath_print(common, ATH_DBG_FATAL,
686 "Unable to initialize hardware; "
687 "initialization status: %d\n", ret);
688 return ret;
689 }
690
691 return 0;
692 }
693 EXPORT_SYMBOL(ath9k_hw_init);
694
695 static void ath9k_hw_init_qos(struct ath_hw *ah)
696 {
697 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
698 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
699
700 REG_WRITE(ah, AR_QOS_NO_ACK,
701 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
702 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
703 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
704
705 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
706 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
707 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
708 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
709 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
710 }
711
712 static void ath9k_hw_init_pll(struct ath_hw *ah,
713 struct ath9k_channel *chan)
714 {
715 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
716
717 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
718
719 /* Switch the core clock for ar9271 to 117Mhz */
720 if (AR_SREV_9271(ah)) {
721 udelay(500);
722 REG_WRITE(ah, 0x50040, 0x304);
723 }
724
725 udelay(RTC_PLL_SETTLE_DELAY);
726
727 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
728 }
729
730 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
731 enum nl80211_iftype opmode)
732 {
733 u32 imr_reg = AR_IMR_TXERR |
734 AR_IMR_TXURN |
735 AR_IMR_RXERR |
736 AR_IMR_RXORN |
737 AR_IMR_BCNMISC;
738
739 if (ah->config.rx_intr_mitigation)
740 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
741 else
742 imr_reg |= AR_IMR_RXOK;
743
744 imr_reg |= AR_IMR_TXOK;
745
746 if (opmode == NL80211_IFTYPE_AP)
747 imr_reg |= AR_IMR_MIB;
748
749 REG_WRITE(ah, AR_IMR, imr_reg);
750 ah->imrs2_reg |= AR_IMR_S2_GTT;
751 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
752
753 if (!AR_SREV_9100(ah)) {
754 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
755 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
756 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
757 }
758 }
759
760 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
761 {
762 u32 val = ath9k_hw_mac_to_clks(ah, us);
763 val = min(val, (u32) 0xFFFF);
764 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
765 }
766
767 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
768 {
769 u32 val = ath9k_hw_mac_to_clks(ah, us);
770 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
771 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
772 }
773
774 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
775 {
776 u32 val = ath9k_hw_mac_to_clks(ah, us);
777 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
778 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
779 }
780
781 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
782 {
783 if (tu > 0xFFFF) {
784 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
785 "bad global tx timeout %u\n", tu);
786 ah->globaltxtimeout = (u32) -1;
787 return false;
788 } else {
789 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
790 ah->globaltxtimeout = tu;
791 return true;
792 }
793 }
794
795 void ath9k_hw_init_global_settings(struct ath_hw *ah)
796 {
797 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
798 int acktimeout;
799 int slottime;
800 int sifstime;
801
802 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
803 ah->misc_mode);
804
805 if (ah->misc_mode != 0)
806 REG_WRITE(ah, AR_PCU_MISC,
807 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
808
809 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
810 sifstime = 16;
811 else
812 sifstime = 10;
813
814 /* As defined by IEEE 802.11-2007 17.3.8.6 */
815 slottime = ah->slottime + 3 * ah->coverage_class;
816 acktimeout = slottime + sifstime;
817
818 /*
819 * Workaround for early ACK timeouts, add an offset to match the
820 * initval's 64us ack timeout value.
821 * This was initially only meant to work around an issue with delayed
822 * BA frames in some implementations, but it has been found to fix ACK
823 * timeout issues in other cases as well.
824 */
825 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
826 acktimeout += 64 - sifstime - ah->slottime;
827
828 ath9k_hw_setslottime(ah, slottime);
829 ath9k_hw_set_ack_timeout(ah, acktimeout);
830 ath9k_hw_set_cts_timeout(ah, acktimeout);
831 if (ah->globaltxtimeout != (u32) -1)
832 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
833 }
834 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
835
836 void ath9k_hw_deinit(struct ath_hw *ah)
837 {
838 struct ath_common *common = ath9k_hw_common(ah);
839
840 if (common->state < ATH_HW_INITIALIZED)
841 goto free_hw;
842
843 if (!AR_SREV_9100(ah))
844 ath9k_hw_ani_disable(ah);
845
846 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
847
848 free_hw:
849 ath9k_hw_rf_free_ext_banks(ah);
850 }
851 EXPORT_SYMBOL(ath9k_hw_deinit);
852
853 /*******/
854 /* INI */
855 /*******/
856
857 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
858 {
859 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
860
861 if (IS_CHAN_B(chan))
862 ctl |= CTL_11B;
863 else if (IS_CHAN_G(chan))
864 ctl |= CTL_11G;
865 else
866 ctl |= CTL_11A;
867
868 return ctl;
869 }
870
871 /****************************************/
872 /* Reset and Channel Switching Routines */
873 /****************************************/
874
875 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
876 {
877 u32 regval;
878
879 /*
880 * set AHB_MODE not to do cacheline prefetches
881 */
882 regval = REG_READ(ah, AR_AHB_MODE);
883 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
884
885 /*
886 * let mac dma reads be in 128 byte chunks
887 */
888 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
889 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
890
891 /*
892 * Restore TX Trigger Level to its pre-reset value.
893 * The initial value depends on whether aggregation is enabled, and is
894 * adjusted whenever underruns are detected.
895 */
896 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
897
898 /*
899 * let mac dma writes be in 128 byte chunks
900 */
901 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
902 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
903
904 /*
905 * Setup receive FIFO threshold to hold off TX activities
906 */
907 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
908
909 /*
910 * reduce the number of usable entries in PCU TXBUF to avoid
911 * wrap around issues.
912 */
913 if (AR_SREV_9285(ah)) {
914 /* For AR9285 the number of Fifos are reduced to half.
915 * So set the usable tx buf size also to half to
916 * avoid data/delimiter underruns
917 */
918 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
919 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
920 } else if (!AR_SREV_9271(ah)) {
921 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
922 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
923 }
924 }
925
926 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
927 {
928 u32 val;
929
930 val = REG_READ(ah, AR_STA_ID1);
931 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
932 switch (opmode) {
933 case NL80211_IFTYPE_AP:
934 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
935 | AR_STA_ID1_KSRCH_MODE);
936 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
937 break;
938 case NL80211_IFTYPE_ADHOC:
939 case NL80211_IFTYPE_MESH_POINT:
940 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
941 | AR_STA_ID1_KSRCH_MODE);
942 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
943 break;
944 case NL80211_IFTYPE_STATION:
945 case NL80211_IFTYPE_MONITOR:
946 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
947 break;
948 }
949 }
950
951 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
952 u32 *coef_mantissa, u32 *coef_exponent)
953 {
954 u32 coef_exp, coef_man;
955
956 for (coef_exp = 31; coef_exp > 0; coef_exp--)
957 if ((coef_scaled >> coef_exp) & 0x1)
958 break;
959
960 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
961
962 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
963
964 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
965 *coef_exponent = coef_exp - 16;
966 }
967
968 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
969 {
970 u32 rst_flags;
971 u32 tmpReg;
972
973 if (AR_SREV_9100(ah)) {
974 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
975 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
976 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
977 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
978 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
979 }
980
981 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
982 AR_RTC_FORCE_WAKE_ON_INT);
983
984 if (AR_SREV_9100(ah)) {
985 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
986 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
987 } else {
988 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
989 if (tmpReg &
990 (AR_INTR_SYNC_LOCAL_TIMEOUT |
991 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
992 u32 val;
993 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
994
995 val = AR_RC_HOSTIF;
996 if (!AR_SREV_9300_20_OR_LATER(ah))
997 val |= AR_RC_AHB;
998 REG_WRITE(ah, AR_RC, val);
999
1000 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1001 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1002
1003 rst_flags = AR_RTC_RC_MAC_WARM;
1004 if (type == ATH9K_RESET_COLD)
1005 rst_flags |= AR_RTC_RC_MAC_COLD;
1006 }
1007
1008 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1009 udelay(50);
1010
1011 REG_WRITE(ah, AR_RTC_RC, 0);
1012 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1013 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1014 "RTC stuck in MAC reset\n");
1015 return false;
1016 }
1017
1018 if (!AR_SREV_9100(ah))
1019 REG_WRITE(ah, AR_RC, 0);
1020
1021 if (AR_SREV_9100(ah))
1022 udelay(50);
1023
1024 return true;
1025 }
1026
1027 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1028 {
1029 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1030 AR_RTC_FORCE_WAKE_ON_INT);
1031
1032 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1033 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1034
1035 REG_WRITE(ah, AR_RTC_RESET, 0);
1036
1037 if (!AR_SREV_9300_20_OR_LATER(ah))
1038 udelay(2);
1039
1040 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1041 REG_WRITE(ah, AR_RC, 0);
1042
1043 REG_WRITE(ah, AR_RTC_RESET, 1);
1044
1045 if (!ath9k_hw_wait(ah,
1046 AR_RTC_STATUS,
1047 AR_RTC_STATUS_M,
1048 AR_RTC_STATUS_ON,
1049 AH_WAIT_TIMEOUT)) {
1050 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1051 "RTC not waking up\n");
1052 return false;
1053 }
1054
1055 ath9k_hw_read_revisions(ah);
1056
1057 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1058 }
1059
1060 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1061 {
1062 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1063 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1064
1065 switch (type) {
1066 case ATH9K_RESET_POWER_ON:
1067 return ath9k_hw_set_reset_power_on(ah);
1068 case ATH9K_RESET_WARM:
1069 case ATH9K_RESET_COLD:
1070 return ath9k_hw_set_reset(ah, type);
1071 default:
1072 return false;
1073 }
1074 }
1075
1076 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1077 struct ath9k_channel *chan)
1078 {
1079 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1080 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1081 return false;
1082 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1083 return false;
1084
1085 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1086 return false;
1087
1088 ah->chip_fullsleep = false;
1089 ath9k_hw_init_pll(ah, chan);
1090 ath9k_hw_set_rfmode(ah, chan);
1091
1092 return true;
1093 }
1094
1095 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1096 struct ath9k_channel *chan)
1097 {
1098 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1099 struct ath_common *common = ath9k_hw_common(ah);
1100 struct ieee80211_channel *channel = chan->chan;
1101 u32 qnum;
1102 int r;
1103
1104 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1105 if (ath9k_hw_numtxpending(ah, qnum)) {
1106 ath_print(common, ATH_DBG_QUEUE,
1107 "Transmit frames pending on "
1108 "queue %d\n", qnum);
1109 return false;
1110 }
1111 }
1112
1113 if (!ath9k_hw_rfbus_req(ah)) {
1114 ath_print(common, ATH_DBG_FATAL,
1115 "Could not kill baseband RX\n");
1116 return false;
1117 }
1118
1119 ath9k_hw_set_channel_regs(ah, chan);
1120
1121 r = ath9k_hw_rf_set_freq(ah, chan);
1122 if (r) {
1123 ath_print(common, ATH_DBG_FATAL,
1124 "Failed to set channel\n");
1125 return false;
1126 }
1127
1128 ah->eep_ops->set_txpower(ah, chan,
1129 ath9k_regd_get_ctl(regulatory, chan),
1130 channel->max_antenna_gain * 2,
1131 channel->max_power * 2,
1132 min((u32) MAX_RATE_POWER,
1133 (u32) regulatory->power_limit));
1134
1135 ath9k_hw_rfbus_done(ah);
1136
1137 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1138 ath9k_hw_set_delta_slope(ah, chan);
1139
1140 ath9k_hw_spur_mitigate_freq(ah, chan);
1141
1142 if (!chan->oneTimeCalsDone)
1143 chan->oneTimeCalsDone = true;
1144
1145 return true;
1146 }
1147
1148 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1149 bool bChannelChange)
1150 {
1151 struct ath_common *common = ath9k_hw_common(ah);
1152 u32 saveLedState;
1153 struct ath9k_channel *curchan = ah->curchan;
1154 u32 saveDefAntenna;
1155 u32 macStaId1;
1156 u64 tsf = 0;
1157 int i, r;
1158
1159 ah->txchainmask = common->tx_chainmask;
1160 ah->rxchainmask = common->rx_chainmask;
1161
1162 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1163 return -EIO;
1164
1165 if (curchan && !ah->chip_fullsleep)
1166 ath9k_hw_getnf(ah, curchan);
1167
1168 if (bChannelChange &&
1169 (ah->chip_fullsleep != true) &&
1170 (ah->curchan != NULL) &&
1171 (chan->channel != ah->curchan->channel) &&
1172 ((chan->channelFlags & CHANNEL_ALL) ==
1173 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1174 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1175 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1176
1177 if (ath9k_hw_channel_change(ah, chan)) {
1178 ath9k_hw_loadnf(ah, ah->curchan);
1179 ath9k_hw_start_nfcal(ah);
1180 return 0;
1181 }
1182 }
1183
1184 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1185 if (saveDefAntenna == 0)
1186 saveDefAntenna = 1;
1187
1188 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1189
1190 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1191 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1192 tsf = ath9k_hw_gettsf64(ah);
1193
1194 saveLedState = REG_READ(ah, AR_CFG_LED) &
1195 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1196 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1197
1198 ath9k_hw_mark_phy_inactive(ah);
1199
1200 /* Only required on the first reset */
1201 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1202 REG_WRITE(ah,
1203 AR9271_RESET_POWER_DOWN_CONTROL,
1204 AR9271_RADIO_RF_RST);
1205 udelay(50);
1206 }
1207
1208 if (!ath9k_hw_chip_reset(ah, chan)) {
1209 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1210 return -EINVAL;
1211 }
1212
1213 /* Only required on the first reset */
1214 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1215 ah->htc_reset_init = false;
1216 REG_WRITE(ah,
1217 AR9271_RESET_POWER_DOWN_CONTROL,
1218 AR9271_GATE_MAC_CTL);
1219 udelay(50);
1220 }
1221
1222 /* Restore TSF */
1223 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1224 ath9k_hw_settsf64(ah, tsf);
1225
1226 if (AR_SREV_9280_10_OR_LATER(ah))
1227 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1228
1229 r = ath9k_hw_process_ini(ah, chan);
1230 if (r)
1231 return r;
1232
1233 /* Setup MFP options for CCMP */
1234 if (AR_SREV_9280_20_OR_LATER(ah)) {
1235 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1236 * frames when constructing CCMP AAD. */
1237 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1238 0xc7ff);
1239 ah->sw_mgmt_crypto = false;
1240 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1241 /* Disable hardware crypto for management frames */
1242 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1243 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1244 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1245 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1246 ah->sw_mgmt_crypto = true;
1247 } else
1248 ah->sw_mgmt_crypto = true;
1249
1250 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1251 ath9k_hw_set_delta_slope(ah, chan);
1252
1253 ath9k_hw_spur_mitigate_freq(ah, chan);
1254 ah->eep_ops->set_board_values(ah, chan);
1255
1256 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1257 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1258 | macStaId1
1259 | AR_STA_ID1_RTS_USE_DEF
1260 | (ah->config.
1261 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1262 | ah->sta_id1_defaults);
1263 ath9k_hw_set_operating_mode(ah, ah->opmode);
1264
1265 ath_hw_setbssidmask(common);
1266
1267 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1268
1269 ath9k_hw_write_associd(ah);
1270
1271 REG_WRITE(ah, AR_ISR, ~0);
1272
1273 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1274
1275 r = ath9k_hw_rf_set_freq(ah, chan);
1276 if (r)
1277 return r;
1278
1279 for (i = 0; i < AR_NUM_DCU; i++)
1280 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1281
1282 ah->intr_txqs = 0;
1283 for (i = 0; i < ah->caps.total_queues; i++)
1284 ath9k_hw_resettxqueue(ah, i);
1285
1286 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1287 ath9k_hw_init_qos(ah);
1288
1289 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1290 ath9k_enable_rfkill(ah);
1291
1292 ath9k_hw_init_global_settings(ah);
1293
1294 if (AR_SREV_9287_12_OR_LATER(ah)) {
1295 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1296 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1297 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1298 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1299 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1300 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1301
1302 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1303 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1304
1305 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1306 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1307 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1308 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1309 }
1310 if (AR_SREV_9287_12_OR_LATER(ah)) {
1311 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1312 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1313 }
1314
1315 REG_WRITE(ah, AR_STA_ID1,
1316 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1317
1318 ath9k_hw_set_dma(ah);
1319
1320 REG_WRITE(ah, AR_OBS, 8);
1321
1322 if (ah->config.rx_intr_mitigation) {
1323 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1324 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1325 }
1326
1327 ath9k_hw_init_bb(ah, chan);
1328
1329 if (!ath9k_hw_init_cal(ah, chan))
1330 return -EIO;
1331
1332 ath9k_hw_restore_chainmask(ah);
1333 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1334
1335 /*
1336 * For big endian systems turn on swapping for descriptors
1337 */
1338 if (AR_SREV_9100(ah)) {
1339 u32 mask;
1340 mask = REG_READ(ah, AR_CFG);
1341 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1342 ath_print(common, ATH_DBG_RESET,
1343 "CFG Byte Swap Set 0x%x\n", mask);
1344 } else {
1345 mask =
1346 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1347 REG_WRITE(ah, AR_CFG, mask);
1348 ath_print(common, ATH_DBG_RESET,
1349 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1350 }
1351 } else {
1352 /* Configure AR9271 target WLAN */
1353 if (AR_SREV_9271(ah))
1354 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1355 #ifdef __BIG_ENDIAN
1356 else
1357 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1358 #endif
1359 }
1360
1361 if (ah->btcoex_hw.enabled)
1362 ath9k_hw_btcoex_enable(ah);
1363
1364 return 0;
1365 }
1366 EXPORT_SYMBOL(ath9k_hw_reset);
1367
1368 /************************/
1369 /* Key Cache Management */
1370 /************************/
1371
1372 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1373 {
1374 u32 keyType;
1375
1376 if (entry >= ah->caps.keycache_size) {
1377 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1378 "keychache entry %u out of range\n", entry);
1379 return false;
1380 }
1381
1382 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1383
1384 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1385 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1386 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1387 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1388 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1389 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1390 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1391 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1392
1393 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1394 u16 micentry = entry + 64;
1395
1396 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1397 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1398 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1399 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1400
1401 }
1402
1403 return true;
1404 }
1405 EXPORT_SYMBOL(ath9k_hw_keyreset);
1406
1407 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1408 {
1409 u32 macHi, macLo;
1410
1411 if (entry >= ah->caps.keycache_size) {
1412 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1413 "keychache entry %u out of range\n", entry);
1414 return false;
1415 }
1416
1417 if (mac != NULL) {
1418 macHi = (mac[5] << 8) | mac[4];
1419 macLo = (mac[3] << 24) |
1420 (mac[2] << 16) |
1421 (mac[1] << 8) |
1422 mac[0];
1423 macLo >>= 1;
1424 macLo |= (macHi & 1) << 31;
1425 macHi >>= 1;
1426 } else {
1427 macLo = macHi = 0;
1428 }
1429 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1430 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1431
1432 return true;
1433 }
1434 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1435
1436 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1437 const struct ath9k_keyval *k,
1438 const u8 *mac)
1439 {
1440 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1441 struct ath_common *common = ath9k_hw_common(ah);
1442 u32 key0, key1, key2, key3, key4;
1443 u32 keyType;
1444
1445 if (entry >= pCap->keycache_size) {
1446 ath_print(common, ATH_DBG_FATAL,
1447 "keycache entry %u out of range\n", entry);
1448 return false;
1449 }
1450
1451 switch (k->kv_type) {
1452 case ATH9K_CIPHER_AES_OCB:
1453 keyType = AR_KEYTABLE_TYPE_AES;
1454 break;
1455 case ATH9K_CIPHER_AES_CCM:
1456 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1457 ath_print(common, ATH_DBG_ANY,
1458 "AES-CCM not supported by mac rev 0x%x\n",
1459 ah->hw_version.macRev);
1460 return false;
1461 }
1462 keyType = AR_KEYTABLE_TYPE_CCM;
1463 break;
1464 case ATH9K_CIPHER_TKIP:
1465 keyType = AR_KEYTABLE_TYPE_TKIP;
1466 if (ATH9K_IS_MIC_ENABLED(ah)
1467 && entry + 64 >= pCap->keycache_size) {
1468 ath_print(common, ATH_DBG_ANY,
1469 "entry %u inappropriate for TKIP\n", entry);
1470 return false;
1471 }
1472 break;
1473 case ATH9K_CIPHER_WEP:
1474 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1475 ath_print(common, ATH_DBG_ANY,
1476 "WEP key length %u too small\n", k->kv_len);
1477 return false;
1478 }
1479 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1480 keyType = AR_KEYTABLE_TYPE_40;
1481 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1482 keyType = AR_KEYTABLE_TYPE_104;
1483 else
1484 keyType = AR_KEYTABLE_TYPE_128;
1485 break;
1486 case ATH9K_CIPHER_CLR:
1487 keyType = AR_KEYTABLE_TYPE_CLR;
1488 break;
1489 default:
1490 ath_print(common, ATH_DBG_FATAL,
1491 "cipher %u not supported\n", k->kv_type);
1492 return false;
1493 }
1494
1495 key0 = get_unaligned_le32(k->kv_val + 0);
1496 key1 = get_unaligned_le16(k->kv_val + 4);
1497 key2 = get_unaligned_le32(k->kv_val + 6);
1498 key3 = get_unaligned_le16(k->kv_val + 10);
1499 key4 = get_unaligned_le32(k->kv_val + 12);
1500 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1501 key4 &= 0xff;
1502
1503 /*
1504 * Note: Key cache registers access special memory area that requires
1505 * two 32-bit writes to actually update the values in the internal
1506 * memory. Consequently, the exact order and pairs used here must be
1507 * maintained.
1508 */
1509
1510 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1511 u16 micentry = entry + 64;
1512
1513 /*
1514 * Write inverted key[47:0] first to avoid Michael MIC errors
1515 * on frames that could be sent or received at the same time.
1516 * The correct key will be written in the end once everything
1517 * else is ready.
1518 */
1519 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1520 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1521
1522 /* Write key[95:48] */
1523 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1524 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1525
1526 /* Write key[127:96] and key type */
1527 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1528 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1529
1530 /* Write MAC address for the entry */
1531 (void) ath9k_hw_keysetmac(ah, entry, mac);
1532
1533 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1534 /*
1535 * TKIP uses two key cache entries:
1536 * Michael MIC TX/RX keys in the same key cache entry
1537 * (idx = main index + 64):
1538 * key0 [31:0] = RX key [31:0]
1539 * key1 [15:0] = TX key [31:16]
1540 * key1 [31:16] = reserved
1541 * key2 [31:0] = RX key [63:32]
1542 * key3 [15:0] = TX key [15:0]
1543 * key3 [31:16] = reserved
1544 * key4 [31:0] = TX key [63:32]
1545 */
1546 u32 mic0, mic1, mic2, mic3, mic4;
1547
1548 mic0 = get_unaligned_le32(k->kv_mic + 0);
1549 mic2 = get_unaligned_le32(k->kv_mic + 4);
1550 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1551 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1552 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1553
1554 /* Write RX[31:0] and TX[31:16] */
1555 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1556 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1557
1558 /* Write RX[63:32] and TX[15:0] */
1559 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1560 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1561
1562 /* Write TX[63:32] and keyType(reserved) */
1563 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1564 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1565 AR_KEYTABLE_TYPE_CLR);
1566
1567 } else {
1568 /*
1569 * TKIP uses four key cache entries (two for group
1570 * keys):
1571 * Michael MIC TX/RX keys are in different key cache
1572 * entries (idx = main index + 64 for TX and
1573 * main index + 32 + 96 for RX):
1574 * key0 [31:0] = TX/RX MIC key [31:0]
1575 * key1 [31:0] = reserved
1576 * key2 [31:0] = TX/RX MIC key [63:32]
1577 * key3 [31:0] = reserved
1578 * key4 [31:0] = reserved
1579 *
1580 * Upper layer code will call this function separately
1581 * for TX and RX keys when these registers offsets are
1582 * used.
1583 */
1584 u32 mic0, mic2;
1585
1586 mic0 = get_unaligned_le32(k->kv_mic + 0);
1587 mic2 = get_unaligned_le32(k->kv_mic + 4);
1588
1589 /* Write MIC key[31:0] */
1590 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1591 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1592
1593 /* Write MIC key[63:32] */
1594 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1595 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1596
1597 /* Write TX[63:32] and keyType(reserved) */
1598 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1599 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1600 AR_KEYTABLE_TYPE_CLR);
1601 }
1602
1603 /* MAC address registers are reserved for the MIC entry */
1604 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1605 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1606
1607 /*
1608 * Write the correct (un-inverted) key[47:0] last to enable
1609 * TKIP now that all other registers are set with correct
1610 * values.
1611 */
1612 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1613 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1614 } else {
1615 /* Write key[47:0] */
1616 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1617 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1618
1619 /* Write key[95:48] */
1620 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1621 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1622
1623 /* Write key[127:96] and key type */
1624 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1625 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1626
1627 /* Write MAC address for the entry */
1628 (void) ath9k_hw_keysetmac(ah, entry, mac);
1629 }
1630
1631 return true;
1632 }
1633 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1634
1635 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1636 {
1637 if (entry < ah->caps.keycache_size) {
1638 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1639 if (val & AR_KEYTABLE_VALID)
1640 return true;
1641 }
1642 return false;
1643 }
1644 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1645
1646 /******************************/
1647 /* Power Management (Chipset) */
1648 /******************************/
1649
1650 /*
1651 * Notify Power Mgt is disabled in self-generated frames.
1652 * If requested, force chip to sleep.
1653 */
1654 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1655 {
1656 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1657 if (setChip) {
1658 /*
1659 * Clear the RTC force wake bit to allow the
1660 * mac to go to sleep.
1661 */
1662 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1663 AR_RTC_FORCE_WAKE_EN);
1664 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1665 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1666
1667 /* Shutdown chip. Active low */
1668 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1669 REG_CLR_BIT(ah, (AR_RTC_RESET),
1670 AR_RTC_RESET_EN);
1671 }
1672 }
1673
1674 /*
1675 * Notify Power Management is enabled in self-generating
1676 * frames. If request, set power mode of chip to
1677 * auto/normal. Duration in units of 128us (1/8 TU).
1678 */
1679 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1680 {
1681 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1682 if (setChip) {
1683 struct ath9k_hw_capabilities *pCap = &ah->caps;
1684
1685 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1686 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1687 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1688 AR_RTC_FORCE_WAKE_ON_INT);
1689 } else {
1690 /*
1691 * Clear the RTC force wake bit to allow the
1692 * mac to go to sleep.
1693 */
1694 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1695 AR_RTC_FORCE_WAKE_EN);
1696 }
1697 }
1698 }
1699
1700 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1701 {
1702 u32 val;
1703 int i;
1704
1705 if (setChip) {
1706 if ((REG_READ(ah, AR_RTC_STATUS) &
1707 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1708 if (ath9k_hw_set_reset_reg(ah,
1709 ATH9K_RESET_POWER_ON) != true) {
1710 return false;
1711 }
1712 if (!AR_SREV_9300_20_OR_LATER(ah))
1713 ath9k_hw_init_pll(ah, NULL);
1714 }
1715 if (AR_SREV_9100(ah))
1716 REG_SET_BIT(ah, AR_RTC_RESET,
1717 AR_RTC_RESET_EN);
1718
1719 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1720 AR_RTC_FORCE_WAKE_EN);
1721 udelay(50);
1722
1723 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1724 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1725 if (val == AR_RTC_STATUS_ON)
1726 break;
1727 udelay(50);
1728 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1729 AR_RTC_FORCE_WAKE_EN);
1730 }
1731 if (i == 0) {
1732 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1733 "Failed to wakeup in %uus\n",
1734 POWER_UP_TIME / 20);
1735 return false;
1736 }
1737 }
1738
1739 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1740
1741 return true;
1742 }
1743
1744 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1745 {
1746 struct ath_common *common = ath9k_hw_common(ah);
1747 int status = true, setChip = true;
1748 static const char *modes[] = {
1749 "AWAKE",
1750 "FULL-SLEEP",
1751 "NETWORK SLEEP",
1752 "UNDEFINED"
1753 };
1754
1755 if (ah->power_mode == mode)
1756 return status;
1757
1758 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1759 modes[ah->power_mode], modes[mode]);
1760
1761 switch (mode) {
1762 case ATH9K_PM_AWAKE:
1763 status = ath9k_hw_set_power_awake(ah, setChip);
1764 break;
1765 case ATH9K_PM_FULL_SLEEP:
1766 ath9k_set_power_sleep(ah, setChip);
1767 ah->chip_fullsleep = true;
1768 break;
1769 case ATH9K_PM_NETWORK_SLEEP:
1770 ath9k_set_power_network_sleep(ah, setChip);
1771 break;
1772 default:
1773 ath_print(common, ATH_DBG_FATAL,
1774 "Unknown power mode %u\n", mode);
1775 return false;
1776 }
1777 ah->power_mode = mode;
1778
1779 return status;
1780 }
1781 EXPORT_SYMBOL(ath9k_hw_setpower);
1782
1783 /*******************/
1784 /* Beacon Handling */
1785 /*******************/
1786
1787 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1788 {
1789 int flags = 0;
1790
1791 ah->beacon_interval = beacon_period;
1792
1793 switch (ah->opmode) {
1794 case NL80211_IFTYPE_STATION:
1795 case NL80211_IFTYPE_MONITOR:
1796 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1797 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1798 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1799 flags |= AR_TBTT_TIMER_EN;
1800 break;
1801 case NL80211_IFTYPE_ADHOC:
1802 case NL80211_IFTYPE_MESH_POINT:
1803 REG_SET_BIT(ah, AR_TXCFG,
1804 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1805 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1806 TU_TO_USEC(next_beacon +
1807 (ah->atim_window ? ah->
1808 atim_window : 1)));
1809 flags |= AR_NDP_TIMER_EN;
1810 case NL80211_IFTYPE_AP:
1811 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1812 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1813 TU_TO_USEC(next_beacon -
1814 ah->config.
1815 dma_beacon_response_time));
1816 REG_WRITE(ah, AR_NEXT_SWBA,
1817 TU_TO_USEC(next_beacon -
1818 ah->config.
1819 sw_beacon_response_time));
1820 flags |=
1821 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1822 break;
1823 default:
1824 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1825 "%s: unsupported opmode: %d\n",
1826 __func__, ah->opmode);
1827 return;
1828 break;
1829 }
1830
1831 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1832 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1833 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1834 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1835
1836 beacon_period &= ~ATH9K_BEACON_ENA;
1837 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1838 ath9k_hw_reset_tsf(ah);
1839 }
1840
1841 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1842 }
1843 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1844
1845 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1846 const struct ath9k_beacon_state *bs)
1847 {
1848 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1849 struct ath9k_hw_capabilities *pCap = &ah->caps;
1850 struct ath_common *common = ath9k_hw_common(ah);
1851
1852 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1853
1854 REG_WRITE(ah, AR_BEACON_PERIOD,
1855 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1856 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1857 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1858
1859 REG_RMW_FIELD(ah, AR_RSSI_THR,
1860 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1861
1862 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1863
1864 if (bs->bs_sleepduration > beaconintval)
1865 beaconintval = bs->bs_sleepduration;
1866
1867 dtimperiod = bs->bs_dtimperiod;
1868 if (bs->bs_sleepduration > dtimperiod)
1869 dtimperiod = bs->bs_sleepduration;
1870
1871 if (beaconintval == dtimperiod)
1872 nextTbtt = bs->bs_nextdtim;
1873 else
1874 nextTbtt = bs->bs_nexttbtt;
1875
1876 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1877 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1878 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1879 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1880
1881 REG_WRITE(ah, AR_NEXT_DTIM,
1882 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1883 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1884
1885 REG_WRITE(ah, AR_SLEEP1,
1886 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1887 | AR_SLEEP1_ASSUME_DTIM);
1888
1889 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1890 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1891 else
1892 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1893
1894 REG_WRITE(ah, AR_SLEEP2,
1895 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1896
1897 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1898 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1899
1900 REG_SET_BIT(ah, AR_TIMER_MODE,
1901 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1902 AR_DTIM_TIMER_EN);
1903
1904 /* TSF Out of Range Threshold */
1905 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1906 }
1907 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1908
1909 /*******************/
1910 /* HW Capabilities */
1911 /*******************/
1912
1913 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1914 {
1915 struct ath9k_hw_capabilities *pCap = &ah->caps;
1916 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1917 struct ath_common *common = ath9k_hw_common(ah);
1918 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1919
1920 u16 capField = 0, eeval;
1921
1922 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1923 regulatory->current_rd = eeval;
1924
1925 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1926 if (AR_SREV_9285_10_OR_LATER(ah))
1927 eeval |= AR9285_RDEXT_DEFAULT;
1928 regulatory->current_rd_ext = eeval;
1929
1930 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1931
1932 if (ah->opmode != NL80211_IFTYPE_AP &&
1933 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1934 if (regulatory->current_rd == 0x64 ||
1935 regulatory->current_rd == 0x65)
1936 regulatory->current_rd += 5;
1937 else if (regulatory->current_rd == 0x41)
1938 regulatory->current_rd = 0x43;
1939 ath_print(common, ATH_DBG_REGULATORY,
1940 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1941 }
1942
1943 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1944 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1945 ath_print(common, ATH_DBG_FATAL,
1946 "no band has been marked as supported in EEPROM.\n");
1947 return -EINVAL;
1948 }
1949
1950 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
1951
1952 if (eeval & AR5416_OPFLAGS_11A) {
1953 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
1954 if (ah->config.ht_enable) {
1955 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
1956 set_bit(ATH9K_MODE_11NA_HT20,
1957 pCap->wireless_modes);
1958 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
1959 set_bit(ATH9K_MODE_11NA_HT40PLUS,
1960 pCap->wireless_modes);
1961 set_bit(ATH9K_MODE_11NA_HT40MINUS,
1962 pCap->wireless_modes);
1963 }
1964 }
1965 }
1966
1967 if (eeval & AR5416_OPFLAGS_11G) {
1968 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
1969 if (ah->config.ht_enable) {
1970 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
1971 set_bit(ATH9K_MODE_11NG_HT20,
1972 pCap->wireless_modes);
1973 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
1974 set_bit(ATH9K_MODE_11NG_HT40PLUS,
1975 pCap->wireless_modes);
1976 set_bit(ATH9K_MODE_11NG_HT40MINUS,
1977 pCap->wireless_modes);
1978 }
1979 }
1980 }
1981
1982 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1983 /*
1984 * For AR9271 we will temporarilly uses the rx chainmax as read from
1985 * the EEPROM.
1986 */
1987 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1988 !(eeval & AR5416_OPFLAGS_11A) &&
1989 !(AR_SREV_9271(ah)))
1990 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1991 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1992 else
1993 /* Use rx_chainmask from EEPROM. */
1994 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1995
1996 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
1997 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1998
1999 pCap->low_2ghz_chan = 2312;
2000 pCap->high_2ghz_chan = 2732;
2001
2002 pCap->low_5ghz_chan = 4920;
2003 pCap->high_5ghz_chan = 6100;
2004
2005 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2006 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2007 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2008
2009 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2010 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2011 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2012
2013 if (ah->config.ht_enable)
2014 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2015 else
2016 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2017
2018 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2019 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2020 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2021 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2022
2023 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2024 pCap->total_queues =
2025 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2026 else
2027 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2028
2029 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2030 pCap->keycache_size =
2031 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2032 else
2033 pCap->keycache_size = AR_KEYTABLE_SIZE;
2034
2035 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2036
2037 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2038 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2039 else
2040 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2041
2042 if (AR_SREV_9271(ah))
2043 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2044 else if (AR_SREV_9285_10_OR_LATER(ah))
2045 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2046 else if (AR_SREV_9280_10_OR_LATER(ah))
2047 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2048 else
2049 pCap->num_gpio_pins = AR_NUM_GPIO;
2050
2051 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2052 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2053 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2054 } else {
2055 pCap->rts_aggr_limit = (8 * 1024);
2056 }
2057
2058 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2059
2060 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2061 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2062 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2063 ah->rfkill_gpio =
2064 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2065 ah->rfkill_polarity =
2066 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2067
2068 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2069 }
2070 #endif
2071 if (AR_SREV_9271(ah))
2072 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2073 else
2074 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2075
2076 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2077 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2078 else
2079 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2080
2081 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2082 pCap->reg_cap =
2083 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2084 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2085 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2086 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2087 } else {
2088 pCap->reg_cap =
2089 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2090 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2091 }
2092
2093 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2094 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2095 AR_SREV_5416(ah))
2096 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2097
2098 pCap->num_antcfg_5ghz =
2099 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2100 pCap->num_antcfg_2ghz =
2101 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2102
2103 if (AR_SREV_9280_10_OR_LATER(ah) &&
2104 ath9k_hw_btcoex_supported(ah)) {
2105 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2106 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2107
2108 if (AR_SREV_9285(ah)) {
2109 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2110 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2111 } else {
2112 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2113 }
2114 } else {
2115 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2116 }
2117
2118 if (AR_SREV_9300_20_OR_LATER(ah)) {
2119 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
2120 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2121 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2122 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2123 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2124 } else {
2125 pCap->tx_desc_len = sizeof(struct ath_desc);
2126 }
2127
2128 return 0;
2129 }
2130
2131 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2132 u32 capability, u32 *result)
2133 {
2134 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2135 switch (type) {
2136 case ATH9K_CAP_CIPHER:
2137 switch (capability) {
2138 case ATH9K_CIPHER_AES_CCM:
2139 case ATH9K_CIPHER_AES_OCB:
2140 case ATH9K_CIPHER_TKIP:
2141 case ATH9K_CIPHER_WEP:
2142 case ATH9K_CIPHER_MIC:
2143 case ATH9K_CIPHER_CLR:
2144 return true;
2145 default:
2146 return false;
2147 }
2148 case ATH9K_CAP_TKIP_MIC:
2149 switch (capability) {
2150 case 0:
2151 return true;
2152 case 1:
2153 return (ah->sta_id1_defaults &
2154 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2155 false;
2156 }
2157 case ATH9K_CAP_TKIP_SPLIT:
2158 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2159 false : true;
2160 case ATH9K_CAP_MCAST_KEYSRCH:
2161 switch (capability) {
2162 case 0:
2163 return true;
2164 case 1:
2165 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2166 return false;
2167 } else {
2168 return (ah->sta_id1_defaults &
2169 AR_STA_ID1_MCAST_KSRCH) ? true :
2170 false;
2171 }
2172 }
2173 return false;
2174 case ATH9K_CAP_TXPOW:
2175 switch (capability) {
2176 case 0:
2177 return 0;
2178 case 1:
2179 *result = regulatory->power_limit;
2180 return 0;
2181 case 2:
2182 *result = regulatory->max_power_level;
2183 return 0;
2184 case 3:
2185 *result = regulatory->tp_scale;
2186 return 0;
2187 }
2188 return false;
2189 case ATH9K_CAP_DS:
2190 return (AR_SREV_9280_20_OR_LATER(ah) &&
2191 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2192 ? false : true;
2193 default:
2194 return false;
2195 }
2196 }
2197 EXPORT_SYMBOL(ath9k_hw_getcapability);
2198
2199 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2200 u32 capability, u32 setting, int *status)
2201 {
2202 switch (type) {
2203 case ATH9K_CAP_TKIP_MIC:
2204 if (setting)
2205 ah->sta_id1_defaults |=
2206 AR_STA_ID1_CRPT_MIC_ENABLE;
2207 else
2208 ah->sta_id1_defaults &=
2209 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2210 return true;
2211 case ATH9K_CAP_MCAST_KEYSRCH:
2212 if (setting)
2213 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2214 else
2215 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2216 return true;
2217 default:
2218 return false;
2219 }
2220 }
2221 EXPORT_SYMBOL(ath9k_hw_setcapability);
2222
2223 /****************************/
2224 /* GPIO / RFKILL / Antennae */
2225 /****************************/
2226
2227 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2228 u32 gpio, u32 type)
2229 {
2230 int addr;
2231 u32 gpio_shift, tmp;
2232
2233 if (gpio > 11)
2234 addr = AR_GPIO_OUTPUT_MUX3;
2235 else if (gpio > 5)
2236 addr = AR_GPIO_OUTPUT_MUX2;
2237 else
2238 addr = AR_GPIO_OUTPUT_MUX1;
2239
2240 gpio_shift = (gpio % 6) * 5;
2241
2242 if (AR_SREV_9280_20_OR_LATER(ah)
2243 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2244 REG_RMW(ah, addr, (type << gpio_shift),
2245 (0x1f << gpio_shift));
2246 } else {
2247 tmp = REG_READ(ah, addr);
2248 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2249 tmp &= ~(0x1f << gpio_shift);
2250 tmp |= (type << gpio_shift);
2251 REG_WRITE(ah, addr, tmp);
2252 }
2253 }
2254
2255 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2256 {
2257 u32 gpio_shift;
2258
2259 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2260
2261 gpio_shift = gpio << 1;
2262
2263 REG_RMW(ah,
2264 AR_GPIO_OE_OUT,
2265 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2266 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2267 }
2268 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2269
2270 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2271 {
2272 #define MS_REG_READ(x, y) \
2273 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2274
2275 if (gpio >= ah->caps.num_gpio_pins)
2276 return 0xffffffff;
2277
2278 if (AR_SREV_9300_20_OR_LATER(ah))
2279 return MS_REG_READ(AR9300, gpio) != 0;
2280 else if (AR_SREV_9271(ah))
2281 return MS_REG_READ(AR9271, gpio) != 0;
2282 else if (AR_SREV_9287_10_OR_LATER(ah))
2283 return MS_REG_READ(AR9287, gpio) != 0;
2284 else if (AR_SREV_9285_10_OR_LATER(ah))
2285 return MS_REG_READ(AR9285, gpio) != 0;
2286 else if (AR_SREV_9280_10_OR_LATER(ah))
2287 return MS_REG_READ(AR928X, gpio) != 0;
2288 else
2289 return MS_REG_READ(AR, gpio) != 0;
2290 }
2291 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2292
2293 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2294 u32 ah_signal_type)
2295 {
2296 u32 gpio_shift;
2297
2298 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2299
2300 gpio_shift = 2 * gpio;
2301
2302 REG_RMW(ah,
2303 AR_GPIO_OE_OUT,
2304 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2305 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2306 }
2307 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2308
2309 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2310 {
2311 if (AR_SREV_9271(ah))
2312 val = ~val;
2313
2314 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2315 AR_GPIO_BIT(gpio));
2316 }
2317 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2318
2319 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2320 {
2321 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2322 }
2323 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2324
2325 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2326 {
2327 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2328 }
2329 EXPORT_SYMBOL(ath9k_hw_setantenna);
2330
2331 /*********************/
2332 /* General Operation */
2333 /*********************/
2334
2335 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2336 {
2337 u32 bits = REG_READ(ah, AR_RX_FILTER);
2338 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2339
2340 if (phybits & AR_PHY_ERR_RADAR)
2341 bits |= ATH9K_RX_FILTER_PHYRADAR;
2342 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2343 bits |= ATH9K_RX_FILTER_PHYERR;
2344
2345 return bits;
2346 }
2347 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2348
2349 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2350 {
2351 u32 phybits;
2352
2353 REG_WRITE(ah, AR_RX_FILTER, bits);
2354
2355 phybits = 0;
2356 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2357 phybits |= AR_PHY_ERR_RADAR;
2358 if (bits & ATH9K_RX_FILTER_PHYERR)
2359 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2360 REG_WRITE(ah, AR_PHY_ERR, phybits);
2361
2362 if (phybits)
2363 REG_WRITE(ah, AR_RXCFG,
2364 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2365 else
2366 REG_WRITE(ah, AR_RXCFG,
2367 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2368 }
2369 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2370
2371 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2372 {
2373 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2374 return false;
2375
2376 ath9k_hw_init_pll(ah, NULL);
2377 return true;
2378 }
2379 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2380
2381 bool ath9k_hw_disable(struct ath_hw *ah)
2382 {
2383 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2384 return false;
2385
2386 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2387 return false;
2388
2389 ath9k_hw_init_pll(ah, NULL);
2390 return true;
2391 }
2392 EXPORT_SYMBOL(ath9k_hw_disable);
2393
2394 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2395 {
2396 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2397 struct ath9k_channel *chan = ah->curchan;
2398 struct ieee80211_channel *channel = chan->chan;
2399
2400 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2401
2402 ah->eep_ops->set_txpower(ah, chan,
2403 ath9k_regd_get_ctl(regulatory, chan),
2404 channel->max_antenna_gain * 2,
2405 channel->max_power * 2,
2406 min((u32) MAX_RATE_POWER,
2407 (u32) regulatory->power_limit));
2408 }
2409 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2410
2411 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2412 {
2413 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2414 }
2415 EXPORT_SYMBOL(ath9k_hw_setmac);
2416
2417 void ath9k_hw_setopmode(struct ath_hw *ah)
2418 {
2419 ath9k_hw_set_operating_mode(ah, ah->opmode);
2420 }
2421 EXPORT_SYMBOL(ath9k_hw_setopmode);
2422
2423 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2424 {
2425 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2426 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2427 }
2428 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2429
2430 void ath9k_hw_write_associd(struct ath_hw *ah)
2431 {
2432 struct ath_common *common = ath9k_hw_common(ah);
2433
2434 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2435 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2436 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2437 }
2438 EXPORT_SYMBOL(ath9k_hw_write_associd);
2439
2440 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2441 {
2442 u64 tsf;
2443
2444 tsf = REG_READ(ah, AR_TSF_U32);
2445 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
2446
2447 return tsf;
2448 }
2449 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2450
2451 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2452 {
2453 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2454 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2455 }
2456 EXPORT_SYMBOL(ath9k_hw_settsf64);
2457
2458 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2459 {
2460 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2461 AH_TSF_WRITE_TIMEOUT))
2462 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2463 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2464
2465 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2466 }
2467 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2468
2469 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2470 {
2471 if (setting)
2472 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2473 else
2474 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2475 }
2476 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2477
2478 /*
2479 * Extend 15-bit time stamp from rx descriptor to
2480 * a full 64-bit TSF using the current h/w TSF.
2481 */
2482 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2483 {
2484 u64 tsf;
2485
2486 tsf = ath9k_hw_gettsf64(ah);
2487 if ((tsf & 0x7fff) < rstamp)
2488 tsf -= 0x8000;
2489 return (tsf & ~0x7fff) | rstamp;
2490 }
2491 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2492
2493 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2494 {
2495 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2496 u32 macmode;
2497
2498 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2499 macmode = AR_2040_JOINED_RX_CLEAR;
2500 else
2501 macmode = 0;
2502
2503 REG_WRITE(ah, AR_2040_MODE, macmode);
2504 }
2505
2506 /* HW Generic timers configuration */
2507
2508 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2509 {
2510 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2511 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2512 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2513 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2514 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2515 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2516 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2517 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2518 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2519 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2520 AR_NDP2_TIMER_MODE, 0x0002},
2521 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2522 AR_NDP2_TIMER_MODE, 0x0004},
2523 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2524 AR_NDP2_TIMER_MODE, 0x0008},
2525 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2526 AR_NDP2_TIMER_MODE, 0x0010},
2527 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2528 AR_NDP2_TIMER_MODE, 0x0020},
2529 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2530 AR_NDP2_TIMER_MODE, 0x0040},
2531 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2532 AR_NDP2_TIMER_MODE, 0x0080}
2533 };
2534
2535 /* HW generic timer primitives */
2536
2537 /* compute and clear index of rightmost 1 */
2538 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2539 {
2540 u32 b;
2541
2542 b = *mask;
2543 b &= (0-b);
2544 *mask &= ~b;
2545 b *= debruijn32;
2546 b >>= 27;
2547
2548 return timer_table->gen_timer_index[b];
2549 }
2550
2551 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2552 {
2553 return REG_READ(ah, AR_TSF_L32);
2554 }
2555 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2556
2557 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2558 void (*trigger)(void *),
2559 void (*overflow)(void *),
2560 void *arg,
2561 u8 timer_index)
2562 {
2563 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2564 struct ath_gen_timer *timer;
2565
2566 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2567
2568 if (timer == NULL) {
2569 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2570 "Failed to allocate memory"
2571 "for hw timer[%d]\n", timer_index);
2572 return NULL;
2573 }
2574
2575 /* allocate a hardware generic timer slot */
2576 timer_table->timers[timer_index] = timer;
2577 timer->index = timer_index;
2578 timer->trigger = trigger;
2579 timer->overflow = overflow;
2580 timer->arg = arg;
2581
2582 return timer;
2583 }
2584 EXPORT_SYMBOL(ath_gen_timer_alloc);
2585
2586 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2587 struct ath_gen_timer *timer,
2588 u32 timer_next,
2589 u32 timer_period)
2590 {
2591 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2592 u32 tsf;
2593
2594 BUG_ON(!timer_period);
2595
2596 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2597
2598 tsf = ath9k_hw_gettsf32(ah);
2599
2600 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2601 "curent tsf %x period %x"
2602 "timer_next %x\n", tsf, timer_period, timer_next);
2603
2604 /*
2605 * Pull timer_next forward if the current TSF already passed it
2606 * because of software latency
2607 */
2608 if (timer_next < tsf)
2609 timer_next = tsf + timer_period;
2610
2611 /*
2612 * Program generic timer registers
2613 */
2614 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2615 timer_next);
2616 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2617 timer_period);
2618 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2619 gen_tmr_configuration[timer->index].mode_mask);
2620
2621 /* Enable both trigger and thresh interrupt masks */
2622 REG_SET_BIT(ah, AR_IMR_S5,
2623 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2624 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2625 }
2626 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2627
2628 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2629 {
2630 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2631
2632 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2633 (timer->index >= ATH_MAX_GEN_TIMER)) {
2634 return;
2635 }
2636
2637 /* Clear generic timer enable bits. */
2638 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2639 gen_tmr_configuration[timer->index].mode_mask);
2640
2641 /* Disable both trigger and thresh interrupt masks */
2642 REG_CLR_BIT(ah, AR_IMR_S5,
2643 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2644 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2645
2646 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2647 }
2648 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2649
2650 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2651 {
2652 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2653
2654 /* free the hardware generic timer slot */
2655 timer_table->timers[timer->index] = NULL;
2656 kfree(timer);
2657 }
2658 EXPORT_SYMBOL(ath_gen_timer_free);
2659
2660 /*
2661 * Generic Timer Interrupts handling
2662 */
2663 void ath_gen_timer_isr(struct ath_hw *ah)
2664 {
2665 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2666 struct ath_gen_timer *timer;
2667 struct ath_common *common = ath9k_hw_common(ah);
2668 u32 trigger_mask, thresh_mask, index;
2669
2670 /* get hardware generic timer interrupt status */
2671 trigger_mask = ah->intr_gen_timer_trigger;
2672 thresh_mask = ah->intr_gen_timer_thresh;
2673 trigger_mask &= timer_table->timer_mask.val;
2674 thresh_mask &= timer_table->timer_mask.val;
2675
2676 trigger_mask &= ~thresh_mask;
2677
2678 while (thresh_mask) {
2679 index = rightmost_index(timer_table, &thresh_mask);
2680 timer = timer_table->timers[index];
2681 BUG_ON(!timer);
2682 ath_print(common, ATH_DBG_HWTIMER,
2683 "TSF overflow for Gen timer %d\n", index);
2684 timer->overflow(timer->arg);
2685 }
2686
2687 while (trigger_mask) {
2688 index = rightmost_index(timer_table, &trigger_mask);
2689 timer = timer_table->timers[index];
2690 BUG_ON(!timer);
2691 ath_print(common, ATH_DBG_HWTIMER,
2692 "Gen timer[%d] trigger\n", index);
2693 timer->trigger(timer->arg);
2694 }
2695 }
2696 EXPORT_SYMBOL(ath_gen_timer_isr);
2697
2698 /********/
2699 /* HTC */
2700 /********/
2701
2702 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2703 {
2704 ah->htc_reset_init = true;
2705 }
2706 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2707
2708 static struct {
2709 u32 version;
2710 const char * name;
2711 } ath_mac_bb_names[] = {
2712 /* Devices with external radios */
2713 { AR_SREV_VERSION_5416_PCI, "5416" },
2714 { AR_SREV_VERSION_5416_PCIE, "5418" },
2715 { AR_SREV_VERSION_9100, "9100" },
2716 { AR_SREV_VERSION_9160, "9160" },
2717 /* Single-chip solutions */
2718 { AR_SREV_VERSION_9280, "9280" },
2719 { AR_SREV_VERSION_9285, "9285" },
2720 { AR_SREV_VERSION_9287, "9287" },
2721 { AR_SREV_VERSION_9271, "9271" },
2722 };
2723
2724 /* For devices with external radios */
2725 static struct {
2726 u16 version;
2727 const char * name;
2728 } ath_rf_names[] = {
2729 { 0, "5133" },
2730 { AR_RAD5133_SREV_MAJOR, "5133" },
2731 { AR_RAD5122_SREV_MAJOR, "5122" },
2732 { AR_RAD2133_SREV_MAJOR, "2133" },
2733 { AR_RAD2122_SREV_MAJOR, "2122" }
2734 };
2735
2736 /*
2737 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2738 */
2739 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2740 {
2741 int i;
2742
2743 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2744 if (ath_mac_bb_names[i].version == mac_bb_version) {
2745 return ath_mac_bb_names[i].name;
2746 }
2747 }
2748
2749 return "????";
2750 }
2751
2752 /*
2753 * Return the RF name. "????" is returned if the RF is unknown.
2754 * Used for devices with external radios.
2755 */
2756 static const char *ath9k_hw_rf_name(u16 rf_version)
2757 {
2758 int i;
2759
2760 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2761 if (ath_rf_names[i].version == rf_version) {
2762 return ath_rf_names[i].name;
2763 }
2764 }
2765
2766 return "????";
2767 }
2768
2769 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2770 {
2771 int used;
2772
2773 /* chipsets >= AR9280 are single-chip */
2774 if (AR_SREV_9280_10_OR_LATER(ah)) {
2775 used = snprintf(hw_name, len,
2776 "Atheros AR%s Rev:%x",
2777 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2778 ah->hw_version.macRev);
2779 }
2780 else {
2781 used = snprintf(hw_name, len,
2782 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2783 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2784 ah->hw_version.macRev,
2785 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2786 AR_RADIO_SREV_MAJOR)),
2787 ah->hw_version.phyRev);
2788 }
2789
2790 hw_name[used] = '\0';
2791 }
2792 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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