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ath9k: Updates for AR9287_12 version of chipset.
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 /*
88 * Read and write, they both share the same lock. We do this to serialize
89 * reads and writes on Atheros 802.11n PCI devices only. This is required
90 * as the FIFO on these devices can only accept sanely 2 requests. After
91 * that the device goes bananas. Serializing the reads/writes prevents this
92 * from happening.
93 */
94
95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
96 {
97 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
98 unsigned long flags;
99 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
102 } else
103 iowrite32(val, ah->ah_sc->mem + reg_offset);
104 }
105
106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
107 {
108 u32 val;
109 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
110 unsigned long flags;
111 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
114 } else
115 val = ioread32(ah->ah_sc->mem + reg_offset);
116 return val;
117 }
118
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
120 {
121 int i;
122
123 BUG_ON(timeout < AH_TIME_QUANTUM);
124
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126 if ((REG_READ(ah, reg) & mask) == val)
127 return true;
128
129 udelay(AH_TIME_QUANTUM);
130 }
131
132 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
135
136 return false;
137 }
138
139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
140 {
141 u32 retval;
142 int i;
143
144 for (i = 0, retval = 0; i < n; i++) {
145 retval = (retval << 1) | (val & 1);
146 val >>= 1;
147 }
148 return retval;
149 }
150
151 bool ath9k_get_channel_edges(struct ath_hw *ah,
152 u16 flags, u16 *low,
153 u16 *high)
154 {
155 struct ath9k_hw_capabilities *pCap = &ah->caps;
156
157 if (flags & CHANNEL_5GHZ) {
158 *low = pCap->low_5ghz_chan;
159 *high = pCap->high_5ghz_chan;
160 return true;
161 }
162 if ((flags & CHANNEL_2GHZ)) {
163 *low = pCap->low_2ghz_chan;
164 *high = pCap->high_2ghz_chan;
165 return true;
166 }
167 return false;
168 }
169
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 const struct ath_rate_table *rates,
172 u32 frameLen, u16 rateix,
173 bool shortPreamble)
174 {
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
176 u32 kbps;
177
178 kbps = rates->info[rateix].ratekbps;
179
180 if (kbps == 0)
181 return 0;
182
183 switch (rates->info[rateix].phy) {
184 case WLAN_RC_PHY_CCK:
185 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186 if (shortPreamble && rates->info[rateix].short_preamble)
187 phyTime >>= 1;
188 numBits = frameLen << 3;
189 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
190 break;
191 case WLAN_RC_PHY_OFDM:
192 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
193 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
194 numBits = OFDM_PLCP_BITS + (frameLen << 3);
195 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196 txTime = OFDM_SIFS_TIME_QUARTER
197 + OFDM_PREAMBLE_TIME_QUARTER
198 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
199 } else if (ah->curchan &&
200 IS_CHAN_HALF_RATE(ah->curchan)) {
201 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
202 numBits = OFDM_PLCP_BITS + (frameLen << 3);
203 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204 txTime = OFDM_SIFS_TIME_HALF +
205 OFDM_PREAMBLE_TIME_HALF
206 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
207 } else {
208 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
209 numBits = OFDM_PLCP_BITS + (frameLen << 3);
210 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
212 + (numSymbols * OFDM_SYMBOL_TIME);
213 }
214 break;
215 default:
216 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
217 "Unknown phy %u (rate ix %u)\n",
218 rates->info[rateix].phy, rateix);
219 txTime = 0;
220 break;
221 }
222
223 return txTime;
224 }
225
226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
227 struct ath9k_channel *chan,
228 struct chan_centers *centers)
229 {
230 int8_t extoff;
231
232 if (!IS_CHAN_HT40(chan)) {
233 centers->ctl_center = centers->ext_center =
234 centers->synth_center = chan->channel;
235 return;
236 }
237
238 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
239 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
240 centers->synth_center =
241 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
242 extoff = 1;
243 } else {
244 centers->synth_center =
245 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
246 extoff = -1;
247 }
248
249 centers->ctl_center =
250 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 centers->ext_center =
252 centers->synth_center + (extoff *
253 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
254 HT40_CHANNEL_CENTER_SHIFT : 15));
255 }
256
257 /******************/
258 /* Chip Revisions */
259 /******************/
260
261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
262 {
263 u32 val;
264
265 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
266
267 if (val == 0xFF) {
268 val = REG_READ(ah, AR_SREV);
269 ah->hw_version.macVersion =
270 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
273 } else {
274 if (!AR_SREV_9100(ah))
275 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
276
277 ah->hw_version.macRev = val & AR_SREV_REVISION;
278
279 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
280 ah->is_pciexpress = true;
281 }
282 }
283
284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
285 {
286 u32 val;
287 int i;
288
289 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
290
291 for (i = 0; i < 8; i++)
292 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
293 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
294 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
295
296 return ath9k_hw_reverse_bits(val, 8);
297 }
298
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
302
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
304 {
305 if (AR_SREV_9100(ah))
306 return;
307
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319 }
320
321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
322 {
323 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
324 u32 regHold[2];
325 u32 patternData[4] = { 0x55555555,
326 0xaaaaaaaa,
327 0x66666666,
328 0x99999999 };
329 int i, j;
330
331 for (i = 0; i < 2; i++) {
332 u32 addr = regAddr[i];
333 u32 wrData, rdData;
334
335 regHold[i] = REG_READ(ah, addr);
336 for (j = 0; j < 0x100; j++) {
337 wrData = (j << 16) | j;
338 REG_WRITE(ah, addr, wrData);
339 rdData = REG_READ(ah, addr);
340 if (rdData != wrData) {
341 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
342 "address test failed "
343 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
344 addr, wrData, rdData);
345 return false;
346 }
347 }
348 for (j = 0; j < 4; j++) {
349 wrData = patternData[j];
350 REG_WRITE(ah, addr, wrData);
351 rdData = REG_READ(ah, addr);
352 if (wrData != rdData) {
353 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
354 "address test failed "
355 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
356 addr, wrData, rdData);
357 return false;
358 }
359 }
360 REG_WRITE(ah, regAddr[i], regHold[i]);
361 }
362 udelay(100);
363
364 return true;
365 }
366
367 static const char *ath9k_hw_devname(u16 devid)
368 {
369 switch (devid) {
370 case AR5416_DEVID_PCI:
371 return "Atheros 5416";
372 case AR5416_DEVID_PCIE:
373 return "Atheros 5418";
374 case AR9160_DEVID_PCI:
375 return "Atheros 9160";
376 case AR5416_AR9100_DEVID:
377 return "Atheros 9100";
378 case AR9280_DEVID_PCI:
379 case AR9280_DEVID_PCIE:
380 return "Atheros 9280";
381 case AR9285_DEVID_PCIE:
382 return "Atheros 9285";
383 case AR5416_DEVID_AR9287_PCI:
384 case AR5416_DEVID_AR9287_PCIE:
385 return "Atheros 9287";
386 }
387
388 return NULL;
389 }
390
391 static void ath9k_hw_init_config(struct ath_hw *ah)
392 {
393 int i;
394
395 ah->config.dma_beacon_response_time = 2;
396 ah->config.sw_beacon_response_time = 10;
397 ah->config.additional_swba_backoff = 0;
398 ah->config.ack_6mb = 0x0;
399 ah->config.cwm_ignore_extcca = 0;
400 ah->config.pcie_powersave_enable = 0;
401 ah->config.pcie_clock_req = 0;
402 ah->config.pcie_waen = 0;
403 ah->config.analog_shiftreg = 1;
404 ah->config.ht_enable = 1;
405 ah->config.ofdm_trig_low = 200;
406 ah->config.ofdm_trig_high = 500;
407 ah->config.cck_trig_high = 200;
408 ah->config.cck_trig_low = 100;
409 ah->config.enable_ani = 1;
410 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
411 ah->config.antenna_switch_swap = 0;
412
413 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
414 ah->config.spurchans[i][0] = AR_NO_SPUR;
415 ah->config.spurchans[i][1] = AR_NO_SPUR;
416 }
417
418 ah->config.intr_mitigation = true;
419
420 /*
421 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
422 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
423 * This means we use it for all AR5416 devices, and the few
424 * minor PCI AR9280 devices out there.
425 *
426 * Serialization is required because these devices do not handle
427 * well the case of two concurrent reads/writes due to the latency
428 * involved. During one read/write another read/write can be issued
429 * on another CPU while the previous read/write may still be working
430 * on our hardware, if we hit this case the hardware poops in a loop.
431 * We prevent this by serializing reads and writes.
432 *
433 * This issue is not present on PCI-Express devices or pre-AR5416
434 * devices (legacy, 802.11abg).
435 */
436 if (num_possible_cpus() > 1)
437 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
438 }
439
440 static void ath9k_hw_init_defaults(struct ath_hw *ah)
441 {
442 ah->hw_version.magic = AR5416_MAGIC;
443 ah->regulatory.country_code = CTRY_DEFAULT;
444 ah->hw_version.subvendorid = 0;
445
446 ah->ah_flags = 0;
447 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
448 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
449 if (!AR_SREV_9100(ah))
450 ah->ah_flags = AH_USE_EEPROM;
451
452 ah->regulatory.power_limit = MAX_RATE_POWER;
453 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
454 ah->atim_window = 0;
455 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
456 ah->beacon_interval = 100;
457 ah->enable_32kHz_clock = DONT_USE_32KHZ;
458 ah->slottime = (u32) -1;
459 ah->acktimeout = (u32) -1;
460 ah->ctstimeout = (u32) -1;
461 ah->globaltxtimeout = (u32) -1;
462
463 ah->gbeacon_rate = 0;
464
465 ah->power_mode = ATH9K_PM_UNDEFINED;
466 }
467
468 static int ath9k_hw_rfattach(struct ath_hw *ah)
469 {
470 bool rfStatus = false;
471 int ecode = 0;
472
473 rfStatus = ath9k_hw_init_rf(ah, &ecode);
474 if (!rfStatus) {
475 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
476 "RF setup failed, status: %u\n", ecode);
477 return ecode;
478 }
479
480 return 0;
481 }
482
483 static int ath9k_hw_rf_claim(struct ath_hw *ah)
484 {
485 u32 val;
486
487 REG_WRITE(ah, AR_PHY(0), 0x00000007);
488
489 val = ath9k_hw_get_radiorev(ah);
490 switch (val & AR_RADIO_SREV_MAJOR) {
491 case 0:
492 val = AR_RAD5133_SREV_MAJOR;
493 break;
494 case AR_RAD5133_SREV_MAJOR:
495 case AR_RAD5122_SREV_MAJOR:
496 case AR_RAD2133_SREV_MAJOR:
497 case AR_RAD2122_SREV_MAJOR:
498 break;
499 default:
500 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
501 "Radio Chip Rev 0x%02X not supported\n",
502 val & AR_RADIO_SREV_MAJOR);
503 return -EOPNOTSUPP;
504 }
505
506 ah->hw_version.analog5GhzRev = val;
507
508 return 0;
509 }
510
511 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
512 {
513 u32 sum;
514 int i;
515 u16 eeval;
516
517 sum = 0;
518 for (i = 0; i < 3; i++) {
519 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
520 sum += eeval;
521 ah->macaddr[2 * i] = eeval >> 8;
522 ah->macaddr[2 * i + 1] = eeval & 0xff;
523 }
524 if (sum == 0 || sum == 0xffff * 3)
525 return -EADDRNOTAVAIL;
526
527 return 0;
528 }
529
530 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
531 {
532 u32 rxgain_type;
533
534 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
535 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
536
537 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
538 INIT_INI_ARRAY(&ah->iniModesRxGain,
539 ar9280Modes_backoff_13db_rxgain_9280_2,
540 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
541 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
542 INIT_INI_ARRAY(&ah->iniModesRxGain,
543 ar9280Modes_backoff_23db_rxgain_9280_2,
544 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
545 else
546 INIT_INI_ARRAY(&ah->iniModesRxGain,
547 ar9280Modes_original_rxgain_9280_2,
548 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
549 } else {
550 INIT_INI_ARRAY(&ah->iniModesRxGain,
551 ar9280Modes_original_rxgain_9280_2,
552 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
553 }
554 }
555
556 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
557 {
558 u32 txgain_type;
559
560 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
561 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
562
563 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
564 INIT_INI_ARRAY(&ah->iniModesTxGain,
565 ar9280Modes_high_power_tx_gain_9280_2,
566 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
567 else
568 INIT_INI_ARRAY(&ah->iniModesTxGain,
569 ar9280Modes_original_tx_gain_9280_2,
570 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
571 } else {
572 INIT_INI_ARRAY(&ah->iniModesTxGain,
573 ar9280Modes_original_tx_gain_9280_2,
574 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
575 }
576 }
577
578 static int ath9k_hw_post_init(struct ath_hw *ah)
579 {
580 int ecode;
581
582 if (!ath9k_hw_chip_test(ah))
583 return -ENODEV;
584
585 ecode = ath9k_hw_rf_claim(ah);
586 if (ecode != 0)
587 return ecode;
588
589 ecode = ath9k_hw_eeprom_init(ah);
590 if (ecode != 0)
591 return ecode;
592
593 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
594 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
595
596 ecode = ath9k_hw_rfattach(ah);
597 if (ecode != 0)
598 return ecode;
599
600 if (!AR_SREV_9100(ah)) {
601 ath9k_hw_ani_setup(ah);
602 ath9k_hw_ani_init(ah);
603 }
604
605 return 0;
606 }
607
608 static bool ath9k_hw_devid_supported(u16 devid)
609 {
610 switch (devid) {
611 case AR5416_DEVID_PCI:
612 case AR5416_DEVID_PCIE:
613 case AR5416_AR9100_DEVID:
614 case AR9160_DEVID_PCI:
615 case AR9280_DEVID_PCI:
616 case AR9280_DEVID_PCIE:
617 case AR9285_DEVID_PCIE:
618 case AR5416_DEVID_AR9287_PCI:
619 case AR5416_DEVID_AR9287_PCIE:
620 return true;
621 default:
622 break;
623 }
624 return false;
625 }
626
627 static bool ath9k_hw_macversion_supported(u32 macversion)
628 {
629 switch (macversion) {
630 case AR_SREV_VERSION_5416_PCI:
631 case AR_SREV_VERSION_5416_PCIE:
632 case AR_SREV_VERSION_9160:
633 case AR_SREV_VERSION_9100:
634 case AR_SREV_VERSION_9280:
635 case AR_SREV_VERSION_9285:
636 case AR_SREV_VERSION_9287:
637 return true;
638 /* Not yet */
639 case AR_SREV_VERSION_9271:
640 default:
641 break;
642 }
643 return false;
644 }
645
646 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
647 {
648 if (AR_SREV_9160_10_OR_LATER(ah)) {
649 if (AR_SREV_9280_10_OR_LATER(ah)) {
650 ah->iq_caldata.calData = &iq_cal_single_sample;
651 ah->adcgain_caldata.calData =
652 &adc_gain_cal_single_sample;
653 ah->adcdc_caldata.calData =
654 &adc_dc_cal_single_sample;
655 ah->adcdc_calinitdata.calData =
656 &adc_init_dc_cal;
657 } else {
658 ah->iq_caldata.calData = &iq_cal_multi_sample;
659 ah->adcgain_caldata.calData =
660 &adc_gain_cal_multi_sample;
661 ah->adcdc_caldata.calData =
662 &adc_dc_cal_multi_sample;
663 ah->adcdc_calinitdata.calData =
664 &adc_init_dc_cal;
665 }
666 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
667 }
668 }
669
670 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
671 {
672 if (AR_SREV_9271(ah)) {
673 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
674 ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
675 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
676 ARRAY_SIZE(ar9271Common_9271_1_0), 2);
677 return;
678 }
679
680 if (AR_SREV_9287_11_OR_LATER(ah)) {
681 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
682 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
683 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
684 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
685 if (ah->config.pcie_clock_req)
686 INIT_INI_ARRAY(&ah->iniPcieSerdes,
687 ar9287PciePhy_clkreq_off_L1_9287_1_1,
688 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
689 else
690 INIT_INI_ARRAY(&ah->iniPcieSerdes,
691 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
692 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
693 2);
694 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
695 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
696 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
697 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
698 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
699
700 if (ah->config.pcie_clock_req)
701 INIT_INI_ARRAY(&ah->iniPcieSerdes,
702 ar9287PciePhy_clkreq_off_L1_9287_1_0,
703 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
704 else
705 INIT_INI_ARRAY(&ah->iniPcieSerdes,
706 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
707 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
708 2);
709 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
710
711
712 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
713 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
714 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
715 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
716
717 if (ah->config.pcie_clock_req) {
718 INIT_INI_ARRAY(&ah->iniPcieSerdes,
719 ar9285PciePhy_clkreq_off_L1_9285_1_2,
720 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
721 } else {
722 INIT_INI_ARRAY(&ah->iniPcieSerdes,
723 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
724 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
725 2);
726 }
727 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
728 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
729 ARRAY_SIZE(ar9285Modes_9285), 6);
730 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
731 ARRAY_SIZE(ar9285Common_9285), 2);
732
733 if (ah->config.pcie_clock_req) {
734 INIT_INI_ARRAY(&ah->iniPcieSerdes,
735 ar9285PciePhy_clkreq_off_L1_9285,
736 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
737 } else {
738 INIT_INI_ARRAY(&ah->iniPcieSerdes,
739 ar9285PciePhy_clkreq_always_on_L1_9285,
740 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
741 }
742 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
743 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
744 ARRAY_SIZE(ar9280Modes_9280_2), 6);
745 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
746 ARRAY_SIZE(ar9280Common_9280_2), 2);
747
748 if (ah->config.pcie_clock_req) {
749 INIT_INI_ARRAY(&ah->iniPcieSerdes,
750 ar9280PciePhy_clkreq_off_L1_9280,
751 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
752 } else {
753 INIT_INI_ARRAY(&ah->iniPcieSerdes,
754 ar9280PciePhy_clkreq_always_on_L1_9280,
755 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
756 }
757 INIT_INI_ARRAY(&ah->iniModesAdditional,
758 ar9280Modes_fast_clock_9280_2,
759 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
760 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
761 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
762 ARRAY_SIZE(ar9280Modes_9280), 6);
763 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
764 ARRAY_SIZE(ar9280Common_9280), 2);
765 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
766 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
767 ARRAY_SIZE(ar5416Modes_9160), 6);
768 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
769 ARRAY_SIZE(ar5416Common_9160), 2);
770 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
771 ARRAY_SIZE(ar5416Bank0_9160), 2);
772 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
773 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
774 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
775 ARRAY_SIZE(ar5416Bank1_9160), 2);
776 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
777 ARRAY_SIZE(ar5416Bank2_9160), 2);
778 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
779 ARRAY_SIZE(ar5416Bank3_9160), 3);
780 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
781 ARRAY_SIZE(ar5416Bank6_9160), 3);
782 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
783 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
784 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
785 ARRAY_SIZE(ar5416Bank7_9160), 2);
786 if (AR_SREV_9160_11(ah)) {
787 INIT_INI_ARRAY(&ah->iniAddac,
788 ar5416Addac_91601_1,
789 ARRAY_SIZE(ar5416Addac_91601_1), 2);
790 } else {
791 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
792 ARRAY_SIZE(ar5416Addac_9160), 2);
793 }
794 } else if (AR_SREV_9100_OR_LATER(ah)) {
795 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
796 ARRAY_SIZE(ar5416Modes_9100), 6);
797 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
798 ARRAY_SIZE(ar5416Common_9100), 2);
799 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
800 ARRAY_SIZE(ar5416Bank0_9100), 2);
801 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
802 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
803 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
804 ARRAY_SIZE(ar5416Bank1_9100), 2);
805 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
806 ARRAY_SIZE(ar5416Bank2_9100), 2);
807 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
808 ARRAY_SIZE(ar5416Bank3_9100), 3);
809 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
810 ARRAY_SIZE(ar5416Bank6_9100), 3);
811 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
812 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
813 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
814 ARRAY_SIZE(ar5416Bank7_9100), 2);
815 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
816 ARRAY_SIZE(ar5416Addac_9100), 2);
817 } else {
818 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
819 ARRAY_SIZE(ar5416Modes), 6);
820 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
821 ARRAY_SIZE(ar5416Common), 2);
822 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
823 ARRAY_SIZE(ar5416Bank0), 2);
824 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
825 ARRAY_SIZE(ar5416BB_RfGain), 3);
826 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
827 ARRAY_SIZE(ar5416Bank1), 2);
828 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
829 ARRAY_SIZE(ar5416Bank2), 2);
830 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
831 ARRAY_SIZE(ar5416Bank3), 3);
832 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
833 ARRAY_SIZE(ar5416Bank6), 3);
834 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
835 ARRAY_SIZE(ar5416Bank6TPC), 3);
836 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
837 ARRAY_SIZE(ar5416Bank7), 2);
838 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
839 ARRAY_SIZE(ar5416Addac), 2);
840 }
841 }
842
843 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
844 {
845 if (AR_SREV_9287_11(ah))
846 INIT_INI_ARRAY(&ah->iniModesRxGain,
847 ar9287Modes_rx_gain_9287_1_1,
848 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
849 else if (AR_SREV_9287_10(ah))
850 INIT_INI_ARRAY(&ah->iniModesRxGain,
851 ar9287Modes_rx_gain_9287_1_0,
852 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
853 else if (AR_SREV_9280_20(ah))
854 ath9k_hw_init_rxgain_ini(ah);
855
856 if (AR_SREV_9287_11(ah)) {
857 INIT_INI_ARRAY(&ah->iniModesTxGain,
858 ar9287Modes_tx_gain_9287_1_1,
859 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
860 } else if (AR_SREV_9287_10(ah)) {
861 INIT_INI_ARRAY(&ah->iniModesTxGain,
862 ar9287Modes_tx_gain_9287_1_0,
863 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
864 } else if (AR_SREV_9280_20(ah)) {
865 ath9k_hw_init_txgain_ini(ah);
866 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
867 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
868
869 /* txgain table */
870 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
871 INIT_INI_ARRAY(&ah->iniModesTxGain,
872 ar9285Modes_high_power_tx_gain_9285_1_2,
873 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
874 } else {
875 INIT_INI_ARRAY(&ah->iniModesTxGain,
876 ar9285Modes_original_tx_gain_9285_1_2,
877 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
878 }
879
880 }
881 }
882
883 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
884 {
885 u32 i, j;
886
887 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
888 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
889
890 /* EEPROM Fixup */
891 for (i = 0; i < ah->iniModes.ia_rows; i++) {
892 u32 reg = INI_RA(&ah->iniModes, i, 0);
893
894 for (j = 1; j < ah->iniModes.ia_columns; j++) {
895 u32 val = INI_RA(&ah->iniModes, i, j);
896
897 INI_RA(&ah->iniModes, i, j) =
898 ath9k_hw_ini_fixup(ah,
899 &ah->eeprom.def,
900 reg, val);
901 }
902 }
903 }
904 }
905
906 int ath9k_hw_init(struct ath_hw *ah)
907 {
908 int r = 0;
909
910 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
911 return -EOPNOTSUPP;
912
913 ath9k_hw_init_defaults(ah);
914 ath9k_hw_init_config(ah);
915
916 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
917 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
918 return -EIO;
919 }
920
921 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
922 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
923 return -EIO;
924 }
925
926 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
927 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
928 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
929 ah->config.serialize_regmode =
930 SER_REG_MODE_ON;
931 } else {
932 ah->config.serialize_regmode =
933 SER_REG_MODE_OFF;
934 }
935 }
936
937 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
938 ah->config.serialize_regmode);
939
940 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
941 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
942 "Mac Chip Rev 0x%02x.%x is not supported by "
943 "this driver\n", ah->hw_version.macVersion,
944 ah->hw_version.macRev);
945 return -EOPNOTSUPP;
946 }
947
948 if (AR_SREV_9100(ah)) {
949 ah->iq_caldata.calData = &iq_cal_multi_sample;
950 ah->supp_cals = IQ_MISMATCH_CAL;
951 ah->is_pciexpress = false;
952 }
953
954 if (AR_SREV_9271(ah))
955 ah->is_pciexpress = false;
956
957 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
958
959 ath9k_hw_init_cal_settings(ah);
960
961 ah->ani_function = ATH9K_ANI_ALL;
962 if (AR_SREV_9280_10_OR_LATER(ah))
963 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
964
965 ath9k_hw_init_mode_regs(ah);
966
967 if (ah->is_pciexpress)
968 ath9k_hw_configpcipowersave(ah, 0);
969 else
970 ath9k_hw_disablepcie(ah);
971
972 r = ath9k_hw_post_init(ah);
973 if (r)
974 return r;
975
976 ath9k_hw_init_mode_gain_regs(ah);
977 ath9k_hw_fill_cap_info(ah);
978 ath9k_hw_init_11a_eeprom_fix(ah);
979
980 r = ath9k_hw_init_macaddr(ah);
981 if (r) {
982 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
983 "Failed to initialize MAC address\n");
984 return r;
985 }
986
987 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
988 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
989 else
990 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
991
992 ath9k_init_nfcal_hist_buffer(ah);
993
994 return 0;
995 }
996
997 static void ath9k_hw_init_bb(struct ath_hw *ah,
998 struct ath9k_channel *chan)
999 {
1000 u32 synthDelay;
1001
1002 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1003 if (IS_CHAN_B(chan))
1004 synthDelay = (4 * synthDelay) / 22;
1005 else
1006 synthDelay /= 10;
1007
1008 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1009
1010 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1011 }
1012
1013 static void ath9k_hw_init_qos(struct ath_hw *ah)
1014 {
1015 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1016 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1017
1018 REG_WRITE(ah, AR_QOS_NO_ACK,
1019 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1020 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1021 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1022
1023 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1024 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1025 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1026 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1027 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1028 }
1029
1030 static void ath9k_hw_init_pll(struct ath_hw *ah,
1031 struct ath9k_channel *chan)
1032 {
1033 u32 pll;
1034
1035 if (AR_SREV_9100(ah)) {
1036 if (chan && IS_CHAN_5GHZ(chan))
1037 pll = 0x1450;
1038 else
1039 pll = 0x1458;
1040 } else {
1041 if (AR_SREV_9280_10_OR_LATER(ah)) {
1042 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1043
1044 if (chan && IS_CHAN_HALF_RATE(chan))
1045 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1046 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1047 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1048
1049 if (chan && IS_CHAN_5GHZ(chan)) {
1050 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1051
1052
1053 if (AR_SREV_9280_20(ah)) {
1054 if (((chan->channel % 20) == 0)
1055 || ((chan->channel % 10) == 0))
1056 pll = 0x2850;
1057 else
1058 pll = 0x142c;
1059 }
1060 } else {
1061 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1062 }
1063
1064 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1065
1066 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1067
1068 if (chan && IS_CHAN_HALF_RATE(chan))
1069 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1070 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1071 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1072
1073 if (chan && IS_CHAN_5GHZ(chan))
1074 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1075 else
1076 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1077 } else {
1078 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1079
1080 if (chan && IS_CHAN_HALF_RATE(chan))
1081 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1082 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1083 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1084
1085 if (chan && IS_CHAN_5GHZ(chan))
1086 pll |= SM(0xa, AR_RTC_PLL_DIV);
1087 else
1088 pll |= SM(0xb, AR_RTC_PLL_DIV);
1089 }
1090 }
1091 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1092
1093 udelay(RTC_PLL_SETTLE_DELAY);
1094
1095 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1096 }
1097
1098 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1099 {
1100 int rx_chainmask, tx_chainmask;
1101
1102 rx_chainmask = ah->rxchainmask;
1103 tx_chainmask = ah->txchainmask;
1104
1105 switch (rx_chainmask) {
1106 case 0x5:
1107 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1108 AR_PHY_SWAP_ALT_CHAIN);
1109 case 0x3:
1110 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1111 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1112 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1113 break;
1114 }
1115 case 0x1:
1116 case 0x2:
1117 case 0x7:
1118 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1119 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1120 break;
1121 default:
1122 break;
1123 }
1124
1125 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1126 if (tx_chainmask == 0x5) {
1127 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1128 AR_PHY_SWAP_ALT_CHAIN);
1129 }
1130 if (AR_SREV_9100(ah))
1131 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1132 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1133 }
1134
1135 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1136 enum nl80211_iftype opmode)
1137 {
1138 ah->mask_reg = AR_IMR_TXERR |
1139 AR_IMR_TXURN |
1140 AR_IMR_RXERR |
1141 AR_IMR_RXORN |
1142 AR_IMR_BCNMISC;
1143
1144 if (ah->config.intr_mitigation)
1145 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1146 else
1147 ah->mask_reg |= AR_IMR_RXOK;
1148
1149 ah->mask_reg |= AR_IMR_TXOK;
1150
1151 if (opmode == NL80211_IFTYPE_AP)
1152 ah->mask_reg |= AR_IMR_MIB;
1153
1154 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1155 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1156
1157 if (!AR_SREV_9100(ah)) {
1158 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1159 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1160 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1161 }
1162 }
1163
1164 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1165 {
1166 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1167 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1168 ah->acktimeout = (u32) -1;
1169 return false;
1170 } else {
1171 REG_RMW_FIELD(ah, AR_TIME_OUT,
1172 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1173 ah->acktimeout = us;
1174 return true;
1175 }
1176 }
1177
1178 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1179 {
1180 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1181 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1182 ah->ctstimeout = (u32) -1;
1183 return false;
1184 } else {
1185 REG_RMW_FIELD(ah, AR_TIME_OUT,
1186 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1187 ah->ctstimeout = us;
1188 return true;
1189 }
1190 }
1191
1192 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1193 {
1194 if (tu > 0xFFFF) {
1195 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1196 "bad global tx timeout %u\n", tu);
1197 ah->globaltxtimeout = (u32) -1;
1198 return false;
1199 } else {
1200 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1201 ah->globaltxtimeout = tu;
1202 return true;
1203 }
1204 }
1205
1206 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1207 {
1208 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1209 ah->misc_mode);
1210
1211 if (ah->misc_mode != 0)
1212 REG_WRITE(ah, AR_PCU_MISC,
1213 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1214 if (ah->slottime != (u32) -1)
1215 ath9k_hw_setslottime(ah, ah->slottime);
1216 if (ah->acktimeout != (u32) -1)
1217 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1218 if (ah->ctstimeout != (u32) -1)
1219 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1220 if (ah->globaltxtimeout != (u32) -1)
1221 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1222 }
1223
1224 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1225 {
1226 return vendorid == ATHEROS_VENDOR_ID ?
1227 ath9k_hw_devname(devid) : NULL;
1228 }
1229
1230 void ath9k_hw_detach(struct ath_hw *ah)
1231 {
1232 if (!AR_SREV_9100(ah))
1233 ath9k_hw_ani_disable(ah);
1234
1235 ath9k_hw_rf_free(ah);
1236 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1237 kfree(ah);
1238 ah = NULL;
1239 }
1240
1241 /*******/
1242 /* INI */
1243 /*******/
1244
1245 static void ath9k_hw_override_ini(struct ath_hw *ah,
1246 struct ath9k_channel *chan)
1247 {
1248 u32 val;
1249
1250 if (AR_SREV_9271(ah)) {
1251 /*
1252 * Enable spectral scan to solution for issues with stuck
1253 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1254 * AR9271 1.1
1255 */
1256 if (AR_SREV_9271_10(ah)) {
1257 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1258 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1259 }
1260 else if (AR_SREV_9271_11(ah))
1261 /*
1262 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1263 * present on AR9271 1.1
1264 */
1265 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1266 return;
1267 }
1268
1269 /*
1270 * Set the RX_ABORT and RX_DIS and clear if off only after
1271 * RXE is set for MAC. This prevents frames with corrupted
1272 * descriptor status.
1273 */
1274 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1275
1276
1277 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1278 AR_SREV_9280_10_OR_LATER(ah))
1279 return;
1280 /*
1281 * Disable BB clock gating
1282 * Necessary to avoid issues on AR5416 2.0
1283 */
1284 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1285 }
1286
1287 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1288 struct ar5416_eeprom_def *pEepData,
1289 u32 reg, u32 value)
1290 {
1291 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1292
1293 switch (ah->hw_version.devid) {
1294 case AR9280_DEVID_PCI:
1295 if (reg == 0x7894) {
1296 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1297 "ini VAL: %x EEPROM: %x\n", value,
1298 (pBase->version & 0xff));
1299
1300 if ((pBase->version & 0xff) > 0x0a) {
1301 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1302 "PWDCLKIND: %d\n",
1303 pBase->pwdclkind);
1304 value &= ~AR_AN_TOP2_PWDCLKIND;
1305 value |= AR_AN_TOP2_PWDCLKIND &
1306 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1307 } else {
1308 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1309 "PWDCLKIND Earlier Rev\n");
1310 }
1311
1312 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1313 "final ini VAL: %x\n", value);
1314 }
1315 break;
1316 }
1317
1318 return value;
1319 }
1320
1321 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1322 struct ar5416_eeprom_def *pEepData,
1323 u32 reg, u32 value)
1324 {
1325 if (ah->eep_map == EEP_MAP_4KBITS)
1326 return value;
1327 else
1328 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1329 }
1330
1331 static void ath9k_olc_init(struct ath_hw *ah)
1332 {
1333 u32 i;
1334
1335 if (OLC_FOR_AR9287_10_LATER) {
1336 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1337 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1338 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1339 AR9287_AN_TXPC0_TXPCMODE,
1340 AR9287_AN_TXPC0_TXPCMODE_S,
1341 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1342 udelay(100);
1343 } else {
1344 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1345 ah->originalGain[i] =
1346 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1347 AR_PHY_TX_GAIN);
1348 ah->PDADCdelta = 0;
1349 }
1350 }
1351
1352 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1353 struct ath9k_channel *chan)
1354 {
1355 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1356
1357 if (IS_CHAN_B(chan))
1358 ctl |= CTL_11B;
1359 else if (IS_CHAN_G(chan))
1360 ctl |= CTL_11G;
1361 else
1362 ctl |= CTL_11A;
1363
1364 return ctl;
1365 }
1366
1367 static int ath9k_hw_process_ini(struct ath_hw *ah,
1368 struct ath9k_channel *chan,
1369 enum ath9k_ht_macmode macmode)
1370 {
1371 int i, regWrites = 0;
1372 struct ieee80211_channel *channel = chan->chan;
1373 u32 modesIndex, freqIndex;
1374
1375 switch (chan->chanmode) {
1376 case CHANNEL_A:
1377 case CHANNEL_A_HT20:
1378 modesIndex = 1;
1379 freqIndex = 1;
1380 break;
1381 case CHANNEL_A_HT40PLUS:
1382 case CHANNEL_A_HT40MINUS:
1383 modesIndex = 2;
1384 freqIndex = 1;
1385 break;
1386 case CHANNEL_G:
1387 case CHANNEL_G_HT20:
1388 case CHANNEL_B:
1389 modesIndex = 4;
1390 freqIndex = 2;
1391 break;
1392 case CHANNEL_G_HT40PLUS:
1393 case CHANNEL_G_HT40MINUS:
1394 modesIndex = 3;
1395 freqIndex = 2;
1396 break;
1397
1398 default:
1399 return -EINVAL;
1400 }
1401
1402 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1403 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1404 ah->eep_ops->set_addac(ah, chan);
1405
1406 if (AR_SREV_5416_22_OR_LATER(ah)) {
1407 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1408 } else {
1409 struct ar5416IniArray temp;
1410 u32 addacSize =
1411 sizeof(u32) * ah->iniAddac.ia_rows *
1412 ah->iniAddac.ia_columns;
1413
1414 memcpy(ah->addac5416_21,
1415 ah->iniAddac.ia_array, addacSize);
1416
1417 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1418
1419 temp.ia_array = ah->addac5416_21;
1420 temp.ia_columns = ah->iniAddac.ia_columns;
1421 temp.ia_rows = ah->iniAddac.ia_rows;
1422 REG_WRITE_ARRAY(&temp, 1, regWrites);
1423 }
1424
1425 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1426
1427 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1428 u32 reg = INI_RA(&ah->iniModes, i, 0);
1429 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1430
1431 REG_WRITE(ah, reg, val);
1432
1433 if (reg >= 0x7800 && reg < 0x78a0
1434 && ah->config.analog_shiftreg) {
1435 udelay(100);
1436 }
1437
1438 DO_DELAY(regWrites);
1439 }
1440
1441 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1442 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1443
1444 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1445 AR_SREV_9287_10_OR_LATER(ah))
1446 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1447
1448 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1449 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1450 u32 val = INI_RA(&ah->iniCommon, i, 1);
1451
1452 REG_WRITE(ah, reg, val);
1453
1454 if (reg >= 0x7800 && reg < 0x78a0
1455 && ah->config.analog_shiftreg) {
1456 udelay(100);
1457 }
1458
1459 DO_DELAY(regWrites);
1460 }
1461
1462 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1463
1464 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1465 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1466 regWrites);
1467 }
1468
1469 ath9k_hw_override_ini(ah, chan);
1470 ath9k_hw_set_regs(ah, chan, macmode);
1471 ath9k_hw_init_chain_masks(ah);
1472
1473 if (OLC_FOR_AR9280_20_LATER)
1474 ath9k_olc_init(ah);
1475
1476 ah->eep_ops->set_txpower(ah, chan,
1477 ath9k_regd_get_ctl(&ah->regulatory, chan),
1478 channel->max_antenna_gain * 2,
1479 channel->max_power * 2,
1480 min((u32) MAX_RATE_POWER,
1481 (u32) ah->regulatory.power_limit));
1482
1483 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1484 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1485 "ar5416SetRfRegs failed\n");
1486 return -EIO;
1487 }
1488
1489 return 0;
1490 }
1491
1492 /****************************************/
1493 /* Reset and Channel Switching Routines */
1494 /****************************************/
1495
1496 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1497 {
1498 u32 rfMode = 0;
1499
1500 if (chan == NULL)
1501 return;
1502
1503 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1504 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1505
1506 if (!AR_SREV_9280_10_OR_LATER(ah))
1507 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1508 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1509
1510 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1511 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1512
1513 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1514 }
1515
1516 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1517 {
1518 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1519 }
1520
1521 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1522 {
1523 u32 regval;
1524
1525 /*
1526 * set AHB_MODE not to do cacheline prefetches
1527 */
1528 regval = REG_READ(ah, AR_AHB_MODE);
1529 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1530
1531 /*
1532 * let mac dma reads be in 128 byte chunks
1533 */
1534 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1535 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1536
1537 /*
1538 * Restore TX Trigger Level to its pre-reset value.
1539 * The initial value depends on whether aggregation is enabled, and is
1540 * adjusted whenever underruns are detected.
1541 */
1542 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1543
1544 /*
1545 * let mac dma writes be in 128 byte chunks
1546 */
1547 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1548 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1549
1550 /*
1551 * Setup receive FIFO threshold to hold off TX activities
1552 */
1553 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1554
1555 /*
1556 * reduce the number of usable entries in PCU TXBUF to avoid
1557 * wrap around issues.
1558 */
1559 if (AR_SREV_9285(ah)) {
1560 /* For AR9285 the number of Fifos are reduced to half.
1561 * So set the usable tx buf size also to half to
1562 * avoid data/delimiter underruns
1563 */
1564 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1565 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1566 } else if (!AR_SREV_9271(ah)) {
1567 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1568 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1569 }
1570 }
1571
1572 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1573 {
1574 u32 val;
1575
1576 val = REG_READ(ah, AR_STA_ID1);
1577 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1578 switch (opmode) {
1579 case NL80211_IFTYPE_AP:
1580 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1581 | AR_STA_ID1_KSRCH_MODE);
1582 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1583 break;
1584 case NL80211_IFTYPE_ADHOC:
1585 case NL80211_IFTYPE_MESH_POINT:
1586 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1587 | AR_STA_ID1_KSRCH_MODE);
1588 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1589 break;
1590 case NL80211_IFTYPE_STATION:
1591 case NL80211_IFTYPE_MONITOR:
1592 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1593 break;
1594 }
1595 }
1596
1597 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1598 u32 coef_scaled,
1599 u32 *coef_mantissa,
1600 u32 *coef_exponent)
1601 {
1602 u32 coef_exp, coef_man;
1603
1604 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1605 if ((coef_scaled >> coef_exp) & 0x1)
1606 break;
1607
1608 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1609
1610 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1611
1612 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1613 *coef_exponent = coef_exp - 16;
1614 }
1615
1616 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1617 struct ath9k_channel *chan)
1618 {
1619 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1620 u32 clockMhzScaled = 0x64000000;
1621 struct chan_centers centers;
1622
1623 if (IS_CHAN_HALF_RATE(chan))
1624 clockMhzScaled = clockMhzScaled >> 1;
1625 else if (IS_CHAN_QUARTER_RATE(chan))
1626 clockMhzScaled = clockMhzScaled >> 2;
1627
1628 ath9k_hw_get_channel_centers(ah, chan, &centers);
1629 coef_scaled = clockMhzScaled / centers.synth_center;
1630
1631 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1632 &ds_coef_exp);
1633
1634 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1635 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1636 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1637 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1638
1639 coef_scaled = (9 * coef_scaled) / 10;
1640
1641 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1642 &ds_coef_exp);
1643
1644 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1645 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1646 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1647 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1648 }
1649
1650 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1651 {
1652 u32 rst_flags;
1653 u32 tmpReg;
1654
1655 if (AR_SREV_9100(ah)) {
1656 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1657 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1658 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1659 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1660 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1661 }
1662
1663 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1664 AR_RTC_FORCE_WAKE_ON_INT);
1665
1666 if (AR_SREV_9100(ah)) {
1667 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1668 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1669 } else {
1670 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1671 if (tmpReg &
1672 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1673 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1674 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1675 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1676 } else {
1677 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1678 }
1679
1680 rst_flags = AR_RTC_RC_MAC_WARM;
1681 if (type == ATH9K_RESET_COLD)
1682 rst_flags |= AR_RTC_RC_MAC_COLD;
1683 }
1684
1685 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1686 udelay(50);
1687
1688 REG_WRITE(ah, AR_RTC_RC, 0);
1689 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1690 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1691 "RTC stuck in MAC reset\n");
1692 return false;
1693 }
1694
1695 if (!AR_SREV_9100(ah))
1696 REG_WRITE(ah, AR_RC, 0);
1697
1698 ath9k_hw_init_pll(ah, NULL);
1699
1700 if (AR_SREV_9100(ah))
1701 udelay(50);
1702
1703 return true;
1704 }
1705
1706 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1707 {
1708 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1709 AR_RTC_FORCE_WAKE_ON_INT);
1710
1711 REG_WRITE(ah, AR_RTC_RESET, 0);
1712 udelay(2);
1713 REG_WRITE(ah, AR_RTC_RESET, 1);
1714
1715 if (!ath9k_hw_wait(ah,
1716 AR_RTC_STATUS,
1717 AR_RTC_STATUS_M,
1718 AR_RTC_STATUS_ON,
1719 AH_WAIT_TIMEOUT)) {
1720 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1721 return false;
1722 }
1723
1724 ath9k_hw_read_revisions(ah);
1725
1726 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1727 }
1728
1729 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1730 {
1731 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1732 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1733
1734 switch (type) {
1735 case ATH9K_RESET_POWER_ON:
1736 return ath9k_hw_set_reset_power_on(ah);
1737 case ATH9K_RESET_WARM:
1738 case ATH9K_RESET_COLD:
1739 return ath9k_hw_set_reset(ah, type);
1740 default:
1741 return false;
1742 }
1743 }
1744
1745 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1746 enum ath9k_ht_macmode macmode)
1747 {
1748 u32 phymode;
1749 u32 enableDacFifo = 0;
1750
1751 if (AR_SREV_9285_10_OR_LATER(ah))
1752 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1753 AR_PHY_FC_ENABLE_DAC_FIFO);
1754
1755 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1756 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1757
1758 if (IS_CHAN_HT40(chan)) {
1759 phymode |= AR_PHY_FC_DYN2040_EN;
1760
1761 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1762 (chan->chanmode == CHANNEL_G_HT40PLUS))
1763 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1764
1765 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1766 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1767 }
1768 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1769
1770 ath9k_hw_set11nmac2040(ah, macmode);
1771
1772 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1773 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1774 }
1775
1776 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1777 struct ath9k_channel *chan)
1778 {
1779 if (OLC_FOR_AR9280_20_LATER) {
1780 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1781 return false;
1782 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1783 return false;
1784
1785 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1786 return false;
1787
1788 ah->chip_fullsleep = false;
1789 ath9k_hw_init_pll(ah, chan);
1790 ath9k_hw_set_rfmode(ah, chan);
1791
1792 return true;
1793 }
1794
1795 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1796 struct ath9k_channel *chan,
1797 enum ath9k_ht_macmode macmode)
1798 {
1799 struct ieee80211_channel *channel = chan->chan;
1800 u32 synthDelay, qnum;
1801
1802 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1803 if (ath9k_hw_numtxpending(ah, qnum)) {
1804 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1805 "Transmit frames pending on queue %d\n", qnum);
1806 return false;
1807 }
1808 }
1809
1810 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1811 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1812 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1813 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1814 "Could not kill baseband RX\n");
1815 return false;
1816 }
1817
1818 ath9k_hw_set_regs(ah, chan, macmode);
1819
1820 if (AR_SREV_9280_10_OR_LATER(ah)) {
1821 ath9k_hw_ar9280_set_channel(ah, chan);
1822 } else {
1823 if (!(ath9k_hw_set_channel(ah, chan))) {
1824 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1825 "Failed to set channel\n");
1826 return false;
1827 }
1828 }
1829
1830 ah->eep_ops->set_txpower(ah, chan,
1831 ath9k_regd_get_ctl(&ah->regulatory, chan),
1832 channel->max_antenna_gain * 2,
1833 channel->max_power * 2,
1834 min((u32) MAX_RATE_POWER,
1835 (u32) ah->regulatory.power_limit));
1836
1837 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1838 if (IS_CHAN_B(chan))
1839 synthDelay = (4 * synthDelay) / 22;
1840 else
1841 synthDelay /= 10;
1842
1843 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1844
1845 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1846
1847 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1848 ath9k_hw_set_delta_slope(ah, chan);
1849
1850 if (AR_SREV_9280_10_OR_LATER(ah))
1851 ath9k_hw_9280_spur_mitigate(ah, chan);
1852 else
1853 ath9k_hw_spur_mitigate(ah, chan);
1854
1855 if (!chan->oneTimeCalsDone)
1856 chan->oneTimeCalsDone = true;
1857
1858 return true;
1859 }
1860
1861 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1862 {
1863 int bb_spur = AR_NO_SPUR;
1864 int freq;
1865 int bin, cur_bin;
1866 int bb_spur_off, spur_subchannel_sd;
1867 int spur_freq_sd;
1868 int spur_delta_phase;
1869 int denominator;
1870 int upper, lower, cur_vit_mask;
1871 int tmp, newVal;
1872 int i;
1873 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1874 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1875 };
1876 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1877 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1878 };
1879 int inc[4] = { 0, 100, 0, 0 };
1880 struct chan_centers centers;
1881
1882 int8_t mask_m[123];
1883 int8_t mask_p[123];
1884 int8_t mask_amt;
1885 int tmp_mask;
1886 int cur_bb_spur;
1887 bool is2GHz = IS_CHAN_2GHZ(chan);
1888
1889 memset(&mask_m, 0, sizeof(int8_t) * 123);
1890 memset(&mask_p, 0, sizeof(int8_t) * 123);
1891
1892 ath9k_hw_get_channel_centers(ah, chan, &centers);
1893 freq = centers.synth_center;
1894
1895 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1896 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1897 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1898
1899 if (is2GHz)
1900 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1901 else
1902 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1903
1904 if (AR_NO_SPUR == cur_bb_spur)
1905 break;
1906 cur_bb_spur = cur_bb_spur - freq;
1907
1908 if (IS_CHAN_HT40(chan)) {
1909 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1910 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1911 bb_spur = cur_bb_spur;
1912 break;
1913 }
1914 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1915 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1916 bb_spur = cur_bb_spur;
1917 break;
1918 }
1919 }
1920
1921 if (AR_NO_SPUR == bb_spur) {
1922 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1923 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1924 return;
1925 } else {
1926 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1927 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1928 }
1929
1930 bin = bb_spur * 320;
1931
1932 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1933
1934 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1935 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1936 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1937 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1938 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1939
1940 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1941 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1942 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1943 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1944 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1945 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1946
1947 if (IS_CHAN_HT40(chan)) {
1948 if (bb_spur < 0) {
1949 spur_subchannel_sd = 1;
1950 bb_spur_off = bb_spur + 10;
1951 } else {
1952 spur_subchannel_sd = 0;
1953 bb_spur_off = bb_spur - 10;
1954 }
1955 } else {
1956 spur_subchannel_sd = 0;
1957 bb_spur_off = bb_spur;
1958 }
1959
1960 if (IS_CHAN_HT40(chan))
1961 spur_delta_phase =
1962 ((bb_spur * 262144) /
1963 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1964 else
1965 spur_delta_phase =
1966 ((bb_spur * 524288) /
1967 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1968
1969 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1970 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1971
1972 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1973 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1974 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1975 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1976
1977 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1978 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1979
1980 cur_bin = -6000;
1981 upper = bin + 100;
1982 lower = bin - 100;
1983
1984 for (i = 0; i < 4; i++) {
1985 int pilot_mask = 0;
1986 int chan_mask = 0;
1987 int bp = 0;
1988 for (bp = 0; bp < 30; bp++) {
1989 if ((cur_bin > lower) && (cur_bin < upper)) {
1990 pilot_mask = pilot_mask | 0x1 << bp;
1991 chan_mask = chan_mask | 0x1 << bp;
1992 }
1993 cur_bin += 100;
1994 }
1995 cur_bin += inc[i];
1996 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1997 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1998 }
1999
2000 cur_vit_mask = 6100;
2001 upper = bin + 120;
2002 lower = bin - 120;
2003
2004 for (i = 0; i < 123; i++) {
2005 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2006
2007 /* workaround for gcc bug #37014 */
2008 volatile int tmp_v = abs(cur_vit_mask - bin);
2009
2010 if (tmp_v < 75)
2011 mask_amt = 1;
2012 else
2013 mask_amt = 0;
2014 if (cur_vit_mask < 0)
2015 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2016 else
2017 mask_p[cur_vit_mask / 100] = mask_amt;
2018 }
2019 cur_vit_mask -= 100;
2020 }
2021
2022 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2023 | (mask_m[48] << 26) | (mask_m[49] << 24)
2024 | (mask_m[50] << 22) | (mask_m[51] << 20)
2025 | (mask_m[52] << 18) | (mask_m[53] << 16)
2026 | (mask_m[54] << 14) | (mask_m[55] << 12)
2027 | (mask_m[56] << 10) | (mask_m[57] << 8)
2028 | (mask_m[58] << 6) | (mask_m[59] << 4)
2029 | (mask_m[60] << 2) | (mask_m[61] << 0);
2030 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2031 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2032
2033 tmp_mask = (mask_m[31] << 28)
2034 | (mask_m[32] << 26) | (mask_m[33] << 24)
2035 | (mask_m[34] << 22) | (mask_m[35] << 20)
2036 | (mask_m[36] << 18) | (mask_m[37] << 16)
2037 | (mask_m[48] << 14) | (mask_m[39] << 12)
2038 | (mask_m[40] << 10) | (mask_m[41] << 8)
2039 | (mask_m[42] << 6) | (mask_m[43] << 4)
2040 | (mask_m[44] << 2) | (mask_m[45] << 0);
2041 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2042 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2043
2044 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2045 | (mask_m[18] << 26) | (mask_m[18] << 24)
2046 | (mask_m[20] << 22) | (mask_m[20] << 20)
2047 | (mask_m[22] << 18) | (mask_m[22] << 16)
2048 | (mask_m[24] << 14) | (mask_m[24] << 12)
2049 | (mask_m[25] << 10) | (mask_m[26] << 8)
2050 | (mask_m[27] << 6) | (mask_m[28] << 4)
2051 | (mask_m[29] << 2) | (mask_m[30] << 0);
2052 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2053 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2054
2055 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2056 | (mask_m[2] << 26) | (mask_m[3] << 24)
2057 | (mask_m[4] << 22) | (mask_m[5] << 20)
2058 | (mask_m[6] << 18) | (mask_m[7] << 16)
2059 | (mask_m[8] << 14) | (mask_m[9] << 12)
2060 | (mask_m[10] << 10) | (mask_m[11] << 8)
2061 | (mask_m[12] << 6) | (mask_m[13] << 4)
2062 | (mask_m[14] << 2) | (mask_m[15] << 0);
2063 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2064 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2065
2066 tmp_mask = (mask_p[15] << 28)
2067 | (mask_p[14] << 26) | (mask_p[13] << 24)
2068 | (mask_p[12] << 22) | (mask_p[11] << 20)
2069 | (mask_p[10] << 18) | (mask_p[9] << 16)
2070 | (mask_p[8] << 14) | (mask_p[7] << 12)
2071 | (mask_p[6] << 10) | (mask_p[5] << 8)
2072 | (mask_p[4] << 6) | (mask_p[3] << 4)
2073 | (mask_p[2] << 2) | (mask_p[1] << 0);
2074 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2075 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2076
2077 tmp_mask = (mask_p[30] << 28)
2078 | (mask_p[29] << 26) | (mask_p[28] << 24)
2079 | (mask_p[27] << 22) | (mask_p[26] << 20)
2080 | (mask_p[25] << 18) | (mask_p[24] << 16)
2081 | (mask_p[23] << 14) | (mask_p[22] << 12)
2082 | (mask_p[21] << 10) | (mask_p[20] << 8)
2083 | (mask_p[19] << 6) | (mask_p[18] << 4)
2084 | (mask_p[17] << 2) | (mask_p[16] << 0);
2085 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2086 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2087
2088 tmp_mask = (mask_p[45] << 28)
2089 | (mask_p[44] << 26) | (mask_p[43] << 24)
2090 | (mask_p[42] << 22) | (mask_p[41] << 20)
2091 | (mask_p[40] << 18) | (mask_p[39] << 16)
2092 | (mask_p[38] << 14) | (mask_p[37] << 12)
2093 | (mask_p[36] << 10) | (mask_p[35] << 8)
2094 | (mask_p[34] << 6) | (mask_p[33] << 4)
2095 | (mask_p[32] << 2) | (mask_p[31] << 0);
2096 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2097 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2098
2099 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2100 | (mask_p[59] << 26) | (mask_p[58] << 24)
2101 | (mask_p[57] << 22) | (mask_p[56] << 20)
2102 | (mask_p[55] << 18) | (mask_p[54] << 16)
2103 | (mask_p[53] << 14) | (mask_p[52] << 12)
2104 | (mask_p[51] << 10) | (mask_p[50] << 8)
2105 | (mask_p[49] << 6) | (mask_p[48] << 4)
2106 | (mask_p[47] << 2) | (mask_p[46] << 0);
2107 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2108 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2109 }
2110
2111 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2112 {
2113 int bb_spur = AR_NO_SPUR;
2114 int bin, cur_bin;
2115 int spur_freq_sd;
2116 int spur_delta_phase;
2117 int denominator;
2118 int upper, lower, cur_vit_mask;
2119 int tmp, new;
2120 int i;
2121 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2122 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2123 };
2124 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2125 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2126 };
2127 int inc[4] = { 0, 100, 0, 0 };
2128
2129 int8_t mask_m[123];
2130 int8_t mask_p[123];
2131 int8_t mask_amt;
2132 int tmp_mask;
2133 int cur_bb_spur;
2134 bool is2GHz = IS_CHAN_2GHZ(chan);
2135
2136 memset(&mask_m, 0, sizeof(int8_t) * 123);
2137 memset(&mask_p, 0, sizeof(int8_t) * 123);
2138
2139 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2140 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2141 if (AR_NO_SPUR == cur_bb_spur)
2142 break;
2143 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2144 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2145 bb_spur = cur_bb_spur;
2146 break;
2147 }
2148 }
2149
2150 if (AR_NO_SPUR == bb_spur)
2151 return;
2152
2153 bin = bb_spur * 32;
2154
2155 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2156 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2157 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2158 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2159 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2160
2161 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2162
2163 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2164 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2165 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2166 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2167 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2168 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2169
2170 spur_delta_phase = ((bb_spur * 524288) / 100) &
2171 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2172
2173 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2174 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2175
2176 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2177 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2178 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2179 REG_WRITE(ah, AR_PHY_TIMING11, new);
2180
2181 cur_bin = -6000;
2182 upper = bin + 100;
2183 lower = bin - 100;
2184
2185 for (i = 0; i < 4; i++) {
2186 int pilot_mask = 0;
2187 int chan_mask = 0;
2188 int bp = 0;
2189 for (bp = 0; bp < 30; bp++) {
2190 if ((cur_bin > lower) && (cur_bin < upper)) {
2191 pilot_mask = pilot_mask | 0x1 << bp;
2192 chan_mask = chan_mask | 0x1 << bp;
2193 }
2194 cur_bin += 100;
2195 }
2196 cur_bin += inc[i];
2197 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2198 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2199 }
2200
2201 cur_vit_mask = 6100;
2202 upper = bin + 120;
2203 lower = bin - 120;
2204
2205 for (i = 0; i < 123; i++) {
2206 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2207
2208 /* workaround for gcc bug #37014 */
2209 volatile int tmp_v = abs(cur_vit_mask - bin);
2210
2211 if (tmp_v < 75)
2212 mask_amt = 1;
2213 else
2214 mask_amt = 0;
2215 if (cur_vit_mask < 0)
2216 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2217 else
2218 mask_p[cur_vit_mask / 100] = mask_amt;
2219 }
2220 cur_vit_mask -= 100;
2221 }
2222
2223 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2224 | (mask_m[48] << 26) | (mask_m[49] << 24)
2225 | (mask_m[50] << 22) | (mask_m[51] << 20)
2226 | (mask_m[52] << 18) | (mask_m[53] << 16)
2227 | (mask_m[54] << 14) | (mask_m[55] << 12)
2228 | (mask_m[56] << 10) | (mask_m[57] << 8)
2229 | (mask_m[58] << 6) | (mask_m[59] << 4)
2230 | (mask_m[60] << 2) | (mask_m[61] << 0);
2231 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2232 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2233
2234 tmp_mask = (mask_m[31] << 28)
2235 | (mask_m[32] << 26) | (mask_m[33] << 24)
2236 | (mask_m[34] << 22) | (mask_m[35] << 20)
2237 | (mask_m[36] << 18) | (mask_m[37] << 16)
2238 | (mask_m[48] << 14) | (mask_m[39] << 12)
2239 | (mask_m[40] << 10) | (mask_m[41] << 8)
2240 | (mask_m[42] << 6) | (mask_m[43] << 4)
2241 | (mask_m[44] << 2) | (mask_m[45] << 0);
2242 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2243 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2244
2245 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2246 | (mask_m[18] << 26) | (mask_m[18] << 24)
2247 | (mask_m[20] << 22) | (mask_m[20] << 20)
2248 | (mask_m[22] << 18) | (mask_m[22] << 16)
2249 | (mask_m[24] << 14) | (mask_m[24] << 12)
2250 | (mask_m[25] << 10) | (mask_m[26] << 8)
2251 | (mask_m[27] << 6) | (mask_m[28] << 4)
2252 | (mask_m[29] << 2) | (mask_m[30] << 0);
2253 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2254 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2255
2256 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2257 | (mask_m[2] << 26) | (mask_m[3] << 24)
2258 | (mask_m[4] << 22) | (mask_m[5] << 20)
2259 | (mask_m[6] << 18) | (mask_m[7] << 16)
2260 | (mask_m[8] << 14) | (mask_m[9] << 12)
2261 | (mask_m[10] << 10) | (mask_m[11] << 8)
2262 | (mask_m[12] << 6) | (mask_m[13] << 4)
2263 | (mask_m[14] << 2) | (mask_m[15] << 0);
2264 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2265 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2266
2267 tmp_mask = (mask_p[15] << 28)
2268 | (mask_p[14] << 26) | (mask_p[13] << 24)
2269 | (mask_p[12] << 22) | (mask_p[11] << 20)
2270 | (mask_p[10] << 18) | (mask_p[9] << 16)
2271 | (mask_p[8] << 14) | (mask_p[7] << 12)
2272 | (mask_p[6] << 10) | (mask_p[5] << 8)
2273 | (mask_p[4] << 6) | (mask_p[3] << 4)
2274 | (mask_p[2] << 2) | (mask_p[1] << 0);
2275 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2276 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2277
2278 tmp_mask = (mask_p[30] << 28)
2279 | (mask_p[29] << 26) | (mask_p[28] << 24)
2280 | (mask_p[27] << 22) | (mask_p[26] << 20)
2281 | (mask_p[25] << 18) | (mask_p[24] << 16)
2282 | (mask_p[23] << 14) | (mask_p[22] << 12)
2283 | (mask_p[21] << 10) | (mask_p[20] << 8)
2284 | (mask_p[19] << 6) | (mask_p[18] << 4)
2285 | (mask_p[17] << 2) | (mask_p[16] << 0);
2286 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2287 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2288
2289 tmp_mask = (mask_p[45] << 28)
2290 | (mask_p[44] << 26) | (mask_p[43] << 24)
2291 | (mask_p[42] << 22) | (mask_p[41] << 20)
2292 | (mask_p[40] << 18) | (mask_p[39] << 16)
2293 | (mask_p[38] << 14) | (mask_p[37] << 12)
2294 | (mask_p[36] << 10) | (mask_p[35] << 8)
2295 | (mask_p[34] << 6) | (mask_p[33] << 4)
2296 | (mask_p[32] << 2) | (mask_p[31] << 0);
2297 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2298 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2299
2300 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2301 | (mask_p[59] << 26) | (mask_p[58] << 24)
2302 | (mask_p[57] << 22) | (mask_p[56] << 20)
2303 | (mask_p[55] << 18) | (mask_p[54] << 16)
2304 | (mask_p[53] << 14) | (mask_p[52] << 12)
2305 | (mask_p[51] << 10) | (mask_p[50] << 8)
2306 | (mask_p[49] << 6) | (mask_p[48] << 4)
2307 | (mask_p[47] << 2) | (mask_p[46] << 0);
2308 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2309 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2310 }
2311
2312 static void ath9k_enable_rfkill(struct ath_hw *ah)
2313 {
2314 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2315 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2316
2317 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2318 AR_GPIO_INPUT_MUX2_RFSILENT);
2319
2320 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2321 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2322 }
2323
2324 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2325 bool bChannelChange)
2326 {
2327 u32 saveLedState;
2328 struct ath_softc *sc = ah->ah_sc;
2329 struct ath9k_channel *curchan = ah->curchan;
2330 u32 saveDefAntenna;
2331 u32 macStaId1;
2332 int i, rx_chainmask, r;
2333
2334 ah->extprotspacing = sc->ht_extprotspacing;
2335 ah->txchainmask = sc->tx_chainmask;
2336 ah->rxchainmask = sc->rx_chainmask;
2337
2338 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2339 return -EIO;
2340
2341 if (curchan)
2342 ath9k_hw_getnf(ah, curchan);
2343
2344 if (bChannelChange &&
2345 (ah->chip_fullsleep != true) &&
2346 (ah->curchan != NULL) &&
2347 (chan->channel != ah->curchan->channel) &&
2348 ((chan->channelFlags & CHANNEL_ALL) ==
2349 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2350 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2351 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2352
2353 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2354 ath9k_hw_loadnf(ah, ah->curchan);
2355 ath9k_hw_start_nfcal(ah);
2356 return 0;
2357 }
2358 }
2359
2360 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2361 if (saveDefAntenna == 0)
2362 saveDefAntenna = 1;
2363
2364 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2365
2366 saveLedState = REG_READ(ah, AR_CFG_LED) &
2367 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2368 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2369
2370 ath9k_hw_mark_phy_inactive(ah);
2371
2372 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2373 REG_WRITE(ah,
2374 AR9271_RESET_POWER_DOWN_CONTROL,
2375 AR9271_RADIO_RF_RST);
2376 udelay(50);
2377 }
2378
2379 if (!ath9k_hw_chip_reset(ah, chan)) {
2380 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2381 return -EINVAL;
2382 }
2383
2384 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2385 ah->htc_reset_init = false;
2386 REG_WRITE(ah,
2387 AR9271_RESET_POWER_DOWN_CONTROL,
2388 AR9271_GATE_MAC_CTL);
2389 udelay(50);
2390 }
2391
2392 if (AR_SREV_9280_10_OR_LATER(ah))
2393 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2394
2395 if (AR_SREV_9287_12_OR_LATER(ah)) {
2396 /* Enable ASYNC FIFO */
2397 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2398 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2399 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2400 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2401 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2402 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2403 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2404 }
2405 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2406 if (r)
2407 return r;
2408
2409 /* Setup MFP options for CCMP */
2410 if (AR_SREV_9280_20_OR_LATER(ah)) {
2411 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2412 * frames when constructing CCMP AAD. */
2413 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2414 0xc7ff);
2415 ah->sw_mgmt_crypto = false;
2416 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2417 /* Disable hardware crypto for management frames */
2418 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2419 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2420 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2421 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2422 ah->sw_mgmt_crypto = true;
2423 } else
2424 ah->sw_mgmt_crypto = true;
2425
2426 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2427 ath9k_hw_set_delta_slope(ah, chan);
2428
2429 if (AR_SREV_9280_10_OR_LATER(ah))
2430 ath9k_hw_9280_spur_mitigate(ah, chan);
2431 else
2432 ath9k_hw_spur_mitigate(ah, chan);
2433
2434 ah->eep_ops->set_board_values(ah, chan);
2435
2436 ath9k_hw_decrease_chain_power(ah, chan);
2437
2438 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2439 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2440 | macStaId1
2441 | AR_STA_ID1_RTS_USE_DEF
2442 | (ah->config.
2443 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2444 | ah->sta_id1_defaults);
2445 ath9k_hw_set_operating_mode(ah, ah->opmode);
2446
2447 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2448 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2449
2450 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2451
2452 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2453 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2454 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2455
2456 REG_WRITE(ah, AR_ISR, ~0);
2457
2458 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2459
2460 if (AR_SREV_9280_10_OR_LATER(ah))
2461 ath9k_hw_ar9280_set_channel(ah, chan);
2462 else
2463 if (!(ath9k_hw_set_channel(ah, chan)))
2464 return -EIO;
2465
2466 for (i = 0; i < AR_NUM_DCU; i++)
2467 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2468
2469 ah->intr_txqs = 0;
2470 for (i = 0; i < ah->caps.total_queues; i++)
2471 ath9k_hw_resettxqueue(ah, i);
2472
2473 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2474 ath9k_hw_init_qos(ah);
2475
2476 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2477 ath9k_enable_rfkill(ah);
2478
2479 ath9k_hw_init_user_settings(ah);
2480
2481 if (AR_SREV_9287_12_OR_LATER(ah)) {
2482 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2483 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2484 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2485 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2486 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2487 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2488
2489 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2490 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2491
2492 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2493 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2494 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2495 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2496 }
2497 if (AR_SREV_9287_12_OR_LATER(ah)) {
2498 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2499 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2500 }
2501
2502 REG_WRITE(ah, AR_STA_ID1,
2503 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2504
2505 ath9k_hw_set_dma(ah);
2506
2507 REG_WRITE(ah, AR_OBS, 8);
2508
2509 if (ah->config.intr_mitigation) {
2510 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2511 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2512 }
2513
2514 ath9k_hw_init_bb(ah, chan);
2515
2516 if (!ath9k_hw_init_cal(ah, chan))
2517 return -EIO;
2518
2519 rx_chainmask = ah->rxchainmask;
2520 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2521 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2522 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2523 }
2524
2525 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2526
2527 /*
2528 * For big endian systems turn on swapping for descriptors
2529 */
2530 if (AR_SREV_9100(ah)) {
2531 u32 mask;
2532 mask = REG_READ(ah, AR_CFG);
2533 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2534 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2535 "CFG Byte Swap Set 0x%x\n", mask);
2536 } else {
2537 mask =
2538 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2539 REG_WRITE(ah, AR_CFG, mask);
2540 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2541 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2542 }
2543 } else {
2544 /* Configure AR9271 target WLAN */
2545 if (AR_SREV_9271(ah))
2546 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2547 #ifdef __BIG_ENDIAN
2548 else
2549 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2550 #endif
2551 }
2552
2553 return 0;
2554 }
2555
2556 /************************/
2557 /* Key Cache Management */
2558 /************************/
2559
2560 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2561 {
2562 u32 keyType;
2563
2564 if (entry >= ah->caps.keycache_size) {
2565 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2566 "keychache entry %u out of range\n", entry);
2567 return false;
2568 }
2569
2570 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2571
2572 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2573 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2574 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2575 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2576 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2577 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2578 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2579 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2580
2581 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2582 u16 micentry = entry + 64;
2583
2584 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2585 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2586 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2587 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2588
2589 }
2590
2591 return true;
2592 }
2593
2594 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2595 {
2596 u32 macHi, macLo;
2597
2598 if (entry >= ah->caps.keycache_size) {
2599 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2600 "keychache entry %u out of range\n", entry);
2601 return false;
2602 }
2603
2604 if (mac != NULL) {
2605 macHi = (mac[5] << 8) | mac[4];
2606 macLo = (mac[3] << 24) |
2607 (mac[2] << 16) |
2608 (mac[1] << 8) |
2609 mac[0];
2610 macLo >>= 1;
2611 macLo |= (macHi & 1) << 31;
2612 macHi >>= 1;
2613 } else {
2614 macLo = macHi = 0;
2615 }
2616 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2617 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2618
2619 return true;
2620 }
2621
2622 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2623 const struct ath9k_keyval *k,
2624 const u8 *mac)
2625 {
2626 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2627 u32 key0, key1, key2, key3, key4;
2628 u32 keyType;
2629
2630 if (entry >= pCap->keycache_size) {
2631 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2632 "keycache entry %u out of range\n", entry);
2633 return false;
2634 }
2635
2636 switch (k->kv_type) {
2637 case ATH9K_CIPHER_AES_OCB:
2638 keyType = AR_KEYTABLE_TYPE_AES;
2639 break;
2640 case ATH9K_CIPHER_AES_CCM:
2641 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2642 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2643 "AES-CCM not supported by mac rev 0x%x\n",
2644 ah->hw_version.macRev);
2645 return false;
2646 }
2647 keyType = AR_KEYTABLE_TYPE_CCM;
2648 break;
2649 case ATH9K_CIPHER_TKIP:
2650 keyType = AR_KEYTABLE_TYPE_TKIP;
2651 if (ATH9K_IS_MIC_ENABLED(ah)
2652 && entry + 64 >= pCap->keycache_size) {
2653 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2654 "entry %u inappropriate for TKIP\n", entry);
2655 return false;
2656 }
2657 break;
2658 case ATH9K_CIPHER_WEP:
2659 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2660 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2661 "WEP key length %u too small\n", k->kv_len);
2662 return false;
2663 }
2664 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2665 keyType = AR_KEYTABLE_TYPE_40;
2666 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2667 keyType = AR_KEYTABLE_TYPE_104;
2668 else
2669 keyType = AR_KEYTABLE_TYPE_128;
2670 break;
2671 case ATH9K_CIPHER_CLR:
2672 keyType = AR_KEYTABLE_TYPE_CLR;
2673 break;
2674 default:
2675 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2676 "cipher %u not supported\n", k->kv_type);
2677 return false;
2678 }
2679
2680 key0 = get_unaligned_le32(k->kv_val + 0);
2681 key1 = get_unaligned_le16(k->kv_val + 4);
2682 key2 = get_unaligned_le32(k->kv_val + 6);
2683 key3 = get_unaligned_le16(k->kv_val + 10);
2684 key4 = get_unaligned_le32(k->kv_val + 12);
2685 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2686 key4 &= 0xff;
2687
2688 /*
2689 * Note: Key cache registers access special memory area that requires
2690 * two 32-bit writes to actually update the values in the internal
2691 * memory. Consequently, the exact order and pairs used here must be
2692 * maintained.
2693 */
2694
2695 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2696 u16 micentry = entry + 64;
2697
2698 /*
2699 * Write inverted key[47:0] first to avoid Michael MIC errors
2700 * on frames that could be sent or received at the same time.
2701 * The correct key will be written in the end once everything
2702 * else is ready.
2703 */
2704 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2705 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2706
2707 /* Write key[95:48] */
2708 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2709 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2710
2711 /* Write key[127:96] and key type */
2712 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2713 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2714
2715 /* Write MAC address for the entry */
2716 (void) ath9k_hw_keysetmac(ah, entry, mac);
2717
2718 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2719 /*
2720 * TKIP uses two key cache entries:
2721 * Michael MIC TX/RX keys in the same key cache entry
2722 * (idx = main index + 64):
2723 * key0 [31:0] = RX key [31:0]
2724 * key1 [15:0] = TX key [31:16]
2725 * key1 [31:16] = reserved
2726 * key2 [31:0] = RX key [63:32]
2727 * key3 [15:0] = TX key [15:0]
2728 * key3 [31:16] = reserved
2729 * key4 [31:0] = TX key [63:32]
2730 */
2731 u32 mic0, mic1, mic2, mic3, mic4;
2732
2733 mic0 = get_unaligned_le32(k->kv_mic + 0);
2734 mic2 = get_unaligned_le32(k->kv_mic + 4);
2735 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2736 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2737 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2738
2739 /* Write RX[31:0] and TX[31:16] */
2740 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2741 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2742
2743 /* Write RX[63:32] and TX[15:0] */
2744 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2745 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2746
2747 /* Write TX[63:32] and keyType(reserved) */
2748 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2749 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2750 AR_KEYTABLE_TYPE_CLR);
2751
2752 } else {
2753 /*
2754 * TKIP uses four key cache entries (two for group
2755 * keys):
2756 * Michael MIC TX/RX keys are in different key cache
2757 * entries (idx = main index + 64 for TX and
2758 * main index + 32 + 96 for RX):
2759 * key0 [31:0] = TX/RX MIC key [31:0]
2760 * key1 [31:0] = reserved
2761 * key2 [31:0] = TX/RX MIC key [63:32]
2762 * key3 [31:0] = reserved
2763 * key4 [31:0] = reserved
2764 *
2765 * Upper layer code will call this function separately
2766 * for TX and RX keys when these registers offsets are
2767 * used.
2768 */
2769 u32 mic0, mic2;
2770
2771 mic0 = get_unaligned_le32(k->kv_mic + 0);
2772 mic2 = get_unaligned_le32(k->kv_mic + 4);
2773
2774 /* Write MIC key[31:0] */
2775 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2776 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2777
2778 /* Write MIC key[63:32] */
2779 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2780 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2781
2782 /* Write TX[63:32] and keyType(reserved) */
2783 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2784 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2785 AR_KEYTABLE_TYPE_CLR);
2786 }
2787
2788 /* MAC address registers are reserved for the MIC entry */
2789 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2790 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2791
2792 /*
2793 * Write the correct (un-inverted) key[47:0] last to enable
2794 * TKIP now that all other registers are set with correct
2795 * values.
2796 */
2797 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2798 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2799 } else {
2800 /* Write key[47:0] */
2801 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2802 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2803
2804 /* Write key[95:48] */
2805 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2806 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2807
2808 /* Write key[127:96] and key type */
2809 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2810 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2811
2812 /* Write MAC address for the entry */
2813 (void) ath9k_hw_keysetmac(ah, entry, mac);
2814 }
2815
2816 return true;
2817 }
2818
2819 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2820 {
2821 if (entry < ah->caps.keycache_size) {
2822 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2823 if (val & AR_KEYTABLE_VALID)
2824 return true;
2825 }
2826 return false;
2827 }
2828
2829 /******************************/
2830 /* Power Management (Chipset) */
2831 /******************************/
2832
2833 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2834 {
2835 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2836 if (setChip) {
2837 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2838 AR_RTC_FORCE_WAKE_EN);
2839 if (!AR_SREV_9100(ah))
2840 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2841
2842 REG_CLR_BIT(ah, (AR_RTC_RESET),
2843 AR_RTC_RESET_EN);
2844 }
2845 }
2846
2847 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2848 {
2849 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2850 if (setChip) {
2851 struct ath9k_hw_capabilities *pCap = &ah->caps;
2852
2853 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2854 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2855 AR_RTC_FORCE_WAKE_ON_INT);
2856 } else {
2857 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2858 AR_RTC_FORCE_WAKE_EN);
2859 }
2860 }
2861 }
2862
2863 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2864 {
2865 u32 val;
2866 int i;
2867
2868 if (setChip) {
2869 if ((REG_READ(ah, AR_RTC_STATUS) &
2870 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2871 if (ath9k_hw_set_reset_reg(ah,
2872 ATH9K_RESET_POWER_ON) != true) {
2873 return false;
2874 }
2875 }
2876 if (AR_SREV_9100(ah))
2877 REG_SET_BIT(ah, AR_RTC_RESET,
2878 AR_RTC_RESET_EN);
2879
2880 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2881 AR_RTC_FORCE_WAKE_EN);
2882 udelay(50);
2883
2884 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2885 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2886 if (val == AR_RTC_STATUS_ON)
2887 break;
2888 udelay(50);
2889 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2890 AR_RTC_FORCE_WAKE_EN);
2891 }
2892 if (i == 0) {
2893 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2894 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2895 return false;
2896 }
2897 }
2898
2899 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2900
2901 return true;
2902 }
2903
2904 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2905 enum ath9k_power_mode mode)
2906 {
2907 int status = true, setChip = true;
2908 static const char *modes[] = {
2909 "AWAKE",
2910 "FULL-SLEEP",
2911 "NETWORK SLEEP",
2912 "UNDEFINED"
2913 };
2914
2915 if (ah->power_mode == mode)
2916 return status;
2917
2918 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2919 modes[ah->power_mode], modes[mode]);
2920
2921 switch (mode) {
2922 case ATH9K_PM_AWAKE:
2923 status = ath9k_hw_set_power_awake(ah, setChip);
2924 break;
2925 case ATH9K_PM_FULL_SLEEP:
2926 ath9k_set_power_sleep(ah, setChip);
2927 ah->chip_fullsleep = true;
2928 break;
2929 case ATH9K_PM_NETWORK_SLEEP:
2930 ath9k_set_power_network_sleep(ah, setChip);
2931 break;
2932 default:
2933 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2934 "Unknown power mode %u\n", mode);
2935 return false;
2936 }
2937 ah->power_mode = mode;
2938
2939 return status;
2940 }
2941
2942 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2943 {
2944 unsigned long flags;
2945 bool ret;
2946
2947 spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2948 ret = ath9k_hw_setpower_nolock(ah, mode);
2949 spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2950
2951 return ret;
2952 }
2953
2954 void ath9k_ps_wakeup(struct ath_softc *sc)
2955 {
2956 unsigned long flags;
2957
2958 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2959 if (++sc->ps_usecount != 1)
2960 goto unlock;
2961
2962 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2963
2964 unlock:
2965 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2966 }
2967
2968 void ath9k_ps_restore(struct ath_softc *sc)
2969 {
2970 unsigned long flags;
2971
2972 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2973 if (--sc->ps_usecount != 0)
2974 goto unlock;
2975
2976 if (sc->ps_enabled &&
2977 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2978 SC_OP_WAIT_FOR_CAB |
2979 SC_OP_WAIT_FOR_PSPOLL_DATA |
2980 SC_OP_WAIT_FOR_TX_ACK)))
2981 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2982
2983 unlock:
2984 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2985 }
2986
2987 /*
2988 * Helper for ASPM support.
2989 *
2990 * Disable PLL when in L0s as well as receiver clock when in L1.
2991 * This power saving option must be enabled through the SerDes.
2992 *
2993 * Programming the SerDes must go through the same 288 bit serial shift
2994 * register as the other analog registers. Hence the 9 writes.
2995 */
2996 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2997 {
2998 u8 i;
2999
3000 if (ah->is_pciexpress != true)
3001 return;
3002
3003 /* Do not touch SerDes registers */
3004 if (ah->config.pcie_powersave_enable == 2)
3005 return;
3006
3007 /* Nothing to do on restore for 11N */
3008 if (restore)
3009 return;
3010
3011 if (AR_SREV_9280_20_OR_LATER(ah)) {
3012 /*
3013 * AR9280 2.0 or later chips use SerDes values from the
3014 * initvals.h initialized depending on chipset during
3015 * ath9k_hw_init()
3016 */
3017 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3018 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3019 INI_RA(&ah->iniPcieSerdes, i, 1));
3020 }
3021 } else if (AR_SREV_9280(ah) &&
3022 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
3023 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3024 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3025
3026 /* RX shut off when elecidle is asserted */
3027 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3028 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3029 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3030
3031 /* Shut off CLKREQ active in L1 */
3032 if (ah->config.pcie_clock_req)
3033 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3034 else
3035 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3036
3037 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3038 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3039 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3040
3041 /* Load the new settings */
3042 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3043
3044 } else {
3045 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3046 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3047
3048 /* RX shut off when elecidle is asserted */
3049 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3050 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3051 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3052
3053 /*
3054 * Ignore ah->ah_config.pcie_clock_req setting for
3055 * pre-AR9280 11n
3056 */
3057 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3058
3059 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3060 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3061 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3062
3063 /* Load the new settings */
3064 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3065 }
3066
3067 udelay(1000);
3068
3069 /* set bit 19 to allow forcing of pcie core into L1 state */
3070 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3071
3072 /* Several PCIe massages to ensure proper behaviour */
3073 if (ah->config.pcie_waen) {
3074 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
3075 } else {
3076 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah))
3077 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
3078 /*
3079 * On AR9280 chips bit 22 of 0x4004 needs to be set to
3080 * otherwise card may disappear.
3081 */
3082 else if (AR_SREV_9280(ah))
3083 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
3084 else
3085 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
3086 }
3087 }
3088
3089 /**********************/
3090 /* Interrupt Handling */
3091 /**********************/
3092
3093 bool ath9k_hw_intrpend(struct ath_hw *ah)
3094 {
3095 u32 host_isr;
3096
3097 if (AR_SREV_9100(ah))
3098 return true;
3099
3100 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3101 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3102 return true;
3103
3104 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3105 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3106 && (host_isr != AR_INTR_SPURIOUS))
3107 return true;
3108
3109 return false;
3110 }
3111
3112 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3113 {
3114 u32 isr = 0;
3115 u32 mask2 = 0;
3116 struct ath9k_hw_capabilities *pCap = &ah->caps;
3117 u32 sync_cause = 0;
3118 bool fatal_int = false;
3119
3120 if (!AR_SREV_9100(ah)) {
3121 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3122 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3123 == AR_RTC_STATUS_ON) {
3124 isr = REG_READ(ah, AR_ISR);
3125 }
3126 }
3127
3128 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3129 AR_INTR_SYNC_DEFAULT;
3130
3131 *masked = 0;
3132
3133 if (!isr && !sync_cause)
3134 return false;
3135 } else {
3136 *masked = 0;
3137 isr = REG_READ(ah, AR_ISR);
3138 }
3139
3140 if (isr) {
3141 if (isr & AR_ISR_BCNMISC) {
3142 u32 isr2;
3143 isr2 = REG_READ(ah, AR_ISR_S2);
3144 if (isr2 & AR_ISR_S2_TIM)
3145 mask2 |= ATH9K_INT_TIM;
3146 if (isr2 & AR_ISR_S2_DTIM)
3147 mask2 |= ATH9K_INT_DTIM;
3148 if (isr2 & AR_ISR_S2_DTIMSYNC)
3149 mask2 |= ATH9K_INT_DTIMSYNC;
3150 if (isr2 & (AR_ISR_S2_CABEND))
3151 mask2 |= ATH9K_INT_CABEND;
3152 if (isr2 & AR_ISR_S2_GTT)
3153 mask2 |= ATH9K_INT_GTT;
3154 if (isr2 & AR_ISR_S2_CST)
3155 mask2 |= ATH9K_INT_CST;
3156 if (isr2 & AR_ISR_S2_TSFOOR)
3157 mask2 |= ATH9K_INT_TSFOOR;
3158 }
3159
3160 isr = REG_READ(ah, AR_ISR_RAC);
3161 if (isr == 0xffffffff) {
3162 *masked = 0;
3163 return false;
3164 }
3165
3166 *masked = isr & ATH9K_INT_COMMON;
3167
3168 if (ah->config.intr_mitigation) {
3169 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3170 *masked |= ATH9K_INT_RX;
3171 }
3172
3173 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3174 *masked |= ATH9K_INT_RX;
3175 if (isr &
3176 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3177 AR_ISR_TXEOL)) {
3178 u32 s0_s, s1_s;
3179
3180 *masked |= ATH9K_INT_TX;
3181
3182 s0_s = REG_READ(ah, AR_ISR_S0_S);
3183 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3184 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3185
3186 s1_s = REG_READ(ah, AR_ISR_S1_S);
3187 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3188 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3189 }
3190
3191 if (isr & AR_ISR_RXORN) {
3192 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3193 "receive FIFO overrun interrupt\n");
3194 }
3195
3196 if (!AR_SREV_9100(ah)) {
3197 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3198 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3199 if (isr5 & AR_ISR_S5_TIM_TIMER)
3200 *masked |= ATH9K_INT_TIM_TIMER;
3201 }
3202 }
3203
3204 *masked |= mask2;
3205 }
3206
3207 if (AR_SREV_9100(ah))
3208 return true;
3209
3210 if (sync_cause) {
3211 fatal_int =
3212 (sync_cause &
3213 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3214 ? true : false;
3215
3216 if (fatal_int) {
3217 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3218 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3219 "received PCI FATAL interrupt\n");
3220 }
3221 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3222 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3223 "received PCI PERR interrupt\n");
3224 }
3225 *masked |= ATH9K_INT_FATAL;
3226 }
3227 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3228 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3229 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3230 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3231 REG_WRITE(ah, AR_RC, 0);
3232 *masked |= ATH9K_INT_FATAL;
3233 }
3234 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3235 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3236 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3237 }
3238
3239 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3240 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3241 }
3242
3243 return true;
3244 }
3245
3246 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3247 {
3248 u32 omask = ah->mask_reg;
3249 u32 mask, mask2;
3250 struct ath9k_hw_capabilities *pCap = &ah->caps;
3251
3252 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3253
3254 if (omask & ATH9K_INT_GLOBAL) {
3255 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3256 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3257 (void) REG_READ(ah, AR_IER);
3258 if (!AR_SREV_9100(ah)) {
3259 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3260 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3261
3262 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3263 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3264 }
3265 }
3266
3267 mask = ints & ATH9K_INT_COMMON;
3268 mask2 = 0;
3269
3270 if (ints & ATH9K_INT_TX) {
3271 if (ah->txok_interrupt_mask)
3272 mask |= AR_IMR_TXOK;
3273 if (ah->txdesc_interrupt_mask)
3274 mask |= AR_IMR_TXDESC;
3275 if (ah->txerr_interrupt_mask)
3276 mask |= AR_IMR_TXERR;
3277 if (ah->txeol_interrupt_mask)
3278 mask |= AR_IMR_TXEOL;
3279 }
3280 if (ints & ATH9K_INT_RX) {
3281 mask |= AR_IMR_RXERR;
3282 if (ah->config.intr_mitigation)
3283 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3284 else
3285 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3286 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3287 mask |= AR_IMR_GENTMR;
3288 }
3289
3290 if (ints & (ATH9K_INT_BMISC)) {
3291 mask |= AR_IMR_BCNMISC;
3292 if (ints & ATH9K_INT_TIM)
3293 mask2 |= AR_IMR_S2_TIM;
3294 if (ints & ATH9K_INT_DTIM)
3295 mask2 |= AR_IMR_S2_DTIM;
3296 if (ints & ATH9K_INT_DTIMSYNC)
3297 mask2 |= AR_IMR_S2_DTIMSYNC;
3298 if (ints & ATH9K_INT_CABEND)
3299 mask2 |= AR_IMR_S2_CABEND;
3300 if (ints & ATH9K_INT_TSFOOR)
3301 mask2 |= AR_IMR_S2_TSFOOR;
3302 }
3303
3304 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3305 mask |= AR_IMR_BCNMISC;
3306 if (ints & ATH9K_INT_GTT)
3307 mask2 |= AR_IMR_S2_GTT;
3308 if (ints & ATH9K_INT_CST)
3309 mask2 |= AR_IMR_S2_CST;
3310 }
3311
3312 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3313 REG_WRITE(ah, AR_IMR, mask);
3314 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3315 AR_IMR_S2_DTIM |
3316 AR_IMR_S2_DTIMSYNC |
3317 AR_IMR_S2_CABEND |
3318 AR_IMR_S2_CABTO |
3319 AR_IMR_S2_TSFOOR |
3320 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3321 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3322 ah->mask_reg = ints;
3323
3324 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3325 if (ints & ATH9K_INT_TIM_TIMER)
3326 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3327 else
3328 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3329 }
3330
3331 if (ints & ATH9K_INT_GLOBAL) {
3332 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3333 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3334 if (!AR_SREV_9100(ah)) {
3335 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3336 AR_INTR_MAC_IRQ);
3337 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3338
3339
3340 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3341 AR_INTR_SYNC_DEFAULT);
3342 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3343 AR_INTR_SYNC_DEFAULT);
3344 }
3345 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3346 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3347 }
3348
3349 return omask;
3350 }
3351
3352 /*******************/
3353 /* Beacon Handling */
3354 /*******************/
3355
3356 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3357 {
3358 int flags = 0;
3359
3360 ah->beacon_interval = beacon_period;
3361
3362 switch (ah->opmode) {
3363 case NL80211_IFTYPE_STATION:
3364 case NL80211_IFTYPE_MONITOR:
3365 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3366 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3367 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3368 flags |= AR_TBTT_TIMER_EN;
3369 break;
3370 case NL80211_IFTYPE_ADHOC:
3371 case NL80211_IFTYPE_MESH_POINT:
3372 REG_SET_BIT(ah, AR_TXCFG,
3373 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3374 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3375 TU_TO_USEC(next_beacon +
3376 (ah->atim_window ? ah->
3377 atim_window : 1)));
3378 flags |= AR_NDP_TIMER_EN;
3379 case NL80211_IFTYPE_AP:
3380 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3381 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3382 TU_TO_USEC(next_beacon -
3383 ah->config.
3384 dma_beacon_response_time));
3385 REG_WRITE(ah, AR_NEXT_SWBA,
3386 TU_TO_USEC(next_beacon -
3387 ah->config.
3388 sw_beacon_response_time));
3389 flags |=
3390 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3391 break;
3392 default:
3393 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3394 "%s: unsupported opmode: %d\n",
3395 __func__, ah->opmode);
3396 return;
3397 break;
3398 }
3399
3400 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3401 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3402 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3403 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3404
3405 beacon_period &= ~ATH9K_BEACON_ENA;
3406 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3407 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3408 ath9k_hw_reset_tsf(ah);
3409 }
3410
3411 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3412 }
3413
3414 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3415 const struct ath9k_beacon_state *bs)
3416 {
3417 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3418 struct ath9k_hw_capabilities *pCap = &ah->caps;
3419
3420 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3421
3422 REG_WRITE(ah, AR_BEACON_PERIOD,
3423 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3424 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3425 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3426
3427 REG_RMW_FIELD(ah, AR_RSSI_THR,
3428 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3429
3430 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3431
3432 if (bs->bs_sleepduration > beaconintval)
3433 beaconintval = bs->bs_sleepduration;
3434
3435 dtimperiod = bs->bs_dtimperiod;
3436 if (bs->bs_sleepduration > dtimperiod)
3437 dtimperiod = bs->bs_sleepduration;
3438
3439 if (beaconintval == dtimperiod)
3440 nextTbtt = bs->bs_nextdtim;
3441 else
3442 nextTbtt = bs->bs_nexttbtt;
3443
3444 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3445 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3446 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3447 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3448
3449 REG_WRITE(ah, AR_NEXT_DTIM,
3450 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3451 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3452
3453 REG_WRITE(ah, AR_SLEEP1,
3454 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3455 | AR_SLEEP1_ASSUME_DTIM);
3456
3457 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3458 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3459 else
3460 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3461
3462 REG_WRITE(ah, AR_SLEEP2,
3463 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3464
3465 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3466 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3467
3468 REG_SET_BIT(ah, AR_TIMER_MODE,
3469 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3470 AR_DTIM_TIMER_EN);
3471
3472 /* TSF Out of Range Threshold */
3473 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3474 }
3475
3476 /*******************/
3477 /* HW Capabilities */
3478 /*******************/
3479
3480 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3481 {
3482 struct ath9k_hw_capabilities *pCap = &ah->caps;
3483 u16 capField = 0, eeval;
3484
3485 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3486 ah->regulatory.current_rd = eeval;
3487
3488 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3489 if (AR_SREV_9285_10_OR_LATER(ah))
3490 eeval |= AR9285_RDEXT_DEFAULT;
3491 ah->regulatory.current_rd_ext = eeval;
3492
3493 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3494
3495 if (ah->opmode != NL80211_IFTYPE_AP &&
3496 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3497 if (ah->regulatory.current_rd == 0x64 ||
3498 ah->regulatory.current_rd == 0x65)
3499 ah->regulatory.current_rd += 5;
3500 else if (ah->regulatory.current_rd == 0x41)
3501 ah->regulatory.current_rd = 0x43;
3502 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3503 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3504 }
3505
3506 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3507 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3508
3509 if (eeval & AR5416_OPFLAGS_11A) {
3510 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3511 if (ah->config.ht_enable) {
3512 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3513 set_bit(ATH9K_MODE_11NA_HT20,
3514 pCap->wireless_modes);
3515 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3516 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3517 pCap->wireless_modes);
3518 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3519 pCap->wireless_modes);
3520 }
3521 }
3522 }
3523
3524 if (eeval & AR5416_OPFLAGS_11G) {
3525 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3526 if (ah->config.ht_enable) {
3527 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3528 set_bit(ATH9K_MODE_11NG_HT20,
3529 pCap->wireless_modes);
3530 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3531 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3532 pCap->wireless_modes);
3533 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3534 pCap->wireless_modes);
3535 }
3536 }
3537 }
3538
3539 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3540 /*
3541 * For AR9271 we will temporarilly uses the rx chainmax as read from
3542 * the EEPROM.
3543 */
3544 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3545 !(eeval & AR5416_OPFLAGS_11A) &&
3546 !(AR_SREV_9271(ah)))
3547 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3548 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3549 else
3550 /* Use rx_chainmask from EEPROM. */
3551 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3552
3553 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3554 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3555
3556 pCap->low_2ghz_chan = 2312;
3557 pCap->high_2ghz_chan = 2732;
3558
3559 pCap->low_5ghz_chan = 4920;
3560 pCap->high_5ghz_chan = 6100;
3561
3562 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3563 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3564 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3565
3566 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3567 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3568 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3569
3570 if (ah->config.ht_enable)
3571 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3572 else
3573 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3574
3575 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3576 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3577 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3578 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3579
3580 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3581 pCap->total_queues =
3582 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3583 else
3584 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3585
3586 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3587 pCap->keycache_size =
3588 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3589 else
3590 pCap->keycache_size = AR_KEYTABLE_SIZE;
3591
3592 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3593 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3594
3595 if (AR_SREV_9285_10_OR_LATER(ah))
3596 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3597 else if (AR_SREV_9280_10_OR_LATER(ah))
3598 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3599 else
3600 pCap->num_gpio_pins = AR_NUM_GPIO;
3601
3602 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3603 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3604 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3605 } else {
3606 pCap->rts_aggr_limit = (8 * 1024);
3607 }
3608
3609 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3610
3611 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3612 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3613 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3614 ah->rfkill_gpio =
3615 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3616 ah->rfkill_polarity =
3617 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3618
3619 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3620 }
3621 #endif
3622
3623 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3624 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3625 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3626 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3627 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3628 (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3629 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3630 else
3631 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3632
3633 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3634 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3635 else
3636 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3637
3638 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3639 pCap->reg_cap =
3640 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3641 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3642 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3643 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3644 } else {
3645 pCap->reg_cap =
3646 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3647 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3648 }
3649
3650 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3651
3652 pCap->num_antcfg_5ghz =
3653 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3654 pCap->num_antcfg_2ghz =
3655 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3656
3657 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3658 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3659 ah->btactive_gpio = 6;
3660 ah->wlanactive_gpio = 5;
3661 }
3662 }
3663
3664 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3665 u32 capability, u32 *result)
3666 {
3667 switch (type) {
3668 case ATH9K_CAP_CIPHER:
3669 switch (capability) {
3670 case ATH9K_CIPHER_AES_CCM:
3671 case ATH9K_CIPHER_AES_OCB:
3672 case ATH9K_CIPHER_TKIP:
3673 case ATH9K_CIPHER_WEP:
3674 case ATH9K_CIPHER_MIC:
3675 case ATH9K_CIPHER_CLR:
3676 return true;
3677 default:
3678 return false;
3679 }
3680 case ATH9K_CAP_TKIP_MIC:
3681 switch (capability) {
3682 case 0:
3683 return true;
3684 case 1:
3685 return (ah->sta_id1_defaults &
3686 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3687 false;
3688 }
3689 case ATH9K_CAP_TKIP_SPLIT:
3690 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3691 false : true;
3692 case ATH9K_CAP_DIVERSITY:
3693 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3694 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3695 true : false;
3696 case ATH9K_CAP_MCAST_KEYSRCH:
3697 switch (capability) {
3698 case 0:
3699 return true;
3700 case 1:
3701 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3702 return false;
3703 } else {
3704 return (ah->sta_id1_defaults &
3705 AR_STA_ID1_MCAST_KSRCH) ? true :
3706 false;
3707 }
3708 }
3709 return false;
3710 case ATH9K_CAP_TXPOW:
3711 switch (capability) {
3712 case 0:
3713 return 0;
3714 case 1:
3715 *result = ah->regulatory.power_limit;
3716 return 0;
3717 case 2:
3718 *result = ah->regulatory.max_power_level;
3719 return 0;
3720 case 3:
3721 *result = ah->regulatory.tp_scale;
3722 return 0;
3723 }
3724 return false;
3725 case ATH9K_CAP_DS:
3726 return (AR_SREV_9280_20_OR_LATER(ah) &&
3727 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3728 ? false : true;
3729 default:
3730 return false;
3731 }
3732 }
3733
3734 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3735 u32 capability, u32 setting, int *status)
3736 {
3737 u32 v;
3738
3739 switch (type) {
3740 case ATH9K_CAP_TKIP_MIC:
3741 if (setting)
3742 ah->sta_id1_defaults |=
3743 AR_STA_ID1_CRPT_MIC_ENABLE;
3744 else
3745 ah->sta_id1_defaults &=
3746 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3747 return true;
3748 case ATH9K_CAP_DIVERSITY:
3749 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3750 if (setting)
3751 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3752 else
3753 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3754 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3755 return true;
3756 case ATH9K_CAP_MCAST_KEYSRCH:
3757 if (setting)
3758 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3759 else
3760 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3761 return true;
3762 default:
3763 return false;
3764 }
3765 }
3766
3767 /****************************/
3768 /* GPIO / RFKILL / Antennae */
3769 /****************************/
3770
3771 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3772 u32 gpio, u32 type)
3773 {
3774 int addr;
3775 u32 gpio_shift, tmp;
3776
3777 if (gpio > 11)
3778 addr = AR_GPIO_OUTPUT_MUX3;
3779 else if (gpio > 5)
3780 addr = AR_GPIO_OUTPUT_MUX2;
3781 else
3782 addr = AR_GPIO_OUTPUT_MUX1;
3783
3784 gpio_shift = (gpio % 6) * 5;
3785
3786 if (AR_SREV_9280_20_OR_LATER(ah)
3787 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3788 REG_RMW(ah, addr, (type << gpio_shift),
3789 (0x1f << gpio_shift));
3790 } else {
3791 tmp = REG_READ(ah, addr);
3792 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3793 tmp &= ~(0x1f << gpio_shift);
3794 tmp |= (type << gpio_shift);
3795 REG_WRITE(ah, addr, tmp);
3796 }
3797 }
3798
3799 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3800 {
3801 u32 gpio_shift;
3802
3803 ASSERT(gpio < ah->caps.num_gpio_pins);
3804
3805 gpio_shift = gpio << 1;
3806
3807 REG_RMW(ah,
3808 AR_GPIO_OE_OUT,
3809 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3810 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3811 }
3812
3813 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3814 {
3815 #define MS_REG_READ(x, y) \
3816 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3817
3818 if (gpio >= ah->caps.num_gpio_pins)
3819 return 0xffffffff;
3820
3821 if (AR_SREV_9287_10_OR_LATER(ah))
3822 return MS_REG_READ(AR9287, gpio) != 0;
3823 else if (AR_SREV_9285_10_OR_LATER(ah))
3824 return MS_REG_READ(AR9285, gpio) != 0;
3825 else if (AR_SREV_9280_10_OR_LATER(ah))
3826 return MS_REG_READ(AR928X, gpio) != 0;
3827 else
3828 return MS_REG_READ(AR, gpio) != 0;
3829 }
3830
3831 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3832 u32 ah_signal_type)
3833 {
3834 u32 gpio_shift;
3835
3836 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3837
3838 gpio_shift = 2 * gpio;
3839
3840 REG_RMW(ah,
3841 AR_GPIO_OE_OUT,
3842 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3843 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3844 }
3845
3846 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3847 {
3848 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3849 AR_GPIO_BIT(gpio));
3850 }
3851
3852 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3853 {
3854 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3855 }
3856
3857 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3858 {
3859 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3860 }
3861
3862 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3863 enum ath9k_ant_setting settings,
3864 struct ath9k_channel *chan,
3865 u8 *tx_chainmask,
3866 u8 *rx_chainmask,
3867 u8 *antenna_cfgd)
3868 {
3869 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3870
3871 if (AR_SREV_9280(ah)) {
3872 if (!tx_chainmask_cfg) {
3873
3874 tx_chainmask_cfg = *tx_chainmask;
3875 rx_chainmask_cfg = *rx_chainmask;
3876 }
3877
3878 switch (settings) {
3879 case ATH9K_ANT_FIXED_A:
3880 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3881 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3882 *antenna_cfgd = true;
3883 break;
3884 case ATH9K_ANT_FIXED_B:
3885 if (ah->caps.tx_chainmask >
3886 ATH9K_ANTENNA1_CHAINMASK) {
3887 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3888 }
3889 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3890 *antenna_cfgd = true;
3891 break;
3892 case ATH9K_ANT_VARIABLE:
3893 *tx_chainmask = tx_chainmask_cfg;
3894 *rx_chainmask = rx_chainmask_cfg;
3895 *antenna_cfgd = true;
3896 break;
3897 default:
3898 break;
3899 }
3900 } else {
3901 ah->config.diversity_control = settings;
3902 }
3903
3904 return true;
3905 }
3906
3907 /*********************/
3908 /* General Operation */
3909 /*********************/
3910
3911 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3912 {
3913 u32 bits = REG_READ(ah, AR_RX_FILTER);
3914 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3915
3916 if (phybits & AR_PHY_ERR_RADAR)
3917 bits |= ATH9K_RX_FILTER_PHYRADAR;
3918 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3919 bits |= ATH9K_RX_FILTER_PHYERR;
3920
3921 return bits;
3922 }
3923
3924 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3925 {
3926 u32 phybits;
3927
3928 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3929 phybits = 0;
3930 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3931 phybits |= AR_PHY_ERR_RADAR;
3932 if (bits & ATH9K_RX_FILTER_PHYERR)
3933 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3934 REG_WRITE(ah, AR_PHY_ERR, phybits);
3935
3936 if (phybits)
3937 REG_WRITE(ah, AR_RXCFG,
3938 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3939 else
3940 REG_WRITE(ah, AR_RXCFG,
3941 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3942 }
3943
3944 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3945 {
3946 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3947 }
3948
3949 bool ath9k_hw_disable(struct ath_hw *ah)
3950 {
3951 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3952 return false;
3953
3954 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3955 }
3956
3957 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3958 {
3959 struct ath9k_channel *chan = ah->curchan;
3960 struct ieee80211_channel *channel = chan->chan;
3961
3962 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3963
3964 ah->eep_ops->set_txpower(ah, chan,
3965 ath9k_regd_get_ctl(&ah->regulatory, chan),
3966 channel->max_antenna_gain * 2,
3967 channel->max_power * 2,
3968 min((u32) MAX_RATE_POWER,
3969 (u32) ah->regulatory.power_limit));
3970 }
3971
3972 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3973 {
3974 memcpy(ah->macaddr, mac, ETH_ALEN);
3975 }
3976
3977 void ath9k_hw_setopmode(struct ath_hw *ah)
3978 {
3979 ath9k_hw_set_operating_mode(ah, ah->opmode);
3980 }
3981
3982 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3983 {
3984 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3985 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3986 }
3987
3988 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3989 {
3990 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3991 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3992 }
3993
3994 void ath9k_hw_write_associd(struct ath_softc *sc)
3995 {
3996 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3997 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3998 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3999 }
4000
4001 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4002 {
4003 u64 tsf;
4004
4005 tsf = REG_READ(ah, AR_TSF_U32);
4006 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4007
4008 return tsf;
4009 }
4010
4011 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4012 {
4013 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4014 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4015 }
4016
4017 void ath9k_hw_reset_tsf(struct ath_hw *ah)
4018 {
4019 ath9k_ps_wakeup(ah->ah_sc);
4020 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4021 AH_TSF_WRITE_TIMEOUT))
4022 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
4023 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4024
4025 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4026 ath9k_ps_restore(ah->ah_sc);
4027 }
4028
4029 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4030 {
4031 if (setting)
4032 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
4033 else
4034 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4035 }
4036
4037 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4038 {
4039 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4040 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
4041 ah->slottime = (u32) -1;
4042 return false;
4043 } else {
4044 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4045 ah->slottime = us;
4046 return true;
4047 }
4048 }
4049
4050 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
4051 {
4052 u32 macmode;
4053
4054 if (mode == ATH9K_HT_MACMODE_2040 &&
4055 !ah->config.cwm_ignore_extcca)
4056 macmode = AR_2040_JOINED_RX_CLEAR;
4057 else
4058 macmode = 0;
4059
4060 REG_WRITE(ah, AR_2040_MODE, macmode);
4061 }
4062
4063 /***************************/
4064 /* Bluetooth Coexistence */
4065 /***************************/
4066
4067 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
4068 {
4069 /* connect bt_active to baseband */
4070 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
4071 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
4072 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
4073
4074 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
4075 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
4076
4077 /* Set input mux for bt_active to gpio pin */
4078 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
4079 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
4080 ah->btactive_gpio);
4081
4082 /* Configure the desired gpio port for input */
4083 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
4084
4085 /* Configure the desired GPIO port for TX_FRAME output */
4086 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
4087 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
4088 }
Linux kernel - Deliverables
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