2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
29 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
30 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
31 struct ar5416_eeprom_def
*pEepData
,
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
39 static int __init
ath9k_init(void)
43 module_init(ath9k_init
);
45 static void __exit
ath9k_exit(void)
49 module_exit(ath9k_exit
);
51 /********************/
52 /* Helper Functions */
53 /********************/
55 static u32
ath9k_hw_mac_clks(struct ath_hw
*ah
, u32 usecs
)
57 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
59 if (!ah
->curchan
) /* should really check for CCK instead */
60 return usecs
*ATH9K_CLOCK_RATE_CCK
;
61 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
62 return usecs
*ATH9K_CLOCK_RATE_2GHZ_OFDM
;
63 return usecs
*ATH9K_CLOCK_RATE_5GHZ_OFDM
;
66 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
68 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
70 if (conf_is_ht40(conf
))
71 return ath9k_hw_mac_clks(ah
, usecs
) * 2;
73 return ath9k_hw_mac_clks(ah
, usecs
);
76 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
80 BUG_ON(timeout
< AH_TIME_QUANTUM
);
82 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
83 if ((REG_READ(ah
, reg
) & mask
) == val
)
86 udelay(AH_TIME_QUANTUM
);
89 ath_print(ath9k_hw_common(ah
), ATH_DBG_ANY
,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
95 EXPORT_SYMBOL(ath9k_hw_wait
);
97 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
102 for (i
= 0, retval
= 0; i
< n
; i
++) {
103 retval
= (retval
<< 1) | (val
& 1);
109 bool ath9k_get_channel_edges(struct ath_hw
*ah
,
113 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
115 if (flags
& CHANNEL_5GHZ
) {
116 *low
= pCap
->low_5ghz_chan
;
117 *high
= pCap
->high_5ghz_chan
;
120 if ((flags
& CHANNEL_2GHZ
)) {
121 *low
= pCap
->low_2ghz_chan
;
122 *high
= pCap
->high_2ghz_chan
;
128 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
130 u32 frameLen
, u16 rateix
,
133 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
139 case WLAN_RC_PHY_CCK
:
140 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
143 numBits
= frameLen
<< 3;
144 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
146 case WLAN_RC_PHY_OFDM
:
147 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
148 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
149 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
150 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
151 txTime
= OFDM_SIFS_TIME_QUARTER
152 + OFDM_PREAMBLE_TIME_QUARTER
153 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
154 } else if (ah
->curchan
&&
155 IS_CHAN_HALF_RATE(ah
->curchan
)) {
156 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
157 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
158 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
159 txTime
= OFDM_SIFS_TIME_HALF
+
160 OFDM_PREAMBLE_TIME_HALF
161 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
163 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
164 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
165 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
166 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
167 + (numSymbols
* OFDM_SYMBOL_TIME
);
171 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
172 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
179 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
181 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
182 struct ath9k_channel
*chan
,
183 struct chan_centers
*centers
)
187 if (!IS_CHAN_HT40(chan
)) {
188 centers
->ctl_center
= centers
->ext_center
=
189 centers
->synth_center
= chan
->channel
;
193 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
194 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
195 centers
->synth_center
=
196 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
199 centers
->synth_center
=
200 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
204 centers
->ctl_center
=
205 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
206 /* 25 MHz spacing is supported by hw but not on upper layers */
207 centers
->ext_center
=
208 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
215 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
219 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
222 val
= REG_READ(ah
, AR_SREV
);
223 ah
->hw_version
.macVersion
=
224 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
225 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
226 ah
->is_pciexpress
= (val
& AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
228 if (!AR_SREV_9100(ah
))
229 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
231 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
233 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
234 ah
->is_pciexpress
= true;
238 static int ath9k_hw_get_radiorev(struct ath_hw
*ah
)
243 REG_WRITE(ah
, AR_PHY(0x36), 0x00007058);
245 for (i
= 0; i
< 8; i
++)
246 REG_WRITE(ah
, AR_PHY(0x20), 0x00010000);
247 val
= (REG_READ(ah
, AR_PHY(256)) >> 24) & 0xff;
248 val
= ((val
& 0xf0) >> 4) | ((val
& 0x0f) << 4);
250 return ath9k_hw_reverse_bits(val
, 8);
253 /************************************/
254 /* HW Attach, Detach, Init Routines */
255 /************************************/
257 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
259 if (AR_SREV_9100(ah
))
262 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
263 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
264 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
265 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
266 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
267 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
268 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
269 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
270 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
272 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
275 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
277 struct ath_common
*common
= ath9k_hw_common(ah
);
278 u32 regAddr
[2] = { AR_STA_ID0
, AR_PHY_BASE
+ (8 << 2) };
280 u32 patternData
[4] = { 0x55555555,
286 for (i
= 0; i
< 2; i
++) {
287 u32 addr
= regAddr
[i
];
290 regHold
[i
] = REG_READ(ah
, addr
);
291 for (j
= 0; j
< 0x100; j
++) {
292 wrData
= (j
<< 16) | j
;
293 REG_WRITE(ah
, addr
, wrData
);
294 rdData
= REG_READ(ah
, addr
);
295 if (rdData
!= wrData
) {
296 ath_print(common
, ATH_DBG_FATAL
,
297 "address test failed "
298 "addr: 0x%08x - wr:0x%08x != "
300 addr
, wrData
, rdData
);
304 for (j
= 0; j
< 4; j
++) {
305 wrData
= patternData
[j
];
306 REG_WRITE(ah
, addr
, wrData
);
307 rdData
= REG_READ(ah
, addr
);
308 if (wrData
!= rdData
) {
309 ath_print(common
, ATH_DBG_FATAL
,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != "
313 addr
, wrData
, rdData
);
317 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
324 static void ath9k_hw_init_config(struct ath_hw
*ah
)
328 ah
->config
.dma_beacon_response_time
= 2;
329 ah
->config
.sw_beacon_response_time
= 10;
330 ah
->config
.additional_swba_backoff
= 0;
331 ah
->config
.ack_6mb
= 0x0;
332 ah
->config
.cwm_ignore_extcca
= 0;
333 ah
->config
.pcie_powersave_enable
= 0;
334 ah
->config
.pcie_clock_req
= 0;
335 ah
->config
.pcie_waen
= 0;
336 ah
->config
.analog_shiftreg
= 1;
337 ah
->config
.ofdm_trig_low
= 200;
338 ah
->config
.ofdm_trig_high
= 500;
339 ah
->config
.cck_trig_high
= 200;
340 ah
->config
.cck_trig_low
= 100;
341 ah
->config
.enable_ani
= 1;
343 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
344 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
345 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
348 if (ah
->hw_version
.devid
!= AR2427_DEVID_PCIE
)
349 ah
->config
.ht_enable
= 1;
351 ah
->config
.ht_enable
= 0;
353 ah
->config
.rx_intr_mitigation
= true;
356 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
357 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
358 * This means we use it for all AR5416 devices, and the few
359 * minor PCI AR9280 devices out there.
361 * Serialization is required because these devices do not handle
362 * well the case of two concurrent reads/writes due to the latency
363 * involved. During one read/write another read/write can be issued
364 * on another CPU while the previous read/write may still be working
365 * on our hardware, if we hit this case the hardware poops in a loop.
366 * We prevent this by serializing reads and writes.
368 * This issue is not present on PCI-Express devices or pre-AR5416
369 * devices (legacy, 802.11abg).
371 if (num_possible_cpus() > 1)
372 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
374 EXPORT_SYMBOL(ath9k_hw_init
);
376 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
378 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
380 regulatory
->country_code
= CTRY_DEFAULT
;
381 regulatory
->power_limit
= MAX_RATE_POWER
;
382 regulatory
->tp_scale
= ATH9K_TP_SCALE_MAX
;
384 ah
->hw_version
.magic
= AR5416_MAGIC
;
385 ah
->hw_version
.subvendorid
= 0;
388 if (ah
->hw_version
.devid
== AR5416_AR9100_DEVID
)
389 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
390 if (!AR_SREV_9100(ah
))
391 ah
->ah_flags
= AH_USE_EEPROM
;
394 ah
->sta_id1_defaults
= AR_STA_ID1_CRPT_MIC_ENABLE
;
395 ah
->beacon_interval
= 100;
396 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
397 ah
->slottime
= (u32
) -1;
398 ah
->globaltxtimeout
= (u32
) -1;
399 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
402 static int ath9k_hw_rf_claim(struct ath_hw
*ah
)
406 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
408 val
= ath9k_hw_get_radiorev(ah
);
409 switch (val
& AR_RADIO_SREV_MAJOR
) {
411 val
= AR_RAD5133_SREV_MAJOR
;
413 case AR_RAD5133_SREV_MAJOR
:
414 case AR_RAD5122_SREV_MAJOR
:
415 case AR_RAD2133_SREV_MAJOR
:
416 case AR_RAD2122_SREV_MAJOR
:
419 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
420 "Radio Chip Rev 0x%02X not supported\n",
421 val
& AR_RADIO_SREV_MAJOR
);
425 ah
->hw_version
.analog5GhzRev
= val
;
430 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
432 struct ath_common
*common
= ath9k_hw_common(ah
);
438 for (i
= 0; i
< 3; i
++) {
439 eeval
= ah
->eep_ops
->get_eeprom(ah
, AR_EEPROM_MAC(i
));
441 common
->macaddr
[2 * i
] = eeval
>> 8;
442 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
444 if (sum
== 0 || sum
== 0xffff * 3)
445 return -EADDRNOTAVAIL
;
450 static void ath9k_hw_init_rxgain_ini(struct ath_hw
*ah
)
454 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_17
) {
455 rxgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_RXGAIN_TYPE
);
457 if (rxgain_type
== AR5416_EEP_RXGAIN_13DB_BACKOFF
)
458 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
459 ar9280Modes_backoff_13db_rxgain_9280_2
,
460 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2
), 6);
461 else if (rxgain_type
== AR5416_EEP_RXGAIN_23DB_BACKOFF
)
462 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
463 ar9280Modes_backoff_23db_rxgain_9280_2
,
464 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2
), 6);
466 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
467 ar9280Modes_original_rxgain_9280_2
,
468 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
470 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
471 ar9280Modes_original_rxgain_9280_2
,
472 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
476 static void ath9k_hw_init_txgain_ini(struct ath_hw
*ah
)
480 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_19
) {
481 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
483 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
)
484 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
485 ar9280Modes_high_power_tx_gain_9280_2
,
486 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2
), 6);
488 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
489 ar9280Modes_original_tx_gain_9280_2
,
490 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
492 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
493 ar9280Modes_original_tx_gain_9280_2
,
494 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
498 static int ath9k_hw_post_init(struct ath_hw
*ah
)
502 if (!AR_SREV_9271(ah
)) {
503 if (!ath9k_hw_chip_test(ah
))
507 ecode
= ath9k_hw_rf_claim(ah
);
511 ecode
= ath9k_hw_eeprom_init(ah
);
515 ath_print(ath9k_hw_common(ah
), ATH_DBG_CONFIG
,
516 "Eeprom VER: %d, REV: %d\n",
517 ah
->eep_ops
->get_eeprom_ver(ah
),
518 ah
->eep_ops
->get_eeprom_rev(ah
));
520 if (!AR_SREV_9280_10_OR_LATER(ah
)) {
521 ecode
= ath9k_hw_rf_alloc_ext_banks(ah
);
523 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
524 "Failed allocating banks for "
530 if (!AR_SREV_9100(ah
)) {
531 ath9k_hw_ani_setup(ah
);
532 ath9k_hw_ani_init(ah
);
538 static bool ath9k_hw_devid_supported(u16 devid
)
541 case AR5416_DEVID_PCI
:
542 case AR5416_DEVID_PCIE
:
543 case AR5416_AR9100_DEVID
:
544 case AR9160_DEVID_PCI
:
545 case AR9280_DEVID_PCI
:
546 case AR9280_DEVID_PCIE
:
547 case AR9285_DEVID_PCIE
:
548 case AR5416_DEVID_AR9287_PCI
:
549 case AR5416_DEVID_AR9287_PCIE
:
551 case AR2427_DEVID_PCIE
:
559 static bool ath9k_hw_macversion_supported(u32 macversion
)
561 switch (macversion
) {
562 case AR_SREV_VERSION_5416_PCI
:
563 case AR_SREV_VERSION_5416_PCIE
:
564 case AR_SREV_VERSION_9160
:
565 case AR_SREV_VERSION_9100
:
566 case AR_SREV_VERSION_9280
:
567 case AR_SREV_VERSION_9285
:
568 case AR_SREV_VERSION_9287
:
569 case AR_SREV_VERSION_9271
:
577 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
579 if (AR_SREV_9160_10_OR_LATER(ah
)) {
580 if (AR_SREV_9280_10_OR_LATER(ah
)) {
581 ah
->iq_caldata
.calData
= &iq_cal_single_sample
;
582 ah
->adcgain_caldata
.calData
=
583 &adc_gain_cal_single_sample
;
584 ah
->adcdc_caldata
.calData
=
585 &adc_dc_cal_single_sample
;
586 ah
->adcdc_calinitdata
.calData
=
589 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
590 ah
->adcgain_caldata
.calData
=
591 &adc_gain_cal_multi_sample
;
592 ah
->adcdc_caldata
.calData
=
593 &adc_dc_cal_multi_sample
;
594 ah
->adcdc_calinitdata
.calData
=
597 ah
->supp_cals
= ADC_GAIN_CAL
| ADC_DC_CAL
| IQ_MISMATCH_CAL
;
601 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
603 if (AR_SREV_9271(ah
)) {
604 INIT_INI_ARRAY(&ah
->iniModes
, ar9271Modes_9271
,
605 ARRAY_SIZE(ar9271Modes_9271
), 6);
606 INIT_INI_ARRAY(&ah
->iniCommon
, ar9271Common_9271
,
607 ARRAY_SIZE(ar9271Common_9271
), 2);
608 INIT_INI_ARRAY(&ah
->iniCommon_normal_cck_fir_coeff_9271
,
609 ar9271Common_normal_cck_fir_coeff_9271
,
610 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271
), 2);
611 INIT_INI_ARRAY(&ah
->iniCommon_japan_2484_cck_fir_coeff_9271
,
612 ar9271Common_japan_2484_cck_fir_coeff_9271
,
613 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271
), 2);
614 INIT_INI_ARRAY(&ah
->iniModes_9271_1_0_only
,
615 ar9271Modes_9271_1_0_only
,
616 ARRAY_SIZE(ar9271Modes_9271_1_0_only
), 6);
617 INIT_INI_ARRAY(&ah
->iniModes_9271_ANI_reg
, ar9271Modes_9271_ANI_reg
,
618 ARRAY_SIZE(ar9271Modes_9271_ANI_reg
), 6);
619 INIT_INI_ARRAY(&ah
->iniModes_high_power_tx_gain_9271
,
620 ar9271Modes_high_power_tx_gain_9271
,
621 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271
), 6);
622 INIT_INI_ARRAY(&ah
->iniModes_normal_power_tx_gain_9271
,
623 ar9271Modes_normal_power_tx_gain_9271
,
624 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271
), 6);
628 if (AR_SREV_9287_11_OR_LATER(ah
)) {
629 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_1
,
630 ARRAY_SIZE(ar9287Modes_9287_1_1
), 6);
631 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_1
,
632 ARRAY_SIZE(ar9287Common_9287_1_1
), 2);
633 if (ah
->config
.pcie_clock_req
)
634 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
635 ar9287PciePhy_clkreq_off_L1_9287_1_1
,
636 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1
), 2);
638 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
639 ar9287PciePhy_clkreq_always_on_L1_9287_1_1
,
640 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1
),
642 } else if (AR_SREV_9287_10_OR_LATER(ah
)) {
643 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_0
,
644 ARRAY_SIZE(ar9287Modes_9287_1_0
), 6);
645 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_0
,
646 ARRAY_SIZE(ar9287Common_9287_1_0
), 2);
648 if (ah
->config
.pcie_clock_req
)
649 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
650 ar9287PciePhy_clkreq_off_L1_9287_1_0
,
651 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0
), 2);
653 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
654 ar9287PciePhy_clkreq_always_on_L1_9287_1_0
,
655 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0
),
657 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
660 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285_1_2
,
661 ARRAY_SIZE(ar9285Modes_9285_1_2
), 6);
662 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285_1_2
,
663 ARRAY_SIZE(ar9285Common_9285_1_2
), 2);
665 if (ah
->config
.pcie_clock_req
) {
666 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
667 ar9285PciePhy_clkreq_off_L1_9285_1_2
,
668 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2
), 2);
670 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
671 ar9285PciePhy_clkreq_always_on_L1_9285_1_2
,
672 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2
),
675 } else if (AR_SREV_9285_10_OR_LATER(ah
)) {
676 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285
,
677 ARRAY_SIZE(ar9285Modes_9285
), 6);
678 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285
,
679 ARRAY_SIZE(ar9285Common_9285
), 2);
681 if (ah
->config
.pcie_clock_req
) {
682 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
683 ar9285PciePhy_clkreq_off_L1_9285
,
684 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285
), 2);
686 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
687 ar9285PciePhy_clkreq_always_on_L1_9285
,
688 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285
), 2);
690 } else if (AR_SREV_9280_20_OR_LATER(ah
)) {
691 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280_2
,
692 ARRAY_SIZE(ar9280Modes_9280_2
), 6);
693 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280_2
,
694 ARRAY_SIZE(ar9280Common_9280_2
), 2);
696 if (ah
->config
.pcie_clock_req
) {
697 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
698 ar9280PciePhy_clkreq_off_L1_9280
,
699 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280
),2);
701 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
702 ar9280PciePhy_clkreq_always_on_L1_9280
,
703 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280
), 2);
705 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
706 ar9280Modes_fast_clock_9280_2
,
707 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2
), 3);
708 } else if (AR_SREV_9280_10_OR_LATER(ah
)) {
709 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280
,
710 ARRAY_SIZE(ar9280Modes_9280
), 6);
711 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280
,
712 ARRAY_SIZE(ar9280Common_9280
), 2);
713 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
714 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9160
,
715 ARRAY_SIZE(ar5416Modes_9160
), 6);
716 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9160
,
717 ARRAY_SIZE(ar5416Common_9160
), 2);
718 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9160
,
719 ARRAY_SIZE(ar5416Bank0_9160
), 2);
720 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9160
,
721 ARRAY_SIZE(ar5416BB_RfGain_9160
), 3);
722 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9160
,
723 ARRAY_SIZE(ar5416Bank1_9160
), 2);
724 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9160
,
725 ARRAY_SIZE(ar5416Bank2_9160
), 2);
726 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9160
,
727 ARRAY_SIZE(ar5416Bank3_9160
), 3);
728 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9160
,
729 ARRAY_SIZE(ar5416Bank6_9160
), 3);
730 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9160
,
731 ARRAY_SIZE(ar5416Bank6TPC_9160
), 3);
732 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9160
,
733 ARRAY_SIZE(ar5416Bank7_9160
), 2);
734 if (AR_SREV_9160_11(ah
)) {
735 INIT_INI_ARRAY(&ah
->iniAddac
,
737 ARRAY_SIZE(ar5416Addac_91601_1
), 2);
739 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9160
,
740 ARRAY_SIZE(ar5416Addac_9160
), 2);
742 } else if (AR_SREV_9100_OR_LATER(ah
)) {
743 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9100
,
744 ARRAY_SIZE(ar5416Modes_9100
), 6);
745 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9100
,
746 ARRAY_SIZE(ar5416Common_9100
), 2);
747 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9100
,
748 ARRAY_SIZE(ar5416Bank0_9100
), 2);
749 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9100
,
750 ARRAY_SIZE(ar5416BB_RfGain_9100
), 3);
751 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9100
,
752 ARRAY_SIZE(ar5416Bank1_9100
), 2);
753 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9100
,
754 ARRAY_SIZE(ar5416Bank2_9100
), 2);
755 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9100
,
756 ARRAY_SIZE(ar5416Bank3_9100
), 3);
757 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9100
,
758 ARRAY_SIZE(ar5416Bank6_9100
), 3);
759 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9100
,
760 ARRAY_SIZE(ar5416Bank6TPC_9100
), 3);
761 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9100
,
762 ARRAY_SIZE(ar5416Bank7_9100
), 2);
763 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9100
,
764 ARRAY_SIZE(ar5416Addac_9100
), 2);
766 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes
,
767 ARRAY_SIZE(ar5416Modes
), 6);
768 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common
,
769 ARRAY_SIZE(ar5416Common
), 2);
770 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0
,
771 ARRAY_SIZE(ar5416Bank0
), 2);
772 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain
,
773 ARRAY_SIZE(ar5416BB_RfGain
), 3);
774 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1
,
775 ARRAY_SIZE(ar5416Bank1
), 2);
776 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2
,
777 ARRAY_SIZE(ar5416Bank2
), 2);
778 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3
,
779 ARRAY_SIZE(ar5416Bank3
), 3);
780 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6
,
781 ARRAY_SIZE(ar5416Bank6
), 3);
782 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC
,
783 ARRAY_SIZE(ar5416Bank6TPC
), 3);
784 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7
,
785 ARRAY_SIZE(ar5416Bank7
), 2);
786 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac
,
787 ARRAY_SIZE(ar5416Addac
), 2);
791 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
793 if (AR_SREV_9287_11_OR_LATER(ah
))
794 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
795 ar9287Modes_rx_gain_9287_1_1
,
796 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1
), 6);
797 else if (AR_SREV_9287_10(ah
))
798 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
799 ar9287Modes_rx_gain_9287_1_0
,
800 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0
), 6);
801 else if (AR_SREV_9280_20(ah
))
802 ath9k_hw_init_rxgain_ini(ah
);
804 if (AR_SREV_9287_11_OR_LATER(ah
)) {
805 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
806 ar9287Modes_tx_gain_9287_1_1
,
807 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1
), 6);
808 } else if (AR_SREV_9287_10(ah
)) {
809 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
810 ar9287Modes_tx_gain_9287_1_0
,
811 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0
), 6);
812 } else if (AR_SREV_9280_20(ah
)) {
813 ath9k_hw_init_txgain_ini(ah
);
814 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
815 u32 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
818 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
) {
819 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
820 ar9285Modes_high_power_tx_gain_9285_1_2
,
821 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2
), 6);
823 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
824 ar9285Modes_original_tx_gain_9285_1_2
,
825 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2
), 6);
831 static void ath9k_hw_init_eeprom_fix(struct ath_hw
*ah
)
835 if (ah
->hw_version
.devid
== AR9280_DEVID_PCI
) {
838 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
839 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
841 for (j
= 1; j
< ah
->iniModes
.ia_columns
; j
++) {
842 u32 val
= INI_RA(&ah
->iniModes
, i
, j
);
844 INI_RA(&ah
->iniModes
, i
, j
) =
845 ath9k_hw_ini_fixup(ah
,
853 int ath9k_hw_init(struct ath_hw
*ah
)
855 struct ath_common
*common
= ath9k_hw_common(ah
);
858 if (!ath9k_hw_devid_supported(ah
->hw_version
.devid
)) {
859 ath_print(common
, ATH_DBG_FATAL
,
860 "Unsupported device ID: 0x%0x\n",
861 ah
->hw_version
.devid
);
865 ath9k_hw_init_defaults(ah
);
866 ath9k_hw_init_config(ah
);
868 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
869 ath_print(common
, ATH_DBG_FATAL
,
870 "Couldn't reset chip\n");
874 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
875 ath_print(common
, ATH_DBG_FATAL
, "Couldn't wakeup chip\n");
879 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
880 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
881 (AR_SREV_9280(ah
) && !ah
->is_pciexpress
)) {
882 ah
->config
.serialize_regmode
=
885 ah
->config
.serialize_regmode
=
890 ath_print(common
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
891 ah
->config
.serialize_regmode
);
893 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
894 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
896 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
898 if (!ath9k_hw_macversion_supported(ah
->hw_version
.macVersion
)) {
899 ath_print(common
, ATH_DBG_FATAL
,
900 "Mac Chip Rev 0x%02x.%x is not supported by "
901 "this driver\n", ah
->hw_version
.macVersion
,
902 ah
->hw_version
.macRev
);
906 if (AR_SREV_9100(ah
)) {
907 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
908 ah
->supp_cals
= IQ_MISMATCH_CAL
;
909 ah
->is_pciexpress
= false;
912 if (AR_SREV_9271(ah
))
913 ah
->is_pciexpress
= false;
915 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
917 ath9k_hw_init_cal_settings(ah
);
919 ah
->ani_function
= ATH9K_ANI_ALL
;
920 if (AR_SREV_9280_10_OR_LATER(ah
)) {
921 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
922 ah
->ath9k_hw_rf_set_freq
= &ath9k_hw_ar9280_set_channel
;
923 ah
->ath9k_hw_spur_mitigate_freq
= &ath9k_hw_9280_spur_mitigate
;
925 ah
->ath9k_hw_rf_set_freq
= &ath9k_hw_set_channel
;
926 ah
->ath9k_hw_spur_mitigate_freq
= &ath9k_hw_spur_mitigate
;
929 ath9k_hw_init_mode_regs(ah
);
931 if (ah
->is_pciexpress
)
932 ath9k_hw_configpcipowersave(ah
, 0, 0);
934 ath9k_hw_disablepcie(ah
);
936 /* Support for Japan ch.14 (2484) spread */
937 if (AR_SREV_9287_11_OR_LATER(ah
)) {
938 INIT_INI_ARRAY(&ah
->iniCckfirNormal
,
939 ar9287Common_normal_cck_fir_coeff_92871_1
,
940 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1
), 2);
941 INIT_INI_ARRAY(&ah
->iniCckfirJapan2484
,
942 ar9287Common_japan_2484_cck_fir_coeff_92871_1
,
943 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1
), 2);
946 r
= ath9k_hw_post_init(ah
);
950 ath9k_hw_init_mode_gain_regs(ah
);
951 r
= ath9k_hw_fill_cap_info(ah
);
955 ath9k_hw_init_eeprom_fix(ah
);
957 r
= ath9k_hw_init_macaddr(ah
);
959 ath_print(common
, ATH_DBG_FATAL
,
960 "Failed to initialize MAC address\n");
964 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
965 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
967 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
969 ath9k_init_nfcal_hist_buffer(ah
);
971 common
->state
= ATH_HW_INITIALIZED
;
976 static void ath9k_hw_init_bb(struct ath_hw
*ah
,
977 struct ath9k_channel
*chan
)
981 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
983 synthDelay
= (4 * synthDelay
) / 22;
987 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_EN
);
989 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
992 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
994 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
995 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
997 REG_WRITE(ah
, AR_QOS_NO_ACK
,
998 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
999 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
1000 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
1002 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
1003 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
1004 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
1005 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
1006 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
1009 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
1010 struct ath9k_channel
*chan
)
1014 if (AR_SREV_9100(ah
)) {
1015 if (chan
&& IS_CHAN_5GHZ(chan
))
1020 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1021 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
1023 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1024 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
1025 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1026 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
1028 if (chan
&& IS_CHAN_5GHZ(chan
)) {
1029 pll
|= SM(0x28, AR_RTC_9160_PLL_DIV
);
1032 if (AR_SREV_9280_20(ah
)) {
1033 if (((chan
->channel
% 20) == 0)
1034 || ((chan
->channel
% 10) == 0))
1040 pll
|= SM(0x2c, AR_RTC_9160_PLL_DIV
);
1043 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1045 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
1047 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1048 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
1049 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1050 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
1052 if (chan
&& IS_CHAN_5GHZ(chan
))
1053 pll
|= SM(0x50, AR_RTC_9160_PLL_DIV
);
1055 pll
|= SM(0x58, AR_RTC_9160_PLL_DIV
);
1057 pll
= AR_RTC_PLL_REFDIV_5
| AR_RTC_PLL_DIV2
;
1059 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1060 pll
|= SM(0x1, AR_RTC_PLL_CLKSEL
);
1061 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1062 pll
|= SM(0x2, AR_RTC_PLL_CLKSEL
);
1064 if (chan
&& IS_CHAN_5GHZ(chan
))
1065 pll
|= SM(0xa, AR_RTC_PLL_DIV
);
1067 pll
|= SM(0xb, AR_RTC_PLL_DIV
);
1070 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
1072 /* Switch the core clock for ar9271 to 117Mhz */
1073 if (AR_SREV_9271(ah
)) {
1075 REG_WRITE(ah
, 0x50040, 0x304);
1078 udelay(RTC_PLL_SETTLE_DELAY
);
1080 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
1083 static void ath9k_hw_init_chain_masks(struct ath_hw
*ah
)
1085 int rx_chainmask
, tx_chainmask
;
1087 rx_chainmask
= ah
->rxchainmask
;
1088 tx_chainmask
= ah
->txchainmask
;
1090 switch (rx_chainmask
) {
1092 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1093 AR_PHY_SWAP_ALT_CHAIN
);
1095 if (ah
->hw_version
.macVersion
== AR_SREV_REVISION_5416_10
) {
1096 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, 0x7);
1097 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, 0x7);
1103 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
1104 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
1110 REG_WRITE(ah
, AR_SELFGEN_MASK
, tx_chainmask
);
1111 if (tx_chainmask
== 0x5) {
1112 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1113 AR_PHY_SWAP_ALT_CHAIN
);
1115 if (AR_SREV_9100(ah
))
1116 REG_WRITE(ah
, AR_PHY_ANALOG_SWAP
,
1117 REG_READ(ah
, AR_PHY_ANALOG_SWAP
) | 0x00000001);
1120 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
1121 enum nl80211_iftype opmode
)
1123 ah
->mask_reg
= AR_IMR_TXERR
|
1129 if (ah
->config
.rx_intr_mitigation
)
1130 ah
->mask_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
1132 ah
->mask_reg
|= AR_IMR_RXOK
;
1134 ah
->mask_reg
|= AR_IMR_TXOK
;
1136 if (opmode
== NL80211_IFTYPE_AP
)
1137 ah
->mask_reg
|= AR_IMR_MIB
;
1139 REG_WRITE(ah
, AR_IMR
, ah
->mask_reg
);
1140 ah
->imrs2_reg
|= AR_IMR_S2_GTT
;
1141 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
1143 if (!AR_SREV_9100(ah
)) {
1144 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
1145 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, AR_INTR_SYNC_DEFAULT
);
1146 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
1150 static void ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
1152 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1153 val
= min(val
, (u32
) 0xFFFF);
1154 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, val
);
1157 static void ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
1159 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1160 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_ACK
));
1161 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK
, val
);
1164 static void ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
1166 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1167 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_CTS
));
1168 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_CTS
, val
);
1171 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
1174 ath_print(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
1175 "bad global tx timeout %u\n", tu
);
1176 ah
->globaltxtimeout
= (u32
) -1;
1179 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
1180 ah
->globaltxtimeout
= tu
;
1185 void ath9k_hw_init_global_settings(struct ath_hw
*ah
)
1187 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
1192 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
1195 if (ah
->misc_mode
!= 0)
1196 REG_WRITE(ah
, AR_PCU_MISC
,
1197 REG_READ(ah
, AR_PCU_MISC
) | ah
->misc_mode
);
1199 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_5GHZ
)
1204 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1205 slottime
= ah
->slottime
+ 3 * ah
->coverage_class
;
1206 acktimeout
= slottime
+ sifstime
;
1209 * Workaround for early ACK timeouts, add an offset to match the
1210 * initval's 64us ack timeout value.
1211 * This was initially only meant to work around an issue with delayed
1212 * BA frames in some implementations, but it has been found to fix ACK
1213 * timeout issues in other cases as well.
1215 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
1216 acktimeout
+= 64 - sifstime
- ah
->slottime
;
1218 ath9k_hw_setslottime(ah
, slottime
);
1219 ath9k_hw_set_ack_timeout(ah
, acktimeout
);
1220 ath9k_hw_set_cts_timeout(ah
, acktimeout
);
1221 if (ah
->globaltxtimeout
!= (u32
) -1)
1222 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1224 EXPORT_SYMBOL(ath9k_hw_init_global_settings
);
1226 void ath9k_hw_deinit(struct ath_hw
*ah
)
1228 struct ath_common
*common
= ath9k_hw_common(ah
);
1230 if (common
->state
<= ATH_HW_INITIALIZED
)
1233 if (!AR_SREV_9100(ah
))
1234 ath9k_hw_ani_disable(ah
);
1236 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1239 if (!AR_SREV_9280_10_OR_LATER(ah
))
1240 ath9k_hw_rf_free_ext_banks(ah
);
1244 EXPORT_SYMBOL(ath9k_hw_deinit
);
1250 static void ath9k_hw_override_ini(struct ath_hw
*ah
,
1251 struct ath9k_channel
*chan
)
1256 * Set the RX_ABORT and RX_DIS and clear if off only after
1257 * RXE is set for MAC. This prevents frames with corrupted
1258 * descriptor status.
1260 REG_SET_BIT(ah
, AR_DIAG_SW
, (AR_DIAG_RX_DIS
| AR_DIAG_RX_ABORT
));
1262 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1263 val
= REG_READ(ah
, AR_PCU_MISC_MODE2
);
1265 if (!AR_SREV_9271(ah
))
1266 val
&= ~AR_PCU_MISC_MODE2_HWWAR1
;
1268 if (AR_SREV_9287_10_OR_LATER(ah
))
1269 val
= val
& (~AR_PCU_MISC_MODE2_HWWAR2
);
1271 REG_WRITE(ah
, AR_PCU_MISC_MODE2
, val
);
1274 if (!AR_SREV_5416_20_OR_LATER(ah
) ||
1275 AR_SREV_9280_10_OR_LATER(ah
))
1278 * Disable BB clock gating
1279 * Necessary to avoid issues on AR5416 2.0
1281 REG_WRITE(ah
, 0x9800 + (651 << 2), 0x11);
1284 * Disable RIFS search on some chips to avoid baseband
1287 if (AR_SREV_9100(ah
) || AR_SREV_9160(ah
)) {
1288 val
= REG_READ(ah
, AR_PHY_HEAVY_CLIP_FACTOR_RIFS
);
1289 val
&= ~AR_PHY_RIFS_INIT_DELAY
;
1290 REG_WRITE(ah
, AR_PHY_HEAVY_CLIP_FACTOR_RIFS
, val
);
1294 static u32
ath9k_hw_def_ini_fixup(struct ath_hw
*ah
,
1295 struct ar5416_eeprom_def
*pEepData
,
1298 struct base_eep_header
*pBase
= &(pEepData
->baseEepHeader
);
1299 struct ath_common
*common
= ath9k_hw_common(ah
);
1301 switch (ah
->hw_version
.devid
) {
1302 case AR9280_DEVID_PCI
:
1303 if (reg
== 0x7894) {
1304 ath_print(common
, ATH_DBG_EEPROM
,
1305 "ini VAL: %x EEPROM: %x\n", value
,
1306 (pBase
->version
& 0xff));
1308 if ((pBase
->version
& 0xff) > 0x0a) {
1309 ath_print(common
, ATH_DBG_EEPROM
,
1312 value
&= ~AR_AN_TOP2_PWDCLKIND
;
1313 value
|= AR_AN_TOP2_PWDCLKIND
&
1314 (pBase
->pwdclkind
<< AR_AN_TOP2_PWDCLKIND_S
);
1316 ath_print(common
, ATH_DBG_EEPROM
,
1317 "PWDCLKIND Earlier Rev\n");
1320 ath_print(common
, ATH_DBG_EEPROM
,
1321 "final ini VAL: %x\n", value
);
1329 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
1330 struct ar5416_eeprom_def
*pEepData
,
1333 if (ah
->eep_map
== EEP_MAP_4KBITS
)
1336 return ath9k_hw_def_ini_fixup(ah
, pEepData
, reg
, value
);
1339 static void ath9k_olc_init(struct ath_hw
*ah
)
1343 if (OLC_FOR_AR9287_10_LATER
) {
1344 REG_SET_BIT(ah
, AR_PHY_TX_PWRCTRL9
,
1345 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL
);
1346 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_TXPC0
,
1347 AR9287_AN_TXPC0_TXPCMODE
,
1348 AR9287_AN_TXPC0_TXPCMODE_S
,
1349 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE
);
1352 for (i
= 0; i
< AR9280_TX_GAIN_TABLE_SIZE
; i
++)
1353 ah
->originalGain
[i
] =
1354 MS(REG_READ(ah
, AR_PHY_TX_GAIN_TBL1
+ i
* 4),
1360 static u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
,
1361 struct ath9k_channel
*chan
)
1363 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
1365 if (IS_CHAN_B(chan
))
1367 else if (IS_CHAN_G(chan
))
1375 static int ath9k_hw_process_ini(struct ath_hw
*ah
,
1376 struct ath9k_channel
*chan
)
1378 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1379 int i
, regWrites
= 0;
1380 struct ieee80211_channel
*channel
= chan
->chan
;
1381 u32 modesIndex
, freqIndex
;
1383 switch (chan
->chanmode
) {
1385 case CHANNEL_A_HT20
:
1389 case CHANNEL_A_HT40PLUS
:
1390 case CHANNEL_A_HT40MINUS
:
1395 case CHANNEL_G_HT20
:
1400 case CHANNEL_G_HT40PLUS
:
1401 case CHANNEL_G_HT40MINUS
:
1410 /* Set correct baseband to analog shift setting to access analog chips */
1411 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
1413 /* Write ADDAC shifts */
1414 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_EXTERNAL_RADIO
);
1415 ah
->eep_ops
->set_addac(ah
, chan
);
1417 if (AR_SREV_5416_22_OR_LATER(ah
)) {
1418 REG_WRITE_ARRAY(&ah
->iniAddac
, 1, regWrites
);
1420 struct ar5416IniArray temp
;
1422 sizeof(u32
) * ah
->iniAddac
.ia_rows
*
1423 ah
->iniAddac
.ia_columns
;
1425 /* For AR5416 2.0/2.1 */
1426 memcpy(ah
->addac5416_21
,
1427 ah
->iniAddac
.ia_array
, addacSize
);
1429 /* override CLKDRV value at [row, column] = [31, 1] */
1430 (ah
->addac5416_21
)[31 * ah
->iniAddac
.ia_columns
+ 1] = 0;
1432 temp
.ia_array
= ah
->addac5416_21
;
1433 temp
.ia_columns
= ah
->iniAddac
.ia_columns
;
1434 temp
.ia_rows
= ah
->iniAddac
.ia_rows
;
1435 REG_WRITE_ARRAY(&temp
, 1, regWrites
);
1438 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_INTERNAL_ADDAC
);
1440 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
1441 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
1442 u32 val
= INI_RA(&ah
->iniModes
, i
, modesIndex
);
1444 REG_WRITE(ah
, reg
, val
);
1446 if (reg
>= 0x7800 && reg
< 0x78a0
1447 && ah
->config
.analog_shiftreg
) {
1451 DO_DELAY(regWrites
);
1454 if (AR_SREV_9280(ah
) || AR_SREV_9287_10_OR_LATER(ah
))
1455 REG_WRITE_ARRAY(&ah
->iniModesRxGain
, modesIndex
, regWrites
);
1457 if (AR_SREV_9280(ah
) || AR_SREV_9285_12_OR_LATER(ah
) ||
1458 AR_SREV_9287_10_OR_LATER(ah
))
1459 REG_WRITE_ARRAY(&ah
->iniModesTxGain
, modesIndex
, regWrites
);
1461 if (AR_SREV_9271_10(ah
))
1462 REG_WRITE_ARRAY(&ah
->iniModes_9271_1_0_only
,
1463 modesIndex
, regWrites
);
1465 /* Write common array parameters */
1466 for (i
= 0; i
< ah
->iniCommon
.ia_rows
; i
++) {
1467 u32 reg
= INI_RA(&ah
->iniCommon
, i
, 0);
1468 u32 val
= INI_RA(&ah
->iniCommon
, i
, 1);
1470 REG_WRITE(ah
, reg
, val
);
1472 if (reg
>= 0x7800 && reg
< 0x78a0
1473 && ah
->config
.analog_shiftreg
) {
1477 DO_DELAY(regWrites
);
1480 if (AR_SREV_9271(ah
)) {
1481 if (ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
) == 1)
1482 REG_WRITE_ARRAY(&ah
->iniModes_high_power_tx_gain_9271
,
1483 modesIndex
, regWrites
);
1485 REG_WRITE_ARRAY(&ah
->iniModes_normal_power_tx_gain_9271
,
1486 modesIndex
, regWrites
);
1489 ath9k_hw_write_regs(ah
, freqIndex
, regWrites
);
1491 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
)) {
1492 REG_WRITE_ARRAY(&ah
->iniModesAdditional
, modesIndex
,
1496 ath9k_hw_override_ini(ah
, chan
);
1497 ath9k_hw_set_regs(ah
, chan
);
1498 ath9k_hw_init_chain_masks(ah
);
1500 if (OLC_FOR_AR9280_20_LATER
)
1504 ah
->eep_ops
->set_txpower(ah
, chan
,
1505 ath9k_regd_get_ctl(regulatory
, chan
),
1506 channel
->max_antenna_gain
* 2,
1507 channel
->max_power
* 2,
1508 min((u32
) MAX_RATE_POWER
,
1509 (u32
) regulatory
->power_limit
));
1511 /* Write analog registers */
1512 if (!ath9k_hw_set_rf_regs(ah
, chan
, freqIndex
)) {
1513 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1514 "ar5416SetRfRegs failed\n");
1521 /****************************************/
1522 /* Reset and Channel Switching Routines */
1523 /****************************************/
1525 static void ath9k_hw_set_rfmode(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1532 rfMode
|= (IS_CHAN_B(chan
) || IS_CHAN_G(chan
))
1533 ? AR_PHY_MODE_DYNAMIC
: AR_PHY_MODE_OFDM
;
1535 if (!AR_SREV_9280_10_OR_LATER(ah
))
1536 rfMode
|= (IS_CHAN_5GHZ(chan
)) ?
1537 AR_PHY_MODE_RF5GHZ
: AR_PHY_MODE_RF2GHZ
;
1539 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
))
1540 rfMode
|= (AR_PHY_MODE_DYNAMIC
| AR_PHY_MODE_DYN_CCK_DISABLE
);
1542 REG_WRITE(ah
, AR_PHY_MODE
, rfMode
);
1545 static void ath9k_hw_mark_phy_inactive(struct ath_hw
*ah
)
1547 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_DIS
);
1550 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1555 * set AHB_MODE not to do cacheline prefetches
1557 regval
= REG_READ(ah
, AR_AHB_MODE
);
1558 REG_WRITE(ah
, AR_AHB_MODE
, regval
| AR_AHB_PREFETCH_RD_EN
);
1561 * let mac dma reads be in 128 byte chunks
1563 regval
= REG_READ(ah
, AR_TXCFG
) & ~AR_TXCFG_DMASZ_MASK
;
1564 REG_WRITE(ah
, AR_TXCFG
, regval
| AR_TXCFG_DMASZ_128B
);
1567 * Restore TX Trigger Level to its pre-reset value.
1568 * The initial value depends on whether aggregation is enabled, and is
1569 * adjusted whenever underruns are detected.
1571 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1574 * let mac dma writes be in 128 byte chunks
1576 regval
= REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_DMASZ_MASK
;
1577 REG_WRITE(ah
, AR_RXCFG
, regval
| AR_RXCFG_DMASZ_128B
);
1580 * Setup receive FIFO threshold to hold off TX activities
1582 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1585 * reduce the number of usable entries in PCU TXBUF to avoid
1586 * wrap around issues.
1588 if (AR_SREV_9285(ah
)) {
1589 /* For AR9285 the number of Fifos are reduced to half.
1590 * So set the usable tx buf size also to half to
1591 * avoid data/delimiter underruns
1593 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1594 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
1595 } else if (!AR_SREV_9271(ah
)) {
1596 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1597 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
1601 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1605 val
= REG_READ(ah
, AR_STA_ID1
);
1606 val
&= ~(AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
);
1608 case NL80211_IFTYPE_AP
:
1609 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_STA_AP
1610 | AR_STA_ID1_KSRCH_MODE
);
1611 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1613 case NL80211_IFTYPE_ADHOC
:
1614 case NL80211_IFTYPE_MESH_POINT
:
1615 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_ADHOC
1616 | AR_STA_ID1_KSRCH_MODE
);
1617 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1619 case NL80211_IFTYPE_STATION
:
1620 case NL80211_IFTYPE_MONITOR
:
1621 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
1626 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
,
1631 u32 coef_exp
, coef_man
;
1633 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1634 if ((coef_scaled
>> coef_exp
) & 0x1)
1637 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1639 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1641 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1642 *coef_exponent
= coef_exp
- 16;
1645 static void ath9k_hw_set_delta_slope(struct ath_hw
*ah
,
1646 struct ath9k_channel
*chan
)
1648 u32 coef_scaled
, ds_coef_exp
, ds_coef_man
;
1649 u32 clockMhzScaled
= 0x64000000;
1650 struct chan_centers centers
;
1652 if (IS_CHAN_HALF_RATE(chan
))
1653 clockMhzScaled
= clockMhzScaled
>> 1;
1654 else if (IS_CHAN_QUARTER_RATE(chan
))
1655 clockMhzScaled
= clockMhzScaled
>> 2;
1657 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1658 coef_scaled
= clockMhzScaled
/ centers
.synth_center
;
1660 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1663 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1664 AR_PHY_TIMING3_DSC_MAN
, ds_coef_man
);
1665 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1666 AR_PHY_TIMING3_DSC_EXP
, ds_coef_exp
);
1668 coef_scaled
= (9 * coef_scaled
) / 10;
1670 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1673 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1674 AR_PHY_HALFGI_DSC_MAN
, ds_coef_man
);
1675 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1676 AR_PHY_HALFGI_DSC_EXP
, ds_coef_exp
);
1679 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1684 if (AR_SREV_9100(ah
)) {
1685 u32 val
= REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1686 val
&= ~AR_RTC_DERIVED_CLK_PERIOD
;
1687 val
|= SM(1, AR_RTC_DERIVED_CLK_PERIOD
);
1688 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, val
);
1689 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1692 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1693 AR_RTC_FORCE_WAKE_ON_INT
);
1695 if (AR_SREV_9100(ah
)) {
1696 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1697 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1699 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1701 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1702 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1703 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1704 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1706 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1709 rst_flags
= AR_RTC_RC_MAC_WARM
;
1710 if (type
== ATH9K_RESET_COLD
)
1711 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1714 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1717 REG_WRITE(ah
, AR_RTC_RC
, 0);
1718 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1719 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1720 "RTC stuck in MAC reset\n");
1724 if (!AR_SREV_9100(ah
))
1725 REG_WRITE(ah
, AR_RC
, 0);
1727 if (AR_SREV_9100(ah
))
1733 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1735 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1736 AR_RTC_FORCE_WAKE_ON_INT
);
1738 if (!AR_SREV_9100(ah
))
1739 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1741 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1744 if (!AR_SREV_9100(ah
))
1745 REG_WRITE(ah
, AR_RC
, 0);
1747 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1749 if (!ath9k_hw_wait(ah
,
1754 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1755 "RTC not waking up\n");
1759 ath9k_hw_read_revisions(ah
);
1761 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1764 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1766 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1767 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1770 case ATH9K_RESET_POWER_ON
:
1771 return ath9k_hw_set_reset_power_on(ah
);
1772 case ATH9K_RESET_WARM
:
1773 case ATH9K_RESET_COLD
:
1774 return ath9k_hw_set_reset(ah
, type
);
1780 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1783 u32 enableDacFifo
= 0;
1785 if (AR_SREV_9285_10_OR_LATER(ah
))
1786 enableDacFifo
= (REG_READ(ah
, AR_PHY_TURBO
) &
1787 AR_PHY_FC_ENABLE_DAC_FIFO
);
1789 phymode
= AR_PHY_FC_HT_EN
| AR_PHY_FC_SHORT_GI_40
1790 | AR_PHY_FC_SINGLE_HT_LTF1
| AR_PHY_FC_WALSH
| enableDacFifo
;
1792 if (IS_CHAN_HT40(chan
)) {
1793 phymode
|= AR_PHY_FC_DYN2040_EN
;
1795 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
1796 (chan
->chanmode
== CHANNEL_G_HT40PLUS
))
1797 phymode
|= AR_PHY_FC_DYN2040_PRI_CH
;
1800 REG_WRITE(ah
, AR_PHY_TURBO
, phymode
);
1802 ath9k_hw_set11nmac2040(ah
);
1804 REG_WRITE(ah
, AR_GTXTO
, 25 << AR_GTXTO_TIMEOUT_LIMIT_S
);
1805 REG_WRITE(ah
, AR_CST
, 0xF << AR_CST_TIMEOUT_LIMIT_S
);
1808 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1809 struct ath9k_channel
*chan
)
1811 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
1812 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1814 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1817 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1820 ah
->chip_fullsleep
= false;
1821 ath9k_hw_init_pll(ah
, chan
);
1822 ath9k_hw_set_rfmode(ah
, chan
);
1827 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1828 struct ath9k_channel
*chan
)
1830 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1831 struct ath_common
*common
= ath9k_hw_common(ah
);
1832 struct ieee80211_channel
*channel
= chan
->chan
;
1833 u32 synthDelay
, qnum
;
1836 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1837 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1838 ath_print(common
, ATH_DBG_QUEUE
,
1839 "Transmit frames pending on "
1840 "queue %d\n", qnum
);
1845 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, AR_PHY_RFBUS_REQ_EN
);
1846 if (!ath9k_hw_wait(ah
, AR_PHY_RFBUS_GRANT
, AR_PHY_RFBUS_GRANT_EN
,
1847 AR_PHY_RFBUS_GRANT_EN
, AH_WAIT_TIMEOUT
)) {
1848 ath_print(common
, ATH_DBG_FATAL
,
1849 "Could not kill baseband RX\n");
1853 ath9k_hw_set_regs(ah
, chan
);
1855 r
= ah
->ath9k_hw_rf_set_freq(ah
, chan
);
1857 ath_print(common
, ATH_DBG_FATAL
,
1858 "Failed to set channel\n");
1862 ah
->eep_ops
->set_txpower(ah
, chan
,
1863 ath9k_regd_get_ctl(regulatory
, chan
),
1864 channel
->max_antenna_gain
* 2,
1865 channel
->max_power
* 2,
1866 min((u32
) MAX_RATE_POWER
,
1867 (u32
) regulatory
->power_limit
));
1869 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
1870 if (IS_CHAN_B(chan
))
1871 synthDelay
= (4 * synthDelay
) / 22;
1875 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
1877 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, 0);
1879 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1880 ath9k_hw_set_delta_slope(ah
, chan
);
1882 ah
->ath9k_hw_spur_mitigate_freq(ah
, chan
);
1884 if (!chan
->oneTimeCalsDone
)
1885 chan
->oneTimeCalsDone
= true;
1890 static void ath9k_enable_rfkill(struct ath_hw
*ah
)
1892 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
,
1893 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB
);
1895 REG_CLR_BIT(ah
, AR_GPIO_INPUT_MUX2
,
1896 AR_GPIO_INPUT_MUX2_RFSILENT
);
1898 ath9k_hw_cfg_gpio_input(ah
, ah
->rfkill_gpio
);
1899 REG_SET_BIT(ah
, AR_PHY_TEST
, RFSILENT_BB
);
1902 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1903 bool bChannelChange
)
1905 struct ath_common
*common
= ath9k_hw_common(ah
);
1907 struct ath9k_channel
*curchan
= ah
->curchan
;
1911 int i
, rx_chainmask
, r
;
1913 ah
->txchainmask
= common
->tx_chainmask
;
1914 ah
->rxchainmask
= common
->rx_chainmask
;
1916 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1919 if (curchan
&& !ah
->chip_fullsleep
)
1920 ath9k_hw_getnf(ah
, curchan
);
1922 if (bChannelChange
&&
1923 (ah
->chip_fullsleep
!= true) &&
1924 (ah
->curchan
!= NULL
) &&
1925 (chan
->channel
!= ah
->curchan
->channel
) &&
1926 ((chan
->channelFlags
& CHANNEL_ALL
) ==
1927 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)) &&
1928 !(AR_SREV_9280(ah
) || IS_CHAN_A_5MHZ_SPACED(chan
) ||
1929 IS_CHAN_A_5MHZ_SPACED(ah
->curchan
))) {
1931 if (ath9k_hw_channel_change(ah
, chan
)) {
1932 ath9k_hw_loadnf(ah
, ah
->curchan
);
1933 ath9k_hw_start_nfcal(ah
);
1938 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1939 if (saveDefAntenna
== 0)
1942 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1944 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1945 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1946 tsf
= ath9k_hw_gettsf64(ah
);
1948 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1949 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1950 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1952 ath9k_hw_mark_phy_inactive(ah
);
1954 /* Only required on the first reset */
1955 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1957 AR9271_RESET_POWER_DOWN_CONTROL
,
1958 AR9271_RADIO_RF_RST
);
1962 if (!ath9k_hw_chip_reset(ah
, chan
)) {
1963 ath_print(common
, ATH_DBG_FATAL
, "Chip reset failed\n");
1967 /* Only required on the first reset */
1968 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1969 ah
->htc_reset_init
= false;
1971 AR9271_RESET_POWER_DOWN_CONTROL
,
1972 AR9271_GATE_MAC_CTL
);
1977 if (tsf
&& AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1978 ath9k_hw_settsf64(ah
, tsf
);
1980 if (AR_SREV_9280_10_OR_LATER(ah
))
1981 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
1983 if (AR_SREV_9287_12_OR_LATER(ah
)) {
1984 /* Enable ASYNC FIFO */
1985 REG_SET_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
1986 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL
);
1987 REG_SET_BIT(ah
, AR_PHY_MODE
, AR_PHY_MODE_ASYNCFIFO
);
1988 REG_CLR_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
1989 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
);
1990 REG_SET_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
1991 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
);
1993 r
= ath9k_hw_process_ini(ah
, chan
);
1997 /* Setup MFP options for CCMP */
1998 if (AR_SREV_9280_20_OR_LATER(ah
)) {
1999 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2000 * frames when constructing CCMP AAD. */
2001 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
2003 ah
->sw_mgmt_crypto
= false;
2004 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
2005 /* Disable hardware crypto for management frames */
2006 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
2007 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
2008 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
2009 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
2010 ah
->sw_mgmt_crypto
= true;
2012 ah
->sw_mgmt_crypto
= true;
2014 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
2015 ath9k_hw_set_delta_slope(ah
, chan
);
2017 ah
->ath9k_hw_spur_mitigate_freq(ah
, chan
);
2018 ah
->eep_ops
->set_board_values(ah
, chan
);
2020 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(common
->macaddr
));
2021 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(common
->macaddr
+ 4)
2023 | AR_STA_ID1_RTS_USE_DEF
2025 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
2026 | ah
->sta_id1_defaults
);
2027 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2029 ath_hw_setbssidmask(common
);
2031 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
2033 ath9k_hw_write_associd(ah
);
2035 REG_WRITE(ah
, AR_ISR
, ~0);
2037 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
2039 r
= ah
->ath9k_hw_rf_set_freq(ah
, chan
);
2043 for (i
= 0; i
< AR_NUM_DCU
; i
++)
2044 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
2047 for (i
= 0; i
< ah
->caps
.total_queues
; i
++)
2048 ath9k_hw_resettxqueue(ah
, i
);
2050 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
2051 ath9k_hw_init_qos(ah
);
2053 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2054 ath9k_enable_rfkill(ah
);
2056 ath9k_hw_init_global_settings(ah
);
2058 if (AR_SREV_9287_12_OR_LATER(ah
)) {
2059 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
,
2060 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR
);
2061 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
,
2062 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR
);
2063 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
,
2064 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR
);
2066 REG_WRITE(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR
);
2067 REG_WRITE(ah
, AR_USEC
, AR_USEC_ASYNC_FIFO_DUR
);
2069 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
2070 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
2071 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
2072 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
2074 if (AR_SREV_9287_12_OR_LATER(ah
)) {
2075 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
2076 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
2079 REG_WRITE(ah
, AR_STA_ID1
,
2080 REG_READ(ah
, AR_STA_ID1
) | AR_STA_ID1_PRESERVE_SEQNUM
);
2082 ath9k_hw_set_dma(ah
);
2084 REG_WRITE(ah
, AR_OBS
, 8);
2086 if (ah
->config
.rx_intr_mitigation
) {
2087 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
2088 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
2091 ath9k_hw_init_bb(ah
, chan
);
2093 if (!ath9k_hw_init_cal(ah
, chan
))
2096 rx_chainmask
= ah
->rxchainmask
;
2097 if ((rx_chainmask
== 0x5) || (rx_chainmask
== 0x3)) {
2098 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
2099 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
2102 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
2105 * For big endian systems turn on swapping for descriptors
2107 if (AR_SREV_9100(ah
)) {
2109 mask
= REG_READ(ah
, AR_CFG
);
2110 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
2111 ath_print(common
, ATH_DBG_RESET
,
2112 "CFG Byte Swap Set 0x%x\n", mask
);
2115 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
2116 REG_WRITE(ah
, AR_CFG
, mask
);
2117 ath_print(common
, ATH_DBG_RESET
,
2118 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
2121 /* Configure AR9271 target WLAN */
2122 if (AR_SREV_9271(ah
))
2123 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
2126 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
2130 if (ah
->btcoex_hw
.enabled
)
2131 ath9k_hw_btcoex_enable(ah
);
2135 EXPORT_SYMBOL(ath9k_hw_reset
);
2137 /************************/
2138 /* Key Cache Management */
2139 /************************/
2141 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
)
2145 if (entry
>= ah
->caps
.keycache_size
) {
2146 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2147 "keychache entry %u out of range\n", entry
);
2151 keyType
= REG_READ(ah
, AR_KEYTABLE_TYPE(entry
));
2153 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), 0);
2154 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), 0);
2155 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), 0);
2156 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), 0);
2157 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), 0);
2158 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), AR_KEYTABLE_TYPE_CLR
);
2159 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), 0);
2160 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), 0);
2162 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2163 u16 micentry
= entry
+ 64;
2165 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), 0);
2166 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2167 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), 0);
2168 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2174 EXPORT_SYMBOL(ath9k_hw_keyreset
);
2176 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
)
2180 if (entry
>= ah
->caps
.keycache_size
) {
2181 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2182 "keychache entry %u out of range\n", entry
);
2187 macHi
= (mac
[5] << 8) | mac
[4];
2188 macLo
= (mac
[3] << 24) |
2193 macLo
|= (macHi
& 1) << 31;
2198 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), macLo
);
2199 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), macHi
| AR_KEYTABLE_VALID
);
2203 EXPORT_SYMBOL(ath9k_hw_keysetmac
);
2205 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
2206 const struct ath9k_keyval
*k
,
2209 const struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2210 struct ath_common
*common
= ath9k_hw_common(ah
);
2211 u32 key0
, key1
, key2
, key3
, key4
;
2214 if (entry
>= pCap
->keycache_size
) {
2215 ath_print(common
, ATH_DBG_FATAL
,
2216 "keycache entry %u out of range\n", entry
);
2220 switch (k
->kv_type
) {
2221 case ATH9K_CIPHER_AES_OCB
:
2222 keyType
= AR_KEYTABLE_TYPE_AES
;
2224 case ATH9K_CIPHER_AES_CCM
:
2225 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_CIPHER_AESCCM
)) {
2226 ath_print(common
, ATH_DBG_ANY
,
2227 "AES-CCM not supported by mac rev 0x%x\n",
2228 ah
->hw_version
.macRev
);
2231 keyType
= AR_KEYTABLE_TYPE_CCM
;
2233 case ATH9K_CIPHER_TKIP
:
2234 keyType
= AR_KEYTABLE_TYPE_TKIP
;
2235 if (ATH9K_IS_MIC_ENABLED(ah
)
2236 && entry
+ 64 >= pCap
->keycache_size
) {
2237 ath_print(common
, ATH_DBG_ANY
,
2238 "entry %u inappropriate for TKIP\n", entry
);
2242 case ATH9K_CIPHER_WEP
:
2243 if (k
->kv_len
< WLAN_KEY_LEN_WEP40
) {
2244 ath_print(common
, ATH_DBG_ANY
,
2245 "WEP key length %u too small\n", k
->kv_len
);
2248 if (k
->kv_len
<= WLAN_KEY_LEN_WEP40
)
2249 keyType
= AR_KEYTABLE_TYPE_40
;
2250 else if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
2251 keyType
= AR_KEYTABLE_TYPE_104
;
2253 keyType
= AR_KEYTABLE_TYPE_128
;
2255 case ATH9K_CIPHER_CLR
:
2256 keyType
= AR_KEYTABLE_TYPE_CLR
;
2259 ath_print(common
, ATH_DBG_FATAL
,
2260 "cipher %u not supported\n", k
->kv_type
);
2264 key0
= get_unaligned_le32(k
->kv_val
+ 0);
2265 key1
= get_unaligned_le16(k
->kv_val
+ 4);
2266 key2
= get_unaligned_le32(k
->kv_val
+ 6);
2267 key3
= get_unaligned_le16(k
->kv_val
+ 10);
2268 key4
= get_unaligned_le32(k
->kv_val
+ 12);
2269 if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
2273 * Note: Key cache registers access special memory area that requires
2274 * two 32-bit writes to actually update the values in the internal
2275 * memory. Consequently, the exact order and pairs used here must be
2279 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2280 u16 micentry
= entry
+ 64;
2283 * Write inverted key[47:0] first to avoid Michael MIC errors
2284 * on frames that could be sent or received at the same time.
2285 * The correct key will be written in the end once everything
2288 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), ~key0
);
2289 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), ~key1
);
2291 /* Write key[95:48] */
2292 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2293 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2295 /* Write key[127:96] and key type */
2296 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2297 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2299 /* Write MAC address for the entry */
2300 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2302 if (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) {
2304 * TKIP uses two key cache entries:
2305 * Michael MIC TX/RX keys in the same key cache entry
2306 * (idx = main index + 64):
2307 * key0 [31:0] = RX key [31:0]
2308 * key1 [15:0] = TX key [31:16]
2309 * key1 [31:16] = reserved
2310 * key2 [31:0] = RX key [63:32]
2311 * key3 [15:0] = TX key [15:0]
2312 * key3 [31:16] = reserved
2313 * key4 [31:0] = TX key [63:32]
2315 u32 mic0
, mic1
, mic2
, mic3
, mic4
;
2317 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2318 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2319 mic1
= get_unaligned_le16(k
->kv_txmic
+ 2) & 0xffff;
2320 mic3
= get_unaligned_le16(k
->kv_txmic
+ 0) & 0xffff;
2321 mic4
= get_unaligned_le32(k
->kv_txmic
+ 4);
2323 /* Write RX[31:0] and TX[31:16] */
2324 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2325 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), mic1
);
2327 /* Write RX[63:32] and TX[15:0] */
2328 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2329 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), mic3
);
2331 /* Write TX[63:32] and keyType(reserved) */
2332 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), mic4
);
2333 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2334 AR_KEYTABLE_TYPE_CLR
);
2338 * TKIP uses four key cache entries (two for group
2340 * Michael MIC TX/RX keys are in different key cache
2341 * entries (idx = main index + 64 for TX and
2342 * main index + 32 + 96 for RX):
2343 * key0 [31:0] = TX/RX MIC key [31:0]
2344 * key1 [31:0] = reserved
2345 * key2 [31:0] = TX/RX MIC key [63:32]
2346 * key3 [31:0] = reserved
2347 * key4 [31:0] = reserved
2349 * Upper layer code will call this function separately
2350 * for TX and RX keys when these registers offsets are
2355 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2356 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2358 /* Write MIC key[31:0] */
2359 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2360 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2362 /* Write MIC key[63:32] */
2363 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2364 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2366 /* Write TX[63:32] and keyType(reserved) */
2367 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), 0);
2368 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2369 AR_KEYTABLE_TYPE_CLR
);
2372 /* MAC address registers are reserved for the MIC entry */
2373 REG_WRITE(ah
, AR_KEYTABLE_MAC0(micentry
), 0);
2374 REG_WRITE(ah
, AR_KEYTABLE_MAC1(micentry
), 0);
2377 * Write the correct (un-inverted) key[47:0] last to enable
2378 * TKIP now that all other registers are set with correct
2381 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2382 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2384 /* Write key[47:0] */
2385 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2386 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2388 /* Write key[95:48] */
2389 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2390 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2392 /* Write key[127:96] and key type */
2393 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2394 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2396 /* Write MAC address for the entry */
2397 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2402 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry
);
2404 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
)
2406 if (entry
< ah
->caps
.keycache_size
) {
2407 u32 val
= REG_READ(ah
, AR_KEYTABLE_MAC1(entry
));
2408 if (val
& AR_KEYTABLE_VALID
)
2413 EXPORT_SYMBOL(ath9k_hw_keyisvalid
);
2415 /******************************/
2416 /* Power Management (Chipset) */
2417 /******************************/
2419 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
2421 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2423 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2424 AR_RTC_FORCE_WAKE_EN
);
2425 if (!AR_SREV_9100(ah
))
2426 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
2428 if (!AR_SREV_5416(ah
) && !AR_SREV_9271(ah
))
2429 REG_CLR_BIT(ah
, (AR_RTC_RESET
),
2434 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
2436 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2438 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2440 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2441 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
2442 AR_RTC_FORCE_WAKE_ON_INT
);
2444 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2445 AR_RTC_FORCE_WAKE_EN
);
2450 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
2456 if ((REG_READ(ah
, AR_RTC_STATUS
) &
2457 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
2458 if (ath9k_hw_set_reset_reg(ah
,
2459 ATH9K_RESET_POWER_ON
) != true) {
2462 ath9k_hw_init_pll(ah
, NULL
);
2464 if (AR_SREV_9100(ah
))
2465 REG_SET_BIT(ah
, AR_RTC_RESET
,
2468 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2469 AR_RTC_FORCE_WAKE_EN
);
2472 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
2473 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
2474 if (val
== AR_RTC_STATUS_ON
)
2477 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2478 AR_RTC_FORCE_WAKE_EN
);
2481 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2482 "Failed to wakeup in %uus\n",
2483 POWER_UP_TIME
/ 20);
2488 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2493 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
2495 struct ath_common
*common
= ath9k_hw_common(ah
);
2496 int status
= true, setChip
= true;
2497 static const char *modes
[] = {
2504 if (ah
->power_mode
== mode
)
2507 ath_print(common
, ATH_DBG_RESET
, "%s -> %s\n",
2508 modes
[ah
->power_mode
], modes
[mode
]);
2511 case ATH9K_PM_AWAKE
:
2512 status
= ath9k_hw_set_power_awake(ah
, setChip
);
2514 case ATH9K_PM_FULL_SLEEP
:
2515 ath9k_set_power_sleep(ah
, setChip
);
2516 ah
->chip_fullsleep
= true;
2518 case ATH9K_PM_NETWORK_SLEEP
:
2519 ath9k_set_power_network_sleep(ah
, setChip
);
2522 ath_print(common
, ATH_DBG_FATAL
,
2523 "Unknown power mode %u\n", mode
);
2526 ah
->power_mode
= mode
;
2530 EXPORT_SYMBOL(ath9k_hw_setpower
);
2533 * Helper for ASPM support.
2535 * Disable PLL when in L0s as well as receiver clock when in L1.
2536 * This power saving option must be enabled through the SerDes.
2538 * Programming the SerDes must go through the same 288 bit serial shift
2539 * register as the other analog registers. Hence the 9 writes.
2541 void ath9k_hw_configpcipowersave(struct ath_hw
*ah
, int restore
, int power_off
)
2546 if (ah
->is_pciexpress
!= true)
2549 /* Do not touch SerDes registers */
2550 if (ah
->config
.pcie_powersave_enable
== 2)
2553 /* Nothing to do on restore for 11N */
2555 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2557 * AR9280 2.0 or later chips use SerDes values from the
2558 * initvals.h initialized depending on chipset during
2561 for (i
= 0; i
< ah
->iniPcieSerdes
.ia_rows
; i
++) {
2562 REG_WRITE(ah
, INI_RA(&ah
->iniPcieSerdes
, i
, 0),
2563 INI_RA(&ah
->iniPcieSerdes
, i
, 1));
2565 } else if (AR_SREV_9280(ah
) &&
2566 (ah
->hw_version
.macRev
== AR_SREV_REVISION_9280_10
)) {
2567 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fd00);
2568 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2570 /* RX shut off when elecidle is asserted */
2571 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xa8000019);
2572 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x13160820);
2573 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980560);
2575 /* Shut off CLKREQ active in L1 */
2576 if (ah
->config
.pcie_clock_req
)
2577 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffc);
2579 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffd);
2581 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2582 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2583 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00043007);
2585 /* Load the new settings */
2586 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2589 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
2590 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2592 /* RX shut off when elecidle is asserted */
2593 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000039);
2594 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x53160824);
2595 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980579);
2598 * Ignore ah->ah_config.pcie_clock_req setting for
2601 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x001defff);
2603 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2604 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2605 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e3007);
2607 /* Load the new settings */
2608 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2613 /* set bit 19 to allow forcing of pcie core into L1 state */
2614 REG_SET_BIT(ah
, AR_PCIE_PM_CTRL
, AR_PCIE_PM_CTRL_ENA
);
2616 /* Several PCIe massages to ensure proper behaviour */
2617 if (ah
->config
.pcie_waen
) {
2618 val
= ah
->config
.pcie_waen
;
2620 val
&= (~AR_WA_D3_L1_DISABLE
);
2622 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
) ||
2624 val
= AR9285_WA_DEFAULT
;
2626 val
&= (~AR_WA_D3_L1_DISABLE
);
2627 } else if (AR_SREV_9280(ah
)) {
2629 * On AR9280 chips bit 22 of 0x4004 needs to be
2630 * set otherwise card may disappear.
2632 val
= AR9280_WA_DEFAULT
;
2634 val
&= (~AR_WA_D3_L1_DISABLE
);
2636 val
= AR_WA_DEFAULT
;
2639 REG_WRITE(ah
, AR_WA
, val
);
2644 * Set PCIe workaround bits
2645 * bit 14 in WA register (disable L1) should only
2646 * be set when device enters D3 and be cleared
2647 * when device comes back to D0.
2649 if (ah
->config
.pcie_waen
) {
2650 if (ah
->config
.pcie_waen
& AR_WA_D3_L1_DISABLE
)
2651 REG_SET_BIT(ah
, AR_WA
, AR_WA_D3_L1_DISABLE
);
2653 if (((AR_SREV_9285(ah
) || AR_SREV_9271(ah
) ||
2654 AR_SREV_9287(ah
)) &&
2655 (AR9285_WA_DEFAULT
& AR_WA_D3_L1_DISABLE
)) ||
2656 (AR_SREV_9280(ah
) &&
2657 (AR9280_WA_DEFAULT
& AR_WA_D3_L1_DISABLE
))) {
2658 REG_SET_BIT(ah
, AR_WA
, AR_WA_D3_L1_DISABLE
);
2663 EXPORT_SYMBOL(ath9k_hw_configpcipowersave
);
2665 /**********************/
2666 /* Interrupt Handling */
2667 /**********************/
2669 bool ath9k_hw_intrpend(struct ath_hw
*ah
)
2673 if (AR_SREV_9100(ah
))
2676 host_isr
= REG_READ(ah
, AR_INTR_ASYNC_CAUSE
);
2677 if ((host_isr
& AR_INTR_MAC_IRQ
) && (host_isr
!= AR_INTR_SPURIOUS
))
2680 host_isr
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
2681 if ((host_isr
& AR_INTR_SYNC_DEFAULT
)
2682 && (host_isr
!= AR_INTR_SPURIOUS
))
2687 EXPORT_SYMBOL(ath9k_hw_intrpend
);
2689 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
)
2693 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2695 bool fatal_int
= false;
2696 struct ath_common
*common
= ath9k_hw_common(ah
);
2698 if (!AR_SREV_9100(ah
)) {
2699 if (REG_READ(ah
, AR_INTR_ASYNC_CAUSE
) & AR_INTR_MAC_IRQ
) {
2700 if ((REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
)
2701 == AR_RTC_STATUS_ON
) {
2702 isr
= REG_READ(ah
, AR_ISR
);
2706 sync_cause
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
) &
2707 AR_INTR_SYNC_DEFAULT
;
2711 if (!isr
&& !sync_cause
)
2715 isr
= REG_READ(ah
, AR_ISR
);
2719 if (isr
& AR_ISR_BCNMISC
) {
2721 isr2
= REG_READ(ah
, AR_ISR_S2
);
2722 if (isr2
& AR_ISR_S2_TIM
)
2723 mask2
|= ATH9K_INT_TIM
;
2724 if (isr2
& AR_ISR_S2_DTIM
)
2725 mask2
|= ATH9K_INT_DTIM
;
2726 if (isr2
& AR_ISR_S2_DTIMSYNC
)
2727 mask2
|= ATH9K_INT_DTIMSYNC
;
2728 if (isr2
& (AR_ISR_S2_CABEND
))
2729 mask2
|= ATH9K_INT_CABEND
;
2730 if (isr2
& AR_ISR_S2_GTT
)
2731 mask2
|= ATH9K_INT_GTT
;
2732 if (isr2
& AR_ISR_S2_CST
)
2733 mask2
|= ATH9K_INT_CST
;
2734 if (isr2
& AR_ISR_S2_TSFOOR
)
2735 mask2
|= ATH9K_INT_TSFOOR
;
2738 isr
= REG_READ(ah
, AR_ISR_RAC
);
2739 if (isr
== 0xffffffff) {
2744 *masked
= isr
& ATH9K_INT_COMMON
;
2746 if (ah
->config
.rx_intr_mitigation
) {
2747 if (isr
& (AR_ISR_RXMINTR
| AR_ISR_RXINTM
))
2748 *masked
|= ATH9K_INT_RX
;
2751 if (isr
& (AR_ISR_RXOK
| AR_ISR_RXERR
))
2752 *masked
|= ATH9K_INT_RX
;
2754 (AR_ISR_TXOK
| AR_ISR_TXDESC
| AR_ISR_TXERR
|
2758 *masked
|= ATH9K_INT_TX
;
2760 s0_s
= REG_READ(ah
, AR_ISR_S0_S
);
2761 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXOK
);
2762 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXDESC
);
2764 s1_s
= REG_READ(ah
, AR_ISR_S1_S
);
2765 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXERR
);
2766 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXEOL
);
2769 if (isr
& AR_ISR_RXORN
) {
2770 ath_print(common
, ATH_DBG_INTERRUPT
,
2771 "receive FIFO overrun interrupt\n");
2774 if (!AR_SREV_9100(ah
)) {
2775 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2776 u32 isr5
= REG_READ(ah
, AR_ISR_S5_S
);
2777 if (isr5
& AR_ISR_S5_TIM_TIMER
)
2778 *masked
|= ATH9K_INT_TIM_TIMER
;
2785 if (AR_SREV_9100(ah
))
2788 if (isr
& AR_ISR_GENTMR
) {
2791 s5_s
= REG_READ(ah
, AR_ISR_S5_S
);
2792 if (isr
& AR_ISR_GENTMR
) {
2793 ah
->intr_gen_timer_trigger
=
2794 MS(s5_s
, AR_ISR_S5_GENTIMER_TRIG
);
2796 ah
->intr_gen_timer_thresh
=
2797 MS(s5_s
, AR_ISR_S5_GENTIMER_THRESH
);
2799 if (ah
->intr_gen_timer_trigger
)
2800 *masked
|= ATH9K_INT_GENTIMER
;
2808 (AR_INTR_SYNC_HOST1_FATAL
| AR_INTR_SYNC_HOST1_PERR
))
2812 if (sync_cause
& AR_INTR_SYNC_HOST1_FATAL
) {
2813 ath_print(common
, ATH_DBG_ANY
,
2814 "received PCI FATAL interrupt\n");
2816 if (sync_cause
& AR_INTR_SYNC_HOST1_PERR
) {
2817 ath_print(common
, ATH_DBG_ANY
,
2818 "received PCI PERR interrupt\n");
2820 *masked
|= ATH9K_INT_FATAL
;
2822 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TIMEOUT
) {
2823 ath_print(common
, ATH_DBG_INTERRUPT
,
2824 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2825 REG_WRITE(ah
, AR_RC
, AR_RC_HOSTIF
);
2826 REG_WRITE(ah
, AR_RC
, 0);
2827 *masked
|= ATH9K_INT_FATAL
;
2829 if (sync_cause
& AR_INTR_SYNC_LOCAL_TIMEOUT
) {
2830 ath_print(common
, ATH_DBG_INTERRUPT
,
2831 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2834 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE_CLR
, sync_cause
);
2835 (void) REG_READ(ah
, AR_INTR_SYNC_CAUSE_CLR
);
2840 EXPORT_SYMBOL(ath9k_hw_getisr
);
2842 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
)
2844 u32 omask
= ah
->mask_reg
;
2846 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2847 struct ath_common
*common
= ath9k_hw_common(ah
);
2849 ath_print(common
, ATH_DBG_INTERRUPT
, "0x%x => 0x%x\n", omask
, ints
);
2851 if (omask
& ATH9K_INT_GLOBAL
) {
2852 ath_print(common
, ATH_DBG_INTERRUPT
, "disable IER\n");
2853 REG_WRITE(ah
, AR_IER
, AR_IER_DISABLE
);
2854 (void) REG_READ(ah
, AR_IER
);
2855 if (!AR_SREV_9100(ah
)) {
2856 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
, 0);
2857 (void) REG_READ(ah
, AR_INTR_ASYNC_ENABLE
);
2859 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
2860 (void) REG_READ(ah
, AR_INTR_SYNC_ENABLE
);
2864 mask
= ints
& ATH9K_INT_COMMON
;
2867 if (ints
& ATH9K_INT_TX
) {
2868 if (ah
->txok_interrupt_mask
)
2869 mask
|= AR_IMR_TXOK
;
2870 if (ah
->txdesc_interrupt_mask
)
2871 mask
|= AR_IMR_TXDESC
;
2872 if (ah
->txerr_interrupt_mask
)
2873 mask
|= AR_IMR_TXERR
;
2874 if (ah
->txeol_interrupt_mask
)
2875 mask
|= AR_IMR_TXEOL
;
2877 if (ints
& ATH9K_INT_RX
) {
2878 mask
|= AR_IMR_RXERR
;
2879 if (ah
->config
.rx_intr_mitigation
)
2880 mask
|= AR_IMR_RXMINTR
| AR_IMR_RXINTM
;
2882 mask
|= AR_IMR_RXOK
| AR_IMR_RXDESC
;
2883 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
2884 mask
|= AR_IMR_GENTMR
;
2887 if (ints
& (ATH9K_INT_BMISC
)) {
2888 mask
|= AR_IMR_BCNMISC
;
2889 if (ints
& ATH9K_INT_TIM
)
2890 mask2
|= AR_IMR_S2_TIM
;
2891 if (ints
& ATH9K_INT_DTIM
)
2892 mask2
|= AR_IMR_S2_DTIM
;
2893 if (ints
& ATH9K_INT_DTIMSYNC
)
2894 mask2
|= AR_IMR_S2_DTIMSYNC
;
2895 if (ints
& ATH9K_INT_CABEND
)
2896 mask2
|= AR_IMR_S2_CABEND
;
2897 if (ints
& ATH9K_INT_TSFOOR
)
2898 mask2
|= AR_IMR_S2_TSFOOR
;
2901 if (ints
& (ATH9K_INT_GTT
| ATH9K_INT_CST
)) {
2902 mask
|= AR_IMR_BCNMISC
;
2903 if (ints
& ATH9K_INT_GTT
)
2904 mask2
|= AR_IMR_S2_GTT
;
2905 if (ints
& ATH9K_INT_CST
)
2906 mask2
|= AR_IMR_S2_CST
;
2909 ath_print(common
, ATH_DBG_INTERRUPT
, "new IMR 0x%x\n", mask
);
2910 REG_WRITE(ah
, AR_IMR
, mask
);
2911 ah
->imrs2_reg
&= ~(AR_IMR_S2_TIM
| AR_IMR_S2_DTIM
| AR_IMR_S2_DTIMSYNC
|
2912 AR_IMR_S2_CABEND
| AR_IMR_S2_CABTO
|
2913 AR_IMR_S2_TSFOOR
| AR_IMR_S2_GTT
| AR_IMR_S2_CST
);
2914 ah
->imrs2_reg
|= mask2
;
2915 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
2916 ah
->mask_reg
= ints
;
2918 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2919 if (ints
& ATH9K_INT_TIM_TIMER
)
2920 REG_SET_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
2922 REG_CLR_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
2925 if (ints
& ATH9K_INT_GLOBAL
) {
2926 ath_print(common
, ATH_DBG_INTERRUPT
, "enable IER\n");
2927 REG_WRITE(ah
, AR_IER
, AR_IER_ENABLE
);
2928 if (!AR_SREV_9100(ah
)) {
2929 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
,
2931 REG_WRITE(ah
, AR_INTR_ASYNC_MASK
, AR_INTR_MAC_IRQ
);
2934 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
,
2935 AR_INTR_SYNC_DEFAULT
);
2936 REG_WRITE(ah
, AR_INTR_SYNC_MASK
,
2937 AR_INTR_SYNC_DEFAULT
);
2939 ath_print(common
, ATH_DBG_INTERRUPT
, "AR_IMR 0x%x IER 0x%x\n",
2940 REG_READ(ah
, AR_IMR
), REG_READ(ah
, AR_IER
));
2945 EXPORT_SYMBOL(ath9k_hw_set_interrupts
);
2947 /*******************/
2948 /* Beacon Handling */
2949 /*******************/
2951 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
2955 ah
->beacon_interval
= beacon_period
;
2957 switch (ah
->opmode
) {
2958 case NL80211_IFTYPE_STATION
:
2959 case NL80211_IFTYPE_MONITOR
:
2960 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
2961 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
2962 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
2963 flags
|= AR_TBTT_TIMER_EN
;
2965 case NL80211_IFTYPE_ADHOC
:
2966 case NL80211_IFTYPE_MESH_POINT
:
2967 REG_SET_BIT(ah
, AR_TXCFG
,
2968 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
2969 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
,
2970 TU_TO_USEC(next_beacon
+
2971 (ah
->atim_window
? ah
->
2973 flags
|= AR_NDP_TIMER_EN
;
2974 case NL80211_IFTYPE_AP
:
2975 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
2976 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
,
2977 TU_TO_USEC(next_beacon
-
2979 dma_beacon_response_time
));
2980 REG_WRITE(ah
, AR_NEXT_SWBA
,
2981 TU_TO_USEC(next_beacon
-
2983 sw_beacon_response_time
));
2985 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
2988 ath_print(ath9k_hw_common(ah
), ATH_DBG_BEACON
,
2989 "%s: unsupported opmode: %d\n",
2990 __func__
, ah
->opmode
);
2995 REG_WRITE(ah
, AR_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
2996 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
2997 REG_WRITE(ah
, AR_SWBA_PERIOD
, TU_TO_USEC(beacon_period
));
2998 REG_WRITE(ah
, AR_NDP_PERIOD
, TU_TO_USEC(beacon_period
));
3000 beacon_period
&= ~ATH9K_BEACON_ENA
;
3001 if (beacon_period
& ATH9K_BEACON_RESET_TSF
) {
3002 ath9k_hw_reset_tsf(ah
);
3005 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
3007 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
3009 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
3010 const struct ath9k_beacon_state
*bs
)
3012 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
3013 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3014 struct ath_common
*common
= ath9k_hw_common(ah
);
3016 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
3018 REG_WRITE(ah
, AR_BEACON_PERIOD
,
3019 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3020 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
3021 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3023 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
3024 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
3026 beaconintval
= bs
->bs_intval
& ATH9K_BEACON_PERIOD
;
3028 if (bs
->bs_sleepduration
> beaconintval
)
3029 beaconintval
= bs
->bs_sleepduration
;
3031 dtimperiod
= bs
->bs_dtimperiod
;
3032 if (bs
->bs_sleepduration
> dtimperiod
)
3033 dtimperiod
= bs
->bs_sleepduration
;
3035 if (beaconintval
== dtimperiod
)
3036 nextTbtt
= bs
->bs_nextdtim
;
3038 nextTbtt
= bs
->bs_nexttbtt
;
3040 ath_print(common
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
3041 ath_print(common
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
3042 ath_print(common
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
3043 ath_print(common
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
3045 REG_WRITE(ah
, AR_NEXT_DTIM
,
3046 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
3047 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
3049 REG_WRITE(ah
, AR_SLEEP1
,
3050 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
3051 | AR_SLEEP1_ASSUME_DTIM
);
3053 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
3054 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
3056 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
3058 REG_WRITE(ah
, AR_SLEEP2
,
3059 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
3061 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
3062 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
3064 REG_SET_BIT(ah
, AR_TIMER_MODE
,
3065 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
3068 /* TSF Out of Range Threshold */
3069 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
3071 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
3073 /*******************/
3074 /* HW Capabilities */
3075 /*******************/
3077 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
3079 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3080 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3081 struct ath_common
*common
= ath9k_hw_common(ah
);
3082 struct ath_btcoex_hw
*btcoex_hw
= &ah
->btcoex_hw
;
3084 u16 capField
= 0, eeval
;
3086 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
3087 regulatory
->current_rd
= eeval
;
3089 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_1
);
3090 if (AR_SREV_9285_10_OR_LATER(ah
))
3091 eeval
|= AR9285_RDEXT_DEFAULT
;
3092 regulatory
->current_rd_ext
= eeval
;
3094 capField
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_CAP
);
3096 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
3097 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
3098 if (regulatory
->current_rd
== 0x64 ||
3099 regulatory
->current_rd
== 0x65)
3100 regulatory
->current_rd
+= 5;
3101 else if (regulatory
->current_rd
== 0x41)
3102 regulatory
->current_rd
= 0x43;
3103 ath_print(common
, ATH_DBG_REGULATORY
,
3104 "regdomain mapped to 0x%x\n", regulatory
->current_rd
);
3107 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
3108 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
3109 ath_print(common
, ATH_DBG_FATAL
,
3110 "no band has been marked as supported in EEPROM.\n");
3114 bitmap_zero(pCap
->wireless_modes
, ATH9K_MODE_MAX
);
3116 if (eeval
& AR5416_OPFLAGS_11A
) {
3117 set_bit(ATH9K_MODE_11A
, pCap
->wireless_modes
);
3118 if (ah
->config
.ht_enable
) {
3119 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT20
))
3120 set_bit(ATH9K_MODE_11NA_HT20
,
3121 pCap
->wireless_modes
);
3122 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT40
)) {
3123 set_bit(ATH9K_MODE_11NA_HT40PLUS
,
3124 pCap
->wireless_modes
);
3125 set_bit(ATH9K_MODE_11NA_HT40MINUS
,
3126 pCap
->wireless_modes
);
3131 if (eeval
& AR5416_OPFLAGS_11G
) {
3132 set_bit(ATH9K_MODE_11G
, pCap
->wireless_modes
);
3133 if (ah
->config
.ht_enable
) {
3134 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT20
))
3135 set_bit(ATH9K_MODE_11NG_HT20
,
3136 pCap
->wireless_modes
);
3137 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT40
)) {
3138 set_bit(ATH9K_MODE_11NG_HT40PLUS
,
3139 pCap
->wireless_modes
);
3140 set_bit(ATH9K_MODE_11NG_HT40MINUS
,
3141 pCap
->wireless_modes
);
3146 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
3148 * For AR9271 we will temporarilly uses the rx chainmax as read from
3151 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
3152 !(eeval
& AR5416_OPFLAGS_11A
) &&
3153 !(AR_SREV_9271(ah
)))
3154 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3155 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
3157 /* Use rx_chainmask from EEPROM. */
3158 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
3160 if (!(AR_SREV_9280(ah
) && (ah
->hw_version
.macRev
== 0)))
3161 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
3163 pCap
->low_2ghz_chan
= 2312;
3164 pCap
->high_2ghz_chan
= 2732;
3166 pCap
->low_5ghz_chan
= 4920;
3167 pCap
->high_5ghz_chan
= 6100;
3169 pCap
->hw_caps
&= ~ATH9K_HW_CAP_CIPHER_CKIP
;
3170 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_TKIP
;
3171 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_AESCCM
;
3173 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MIC_CKIP
;
3174 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_TKIP
;
3175 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_AESCCM
;
3177 if (ah
->config
.ht_enable
)
3178 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
3180 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
3182 pCap
->hw_caps
|= ATH9K_HW_CAP_GTT
;
3183 pCap
->hw_caps
|= ATH9K_HW_CAP_VEOL
;
3184 pCap
->hw_caps
|= ATH9K_HW_CAP_BSSIDMASK
;
3185 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MCAST_KEYSEARCH
;
3187 if (capField
& AR_EEPROM_EEPCAP_MAXQCU
)
3188 pCap
->total_queues
=
3189 MS(capField
, AR_EEPROM_EEPCAP_MAXQCU
);
3191 pCap
->total_queues
= ATH9K_NUM_TX_QUEUES
;
3193 if (capField
& AR_EEPROM_EEPCAP_KC_ENTRIES
)
3194 pCap
->keycache_size
=
3195 1 << MS(capField
, AR_EEPROM_EEPCAP_KC_ENTRIES
);
3197 pCap
->keycache_size
= AR_KEYTABLE_SIZE
;
3199 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCC
;
3201 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
3202 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
>> 1;
3204 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
;
3206 if (AR_SREV_9271(ah
))
3207 pCap
->num_gpio_pins
= AR9271_NUM_GPIO
;
3208 else if (AR_SREV_9285_10_OR_LATER(ah
))
3209 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
3210 else if (AR_SREV_9280_10_OR_LATER(ah
))
3211 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
3213 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
3215 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
3216 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
3217 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
3219 pCap
->rts_aggr_limit
= (8 * 1024);
3222 pCap
->hw_caps
|= ATH9K_HW_CAP_ENHANCEDPM
;
3224 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3225 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
3226 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
3228 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
3229 ah
->rfkill_polarity
=
3230 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
3232 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
3236 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
3238 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
3239 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
3241 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
3243 if (regulatory
->current_rd_ext
& (1 << REG_EXT_JAPAN_MIDBAND
)) {
3245 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3246 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
|
3247 AR_EEPROM_EEREGCAP_EN_KK_U2
|
3248 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
;
3251 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3252 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
;
3255 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3256 if (regulatory
->current_rd_ext
& (1 << REG_EXT_FCC_MIDBAND
) &&
3258 pCap
->reg_cap
|= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
;
3260 pCap
->num_antcfg_5ghz
=
3261 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_5GHZ
);
3262 pCap
->num_antcfg_2ghz
=
3263 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_2GHZ
);
3265 if (AR_SREV_9280_10_OR_LATER(ah
) &&
3266 ath9k_hw_btcoex_supported(ah
)) {
3267 btcoex_hw
->btactive_gpio
= ATH_BTACTIVE_GPIO
;
3268 btcoex_hw
->wlanactive_gpio
= ATH_WLANACTIVE_GPIO
;
3270 if (AR_SREV_9285(ah
)) {
3271 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_3WIRE
;
3272 btcoex_hw
->btpriority_gpio
= ATH_BTPRIORITY_GPIO
;
3274 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_2WIRE
;
3277 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_NONE
;
3283 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3284 u32 capability
, u32
*result
)
3286 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3288 case ATH9K_CAP_CIPHER
:
3289 switch (capability
) {
3290 case ATH9K_CIPHER_AES_CCM
:
3291 case ATH9K_CIPHER_AES_OCB
:
3292 case ATH9K_CIPHER_TKIP
:
3293 case ATH9K_CIPHER_WEP
:
3294 case ATH9K_CIPHER_MIC
:
3295 case ATH9K_CIPHER_CLR
:
3300 case ATH9K_CAP_TKIP_MIC
:
3301 switch (capability
) {
3305 return (ah
->sta_id1_defaults
&
3306 AR_STA_ID1_CRPT_MIC_ENABLE
) ? true :
3309 case ATH9K_CAP_TKIP_SPLIT
:
3310 return (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) ?
3312 case ATH9K_CAP_DIVERSITY
:
3313 return (REG_READ(ah
, AR_PHY_CCK_DETECT
) &
3314 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
) ?
3316 case ATH9K_CAP_MCAST_KEYSRCH
:
3317 switch (capability
) {
3321 if (REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_ADHOC
) {
3324 return (ah
->sta_id1_defaults
&
3325 AR_STA_ID1_MCAST_KSRCH
) ? true :
3330 case ATH9K_CAP_TXPOW
:
3331 switch (capability
) {
3335 *result
= regulatory
->power_limit
;
3338 *result
= regulatory
->max_power_level
;
3341 *result
= regulatory
->tp_scale
;
3346 return (AR_SREV_9280_20_OR_LATER(ah
) &&
3347 (ah
->eep_ops
->get_eeprom(ah
, EEP_RC_CHAIN_MASK
) == 1))
3353 EXPORT_SYMBOL(ath9k_hw_getcapability
);
3355 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3356 u32 capability
, u32 setting
, int *status
)
3361 case ATH9K_CAP_TKIP_MIC
:
3363 ah
->sta_id1_defaults
|=
3364 AR_STA_ID1_CRPT_MIC_ENABLE
;
3366 ah
->sta_id1_defaults
&=
3367 ~AR_STA_ID1_CRPT_MIC_ENABLE
;
3369 case ATH9K_CAP_DIVERSITY
:
3370 v
= REG_READ(ah
, AR_PHY_CCK_DETECT
);
3372 v
|= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3374 v
&= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3375 REG_WRITE(ah
, AR_PHY_CCK_DETECT
, v
);
3377 case ATH9K_CAP_MCAST_KEYSRCH
:
3379 ah
->sta_id1_defaults
|= AR_STA_ID1_MCAST_KSRCH
;
3381 ah
->sta_id1_defaults
&= ~AR_STA_ID1_MCAST_KSRCH
;
3387 EXPORT_SYMBOL(ath9k_hw_setcapability
);
3389 /****************************/
3390 /* GPIO / RFKILL / Antennae */
3391 /****************************/
3393 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
3397 u32 gpio_shift
, tmp
;
3400 addr
= AR_GPIO_OUTPUT_MUX3
;
3402 addr
= AR_GPIO_OUTPUT_MUX2
;
3404 addr
= AR_GPIO_OUTPUT_MUX1
;
3406 gpio_shift
= (gpio
% 6) * 5;
3408 if (AR_SREV_9280_20_OR_LATER(ah
)
3409 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
3410 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
3411 (0x1f << gpio_shift
));
3413 tmp
= REG_READ(ah
, addr
);
3414 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
3415 tmp
&= ~(0x1f << gpio_shift
);
3416 tmp
|= (type
<< gpio_shift
);
3417 REG_WRITE(ah
, addr
, tmp
);
3421 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
3425 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
3427 gpio_shift
= gpio
<< 1;
3431 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
3432 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3434 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
3436 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
3438 #define MS_REG_READ(x, y) \
3439 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3441 if (gpio
>= ah
->caps
.num_gpio_pins
)
3444 if (AR_SREV_9271(ah
))
3445 return MS_REG_READ(AR9271
, gpio
) != 0;
3446 else if (AR_SREV_9287_10_OR_LATER(ah
))
3447 return MS_REG_READ(AR9287
, gpio
) != 0;
3448 else if (AR_SREV_9285_10_OR_LATER(ah
))
3449 return MS_REG_READ(AR9285
, gpio
) != 0;
3450 else if (AR_SREV_9280_10_OR_LATER(ah
))
3451 return MS_REG_READ(AR928X
, gpio
) != 0;
3453 return MS_REG_READ(AR
, gpio
) != 0;
3455 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
3457 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
3462 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
3464 gpio_shift
= 2 * gpio
;
3468 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
3469 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3471 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
3473 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
3475 if (AR_SREV_9271(ah
))
3478 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
3481 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
3483 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
3485 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
3487 EXPORT_SYMBOL(ath9k_hw_getdefantenna
);
3489 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
3491 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
3493 EXPORT_SYMBOL(ath9k_hw_setantenna
);
3495 /*********************/
3496 /* General Operation */
3497 /*********************/
3499 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
3501 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
3502 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
3504 if (phybits
& AR_PHY_ERR_RADAR
)
3505 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
3506 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
3507 bits
|= ATH9K_RX_FILTER_PHYERR
;
3511 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
3513 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
3517 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
3520 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
3521 phybits
|= AR_PHY_ERR_RADAR
;
3522 if (bits
& ATH9K_RX_FILTER_PHYERR
)
3523 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
3524 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
3527 REG_WRITE(ah
, AR_RXCFG
,
3528 REG_READ(ah
, AR_RXCFG
) | AR_RXCFG_ZLFDMA
);
3530 REG_WRITE(ah
, AR_RXCFG
,
3531 REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_ZLFDMA
);
3533 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
3535 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
3537 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
3540 ath9k_hw_init_pll(ah
, NULL
);
3543 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
3545 bool ath9k_hw_disable(struct ath_hw
*ah
)
3547 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
3550 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
3553 ath9k_hw_init_pll(ah
, NULL
);
3556 EXPORT_SYMBOL(ath9k_hw_disable
);
3558 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
)
3560 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3561 struct ath9k_channel
*chan
= ah
->curchan
;
3562 struct ieee80211_channel
*channel
= chan
->chan
;
3564 regulatory
->power_limit
= min(limit
, (u32
) MAX_RATE_POWER
);
3566 ah
->eep_ops
->set_txpower(ah
, chan
,
3567 ath9k_regd_get_ctl(regulatory
, chan
),
3568 channel
->max_antenna_gain
* 2,
3569 channel
->max_power
* 2,
3570 min((u32
) MAX_RATE_POWER
,
3571 (u32
) regulatory
->power_limit
));
3573 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
3575 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
)
3577 memcpy(ath9k_hw_common(ah
)->macaddr
, mac
, ETH_ALEN
);
3579 EXPORT_SYMBOL(ath9k_hw_setmac
);
3581 void ath9k_hw_setopmode(struct ath_hw
*ah
)
3583 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
3585 EXPORT_SYMBOL(ath9k_hw_setopmode
);
3587 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
3589 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
3590 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
3592 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
3594 void ath9k_hw_write_associd(struct ath_hw
*ah
)
3596 struct ath_common
*common
= ath9k_hw_common(ah
);
3598 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
3599 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
3600 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
3602 EXPORT_SYMBOL(ath9k_hw_write_associd
);
3604 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
3608 tsf
= REG_READ(ah
, AR_TSF_U32
);
3609 tsf
= (tsf
<< 32) | REG_READ(ah
, AR_TSF_L32
);
3613 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
3615 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
3617 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
3618 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
3620 EXPORT_SYMBOL(ath9k_hw_settsf64
);
3622 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
3624 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
3625 AH_TSF_WRITE_TIMEOUT
))
3626 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
3627 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3629 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
3631 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
3633 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
3636 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
3638 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
3640 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
3643 * Extend 15-bit time stamp from rx descriptor to
3644 * a full 64-bit TSF using the current h/w TSF.
3646 u64
ath9k_hw_extend_tsf(struct ath_hw
*ah
, u32 rstamp
)
3650 tsf
= ath9k_hw_gettsf64(ah
);
3651 if ((tsf
& 0x7fff) < rstamp
)
3653 return (tsf
& ~0x7fff) | rstamp
;
3655 EXPORT_SYMBOL(ath9k_hw_extend_tsf
);
3657 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
)
3659 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
3662 if (conf_is_ht40(conf
) && !ah
->config
.cwm_ignore_extcca
)
3663 macmode
= AR_2040_JOINED_RX_CLEAR
;
3667 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
3670 /* HW Generic timers configuration */
3672 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
3674 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3675 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3676 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3677 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3678 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3679 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3680 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3681 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3682 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
3683 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
3684 AR_NDP2_TIMER_MODE
, 0x0002},
3685 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
3686 AR_NDP2_TIMER_MODE
, 0x0004},
3687 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
3688 AR_NDP2_TIMER_MODE
, 0x0008},
3689 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
3690 AR_NDP2_TIMER_MODE
, 0x0010},
3691 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
3692 AR_NDP2_TIMER_MODE
, 0x0020},
3693 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
3694 AR_NDP2_TIMER_MODE
, 0x0040},
3695 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
3696 AR_NDP2_TIMER_MODE
, 0x0080}
3699 /* HW generic timer primitives */
3701 /* compute and clear index of rightmost 1 */
3702 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
3712 return timer_table
->gen_timer_index
[b
];
3715 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
3717 return REG_READ(ah
, AR_TSF_L32
);
3719 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
3721 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
3722 void (*trigger
)(void *),
3723 void (*overflow
)(void *),
3727 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3728 struct ath_gen_timer
*timer
;
3730 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
3732 if (timer
== NULL
) {
3733 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
3734 "Failed to allocate memory"
3735 "for hw timer[%d]\n", timer_index
);
3739 /* allocate a hardware generic timer slot */
3740 timer_table
->timers
[timer_index
] = timer
;
3741 timer
->index
= timer_index
;
3742 timer
->trigger
= trigger
;
3743 timer
->overflow
= overflow
;
3748 EXPORT_SYMBOL(ath_gen_timer_alloc
);
3750 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
3751 struct ath_gen_timer
*timer
,
3755 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3758 BUG_ON(!timer_period
);
3760 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3762 tsf
= ath9k_hw_gettsf32(ah
);
3764 ath_print(ath9k_hw_common(ah
), ATH_DBG_HWTIMER
,
3765 "curent tsf %x period %x"
3766 "timer_next %x\n", tsf
, timer_period
, timer_next
);
3769 * Pull timer_next forward if the current TSF already passed it
3770 * because of software latency
3772 if (timer_next
< tsf
)
3773 timer_next
= tsf
+ timer_period
;
3776 * Program generic timer registers
3778 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
3780 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
3782 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3783 gen_tmr_configuration
[timer
->index
].mode_mask
);
3785 /* Enable both trigger and thresh interrupt masks */
3786 REG_SET_BIT(ah
, AR_IMR_S5
,
3787 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3788 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3790 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
3792 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3794 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3796 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
3797 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
3801 /* Clear generic timer enable bits. */
3802 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3803 gen_tmr_configuration
[timer
->index
].mode_mask
);
3805 /* Disable both trigger and thresh interrupt masks */
3806 REG_CLR_BIT(ah
, AR_IMR_S5
,
3807 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3808 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3810 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3812 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
3814 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3816 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3818 /* free the hardware generic timer slot */
3819 timer_table
->timers
[timer
->index
] = NULL
;
3822 EXPORT_SYMBOL(ath_gen_timer_free
);
3825 * Generic Timer Interrupts handling
3827 void ath_gen_timer_isr(struct ath_hw
*ah
)
3829 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3830 struct ath_gen_timer
*timer
;
3831 struct ath_common
*common
= ath9k_hw_common(ah
);
3832 u32 trigger_mask
, thresh_mask
, index
;
3834 /* get hardware generic timer interrupt status */
3835 trigger_mask
= ah
->intr_gen_timer_trigger
;
3836 thresh_mask
= ah
->intr_gen_timer_thresh
;
3837 trigger_mask
&= timer_table
->timer_mask
.val
;
3838 thresh_mask
&= timer_table
->timer_mask
.val
;
3840 trigger_mask
&= ~thresh_mask
;
3842 while (thresh_mask
) {
3843 index
= rightmost_index(timer_table
, &thresh_mask
);
3844 timer
= timer_table
->timers
[index
];
3846 ath_print(common
, ATH_DBG_HWTIMER
,
3847 "TSF overflow for Gen timer %d\n", index
);
3848 timer
->overflow(timer
->arg
);
3851 while (trigger_mask
) {
3852 index
= rightmost_index(timer_table
, &trigger_mask
);
3853 timer
= timer_table
->timers
[index
];
3855 ath_print(common
, ATH_DBG_HWTIMER
,
3856 "Gen timer[%d] trigger\n", index
);
3857 timer
->trigger(timer
->arg
);
3860 EXPORT_SYMBOL(ath_gen_timer_isr
);
3866 void ath9k_hw_htc_resetinit(struct ath_hw
*ah
)
3868 ah
->htc_reset_init
= true;
3870 EXPORT_SYMBOL(ath9k_hw_htc_resetinit
);
3875 } ath_mac_bb_names
[] = {
3876 /* Devices with external radios */
3877 { AR_SREV_VERSION_5416_PCI
, "5416" },
3878 { AR_SREV_VERSION_5416_PCIE
, "5418" },
3879 { AR_SREV_VERSION_9100
, "9100" },
3880 { AR_SREV_VERSION_9160
, "9160" },
3881 /* Single-chip solutions */
3882 { AR_SREV_VERSION_9280
, "9280" },
3883 { AR_SREV_VERSION_9285
, "9285" },
3884 { AR_SREV_VERSION_9287
, "9287" },
3885 { AR_SREV_VERSION_9271
, "9271" },
3888 /* For devices with external radios */
3892 } ath_rf_names
[] = {
3894 { AR_RAD5133_SREV_MAJOR
, "5133" },
3895 { AR_RAD5122_SREV_MAJOR
, "5122" },
3896 { AR_RAD2133_SREV_MAJOR
, "2133" },
3897 { AR_RAD2122_SREV_MAJOR
, "2122" }
3901 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3903 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
3907 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
3908 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
3909 return ath_mac_bb_names
[i
].name
;
3917 * Return the RF name. "????" is returned if the RF is unknown.
3918 * Used for devices with external radios.
3920 static const char *ath9k_hw_rf_name(u16 rf_version
)
3924 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
3925 if (ath_rf_names
[i
].version
== rf_version
) {
3926 return ath_rf_names
[i
].name
;
3933 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
3937 /* chipsets >= AR9280 are single-chip */
3938 if (AR_SREV_9280_10_OR_LATER(ah
)) {
3939 used
= snprintf(hw_name
, len
,
3940 "Atheros AR%s Rev:%x",
3941 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3942 ah
->hw_version
.macRev
);
3945 used
= snprintf(hw_name
, len
,
3946 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3947 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3948 ah
->hw_version
.macRev
,
3949 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
&
3950 AR_RADIO_SREV_MAJOR
)),
3951 ah
->hw_version
.phyRev
);
3954 hw_name
[used
] = '\0';
3956 EXPORT_SYMBOL(ath9k_hw_name
);