2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
30 MODULE_AUTHOR("Atheros Communications");
31 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33 MODULE_LICENSE("Dual BSD/GPL");
35 static int __init
ath9k_init(void)
39 module_init(ath9k_init
);
41 static void __exit
ath9k_exit(void)
45 module_exit(ath9k_exit
);
47 /* Private hardware callbacks */
49 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
51 ath9k_hw_private_ops(ah
)->init_cal_settings(ah
);
54 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
56 ath9k_hw_private_ops(ah
)->init_mode_regs(ah
);
59 static bool ath9k_hw_macversion_supported(struct ath_hw
*ah
)
61 struct ath_hw_private_ops
*priv_ops
= ath9k_hw_private_ops(ah
);
63 return priv_ops
->macversion_supported(ah
->hw_version
.macVersion
);
66 static u32
ath9k_hw_compute_pll_control(struct ath_hw
*ah
,
67 struct ath9k_channel
*chan
)
69 return ath9k_hw_private_ops(ah
)->compute_pll_control(ah
, chan
);
72 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
74 if (!ath9k_hw_private_ops(ah
)->init_mode_gain_regs
)
77 ath9k_hw_private_ops(ah
)->init_mode_gain_regs(ah
);
80 /********************/
81 /* Helper Functions */
82 /********************/
84 static u32
ath9k_hw_mac_clks(struct ath_hw
*ah
, u32 usecs
)
86 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
88 if (!ah
->curchan
) /* should really check for CCK instead */
89 return usecs
*ATH9K_CLOCK_RATE_CCK
;
90 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
91 return usecs
*ATH9K_CLOCK_RATE_2GHZ_OFDM
;
92 return usecs
*ATH9K_CLOCK_RATE_5GHZ_OFDM
;
95 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
97 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
99 if (conf_is_ht40(conf
))
100 return ath9k_hw_mac_clks(ah
, usecs
) * 2;
102 return ath9k_hw_mac_clks(ah
, usecs
);
105 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
109 BUG_ON(timeout
< AH_TIME_QUANTUM
);
111 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
112 if ((REG_READ(ah
, reg
) & mask
) == val
)
115 udelay(AH_TIME_QUANTUM
);
118 ath_print(ath9k_hw_common(ah
), ATH_DBG_ANY
,
119 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
120 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
124 EXPORT_SYMBOL(ath9k_hw_wait
);
126 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
131 for (i
= 0, retval
= 0; i
< n
; i
++) {
132 retval
= (retval
<< 1) | (val
& 1);
138 bool ath9k_get_channel_edges(struct ath_hw
*ah
,
142 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
144 if (flags
& CHANNEL_5GHZ
) {
145 *low
= pCap
->low_5ghz_chan
;
146 *high
= pCap
->high_5ghz_chan
;
149 if ((flags
& CHANNEL_2GHZ
)) {
150 *low
= pCap
->low_2ghz_chan
;
151 *high
= pCap
->high_2ghz_chan
;
157 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
159 u32 frameLen
, u16 rateix
,
162 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
168 case WLAN_RC_PHY_CCK
:
169 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
172 numBits
= frameLen
<< 3;
173 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
175 case WLAN_RC_PHY_OFDM
:
176 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
177 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
178 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
179 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
180 txTime
= OFDM_SIFS_TIME_QUARTER
181 + OFDM_PREAMBLE_TIME_QUARTER
182 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
183 } else if (ah
->curchan
&&
184 IS_CHAN_HALF_RATE(ah
->curchan
)) {
185 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
186 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
187 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
188 txTime
= OFDM_SIFS_TIME_HALF
+
189 OFDM_PREAMBLE_TIME_HALF
190 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
192 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
193 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
194 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
195 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
196 + (numSymbols
* OFDM_SYMBOL_TIME
);
200 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
201 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
208 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
210 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
211 struct ath9k_channel
*chan
,
212 struct chan_centers
*centers
)
216 if (!IS_CHAN_HT40(chan
)) {
217 centers
->ctl_center
= centers
->ext_center
=
218 centers
->synth_center
= chan
->channel
;
222 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
223 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
224 centers
->synth_center
=
225 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
228 centers
->synth_center
=
229 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
233 centers
->ctl_center
=
234 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
235 /* 25 MHz spacing is supported by hw but not on upper layers */
236 centers
->ext_center
=
237 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
244 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
248 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
251 val
= REG_READ(ah
, AR_SREV
);
252 ah
->hw_version
.macVersion
=
253 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
254 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
255 ah
->is_pciexpress
= (val
& AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
257 if (!AR_SREV_9100(ah
))
258 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
260 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
262 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
263 ah
->is_pciexpress
= true;
267 static int ath9k_hw_get_radiorev(struct ath_hw
*ah
)
272 REG_WRITE(ah
, AR_PHY(0x36), 0x00007058);
274 for (i
= 0; i
< 8; i
++)
275 REG_WRITE(ah
, AR_PHY(0x20), 0x00010000);
276 val
= (REG_READ(ah
, AR_PHY(256)) >> 24) & 0xff;
277 val
= ((val
& 0xf0) >> 4) | ((val
& 0x0f) << 4);
279 return ath9k_hw_reverse_bits(val
, 8);
282 /************************************/
283 /* HW Attach, Detach, Init Routines */
284 /************************************/
286 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
288 if (AR_SREV_9100(ah
))
291 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
292 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
293 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
294 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
295 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
296 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
297 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
298 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
299 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
301 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
304 /* This should work for all families including legacy */
305 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
307 struct ath_common
*common
= ath9k_hw_common(ah
);
308 u32 regAddr
[2] = { AR_STA_ID0
};
310 u32 patternData
[4] = { 0x55555555,
316 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
318 regAddr
[1] = AR_PHY_BASE
+ (8 << 2);
322 for (i
= 0; i
< loop_max
; i
++) {
323 u32 addr
= regAddr
[i
];
326 regHold
[i
] = REG_READ(ah
, addr
);
327 for (j
= 0; j
< 0x100; j
++) {
328 wrData
= (j
<< 16) | j
;
329 REG_WRITE(ah
, addr
, wrData
);
330 rdData
= REG_READ(ah
, addr
);
331 if (rdData
!= wrData
) {
332 ath_print(common
, ATH_DBG_FATAL
,
333 "address test failed "
334 "addr: 0x%08x - wr:0x%08x != "
336 addr
, wrData
, rdData
);
340 for (j
= 0; j
< 4; j
++) {
341 wrData
= patternData
[j
];
342 REG_WRITE(ah
, addr
, wrData
);
343 rdData
= REG_READ(ah
, addr
);
344 if (wrData
!= rdData
) {
345 ath_print(common
, ATH_DBG_FATAL
,
346 "address test failed "
347 "addr: 0x%08x - wr:0x%08x != "
349 addr
, wrData
, rdData
);
353 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
360 static void ath9k_hw_init_config(struct ath_hw
*ah
)
364 ah
->config
.dma_beacon_response_time
= 2;
365 ah
->config
.sw_beacon_response_time
= 10;
366 ah
->config
.additional_swba_backoff
= 0;
367 ah
->config
.ack_6mb
= 0x0;
368 ah
->config
.cwm_ignore_extcca
= 0;
369 ah
->config
.pcie_powersave_enable
= 0;
370 ah
->config
.pcie_clock_req
= 0;
371 ah
->config
.pcie_waen
= 0;
372 ah
->config
.analog_shiftreg
= 1;
373 ah
->config
.ofdm_trig_low
= 200;
374 ah
->config
.ofdm_trig_high
= 500;
375 ah
->config
.cck_trig_high
= 200;
376 ah
->config
.cck_trig_low
= 100;
379 * For now ANI is disabled for AR9003, it is still
382 if (!AR_SREV_9300_20_OR_LATER(ah
))
383 ah
->config
.enable_ani
= 1;
385 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
386 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
387 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
390 if (ah
->hw_version
.devid
!= AR2427_DEVID_PCIE
)
391 ah
->config
.ht_enable
= 1;
393 ah
->config
.ht_enable
= 0;
395 ah
->config
.rx_intr_mitigation
= true;
398 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
399 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
400 * This means we use it for all AR5416 devices, and the few
401 * minor PCI AR9280 devices out there.
403 * Serialization is required because these devices do not handle
404 * well the case of two concurrent reads/writes due to the latency
405 * involved. During one read/write another read/write can be issued
406 * on another CPU while the previous read/write may still be working
407 * on our hardware, if we hit this case the hardware poops in a loop.
408 * We prevent this by serializing reads and writes.
410 * This issue is not present on PCI-Express devices or pre-AR5416
411 * devices (legacy, 802.11abg).
413 if (num_possible_cpus() > 1)
414 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
417 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
419 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
421 regulatory
->country_code
= CTRY_DEFAULT
;
422 regulatory
->power_limit
= MAX_RATE_POWER
;
423 regulatory
->tp_scale
= ATH9K_TP_SCALE_MAX
;
425 ah
->hw_version
.magic
= AR5416_MAGIC
;
426 ah
->hw_version
.subvendorid
= 0;
429 if (!AR_SREV_9100(ah
))
430 ah
->ah_flags
= AH_USE_EEPROM
;
433 ah
->sta_id1_defaults
= AR_STA_ID1_CRPT_MIC_ENABLE
;
434 ah
->beacon_interval
= 100;
435 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
436 ah
->slottime
= (u32
) -1;
437 ah
->globaltxtimeout
= (u32
) -1;
438 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
441 static int ath9k_hw_rf_claim(struct ath_hw
*ah
)
445 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
447 val
= ath9k_hw_get_radiorev(ah
);
448 switch (val
& AR_RADIO_SREV_MAJOR
) {
450 val
= AR_RAD5133_SREV_MAJOR
;
452 case AR_RAD5133_SREV_MAJOR
:
453 case AR_RAD5122_SREV_MAJOR
:
454 case AR_RAD2133_SREV_MAJOR
:
455 case AR_RAD2122_SREV_MAJOR
:
458 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
459 "Radio Chip Rev 0x%02X not supported\n",
460 val
& AR_RADIO_SREV_MAJOR
);
464 ah
->hw_version
.analog5GhzRev
= val
;
469 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
471 struct ath_common
*common
= ath9k_hw_common(ah
);
475 u32 EEP_MAC
[] = { EEP_MAC_LSW
, EEP_MAC_MID
, EEP_MAC_MSW
};
478 for (i
= 0; i
< 3; i
++) {
479 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_MAC
[i
]);
481 common
->macaddr
[2 * i
] = eeval
>> 8;
482 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
484 if (sum
== 0 || sum
== 0xffff * 3)
485 return -EADDRNOTAVAIL
;
490 static int ath9k_hw_post_init(struct ath_hw
*ah
)
494 if (!AR_SREV_9271(ah
)) {
495 if (!ath9k_hw_chip_test(ah
))
499 ecode
= ath9k_hw_rf_claim(ah
);
503 ecode
= ath9k_hw_eeprom_init(ah
);
507 ath_print(ath9k_hw_common(ah
), ATH_DBG_CONFIG
,
508 "Eeprom VER: %d, REV: %d\n",
509 ah
->eep_ops
->get_eeprom_ver(ah
),
510 ah
->eep_ops
->get_eeprom_rev(ah
));
512 ecode
= ath9k_hw_rf_alloc_ext_banks(ah
);
514 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
515 "Failed allocating banks for "
520 if (!AR_SREV_9100(ah
)) {
521 ath9k_hw_ani_setup(ah
);
522 ath9k_hw_ani_init(ah
);
528 static void ath9k_hw_init_eeprom_fix(struct ath_hw
*ah
)
530 struct base_eep_header
*pBase
= &(ah
->eeprom
.def
.baseEepHeader
);
531 struct ath_common
*common
= ath9k_hw_common(ah
);
533 ah
->need_an_top2_fixup
= (ah
->hw_version
.devid
== AR9280_DEVID_PCI
) &&
534 !AR_SREV_9285(ah
) && !AR_SREV_9271(ah
) &&
535 ((pBase
->version
& 0xff) > 0x0a) &&
536 (pBase
->pwdclkind
== 0);
538 if (ah
->need_an_top2_fixup
)
539 ath_print(common
, ATH_DBG_EEPROM
,
540 "needs fixup for AR_AN_TOP2 register\n");
543 static void ath9k_hw_attach_ops(struct ath_hw
*ah
)
545 if (AR_SREV_9300_20_OR_LATER(ah
))
546 ar9003_hw_attach_ops(ah
);
548 ar9002_hw_attach_ops(ah
);
551 /* Called for all hardware families */
552 static int __ath9k_hw_init(struct ath_hw
*ah
)
554 struct ath_common
*common
= ath9k_hw_common(ah
);
557 if (ah
->hw_version
.devid
== AR5416_AR9100_DEVID
)
558 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
560 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
561 ath_print(common
, ATH_DBG_FATAL
,
562 "Couldn't reset chip\n");
566 ath9k_hw_init_defaults(ah
);
567 ath9k_hw_init_config(ah
);
569 ath9k_hw_attach_ops(ah
);
571 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
572 ath_print(common
, ATH_DBG_FATAL
, "Couldn't wakeup chip\n");
576 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
577 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
578 (AR_SREV_9280(ah
) && !ah
->is_pciexpress
)) {
579 ah
->config
.serialize_regmode
=
582 ah
->config
.serialize_regmode
=
587 ath_print(common
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
588 ah
->config
.serialize_regmode
);
590 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
591 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
593 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
595 if (!ath9k_hw_macversion_supported(ah
)) {
596 ath_print(common
, ATH_DBG_FATAL
,
597 "Mac Chip Rev 0x%02x.%x is not supported by "
598 "this driver\n", ah
->hw_version
.macVersion
,
599 ah
->hw_version
.macRev
);
603 if (AR_SREV_9271(ah
) || AR_SREV_9100(ah
))
604 ah
->is_pciexpress
= false;
606 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
607 ath9k_hw_init_cal_settings(ah
);
609 ah
->ani_function
= ATH9K_ANI_ALL
;
610 if (AR_SREV_9280_10_OR_LATER(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
611 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
613 ath9k_hw_init_mode_regs(ah
);
615 if (ah
->is_pciexpress
)
616 ath9k_hw_configpcipowersave(ah
, 0, 0);
618 ath9k_hw_disablepcie(ah
);
620 if (!AR_SREV_9300_20_OR_LATER(ah
))
621 ar9002_hw_cck_chan14_spread(ah
);
623 r
= ath9k_hw_post_init(ah
);
627 ath9k_hw_init_mode_gain_regs(ah
);
628 r
= ath9k_hw_fill_cap_info(ah
);
632 ath9k_hw_init_eeprom_fix(ah
);
634 r
= ath9k_hw_init_macaddr(ah
);
636 ath_print(common
, ATH_DBG_FATAL
,
637 "Failed to initialize MAC address\n");
641 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
642 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
644 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
646 if (AR_SREV_9300_20_OR_LATER(ah
))
647 ar9003_hw_set_nf_limits(ah
);
649 ath9k_init_nfcal_hist_buffer(ah
);
651 common
->state
= ATH_HW_INITIALIZED
;
656 int ath9k_hw_init(struct ath_hw
*ah
)
659 struct ath_common
*common
= ath9k_hw_common(ah
);
661 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
662 switch (ah
->hw_version
.devid
) {
663 case AR5416_DEVID_PCI
:
664 case AR5416_DEVID_PCIE
:
665 case AR5416_AR9100_DEVID
:
666 case AR9160_DEVID_PCI
:
667 case AR9280_DEVID_PCI
:
668 case AR9280_DEVID_PCIE
:
669 case AR9285_DEVID_PCIE
:
670 case AR9287_DEVID_PCI
:
671 case AR9287_DEVID_PCIE
:
672 case AR2427_DEVID_PCIE
:
673 case AR9300_DEVID_PCIE
:
676 if (common
->bus_ops
->ath_bus_type
== ATH_USB
)
678 ath_print(common
, ATH_DBG_FATAL
,
679 "Hardware device ID 0x%04x not supported\n",
680 ah
->hw_version
.devid
);
684 ret
= __ath9k_hw_init(ah
);
686 ath_print(common
, ATH_DBG_FATAL
,
687 "Unable to initialize hardware; "
688 "initialization status: %d\n", ret
);
694 EXPORT_SYMBOL(ath9k_hw_init
);
696 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
698 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
699 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
701 REG_WRITE(ah
, AR_QOS_NO_ACK
,
702 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
703 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
704 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
706 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
707 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
708 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
709 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
710 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
713 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
714 struct ath9k_channel
*chan
)
716 u32 pll
= ath9k_hw_compute_pll_control(ah
, chan
);
718 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
720 /* Switch the core clock for ar9271 to 117Mhz */
721 if (AR_SREV_9271(ah
)) {
723 REG_WRITE(ah
, 0x50040, 0x304);
726 udelay(RTC_PLL_SETTLE_DELAY
);
728 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
731 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
732 enum nl80211_iftype opmode
)
734 u32 imr_reg
= AR_IMR_TXERR
|
740 if (AR_SREV_9300_20_OR_LATER(ah
)) {
741 imr_reg
|= AR_IMR_RXOK_HP
;
742 if (ah
->config
.rx_intr_mitigation
)
743 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
745 imr_reg
|= AR_IMR_RXOK_LP
;
748 if (ah
->config
.rx_intr_mitigation
)
749 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
751 imr_reg
|= AR_IMR_RXOK
;
754 if (ah
->config
.tx_intr_mitigation
)
755 imr_reg
|= AR_IMR_TXINTM
| AR_IMR_TXMINTR
;
757 imr_reg
|= AR_IMR_TXOK
;
759 if (opmode
== NL80211_IFTYPE_AP
)
760 imr_reg
|= AR_IMR_MIB
;
762 REG_WRITE(ah
, AR_IMR
, imr_reg
);
763 ah
->imrs2_reg
|= AR_IMR_S2_GTT
;
764 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
766 if (!AR_SREV_9100(ah
)) {
767 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
768 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, AR_INTR_SYNC_DEFAULT
);
769 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
772 if (AR_SREV_9300_20_OR_LATER(ah
)) {
773 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_ENABLE
, 0);
774 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_MASK
, 0);
775 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_ENABLE
, 0);
776 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_MASK
, 0);
780 static void ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
782 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
783 val
= min(val
, (u32
) 0xFFFF);
784 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, val
);
787 static void ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
789 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
790 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_ACK
));
791 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK
, val
);
794 static void ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
796 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
797 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_CTS
));
798 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_CTS
, val
);
801 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
804 ath_print(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
805 "bad global tx timeout %u\n", tu
);
806 ah
->globaltxtimeout
= (u32
) -1;
809 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
810 ah
->globaltxtimeout
= tu
;
815 void ath9k_hw_init_global_settings(struct ath_hw
*ah
)
817 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
822 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
825 if (ah
->misc_mode
!= 0)
826 REG_WRITE(ah
, AR_PCU_MISC
,
827 REG_READ(ah
, AR_PCU_MISC
) | ah
->misc_mode
);
829 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_5GHZ
)
834 /* As defined by IEEE 802.11-2007 17.3.8.6 */
835 slottime
= ah
->slottime
+ 3 * ah
->coverage_class
;
836 acktimeout
= slottime
+ sifstime
;
839 * Workaround for early ACK timeouts, add an offset to match the
840 * initval's 64us ack timeout value.
841 * This was initially only meant to work around an issue with delayed
842 * BA frames in some implementations, but it has been found to fix ACK
843 * timeout issues in other cases as well.
845 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
846 acktimeout
+= 64 - sifstime
- ah
->slottime
;
848 ath9k_hw_setslottime(ah
, slottime
);
849 ath9k_hw_set_ack_timeout(ah
, acktimeout
);
850 ath9k_hw_set_cts_timeout(ah
, acktimeout
);
851 if (ah
->globaltxtimeout
!= (u32
) -1)
852 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
854 EXPORT_SYMBOL(ath9k_hw_init_global_settings
);
856 void ath9k_hw_deinit(struct ath_hw
*ah
)
858 struct ath_common
*common
= ath9k_hw_common(ah
);
860 if (common
->state
< ATH_HW_INITIALIZED
)
863 if (!AR_SREV_9100(ah
))
864 ath9k_hw_ani_disable(ah
);
866 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
869 ath9k_hw_rf_free_ext_banks(ah
);
871 EXPORT_SYMBOL(ath9k_hw_deinit
);
877 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
)
879 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
883 else if (IS_CHAN_G(chan
))
891 /****************************************/
892 /* Reset and Channel Switching Routines */
893 /****************************************/
895 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
900 * set AHB_MODE not to do cacheline prefetches
902 regval
= REG_READ(ah
, AR_AHB_MODE
);
903 REG_WRITE(ah
, AR_AHB_MODE
, regval
| AR_AHB_PREFETCH_RD_EN
);
906 * let mac dma reads be in 128 byte chunks
908 regval
= REG_READ(ah
, AR_TXCFG
) & ~AR_TXCFG_DMASZ_MASK
;
909 REG_WRITE(ah
, AR_TXCFG
, regval
| AR_TXCFG_DMASZ_128B
);
912 * Restore TX Trigger Level to its pre-reset value.
913 * The initial value depends on whether aggregation is enabled, and is
914 * adjusted whenever underruns are detected.
916 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
919 * let mac dma writes be in 128 byte chunks
921 regval
= REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_DMASZ_MASK
;
922 REG_WRITE(ah
, AR_RXCFG
, regval
| AR_RXCFG_DMASZ_128B
);
925 * Setup receive FIFO threshold to hold off TX activities
927 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
930 * reduce the number of usable entries in PCU TXBUF to avoid
931 * wrap around issues.
933 if (AR_SREV_9285(ah
)) {
934 /* For AR9285 the number of Fifos are reduced to half.
935 * So set the usable tx buf size also to half to
936 * avoid data/delimiter underruns
938 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
939 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
940 } else if (!AR_SREV_9271(ah
)) {
941 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
942 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
946 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
950 val
= REG_READ(ah
, AR_STA_ID1
);
951 val
&= ~(AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
);
953 case NL80211_IFTYPE_AP
:
954 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_STA_AP
955 | AR_STA_ID1_KSRCH_MODE
);
956 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
958 case NL80211_IFTYPE_ADHOC
:
959 case NL80211_IFTYPE_MESH_POINT
:
960 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_ADHOC
961 | AR_STA_ID1_KSRCH_MODE
);
962 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
964 case NL80211_IFTYPE_STATION
:
965 case NL80211_IFTYPE_MONITOR
:
966 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
971 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
972 u32
*coef_mantissa
, u32
*coef_exponent
)
974 u32 coef_exp
, coef_man
;
976 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
977 if ((coef_scaled
>> coef_exp
) & 0x1)
980 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
982 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
984 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
985 *coef_exponent
= coef_exp
- 16;
988 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
993 if (AR_SREV_9100(ah
)) {
994 u32 val
= REG_READ(ah
, AR_RTC_DERIVED_CLK
);
995 val
&= ~AR_RTC_DERIVED_CLK_PERIOD
;
996 val
|= SM(1, AR_RTC_DERIVED_CLK_PERIOD
);
997 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, val
);
998 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1001 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1002 AR_RTC_FORCE_WAKE_ON_INT
);
1004 if (AR_SREV_9100(ah
)) {
1005 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1006 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1008 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1010 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1011 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1013 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1016 if (!AR_SREV_9300_20_OR_LATER(ah
))
1018 REG_WRITE(ah
, AR_RC
, val
);
1020 } else if (!AR_SREV_9300_20_OR_LATER(ah
))
1021 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1023 rst_flags
= AR_RTC_RC_MAC_WARM
;
1024 if (type
== ATH9K_RESET_COLD
)
1025 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1028 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1031 REG_WRITE(ah
, AR_RTC_RC
, 0);
1032 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1033 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1034 "RTC stuck in MAC reset\n");
1038 if (!AR_SREV_9100(ah
))
1039 REG_WRITE(ah
, AR_RC
, 0);
1041 if (AR_SREV_9100(ah
))
1047 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1049 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1050 AR_RTC_FORCE_WAKE_ON_INT
);
1052 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1053 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1055 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1057 if (!AR_SREV_9300_20_OR_LATER(ah
))
1060 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1061 REG_WRITE(ah
, AR_RC
, 0);
1063 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1065 if (!ath9k_hw_wait(ah
,
1070 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1071 "RTC not waking up\n");
1075 ath9k_hw_read_revisions(ah
);
1077 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1080 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1082 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1083 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1086 case ATH9K_RESET_POWER_ON
:
1087 return ath9k_hw_set_reset_power_on(ah
);
1088 case ATH9K_RESET_WARM
:
1089 case ATH9K_RESET_COLD
:
1090 return ath9k_hw_set_reset(ah
, type
);
1096 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1097 struct ath9k_channel
*chan
)
1099 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
1100 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1102 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1105 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1108 ah
->chip_fullsleep
= false;
1109 ath9k_hw_init_pll(ah
, chan
);
1110 ath9k_hw_set_rfmode(ah
, chan
);
1115 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1116 struct ath9k_channel
*chan
)
1118 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1119 struct ath_common
*common
= ath9k_hw_common(ah
);
1120 struct ieee80211_channel
*channel
= chan
->chan
;
1124 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1125 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1126 ath_print(common
, ATH_DBG_QUEUE
,
1127 "Transmit frames pending on "
1128 "queue %d\n", qnum
);
1133 if (!ath9k_hw_rfbus_req(ah
)) {
1134 ath_print(common
, ATH_DBG_FATAL
,
1135 "Could not kill baseband RX\n");
1139 ath9k_hw_set_channel_regs(ah
, chan
);
1141 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1143 ath_print(common
, ATH_DBG_FATAL
,
1144 "Failed to set channel\n");
1148 ah
->eep_ops
->set_txpower(ah
, chan
,
1149 ath9k_regd_get_ctl(regulatory
, chan
),
1150 channel
->max_antenna_gain
* 2,
1151 channel
->max_power
* 2,
1152 min((u32
) MAX_RATE_POWER
,
1153 (u32
) regulatory
->power_limit
));
1155 ath9k_hw_rfbus_done(ah
);
1157 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1158 ath9k_hw_set_delta_slope(ah
, chan
);
1160 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1162 if (!chan
->oneTimeCalsDone
)
1163 chan
->oneTimeCalsDone
= true;
1168 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1169 bool bChannelChange
)
1171 struct ath_common
*common
= ath9k_hw_common(ah
);
1173 struct ath9k_channel
*curchan
= ah
->curchan
;
1179 ah
->txchainmask
= common
->tx_chainmask
;
1180 ah
->rxchainmask
= common
->rx_chainmask
;
1182 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1185 if (curchan
&& !ah
->chip_fullsleep
)
1186 ath9k_hw_getnf(ah
, curchan
);
1188 if (bChannelChange
&&
1189 (ah
->chip_fullsleep
!= true) &&
1190 (ah
->curchan
!= NULL
) &&
1191 (chan
->channel
!= ah
->curchan
->channel
) &&
1192 ((chan
->channelFlags
& CHANNEL_ALL
) ==
1193 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)) &&
1194 !(AR_SREV_9280(ah
) || IS_CHAN_A_5MHZ_SPACED(chan
) ||
1195 IS_CHAN_A_5MHZ_SPACED(ah
->curchan
))) {
1197 if (ath9k_hw_channel_change(ah
, chan
)) {
1198 ath9k_hw_loadnf(ah
, ah
->curchan
);
1199 ath9k_hw_start_nfcal(ah
);
1204 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1205 if (saveDefAntenna
== 0)
1208 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1210 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1211 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1212 tsf
= ath9k_hw_gettsf64(ah
);
1214 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1215 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1216 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1218 ath9k_hw_mark_phy_inactive(ah
);
1220 /* Only required on the first reset */
1221 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1223 AR9271_RESET_POWER_DOWN_CONTROL
,
1224 AR9271_RADIO_RF_RST
);
1228 if (!ath9k_hw_chip_reset(ah
, chan
)) {
1229 ath_print(common
, ATH_DBG_FATAL
, "Chip reset failed\n");
1233 /* Only required on the first reset */
1234 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1235 ah
->htc_reset_init
= false;
1237 AR9271_RESET_POWER_DOWN_CONTROL
,
1238 AR9271_GATE_MAC_CTL
);
1243 if (tsf
&& AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1244 ath9k_hw_settsf64(ah
, tsf
);
1246 if (AR_SREV_9280_10_OR_LATER(ah
))
1247 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
1249 r
= ath9k_hw_process_ini(ah
, chan
);
1253 /* Setup MFP options for CCMP */
1254 if (AR_SREV_9280_20_OR_LATER(ah
)) {
1255 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1256 * frames when constructing CCMP AAD. */
1257 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
1259 ah
->sw_mgmt_crypto
= false;
1260 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1261 /* Disable hardware crypto for management frames */
1262 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
1263 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
1264 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1265 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
1266 ah
->sw_mgmt_crypto
= true;
1268 ah
->sw_mgmt_crypto
= true;
1270 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1271 ath9k_hw_set_delta_slope(ah
, chan
);
1273 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1274 ah
->eep_ops
->set_board_values(ah
, chan
);
1276 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(common
->macaddr
));
1277 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(common
->macaddr
+ 4)
1279 | AR_STA_ID1_RTS_USE_DEF
1281 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
1282 | ah
->sta_id1_defaults
);
1283 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
1285 ath_hw_setbssidmask(common
);
1287 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
1289 ath9k_hw_write_associd(ah
);
1291 REG_WRITE(ah
, AR_ISR
, ~0);
1293 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
1295 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1299 for (i
= 0; i
< AR_NUM_DCU
; i
++)
1300 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
1303 for (i
= 0; i
< ah
->caps
.total_queues
; i
++)
1304 ath9k_hw_resettxqueue(ah
, i
);
1306 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
1307 ath9k_hw_init_qos(ah
);
1309 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1310 ath9k_enable_rfkill(ah
);
1312 ath9k_hw_init_global_settings(ah
);
1314 if (AR_SREV_9287_12_OR_LATER(ah
)) {
1315 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
,
1316 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR
);
1317 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
,
1318 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR
);
1319 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
,
1320 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR
);
1322 REG_WRITE(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR
);
1323 REG_WRITE(ah
, AR_USEC
, AR_USEC_ASYNC_FIFO_DUR
);
1325 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
1326 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
1327 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
1328 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
1330 if (AR_SREV_9287_12_OR_LATER(ah
)) {
1331 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1332 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
1335 REG_WRITE(ah
, AR_STA_ID1
,
1336 REG_READ(ah
, AR_STA_ID1
) | AR_STA_ID1_PRESERVE_SEQNUM
);
1338 ath9k_hw_set_dma(ah
);
1340 REG_WRITE(ah
, AR_OBS
, 8);
1342 if (ah
->config
.rx_intr_mitigation
) {
1343 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
1344 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
1347 ath9k_hw_init_bb(ah
, chan
);
1349 if (!ath9k_hw_init_cal(ah
, chan
))
1352 ath9k_hw_restore_chainmask(ah
);
1353 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
1356 * For big endian systems turn on swapping for descriptors
1358 if (AR_SREV_9100(ah
)) {
1360 mask
= REG_READ(ah
, AR_CFG
);
1361 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
1362 ath_print(common
, ATH_DBG_RESET
,
1363 "CFG Byte Swap Set 0x%x\n", mask
);
1366 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
1367 REG_WRITE(ah
, AR_CFG
, mask
);
1368 ath_print(common
, ATH_DBG_RESET
,
1369 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
1372 /* Configure AR9271 target WLAN */
1373 if (AR_SREV_9271(ah
))
1374 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
1377 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1381 if (ah
->btcoex_hw
.enabled
)
1382 ath9k_hw_btcoex_enable(ah
);
1386 EXPORT_SYMBOL(ath9k_hw_reset
);
1388 /************************/
1389 /* Key Cache Management */
1390 /************************/
1392 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
)
1396 if (entry
>= ah
->caps
.keycache_size
) {
1397 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1398 "keychache entry %u out of range\n", entry
);
1402 keyType
= REG_READ(ah
, AR_KEYTABLE_TYPE(entry
));
1404 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), 0);
1405 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), 0);
1406 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), 0);
1407 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), 0);
1408 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), 0);
1409 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), AR_KEYTABLE_TYPE_CLR
);
1410 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), 0);
1411 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), 0);
1413 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
1414 u16 micentry
= entry
+ 64;
1416 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), 0);
1417 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
1418 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), 0);
1419 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
1425 EXPORT_SYMBOL(ath9k_hw_keyreset
);
1427 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
)
1431 if (entry
>= ah
->caps
.keycache_size
) {
1432 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1433 "keychache entry %u out of range\n", entry
);
1438 macHi
= (mac
[5] << 8) | mac
[4];
1439 macLo
= (mac
[3] << 24) |
1444 macLo
|= (macHi
& 1) << 31;
1449 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), macLo
);
1450 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), macHi
| AR_KEYTABLE_VALID
);
1454 EXPORT_SYMBOL(ath9k_hw_keysetmac
);
1456 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
1457 const struct ath9k_keyval
*k
,
1460 const struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1461 struct ath_common
*common
= ath9k_hw_common(ah
);
1462 u32 key0
, key1
, key2
, key3
, key4
;
1465 if (entry
>= pCap
->keycache_size
) {
1466 ath_print(common
, ATH_DBG_FATAL
,
1467 "keycache entry %u out of range\n", entry
);
1471 switch (k
->kv_type
) {
1472 case ATH9K_CIPHER_AES_OCB
:
1473 keyType
= AR_KEYTABLE_TYPE_AES
;
1475 case ATH9K_CIPHER_AES_CCM
:
1476 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_CIPHER_AESCCM
)) {
1477 ath_print(common
, ATH_DBG_ANY
,
1478 "AES-CCM not supported by mac rev 0x%x\n",
1479 ah
->hw_version
.macRev
);
1482 keyType
= AR_KEYTABLE_TYPE_CCM
;
1484 case ATH9K_CIPHER_TKIP
:
1485 keyType
= AR_KEYTABLE_TYPE_TKIP
;
1486 if (ATH9K_IS_MIC_ENABLED(ah
)
1487 && entry
+ 64 >= pCap
->keycache_size
) {
1488 ath_print(common
, ATH_DBG_ANY
,
1489 "entry %u inappropriate for TKIP\n", entry
);
1493 case ATH9K_CIPHER_WEP
:
1494 if (k
->kv_len
< WLAN_KEY_LEN_WEP40
) {
1495 ath_print(common
, ATH_DBG_ANY
,
1496 "WEP key length %u too small\n", k
->kv_len
);
1499 if (k
->kv_len
<= WLAN_KEY_LEN_WEP40
)
1500 keyType
= AR_KEYTABLE_TYPE_40
;
1501 else if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
1502 keyType
= AR_KEYTABLE_TYPE_104
;
1504 keyType
= AR_KEYTABLE_TYPE_128
;
1506 case ATH9K_CIPHER_CLR
:
1507 keyType
= AR_KEYTABLE_TYPE_CLR
;
1510 ath_print(common
, ATH_DBG_FATAL
,
1511 "cipher %u not supported\n", k
->kv_type
);
1515 key0
= get_unaligned_le32(k
->kv_val
+ 0);
1516 key1
= get_unaligned_le16(k
->kv_val
+ 4);
1517 key2
= get_unaligned_le32(k
->kv_val
+ 6);
1518 key3
= get_unaligned_le16(k
->kv_val
+ 10);
1519 key4
= get_unaligned_le32(k
->kv_val
+ 12);
1520 if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
1524 * Note: Key cache registers access special memory area that requires
1525 * two 32-bit writes to actually update the values in the internal
1526 * memory. Consequently, the exact order and pairs used here must be
1530 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
1531 u16 micentry
= entry
+ 64;
1534 * Write inverted key[47:0] first to avoid Michael MIC errors
1535 * on frames that could be sent or received at the same time.
1536 * The correct key will be written in the end once everything
1539 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), ~key0
);
1540 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), ~key1
);
1542 /* Write key[95:48] */
1543 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
1544 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
1546 /* Write key[127:96] and key type */
1547 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
1548 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
1550 /* Write MAC address for the entry */
1551 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
1553 if (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) {
1555 * TKIP uses two key cache entries:
1556 * Michael MIC TX/RX keys in the same key cache entry
1557 * (idx = main index + 64):
1558 * key0 [31:0] = RX key [31:0]
1559 * key1 [15:0] = TX key [31:16]
1560 * key1 [31:16] = reserved
1561 * key2 [31:0] = RX key [63:32]
1562 * key3 [15:0] = TX key [15:0]
1563 * key3 [31:16] = reserved
1564 * key4 [31:0] = TX key [63:32]
1566 u32 mic0
, mic1
, mic2
, mic3
, mic4
;
1568 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
1569 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
1570 mic1
= get_unaligned_le16(k
->kv_txmic
+ 2) & 0xffff;
1571 mic3
= get_unaligned_le16(k
->kv_txmic
+ 0) & 0xffff;
1572 mic4
= get_unaligned_le32(k
->kv_txmic
+ 4);
1574 /* Write RX[31:0] and TX[31:16] */
1575 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
1576 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), mic1
);
1578 /* Write RX[63:32] and TX[15:0] */
1579 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
1580 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), mic3
);
1582 /* Write TX[63:32] and keyType(reserved) */
1583 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), mic4
);
1584 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
1585 AR_KEYTABLE_TYPE_CLR
);
1589 * TKIP uses four key cache entries (two for group
1591 * Michael MIC TX/RX keys are in different key cache
1592 * entries (idx = main index + 64 for TX and
1593 * main index + 32 + 96 for RX):
1594 * key0 [31:0] = TX/RX MIC key [31:0]
1595 * key1 [31:0] = reserved
1596 * key2 [31:0] = TX/RX MIC key [63:32]
1597 * key3 [31:0] = reserved
1598 * key4 [31:0] = reserved
1600 * Upper layer code will call this function separately
1601 * for TX and RX keys when these registers offsets are
1606 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
1607 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
1609 /* Write MIC key[31:0] */
1610 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
1611 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
1613 /* Write MIC key[63:32] */
1614 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
1615 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
1617 /* Write TX[63:32] and keyType(reserved) */
1618 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), 0);
1619 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
1620 AR_KEYTABLE_TYPE_CLR
);
1623 /* MAC address registers are reserved for the MIC entry */
1624 REG_WRITE(ah
, AR_KEYTABLE_MAC0(micentry
), 0);
1625 REG_WRITE(ah
, AR_KEYTABLE_MAC1(micentry
), 0);
1628 * Write the correct (un-inverted) key[47:0] last to enable
1629 * TKIP now that all other registers are set with correct
1632 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
1633 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
1635 /* Write key[47:0] */
1636 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
1637 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
1639 /* Write key[95:48] */
1640 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
1641 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
1643 /* Write key[127:96] and key type */
1644 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
1645 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
1647 /* Write MAC address for the entry */
1648 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
1653 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry
);
1655 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
)
1657 if (entry
< ah
->caps
.keycache_size
) {
1658 u32 val
= REG_READ(ah
, AR_KEYTABLE_MAC1(entry
));
1659 if (val
& AR_KEYTABLE_VALID
)
1664 EXPORT_SYMBOL(ath9k_hw_keyisvalid
);
1666 /******************************/
1667 /* Power Management (Chipset) */
1668 /******************************/
1671 * Notify Power Mgt is disabled in self-generated frames.
1672 * If requested, force chip to sleep.
1674 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
1676 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1679 * Clear the RTC force wake bit to allow the
1680 * mac to go to sleep.
1682 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
1683 AR_RTC_FORCE_WAKE_EN
);
1684 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1685 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1687 /* Shutdown chip. Active low */
1688 if (!AR_SREV_5416(ah
) && !AR_SREV_9271(ah
))
1689 REG_CLR_BIT(ah
, (AR_RTC_RESET
),
1695 * Notify Power Management is enabled in self-generating
1696 * frames. If request, set power mode of chip to
1697 * auto/normal. Duration in units of 128us (1/8 TU).
1699 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
1701 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1703 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1705 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
1706 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1707 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1708 AR_RTC_FORCE_WAKE_ON_INT
);
1711 * Clear the RTC force wake bit to allow the
1712 * mac to go to sleep.
1714 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
1715 AR_RTC_FORCE_WAKE_EN
);
1720 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
1726 if ((REG_READ(ah
, AR_RTC_STATUS
) &
1727 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
1728 if (ath9k_hw_set_reset_reg(ah
,
1729 ATH9K_RESET_POWER_ON
) != true) {
1732 if (!AR_SREV_9300_20_OR_LATER(ah
))
1733 ath9k_hw_init_pll(ah
, NULL
);
1735 if (AR_SREV_9100(ah
))
1736 REG_SET_BIT(ah
, AR_RTC_RESET
,
1739 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
1740 AR_RTC_FORCE_WAKE_EN
);
1743 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
1744 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
1745 if (val
== AR_RTC_STATUS_ON
)
1748 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
1749 AR_RTC_FORCE_WAKE_EN
);
1752 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1753 "Failed to wakeup in %uus\n",
1754 POWER_UP_TIME
/ 20);
1759 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1764 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
1766 struct ath_common
*common
= ath9k_hw_common(ah
);
1767 int status
= true, setChip
= true;
1768 static const char *modes
[] = {
1775 if (ah
->power_mode
== mode
)
1778 ath_print(common
, ATH_DBG_RESET
, "%s -> %s\n",
1779 modes
[ah
->power_mode
], modes
[mode
]);
1782 case ATH9K_PM_AWAKE
:
1783 status
= ath9k_hw_set_power_awake(ah
, setChip
);
1785 case ATH9K_PM_FULL_SLEEP
:
1786 ath9k_set_power_sleep(ah
, setChip
);
1787 ah
->chip_fullsleep
= true;
1789 case ATH9K_PM_NETWORK_SLEEP
:
1790 ath9k_set_power_network_sleep(ah
, setChip
);
1793 ath_print(common
, ATH_DBG_FATAL
,
1794 "Unknown power mode %u\n", mode
);
1797 ah
->power_mode
= mode
;
1801 EXPORT_SYMBOL(ath9k_hw_setpower
);
1803 /*******************/
1804 /* Beacon Handling */
1805 /*******************/
1807 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
1811 ah
->beacon_interval
= beacon_period
;
1813 switch (ah
->opmode
) {
1814 case NL80211_IFTYPE_STATION
:
1815 case NL80211_IFTYPE_MONITOR
:
1816 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
1817 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
1818 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
1819 flags
|= AR_TBTT_TIMER_EN
;
1821 case NL80211_IFTYPE_ADHOC
:
1822 case NL80211_IFTYPE_MESH_POINT
:
1823 REG_SET_BIT(ah
, AR_TXCFG
,
1824 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
1825 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
,
1826 TU_TO_USEC(next_beacon
+
1827 (ah
->atim_window
? ah
->
1829 flags
|= AR_NDP_TIMER_EN
;
1830 case NL80211_IFTYPE_AP
:
1831 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
1832 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
,
1833 TU_TO_USEC(next_beacon
-
1835 dma_beacon_response_time
));
1836 REG_WRITE(ah
, AR_NEXT_SWBA
,
1837 TU_TO_USEC(next_beacon
-
1839 sw_beacon_response_time
));
1841 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
1844 ath_print(ath9k_hw_common(ah
), ATH_DBG_BEACON
,
1845 "%s: unsupported opmode: %d\n",
1846 __func__
, ah
->opmode
);
1851 REG_WRITE(ah
, AR_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
1852 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
1853 REG_WRITE(ah
, AR_SWBA_PERIOD
, TU_TO_USEC(beacon_period
));
1854 REG_WRITE(ah
, AR_NDP_PERIOD
, TU_TO_USEC(beacon_period
));
1856 beacon_period
&= ~ATH9K_BEACON_ENA
;
1857 if (beacon_period
& ATH9K_BEACON_RESET_TSF
) {
1858 ath9k_hw_reset_tsf(ah
);
1861 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
1863 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
1865 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
1866 const struct ath9k_beacon_state
*bs
)
1868 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
1869 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1870 struct ath_common
*common
= ath9k_hw_common(ah
);
1872 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
1874 REG_WRITE(ah
, AR_BEACON_PERIOD
,
1875 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
1876 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
1877 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
1879 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
1880 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
1882 beaconintval
= bs
->bs_intval
& ATH9K_BEACON_PERIOD
;
1884 if (bs
->bs_sleepduration
> beaconintval
)
1885 beaconintval
= bs
->bs_sleepduration
;
1887 dtimperiod
= bs
->bs_dtimperiod
;
1888 if (bs
->bs_sleepduration
> dtimperiod
)
1889 dtimperiod
= bs
->bs_sleepduration
;
1891 if (beaconintval
== dtimperiod
)
1892 nextTbtt
= bs
->bs_nextdtim
;
1894 nextTbtt
= bs
->bs_nexttbtt
;
1896 ath_print(common
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
1897 ath_print(common
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
1898 ath_print(common
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
1899 ath_print(common
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
1901 REG_WRITE(ah
, AR_NEXT_DTIM
,
1902 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
1903 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
1905 REG_WRITE(ah
, AR_SLEEP1
,
1906 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
1907 | AR_SLEEP1_ASSUME_DTIM
);
1909 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
1910 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
1912 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
1914 REG_WRITE(ah
, AR_SLEEP2
,
1915 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
1917 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
1918 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
1920 REG_SET_BIT(ah
, AR_TIMER_MODE
,
1921 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
1924 /* TSF Out of Range Threshold */
1925 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
1927 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
1929 /*******************/
1930 /* HW Capabilities */
1931 /*******************/
1933 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
1935 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1936 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1937 struct ath_common
*common
= ath9k_hw_common(ah
);
1938 struct ath_btcoex_hw
*btcoex_hw
= &ah
->btcoex_hw
;
1940 u16 capField
= 0, eeval
;
1942 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
1943 regulatory
->current_rd
= eeval
;
1945 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_1
);
1946 if (AR_SREV_9285_10_OR_LATER(ah
))
1947 eeval
|= AR9285_RDEXT_DEFAULT
;
1948 regulatory
->current_rd_ext
= eeval
;
1950 capField
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_CAP
);
1952 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
1953 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
1954 if (regulatory
->current_rd
== 0x64 ||
1955 regulatory
->current_rd
== 0x65)
1956 regulatory
->current_rd
+= 5;
1957 else if (regulatory
->current_rd
== 0x41)
1958 regulatory
->current_rd
= 0x43;
1959 ath_print(common
, ATH_DBG_REGULATORY
,
1960 "regdomain mapped to 0x%x\n", regulatory
->current_rd
);
1963 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
1964 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
1965 ath_print(common
, ATH_DBG_FATAL
,
1966 "no band has been marked as supported in EEPROM.\n");
1970 bitmap_zero(pCap
->wireless_modes
, ATH9K_MODE_MAX
);
1972 if (eeval
& AR5416_OPFLAGS_11A
) {
1973 set_bit(ATH9K_MODE_11A
, pCap
->wireless_modes
);
1974 if (ah
->config
.ht_enable
) {
1975 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT20
))
1976 set_bit(ATH9K_MODE_11NA_HT20
,
1977 pCap
->wireless_modes
);
1978 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT40
)) {
1979 set_bit(ATH9K_MODE_11NA_HT40PLUS
,
1980 pCap
->wireless_modes
);
1981 set_bit(ATH9K_MODE_11NA_HT40MINUS
,
1982 pCap
->wireless_modes
);
1987 if (eeval
& AR5416_OPFLAGS_11G
) {
1988 set_bit(ATH9K_MODE_11G
, pCap
->wireless_modes
);
1989 if (ah
->config
.ht_enable
) {
1990 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT20
))
1991 set_bit(ATH9K_MODE_11NG_HT20
,
1992 pCap
->wireless_modes
);
1993 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT40
)) {
1994 set_bit(ATH9K_MODE_11NG_HT40PLUS
,
1995 pCap
->wireless_modes
);
1996 set_bit(ATH9K_MODE_11NG_HT40MINUS
,
1997 pCap
->wireless_modes
);
2002 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
2004 * For AR9271 we will temporarilly uses the rx chainmax as read from
2007 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
2008 !(eeval
& AR5416_OPFLAGS_11A
) &&
2009 !(AR_SREV_9271(ah
)))
2010 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2011 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
2013 /* Use rx_chainmask from EEPROM. */
2014 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
2016 if (!(AR_SREV_9280(ah
) && (ah
->hw_version
.macRev
== 0)))
2017 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
2019 pCap
->low_2ghz_chan
= 2312;
2020 pCap
->high_2ghz_chan
= 2732;
2022 pCap
->low_5ghz_chan
= 4920;
2023 pCap
->high_5ghz_chan
= 6100;
2025 pCap
->hw_caps
&= ~ATH9K_HW_CAP_CIPHER_CKIP
;
2026 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_TKIP
;
2027 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_AESCCM
;
2029 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MIC_CKIP
;
2030 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_TKIP
;
2031 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_AESCCM
;
2033 if (ah
->config
.ht_enable
)
2034 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
2036 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
2038 pCap
->hw_caps
|= ATH9K_HW_CAP_GTT
;
2039 pCap
->hw_caps
|= ATH9K_HW_CAP_VEOL
;
2040 pCap
->hw_caps
|= ATH9K_HW_CAP_BSSIDMASK
;
2041 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MCAST_KEYSEARCH
;
2043 if (capField
& AR_EEPROM_EEPCAP_MAXQCU
)
2044 pCap
->total_queues
=
2045 MS(capField
, AR_EEPROM_EEPCAP_MAXQCU
);
2047 pCap
->total_queues
= ATH9K_NUM_TX_QUEUES
;
2049 if (capField
& AR_EEPROM_EEPCAP_KC_ENTRIES
)
2050 pCap
->keycache_size
=
2051 1 << MS(capField
, AR_EEPROM_EEPCAP_KC_ENTRIES
);
2053 pCap
->keycache_size
= AR_KEYTABLE_SIZE
;
2055 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCC
;
2057 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
2058 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
>> 1;
2060 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
;
2062 if (AR_SREV_9271(ah
))
2063 pCap
->num_gpio_pins
= AR9271_NUM_GPIO
;
2064 else if (AR_SREV_9285_10_OR_LATER(ah
))
2065 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
2066 else if (AR_SREV_9280_10_OR_LATER(ah
))
2067 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
2069 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
2071 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
2072 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
2073 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
2075 pCap
->rts_aggr_limit
= (8 * 1024);
2078 pCap
->hw_caps
|= ATH9K_HW_CAP_ENHANCEDPM
;
2080 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2081 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
2082 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
2084 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
2085 ah
->rfkill_polarity
=
2086 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
2088 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
2091 if (AR_SREV_9271(ah
))
2092 pCap
->hw_caps
|= ATH9K_HW_CAP_AUTOSLEEP
;
2094 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
2096 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
2097 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
2099 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
2101 if (regulatory
->current_rd_ext
& (1 << REG_EXT_JAPAN_MIDBAND
)) {
2103 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
2104 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
|
2105 AR_EEPROM_EEREGCAP_EN_KK_U2
|
2106 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
;
2109 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
2110 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
;
2113 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2114 if (regulatory
->current_rd_ext
& (1 << REG_EXT_FCC_MIDBAND
) &&
2116 pCap
->reg_cap
|= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
;
2118 pCap
->num_antcfg_5ghz
=
2119 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_5GHZ
);
2120 pCap
->num_antcfg_2ghz
=
2121 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_2GHZ
);
2123 if (AR_SREV_9280_10_OR_LATER(ah
) &&
2124 ath9k_hw_btcoex_supported(ah
)) {
2125 btcoex_hw
->btactive_gpio
= ATH_BTACTIVE_GPIO
;
2126 btcoex_hw
->wlanactive_gpio
= ATH_WLANACTIVE_GPIO
;
2128 if (AR_SREV_9285(ah
)) {
2129 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_3WIRE
;
2130 btcoex_hw
->btpriority_gpio
= ATH_BTPRIORITY_GPIO
;
2132 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_2WIRE
;
2135 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_NONE
;
2138 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2139 pCap
->hw_caps
|= ATH9K_HW_CAP_EDMA
;
2140 pCap
->rx_hp_qdepth
= ATH9K_HW_RX_HP_QDEPTH
;
2141 pCap
->rx_lp_qdepth
= ATH9K_HW_RX_LP_QDEPTH
;
2142 pCap
->rx_status_len
= sizeof(struct ar9003_rxs
);
2143 pCap
->tx_desc_len
= sizeof(struct ar9003_txc
);
2145 pCap
->tx_desc_len
= sizeof(struct ath_desc
);
2148 if (AR_SREV_9300_20_OR_LATER(ah
))
2149 pCap
->hw_caps
|= ATH9K_HW_CAP_RAC_SUPPORTED
;
2154 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
2155 u32 capability
, u32
*result
)
2157 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2159 case ATH9K_CAP_CIPHER
:
2160 switch (capability
) {
2161 case ATH9K_CIPHER_AES_CCM
:
2162 case ATH9K_CIPHER_AES_OCB
:
2163 case ATH9K_CIPHER_TKIP
:
2164 case ATH9K_CIPHER_WEP
:
2165 case ATH9K_CIPHER_MIC
:
2166 case ATH9K_CIPHER_CLR
:
2171 case ATH9K_CAP_TKIP_MIC
:
2172 switch (capability
) {
2176 return (ah
->sta_id1_defaults
&
2177 AR_STA_ID1_CRPT_MIC_ENABLE
) ? true :
2180 case ATH9K_CAP_TKIP_SPLIT
:
2181 return (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) ?
2183 case ATH9K_CAP_MCAST_KEYSRCH
:
2184 switch (capability
) {
2188 if (REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_ADHOC
) {
2191 return (ah
->sta_id1_defaults
&
2192 AR_STA_ID1_MCAST_KSRCH
) ? true :
2197 case ATH9K_CAP_TXPOW
:
2198 switch (capability
) {
2202 *result
= regulatory
->power_limit
;
2205 *result
= regulatory
->max_power_level
;
2208 *result
= regulatory
->tp_scale
;
2213 return (AR_SREV_9280_20_OR_LATER(ah
) &&
2214 (ah
->eep_ops
->get_eeprom(ah
, EEP_RC_CHAIN_MASK
) == 1))
2220 EXPORT_SYMBOL(ath9k_hw_getcapability
);
2222 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
2223 u32 capability
, u32 setting
, int *status
)
2226 case ATH9K_CAP_TKIP_MIC
:
2228 ah
->sta_id1_defaults
|=
2229 AR_STA_ID1_CRPT_MIC_ENABLE
;
2231 ah
->sta_id1_defaults
&=
2232 ~AR_STA_ID1_CRPT_MIC_ENABLE
;
2234 case ATH9K_CAP_MCAST_KEYSRCH
:
2236 ah
->sta_id1_defaults
|= AR_STA_ID1_MCAST_KSRCH
;
2238 ah
->sta_id1_defaults
&= ~AR_STA_ID1_MCAST_KSRCH
;
2244 EXPORT_SYMBOL(ath9k_hw_setcapability
);
2246 /****************************/
2247 /* GPIO / RFKILL / Antennae */
2248 /****************************/
2250 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
2254 u32 gpio_shift
, tmp
;
2257 addr
= AR_GPIO_OUTPUT_MUX3
;
2259 addr
= AR_GPIO_OUTPUT_MUX2
;
2261 addr
= AR_GPIO_OUTPUT_MUX1
;
2263 gpio_shift
= (gpio
% 6) * 5;
2265 if (AR_SREV_9280_20_OR_LATER(ah
)
2266 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
2267 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
2268 (0x1f << gpio_shift
));
2270 tmp
= REG_READ(ah
, addr
);
2271 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
2272 tmp
&= ~(0x1f << gpio_shift
);
2273 tmp
|= (type
<< gpio_shift
);
2274 REG_WRITE(ah
, addr
, tmp
);
2278 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
2282 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
2284 gpio_shift
= gpio
<< 1;
2288 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
2289 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2291 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
2293 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
2295 #define MS_REG_READ(x, y) \
2296 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2298 if (gpio
>= ah
->caps
.num_gpio_pins
)
2301 if (AR_SREV_9300_20_OR_LATER(ah
))
2302 return MS_REG_READ(AR9300
, gpio
) != 0;
2303 else if (AR_SREV_9271(ah
))
2304 return MS_REG_READ(AR9271
, gpio
) != 0;
2305 else if (AR_SREV_9287_10_OR_LATER(ah
))
2306 return MS_REG_READ(AR9287
, gpio
) != 0;
2307 else if (AR_SREV_9285_10_OR_LATER(ah
))
2308 return MS_REG_READ(AR9285
, gpio
) != 0;
2309 else if (AR_SREV_9280_10_OR_LATER(ah
))
2310 return MS_REG_READ(AR928X
, gpio
) != 0;
2312 return MS_REG_READ(AR
, gpio
) != 0;
2314 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
2316 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
2321 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
2323 gpio_shift
= 2 * gpio
;
2327 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
2328 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2330 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
2332 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
2334 if (AR_SREV_9271(ah
))
2337 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
2340 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
2342 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
2344 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
2346 EXPORT_SYMBOL(ath9k_hw_getdefantenna
);
2348 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
2350 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
2352 EXPORT_SYMBOL(ath9k_hw_setantenna
);
2354 /*********************/
2355 /* General Operation */
2356 /*********************/
2358 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
2360 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
2361 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
2363 if (phybits
& AR_PHY_ERR_RADAR
)
2364 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
2365 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
2366 bits
|= ATH9K_RX_FILTER_PHYERR
;
2370 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
2372 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
2376 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
2379 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
2380 phybits
|= AR_PHY_ERR_RADAR
;
2381 if (bits
& ATH9K_RX_FILTER_PHYERR
)
2382 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
2383 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
2386 REG_WRITE(ah
, AR_RXCFG
,
2387 REG_READ(ah
, AR_RXCFG
) | AR_RXCFG_ZLFDMA
);
2389 REG_WRITE(ah
, AR_RXCFG
,
2390 REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_ZLFDMA
);
2392 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
2394 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
2396 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
2399 ath9k_hw_init_pll(ah
, NULL
);
2402 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
2404 bool ath9k_hw_disable(struct ath_hw
*ah
)
2406 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
2409 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
2412 ath9k_hw_init_pll(ah
, NULL
);
2415 EXPORT_SYMBOL(ath9k_hw_disable
);
2417 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
)
2419 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2420 struct ath9k_channel
*chan
= ah
->curchan
;
2421 struct ieee80211_channel
*channel
= chan
->chan
;
2423 regulatory
->power_limit
= min(limit
, (u32
) MAX_RATE_POWER
);
2425 ah
->eep_ops
->set_txpower(ah
, chan
,
2426 ath9k_regd_get_ctl(regulatory
, chan
),
2427 channel
->max_antenna_gain
* 2,
2428 channel
->max_power
* 2,
2429 min((u32
) MAX_RATE_POWER
,
2430 (u32
) regulatory
->power_limit
));
2432 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
2434 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
)
2436 memcpy(ath9k_hw_common(ah
)->macaddr
, mac
, ETH_ALEN
);
2438 EXPORT_SYMBOL(ath9k_hw_setmac
);
2440 void ath9k_hw_setopmode(struct ath_hw
*ah
)
2442 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2444 EXPORT_SYMBOL(ath9k_hw_setopmode
);
2446 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
2448 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
2449 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
2451 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
2453 void ath9k_hw_write_associd(struct ath_hw
*ah
)
2455 struct ath_common
*common
= ath9k_hw_common(ah
);
2457 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
2458 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
2459 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
2461 EXPORT_SYMBOL(ath9k_hw_write_associd
);
2463 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
2467 tsf
= REG_READ(ah
, AR_TSF_U32
);
2468 tsf
= (tsf
<< 32) | REG_READ(ah
, AR_TSF_L32
);
2472 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
2474 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
2476 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
2477 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
2479 EXPORT_SYMBOL(ath9k_hw_settsf64
);
2481 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
2483 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
2484 AH_TSF_WRITE_TIMEOUT
))
2485 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
2486 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2488 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
2490 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
2492 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
2495 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
2497 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
2499 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
2502 * Extend 15-bit time stamp from rx descriptor to
2503 * a full 64-bit TSF using the current h/w TSF.
2505 u64
ath9k_hw_extend_tsf(struct ath_hw
*ah
, u32 rstamp
)
2509 tsf
= ath9k_hw_gettsf64(ah
);
2510 if ((tsf
& 0x7fff) < rstamp
)
2512 return (tsf
& ~0x7fff) | rstamp
;
2514 EXPORT_SYMBOL(ath9k_hw_extend_tsf
);
2516 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
)
2518 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
2521 if (conf_is_ht40(conf
) && !ah
->config
.cwm_ignore_extcca
)
2522 macmode
= AR_2040_JOINED_RX_CLEAR
;
2526 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
2529 /* HW Generic timers configuration */
2531 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
2533 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2534 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2535 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2536 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2537 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2538 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2539 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2540 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2541 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
2542 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
2543 AR_NDP2_TIMER_MODE
, 0x0002},
2544 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
2545 AR_NDP2_TIMER_MODE
, 0x0004},
2546 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
2547 AR_NDP2_TIMER_MODE
, 0x0008},
2548 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
2549 AR_NDP2_TIMER_MODE
, 0x0010},
2550 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
2551 AR_NDP2_TIMER_MODE
, 0x0020},
2552 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
2553 AR_NDP2_TIMER_MODE
, 0x0040},
2554 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
2555 AR_NDP2_TIMER_MODE
, 0x0080}
2558 /* HW generic timer primitives */
2560 /* compute and clear index of rightmost 1 */
2561 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
2571 return timer_table
->gen_timer_index
[b
];
2574 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
2576 return REG_READ(ah
, AR_TSF_L32
);
2578 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
2580 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
2581 void (*trigger
)(void *),
2582 void (*overflow
)(void *),
2586 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2587 struct ath_gen_timer
*timer
;
2589 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
2591 if (timer
== NULL
) {
2592 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2593 "Failed to allocate memory"
2594 "for hw timer[%d]\n", timer_index
);
2598 /* allocate a hardware generic timer slot */
2599 timer_table
->timers
[timer_index
] = timer
;
2600 timer
->index
= timer_index
;
2601 timer
->trigger
= trigger
;
2602 timer
->overflow
= overflow
;
2607 EXPORT_SYMBOL(ath_gen_timer_alloc
);
2609 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
2610 struct ath_gen_timer
*timer
,
2614 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2617 BUG_ON(!timer_period
);
2619 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
2621 tsf
= ath9k_hw_gettsf32(ah
);
2623 ath_print(ath9k_hw_common(ah
), ATH_DBG_HWTIMER
,
2624 "curent tsf %x period %x"
2625 "timer_next %x\n", tsf
, timer_period
, timer_next
);
2628 * Pull timer_next forward if the current TSF already passed it
2629 * because of software latency
2631 if (timer_next
< tsf
)
2632 timer_next
= tsf
+ timer_period
;
2635 * Program generic timer registers
2637 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
2639 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
2641 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2642 gen_tmr_configuration
[timer
->index
].mode_mask
);
2644 /* Enable both trigger and thresh interrupt masks */
2645 REG_SET_BIT(ah
, AR_IMR_S5
,
2646 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
2647 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
2649 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
2651 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
2653 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2655 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
2656 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
2660 /* Clear generic timer enable bits. */
2661 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2662 gen_tmr_configuration
[timer
->index
].mode_mask
);
2664 /* Disable both trigger and thresh interrupt masks */
2665 REG_CLR_BIT(ah
, AR_IMR_S5
,
2666 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
2667 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
2669 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
2671 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
2673 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
2675 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2677 /* free the hardware generic timer slot */
2678 timer_table
->timers
[timer
->index
] = NULL
;
2681 EXPORT_SYMBOL(ath_gen_timer_free
);
2684 * Generic Timer Interrupts handling
2686 void ath_gen_timer_isr(struct ath_hw
*ah
)
2688 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2689 struct ath_gen_timer
*timer
;
2690 struct ath_common
*common
= ath9k_hw_common(ah
);
2691 u32 trigger_mask
, thresh_mask
, index
;
2693 /* get hardware generic timer interrupt status */
2694 trigger_mask
= ah
->intr_gen_timer_trigger
;
2695 thresh_mask
= ah
->intr_gen_timer_thresh
;
2696 trigger_mask
&= timer_table
->timer_mask
.val
;
2697 thresh_mask
&= timer_table
->timer_mask
.val
;
2699 trigger_mask
&= ~thresh_mask
;
2701 while (thresh_mask
) {
2702 index
= rightmost_index(timer_table
, &thresh_mask
);
2703 timer
= timer_table
->timers
[index
];
2705 ath_print(common
, ATH_DBG_HWTIMER
,
2706 "TSF overflow for Gen timer %d\n", index
);
2707 timer
->overflow(timer
->arg
);
2710 while (trigger_mask
) {
2711 index
= rightmost_index(timer_table
, &trigger_mask
);
2712 timer
= timer_table
->timers
[index
];
2714 ath_print(common
, ATH_DBG_HWTIMER
,
2715 "Gen timer[%d] trigger\n", index
);
2716 timer
->trigger(timer
->arg
);
2719 EXPORT_SYMBOL(ath_gen_timer_isr
);
2725 void ath9k_hw_htc_resetinit(struct ath_hw
*ah
)
2727 ah
->htc_reset_init
= true;
2729 EXPORT_SYMBOL(ath9k_hw_htc_resetinit
);
2734 } ath_mac_bb_names
[] = {
2735 /* Devices with external radios */
2736 { AR_SREV_VERSION_5416_PCI
, "5416" },
2737 { AR_SREV_VERSION_5416_PCIE
, "5418" },
2738 { AR_SREV_VERSION_9100
, "9100" },
2739 { AR_SREV_VERSION_9160
, "9160" },
2740 /* Single-chip solutions */
2741 { AR_SREV_VERSION_9280
, "9280" },
2742 { AR_SREV_VERSION_9285
, "9285" },
2743 { AR_SREV_VERSION_9287
, "9287" },
2744 { AR_SREV_VERSION_9271
, "9271" },
2747 /* For devices with external radios */
2751 } ath_rf_names
[] = {
2753 { AR_RAD5133_SREV_MAJOR
, "5133" },
2754 { AR_RAD5122_SREV_MAJOR
, "5122" },
2755 { AR_RAD2133_SREV_MAJOR
, "2133" },
2756 { AR_RAD2122_SREV_MAJOR
, "2122" }
2760 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2762 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
2766 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
2767 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
2768 return ath_mac_bb_names
[i
].name
;
2776 * Return the RF name. "????" is returned if the RF is unknown.
2777 * Used for devices with external radios.
2779 static const char *ath9k_hw_rf_name(u16 rf_version
)
2783 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
2784 if (ath_rf_names
[i
].version
== rf_version
) {
2785 return ath_rf_names
[i
].name
;
2792 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
2796 /* chipsets >= AR9280 are single-chip */
2797 if (AR_SREV_9280_10_OR_LATER(ah
)) {
2798 used
= snprintf(hw_name
, len
,
2799 "Atheros AR%s Rev:%x",
2800 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
2801 ah
->hw_version
.macRev
);
2804 used
= snprintf(hw_name
, len
,
2805 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2806 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
2807 ah
->hw_version
.macRev
,
2808 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
&
2809 AR_RADIO_SREV_MAJOR
)),
2810 ah
->hw_version
.phyRev
);
2813 hw_name
[used
] = '\0';
2815 EXPORT_SYMBOL(ath9k_hw_name
);