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ath9k_hw: Fill get_isr() for AR9003
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "hw-ops.h"
22 #include "rc.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29
30 MODULE_AUTHOR("Atheros Communications");
31 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33 MODULE_LICENSE("Dual BSD/GPL");
34
35 static int __init ath9k_init(void)
36 {
37 return 0;
38 }
39 module_init(ath9k_init);
40
41 static void __exit ath9k_exit(void)
42 {
43 return;
44 }
45 module_exit(ath9k_exit);
46
47 /* Private hardware callbacks */
48
49 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
50 {
51 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 }
53
54 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
55 {
56 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 }
58
59 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
60 {
61 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
62
63 return priv_ops->macversion_supported(ah->hw_version.macVersion);
64 }
65
66 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
67 struct ath9k_channel *chan)
68 {
69 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
70 }
71
72 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
73 {
74 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87
88 if (!ah->curchan) /* should really check for CCK instead */
89 return usecs *ATH9K_CLOCK_RATE_CCK;
90 if (conf->channel->band == IEEE80211_BAND_2GHZ)
91 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
92 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
93 }
94
95 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
96 {
97 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
98
99 if (conf_is_ht40(conf))
100 return ath9k_hw_mac_clks(ah, usecs) * 2;
101 else
102 return ath9k_hw_mac_clks(ah, usecs);
103 }
104
105 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
106 {
107 int i;
108
109 BUG_ON(timeout < AH_TIME_QUANTUM);
110
111 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
112 if ((REG_READ(ah, reg) & mask) == val)
113 return true;
114
115 udelay(AH_TIME_QUANTUM);
116 }
117
118 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
119 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
120 timeout, reg, REG_READ(ah, reg), mask, val);
121
122 return false;
123 }
124 EXPORT_SYMBOL(ath9k_hw_wait);
125
126 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
127 {
128 u32 retval;
129 int i;
130
131 for (i = 0, retval = 0; i < n; i++) {
132 retval = (retval << 1) | (val & 1);
133 val >>= 1;
134 }
135 return retval;
136 }
137
138 bool ath9k_get_channel_edges(struct ath_hw *ah,
139 u16 flags, u16 *low,
140 u16 *high)
141 {
142 struct ath9k_hw_capabilities *pCap = &ah->caps;
143
144 if (flags & CHANNEL_5GHZ) {
145 *low = pCap->low_5ghz_chan;
146 *high = pCap->high_5ghz_chan;
147 return true;
148 }
149 if ((flags & CHANNEL_2GHZ)) {
150 *low = pCap->low_2ghz_chan;
151 *high = pCap->high_2ghz_chan;
152 return true;
153 }
154 return false;
155 }
156
157 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
158 u8 phy, int kbps,
159 u32 frameLen, u16 rateix,
160 bool shortPreamble)
161 {
162 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
163
164 if (kbps == 0)
165 return 0;
166
167 switch (phy) {
168 case WLAN_RC_PHY_CCK:
169 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
170 if (shortPreamble)
171 phyTime >>= 1;
172 numBits = frameLen << 3;
173 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
174 break;
175 case WLAN_RC_PHY_OFDM:
176 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
180 txTime = OFDM_SIFS_TIME_QUARTER
181 + OFDM_PREAMBLE_TIME_QUARTER
182 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
183 } else if (ah->curchan &&
184 IS_CHAN_HALF_RATE(ah->curchan)) {
185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME_HALF +
189 OFDM_PREAMBLE_TIME_HALF
190 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
191 } else {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
196 + (numSymbols * OFDM_SYMBOL_TIME);
197 }
198 break;
199 default:
200 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
201 "Unknown phy %u (rate ix %u)\n", phy, rateix);
202 txTime = 0;
203 break;
204 }
205
206 return txTime;
207 }
208 EXPORT_SYMBOL(ath9k_hw_computetxtime);
209
210 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
211 struct ath9k_channel *chan,
212 struct chan_centers *centers)
213 {
214 int8_t extoff;
215
216 if (!IS_CHAN_HT40(chan)) {
217 centers->ctl_center = centers->ext_center =
218 centers->synth_center = chan->channel;
219 return;
220 }
221
222 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
223 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
224 centers->synth_center =
225 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
226 extoff = 1;
227 } else {
228 centers->synth_center =
229 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
230 extoff = -1;
231 }
232
233 centers->ctl_center =
234 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
235 /* 25 MHz spacing is supported by hw but not on upper layers */
236 centers->ext_center =
237 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
238 }
239
240 /******************/
241 /* Chip Revisions */
242 /******************/
243
244 static void ath9k_hw_read_revisions(struct ath_hw *ah)
245 {
246 u32 val;
247
248 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
249
250 if (val == 0xFF) {
251 val = REG_READ(ah, AR_SREV);
252 ah->hw_version.macVersion =
253 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
254 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
255 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
256 } else {
257 if (!AR_SREV_9100(ah))
258 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
259
260 ah->hw_version.macRev = val & AR_SREV_REVISION;
261
262 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
263 ah->is_pciexpress = true;
264 }
265 }
266
267 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
268 {
269 u32 val;
270 int i;
271
272 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
273
274 for (i = 0; i < 8; i++)
275 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
276 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
277 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
278
279 return ath9k_hw_reverse_bits(val, 8);
280 }
281
282 /************************************/
283 /* HW Attach, Detach, Init Routines */
284 /************************************/
285
286 static void ath9k_hw_disablepcie(struct ath_hw *ah)
287 {
288 if (AR_SREV_9100(ah))
289 return;
290
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
300
301 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
302 }
303
304 /* This should work for all families including legacy */
305 static bool ath9k_hw_chip_test(struct ath_hw *ah)
306 {
307 struct ath_common *common = ath9k_hw_common(ah);
308 u32 regAddr[2] = { AR_STA_ID0 };
309 u32 regHold[2];
310 u32 patternData[4] = { 0x55555555,
311 0xaaaaaaaa,
312 0x66666666,
313 0x99999999 };
314 int i, j, loop_max;
315
316 if (!AR_SREV_9300_20_OR_LATER(ah)) {
317 loop_max = 2;
318 regAddr[1] = AR_PHY_BASE + (8 << 2);
319 } else
320 loop_max = 1;
321
322 for (i = 0; i < loop_max; i++) {
323 u32 addr = regAddr[i];
324 u32 wrData, rdData;
325
326 regHold[i] = REG_READ(ah, addr);
327 for (j = 0; j < 0x100; j++) {
328 wrData = (j << 16) | j;
329 REG_WRITE(ah, addr, wrData);
330 rdData = REG_READ(ah, addr);
331 if (rdData != wrData) {
332 ath_print(common, ATH_DBG_FATAL,
333 "address test failed "
334 "addr: 0x%08x - wr:0x%08x != "
335 "rd:0x%08x\n",
336 addr, wrData, rdData);
337 return false;
338 }
339 }
340 for (j = 0; j < 4; j++) {
341 wrData = patternData[j];
342 REG_WRITE(ah, addr, wrData);
343 rdData = REG_READ(ah, addr);
344 if (wrData != rdData) {
345 ath_print(common, ATH_DBG_FATAL,
346 "address test failed "
347 "addr: 0x%08x - wr:0x%08x != "
348 "rd:0x%08x\n",
349 addr, wrData, rdData);
350 return false;
351 }
352 }
353 REG_WRITE(ah, regAddr[i], regHold[i]);
354 }
355 udelay(100);
356
357 return true;
358 }
359
360 static void ath9k_hw_init_config(struct ath_hw *ah)
361 {
362 int i;
363
364 ah->config.dma_beacon_response_time = 2;
365 ah->config.sw_beacon_response_time = 10;
366 ah->config.additional_swba_backoff = 0;
367 ah->config.ack_6mb = 0x0;
368 ah->config.cwm_ignore_extcca = 0;
369 ah->config.pcie_powersave_enable = 0;
370 ah->config.pcie_clock_req = 0;
371 ah->config.pcie_waen = 0;
372 ah->config.analog_shiftreg = 1;
373 ah->config.ofdm_trig_low = 200;
374 ah->config.ofdm_trig_high = 500;
375 ah->config.cck_trig_high = 200;
376 ah->config.cck_trig_low = 100;
377
378 /*
379 * For now ANI is disabled for AR9003, it is still
380 * being tested.
381 */
382 if (!AR_SREV_9300_20_OR_LATER(ah))
383 ah->config.enable_ani = 1;
384
385 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
386 ah->config.spurchans[i][0] = AR_NO_SPUR;
387 ah->config.spurchans[i][1] = AR_NO_SPUR;
388 }
389
390 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
391 ah->config.ht_enable = 1;
392 else
393 ah->config.ht_enable = 0;
394
395 ah->config.rx_intr_mitigation = true;
396
397 /*
398 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
399 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
400 * This means we use it for all AR5416 devices, and the few
401 * minor PCI AR9280 devices out there.
402 *
403 * Serialization is required because these devices do not handle
404 * well the case of two concurrent reads/writes due to the latency
405 * involved. During one read/write another read/write can be issued
406 * on another CPU while the previous read/write may still be working
407 * on our hardware, if we hit this case the hardware poops in a loop.
408 * We prevent this by serializing reads and writes.
409 *
410 * This issue is not present on PCI-Express devices or pre-AR5416
411 * devices (legacy, 802.11abg).
412 */
413 if (num_possible_cpus() > 1)
414 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
415 }
416
417 static void ath9k_hw_init_defaults(struct ath_hw *ah)
418 {
419 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
420
421 regulatory->country_code = CTRY_DEFAULT;
422 regulatory->power_limit = MAX_RATE_POWER;
423 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
424
425 ah->hw_version.magic = AR5416_MAGIC;
426 ah->hw_version.subvendorid = 0;
427
428 ah->ah_flags = 0;
429 if (!AR_SREV_9100(ah))
430 ah->ah_flags = AH_USE_EEPROM;
431
432 ah->atim_window = 0;
433 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
434 ah->beacon_interval = 100;
435 ah->enable_32kHz_clock = DONT_USE_32KHZ;
436 ah->slottime = (u32) -1;
437 ah->globaltxtimeout = (u32) -1;
438 ah->power_mode = ATH9K_PM_UNDEFINED;
439 }
440
441 static int ath9k_hw_rf_claim(struct ath_hw *ah)
442 {
443 u32 val;
444
445 REG_WRITE(ah, AR_PHY(0), 0x00000007);
446
447 val = ath9k_hw_get_radiorev(ah);
448 switch (val & AR_RADIO_SREV_MAJOR) {
449 case 0:
450 val = AR_RAD5133_SREV_MAJOR;
451 break;
452 case AR_RAD5133_SREV_MAJOR:
453 case AR_RAD5122_SREV_MAJOR:
454 case AR_RAD2133_SREV_MAJOR:
455 case AR_RAD2122_SREV_MAJOR:
456 break;
457 default:
458 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
459 "Radio Chip Rev 0x%02X not supported\n",
460 val & AR_RADIO_SREV_MAJOR);
461 return -EOPNOTSUPP;
462 }
463
464 ah->hw_version.analog5GhzRev = val;
465
466 return 0;
467 }
468
469 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
470 {
471 struct ath_common *common = ath9k_hw_common(ah);
472 u32 sum;
473 int i;
474 u16 eeval;
475 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
476
477 sum = 0;
478 for (i = 0; i < 3; i++) {
479 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
480 sum += eeval;
481 common->macaddr[2 * i] = eeval >> 8;
482 common->macaddr[2 * i + 1] = eeval & 0xff;
483 }
484 if (sum == 0 || sum == 0xffff * 3)
485 return -EADDRNOTAVAIL;
486
487 return 0;
488 }
489
490 static int ath9k_hw_post_init(struct ath_hw *ah)
491 {
492 int ecode;
493
494 if (!AR_SREV_9271(ah)) {
495 if (!ath9k_hw_chip_test(ah))
496 return -ENODEV;
497 }
498
499 ecode = ath9k_hw_rf_claim(ah);
500 if (ecode != 0)
501 return ecode;
502
503 ecode = ath9k_hw_eeprom_init(ah);
504 if (ecode != 0)
505 return ecode;
506
507 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
508 "Eeprom VER: %d, REV: %d\n",
509 ah->eep_ops->get_eeprom_ver(ah),
510 ah->eep_ops->get_eeprom_rev(ah));
511
512 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
513 if (ecode) {
514 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
515 "Failed allocating banks for "
516 "external radio\n");
517 return ecode;
518 }
519
520 if (!AR_SREV_9100(ah)) {
521 ath9k_hw_ani_setup(ah);
522 ath9k_hw_ani_init(ah);
523 }
524
525 return 0;
526 }
527
528 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
529 {
530 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
531 struct ath_common *common = ath9k_hw_common(ah);
532
533 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
534 !AR_SREV_9285(ah) && !AR_SREV_9271(ah) &&
535 ((pBase->version & 0xff) > 0x0a) &&
536 (pBase->pwdclkind == 0);
537
538 if (ah->need_an_top2_fixup)
539 ath_print(common, ATH_DBG_EEPROM,
540 "needs fixup for AR_AN_TOP2 register\n");
541 }
542
543 static void ath9k_hw_attach_ops(struct ath_hw *ah)
544 {
545 if (AR_SREV_9300_20_OR_LATER(ah))
546 ar9003_hw_attach_ops(ah);
547 else
548 ar9002_hw_attach_ops(ah);
549 }
550
551 /* Called for all hardware families */
552 static int __ath9k_hw_init(struct ath_hw *ah)
553 {
554 struct ath_common *common = ath9k_hw_common(ah);
555 int r = 0;
556
557 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
558 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
559
560 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
561 ath_print(common, ATH_DBG_FATAL,
562 "Couldn't reset chip\n");
563 return -EIO;
564 }
565
566 ath9k_hw_init_defaults(ah);
567 ath9k_hw_init_config(ah);
568
569 ath9k_hw_attach_ops(ah);
570
571 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
572 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
573 return -EIO;
574 }
575
576 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
577 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
578 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
579 ah->config.serialize_regmode =
580 SER_REG_MODE_ON;
581 } else {
582 ah->config.serialize_regmode =
583 SER_REG_MODE_OFF;
584 }
585 }
586
587 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
588 ah->config.serialize_regmode);
589
590 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
591 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
592 else
593 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
594
595 if (!ath9k_hw_macversion_supported(ah)) {
596 ath_print(common, ATH_DBG_FATAL,
597 "Mac Chip Rev 0x%02x.%x is not supported by "
598 "this driver\n", ah->hw_version.macVersion,
599 ah->hw_version.macRev);
600 return -EOPNOTSUPP;
601 }
602
603 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
604 ah->is_pciexpress = false;
605
606 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
607 ath9k_hw_init_cal_settings(ah);
608
609 ah->ani_function = ATH9K_ANI_ALL;
610 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
611 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
612
613 ath9k_hw_init_mode_regs(ah);
614
615 if (ah->is_pciexpress)
616 ath9k_hw_configpcipowersave(ah, 0, 0);
617 else
618 ath9k_hw_disablepcie(ah);
619
620 if (!AR_SREV_9300_20_OR_LATER(ah))
621 ar9002_hw_cck_chan14_spread(ah);
622
623 r = ath9k_hw_post_init(ah);
624 if (r)
625 return r;
626
627 ath9k_hw_init_mode_gain_regs(ah);
628 r = ath9k_hw_fill_cap_info(ah);
629 if (r)
630 return r;
631
632 ath9k_hw_init_eeprom_fix(ah);
633
634 r = ath9k_hw_init_macaddr(ah);
635 if (r) {
636 ath_print(common, ATH_DBG_FATAL,
637 "Failed to initialize MAC address\n");
638 return r;
639 }
640
641 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
642 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
643 else
644 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
645
646 if (AR_SREV_9300_20_OR_LATER(ah))
647 ar9003_hw_set_nf_limits(ah);
648
649 ath9k_init_nfcal_hist_buffer(ah);
650
651 common->state = ATH_HW_INITIALIZED;
652
653 return 0;
654 }
655
656 int ath9k_hw_init(struct ath_hw *ah)
657 {
658 int ret;
659 struct ath_common *common = ath9k_hw_common(ah);
660
661 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
662 switch (ah->hw_version.devid) {
663 case AR5416_DEVID_PCI:
664 case AR5416_DEVID_PCIE:
665 case AR5416_AR9100_DEVID:
666 case AR9160_DEVID_PCI:
667 case AR9280_DEVID_PCI:
668 case AR9280_DEVID_PCIE:
669 case AR9285_DEVID_PCIE:
670 case AR9287_DEVID_PCI:
671 case AR9287_DEVID_PCIE:
672 case AR2427_DEVID_PCIE:
673 case AR9300_DEVID_PCIE:
674 break;
675 default:
676 if (common->bus_ops->ath_bus_type == ATH_USB)
677 break;
678 ath_print(common, ATH_DBG_FATAL,
679 "Hardware device ID 0x%04x not supported\n",
680 ah->hw_version.devid);
681 return -EOPNOTSUPP;
682 }
683
684 ret = __ath9k_hw_init(ah);
685 if (ret) {
686 ath_print(common, ATH_DBG_FATAL,
687 "Unable to initialize hardware; "
688 "initialization status: %d\n", ret);
689 return ret;
690 }
691
692 return 0;
693 }
694 EXPORT_SYMBOL(ath9k_hw_init);
695
696 static void ath9k_hw_init_qos(struct ath_hw *ah)
697 {
698 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
699 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
700
701 REG_WRITE(ah, AR_QOS_NO_ACK,
702 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
703 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
704 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
705
706 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
707 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
708 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
709 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
710 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
711 }
712
713 static void ath9k_hw_init_pll(struct ath_hw *ah,
714 struct ath9k_channel *chan)
715 {
716 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
717
718 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
719
720 /* Switch the core clock for ar9271 to 117Mhz */
721 if (AR_SREV_9271(ah)) {
722 udelay(500);
723 REG_WRITE(ah, 0x50040, 0x304);
724 }
725
726 udelay(RTC_PLL_SETTLE_DELAY);
727
728 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
729 }
730
731 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
732 enum nl80211_iftype opmode)
733 {
734 u32 imr_reg = AR_IMR_TXERR |
735 AR_IMR_TXURN |
736 AR_IMR_RXERR |
737 AR_IMR_RXORN |
738 AR_IMR_BCNMISC;
739
740 if (AR_SREV_9300_20_OR_LATER(ah)) {
741 imr_reg |= AR_IMR_RXOK_HP;
742 if (ah->config.rx_intr_mitigation)
743 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
744 else
745 imr_reg |= AR_IMR_RXOK_LP;
746
747 } else {
748 if (ah->config.rx_intr_mitigation)
749 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
750 else
751 imr_reg |= AR_IMR_RXOK;
752 }
753
754 if (ah->config.tx_intr_mitigation)
755 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
756 else
757 imr_reg |= AR_IMR_TXOK;
758
759 if (opmode == NL80211_IFTYPE_AP)
760 imr_reg |= AR_IMR_MIB;
761
762 REG_WRITE(ah, AR_IMR, imr_reg);
763 ah->imrs2_reg |= AR_IMR_S2_GTT;
764 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
765
766 if (!AR_SREV_9100(ah)) {
767 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
768 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
769 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
770 }
771
772 if (AR_SREV_9300_20_OR_LATER(ah)) {
773 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
774 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
775 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
776 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
777 }
778 }
779
780 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
781 {
782 u32 val = ath9k_hw_mac_to_clks(ah, us);
783 val = min(val, (u32) 0xFFFF);
784 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
785 }
786
787 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
788 {
789 u32 val = ath9k_hw_mac_to_clks(ah, us);
790 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
791 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
792 }
793
794 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
795 {
796 u32 val = ath9k_hw_mac_to_clks(ah, us);
797 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
798 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
799 }
800
801 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
802 {
803 if (tu > 0xFFFF) {
804 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
805 "bad global tx timeout %u\n", tu);
806 ah->globaltxtimeout = (u32) -1;
807 return false;
808 } else {
809 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
810 ah->globaltxtimeout = tu;
811 return true;
812 }
813 }
814
815 void ath9k_hw_init_global_settings(struct ath_hw *ah)
816 {
817 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
818 int acktimeout;
819 int slottime;
820 int sifstime;
821
822 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
823 ah->misc_mode);
824
825 if (ah->misc_mode != 0)
826 REG_WRITE(ah, AR_PCU_MISC,
827 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
828
829 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
830 sifstime = 16;
831 else
832 sifstime = 10;
833
834 /* As defined by IEEE 802.11-2007 17.3.8.6 */
835 slottime = ah->slottime + 3 * ah->coverage_class;
836 acktimeout = slottime + sifstime;
837
838 /*
839 * Workaround for early ACK timeouts, add an offset to match the
840 * initval's 64us ack timeout value.
841 * This was initially only meant to work around an issue with delayed
842 * BA frames in some implementations, but it has been found to fix ACK
843 * timeout issues in other cases as well.
844 */
845 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
846 acktimeout += 64 - sifstime - ah->slottime;
847
848 ath9k_hw_setslottime(ah, slottime);
849 ath9k_hw_set_ack_timeout(ah, acktimeout);
850 ath9k_hw_set_cts_timeout(ah, acktimeout);
851 if (ah->globaltxtimeout != (u32) -1)
852 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
853 }
854 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
855
856 void ath9k_hw_deinit(struct ath_hw *ah)
857 {
858 struct ath_common *common = ath9k_hw_common(ah);
859
860 if (common->state < ATH_HW_INITIALIZED)
861 goto free_hw;
862
863 if (!AR_SREV_9100(ah))
864 ath9k_hw_ani_disable(ah);
865
866 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
867
868 free_hw:
869 ath9k_hw_rf_free_ext_banks(ah);
870 }
871 EXPORT_SYMBOL(ath9k_hw_deinit);
872
873 /*******/
874 /* INI */
875 /*******/
876
877 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
878 {
879 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
880
881 if (IS_CHAN_B(chan))
882 ctl |= CTL_11B;
883 else if (IS_CHAN_G(chan))
884 ctl |= CTL_11G;
885 else
886 ctl |= CTL_11A;
887
888 return ctl;
889 }
890
891 /****************************************/
892 /* Reset and Channel Switching Routines */
893 /****************************************/
894
895 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
896 {
897 u32 regval;
898
899 /*
900 * set AHB_MODE not to do cacheline prefetches
901 */
902 regval = REG_READ(ah, AR_AHB_MODE);
903 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
904
905 /*
906 * let mac dma reads be in 128 byte chunks
907 */
908 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
909 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
910
911 /*
912 * Restore TX Trigger Level to its pre-reset value.
913 * The initial value depends on whether aggregation is enabled, and is
914 * adjusted whenever underruns are detected.
915 */
916 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
917
918 /*
919 * let mac dma writes be in 128 byte chunks
920 */
921 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
922 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
923
924 /*
925 * Setup receive FIFO threshold to hold off TX activities
926 */
927 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
928
929 /*
930 * reduce the number of usable entries in PCU TXBUF to avoid
931 * wrap around issues.
932 */
933 if (AR_SREV_9285(ah)) {
934 /* For AR9285 the number of Fifos are reduced to half.
935 * So set the usable tx buf size also to half to
936 * avoid data/delimiter underruns
937 */
938 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
939 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
940 } else if (!AR_SREV_9271(ah)) {
941 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
942 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
943 }
944 }
945
946 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
947 {
948 u32 val;
949
950 val = REG_READ(ah, AR_STA_ID1);
951 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
952 switch (opmode) {
953 case NL80211_IFTYPE_AP:
954 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
955 | AR_STA_ID1_KSRCH_MODE);
956 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
957 break;
958 case NL80211_IFTYPE_ADHOC:
959 case NL80211_IFTYPE_MESH_POINT:
960 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
961 | AR_STA_ID1_KSRCH_MODE);
962 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
963 break;
964 case NL80211_IFTYPE_STATION:
965 case NL80211_IFTYPE_MONITOR:
966 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
967 break;
968 }
969 }
970
971 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
972 u32 *coef_mantissa, u32 *coef_exponent)
973 {
974 u32 coef_exp, coef_man;
975
976 for (coef_exp = 31; coef_exp > 0; coef_exp--)
977 if ((coef_scaled >> coef_exp) & 0x1)
978 break;
979
980 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
981
982 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
983
984 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
985 *coef_exponent = coef_exp - 16;
986 }
987
988 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
989 {
990 u32 rst_flags;
991 u32 tmpReg;
992
993 if (AR_SREV_9100(ah)) {
994 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
995 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
996 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
997 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
998 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
999 }
1000
1001 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1002 AR_RTC_FORCE_WAKE_ON_INT);
1003
1004 if (AR_SREV_9100(ah)) {
1005 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1006 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1007 } else {
1008 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1009 if (tmpReg &
1010 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1011 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1012 u32 val;
1013 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1014
1015 val = AR_RC_HOSTIF;
1016 if (!AR_SREV_9300_20_OR_LATER(ah))
1017 val |= AR_RC_AHB;
1018 REG_WRITE(ah, AR_RC, val);
1019
1020 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1021 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1022
1023 rst_flags = AR_RTC_RC_MAC_WARM;
1024 if (type == ATH9K_RESET_COLD)
1025 rst_flags |= AR_RTC_RC_MAC_COLD;
1026 }
1027
1028 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1029 udelay(50);
1030
1031 REG_WRITE(ah, AR_RTC_RC, 0);
1032 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1033 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1034 "RTC stuck in MAC reset\n");
1035 return false;
1036 }
1037
1038 if (!AR_SREV_9100(ah))
1039 REG_WRITE(ah, AR_RC, 0);
1040
1041 if (AR_SREV_9100(ah))
1042 udelay(50);
1043
1044 return true;
1045 }
1046
1047 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1048 {
1049 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1050 AR_RTC_FORCE_WAKE_ON_INT);
1051
1052 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1053 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1054
1055 REG_WRITE(ah, AR_RTC_RESET, 0);
1056
1057 if (!AR_SREV_9300_20_OR_LATER(ah))
1058 udelay(2);
1059
1060 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1061 REG_WRITE(ah, AR_RC, 0);
1062
1063 REG_WRITE(ah, AR_RTC_RESET, 1);
1064
1065 if (!ath9k_hw_wait(ah,
1066 AR_RTC_STATUS,
1067 AR_RTC_STATUS_M,
1068 AR_RTC_STATUS_ON,
1069 AH_WAIT_TIMEOUT)) {
1070 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1071 "RTC not waking up\n");
1072 return false;
1073 }
1074
1075 ath9k_hw_read_revisions(ah);
1076
1077 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1078 }
1079
1080 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1081 {
1082 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1083 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1084
1085 switch (type) {
1086 case ATH9K_RESET_POWER_ON:
1087 return ath9k_hw_set_reset_power_on(ah);
1088 case ATH9K_RESET_WARM:
1089 case ATH9K_RESET_COLD:
1090 return ath9k_hw_set_reset(ah, type);
1091 default:
1092 return false;
1093 }
1094 }
1095
1096 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1097 struct ath9k_channel *chan)
1098 {
1099 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1100 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1101 return false;
1102 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1103 return false;
1104
1105 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1106 return false;
1107
1108 ah->chip_fullsleep = false;
1109 ath9k_hw_init_pll(ah, chan);
1110 ath9k_hw_set_rfmode(ah, chan);
1111
1112 return true;
1113 }
1114
1115 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1116 struct ath9k_channel *chan)
1117 {
1118 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1119 struct ath_common *common = ath9k_hw_common(ah);
1120 struct ieee80211_channel *channel = chan->chan;
1121 u32 qnum;
1122 int r;
1123
1124 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1125 if (ath9k_hw_numtxpending(ah, qnum)) {
1126 ath_print(common, ATH_DBG_QUEUE,
1127 "Transmit frames pending on "
1128 "queue %d\n", qnum);
1129 return false;
1130 }
1131 }
1132
1133 if (!ath9k_hw_rfbus_req(ah)) {
1134 ath_print(common, ATH_DBG_FATAL,
1135 "Could not kill baseband RX\n");
1136 return false;
1137 }
1138
1139 ath9k_hw_set_channel_regs(ah, chan);
1140
1141 r = ath9k_hw_rf_set_freq(ah, chan);
1142 if (r) {
1143 ath_print(common, ATH_DBG_FATAL,
1144 "Failed to set channel\n");
1145 return false;
1146 }
1147
1148 ah->eep_ops->set_txpower(ah, chan,
1149 ath9k_regd_get_ctl(regulatory, chan),
1150 channel->max_antenna_gain * 2,
1151 channel->max_power * 2,
1152 min((u32) MAX_RATE_POWER,
1153 (u32) regulatory->power_limit));
1154
1155 ath9k_hw_rfbus_done(ah);
1156
1157 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1158 ath9k_hw_set_delta_slope(ah, chan);
1159
1160 ath9k_hw_spur_mitigate_freq(ah, chan);
1161
1162 if (!chan->oneTimeCalsDone)
1163 chan->oneTimeCalsDone = true;
1164
1165 return true;
1166 }
1167
1168 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1169 bool bChannelChange)
1170 {
1171 struct ath_common *common = ath9k_hw_common(ah);
1172 u32 saveLedState;
1173 struct ath9k_channel *curchan = ah->curchan;
1174 u32 saveDefAntenna;
1175 u32 macStaId1;
1176 u64 tsf = 0;
1177 int i, r;
1178
1179 ah->txchainmask = common->tx_chainmask;
1180 ah->rxchainmask = common->rx_chainmask;
1181
1182 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1183 return -EIO;
1184
1185 if (curchan && !ah->chip_fullsleep)
1186 ath9k_hw_getnf(ah, curchan);
1187
1188 if (bChannelChange &&
1189 (ah->chip_fullsleep != true) &&
1190 (ah->curchan != NULL) &&
1191 (chan->channel != ah->curchan->channel) &&
1192 ((chan->channelFlags & CHANNEL_ALL) ==
1193 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1194 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1195 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1196
1197 if (ath9k_hw_channel_change(ah, chan)) {
1198 ath9k_hw_loadnf(ah, ah->curchan);
1199 ath9k_hw_start_nfcal(ah);
1200 return 0;
1201 }
1202 }
1203
1204 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1205 if (saveDefAntenna == 0)
1206 saveDefAntenna = 1;
1207
1208 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1209
1210 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1211 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1212 tsf = ath9k_hw_gettsf64(ah);
1213
1214 saveLedState = REG_READ(ah, AR_CFG_LED) &
1215 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1216 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1217
1218 ath9k_hw_mark_phy_inactive(ah);
1219
1220 /* Only required on the first reset */
1221 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1222 REG_WRITE(ah,
1223 AR9271_RESET_POWER_DOWN_CONTROL,
1224 AR9271_RADIO_RF_RST);
1225 udelay(50);
1226 }
1227
1228 if (!ath9k_hw_chip_reset(ah, chan)) {
1229 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1230 return -EINVAL;
1231 }
1232
1233 /* Only required on the first reset */
1234 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1235 ah->htc_reset_init = false;
1236 REG_WRITE(ah,
1237 AR9271_RESET_POWER_DOWN_CONTROL,
1238 AR9271_GATE_MAC_CTL);
1239 udelay(50);
1240 }
1241
1242 /* Restore TSF */
1243 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1244 ath9k_hw_settsf64(ah, tsf);
1245
1246 if (AR_SREV_9280_10_OR_LATER(ah))
1247 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1248
1249 r = ath9k_hw_process_ini(ah, chan);
1250 if (r)
1251 return r;
1252
1253 /* Setup MFP options for CCMP */
1254 if (AR_SREV_9280_20_OR_LATER(ah)) {
1255 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1256 * frames when constructing CCMP AAD. */
1257 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1258 0xc7ff);
1259 ah->sw_mgmt_crypto = false;
1260 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1261 /* Disable hardware crypto for management frames */
1262 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1263 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1264 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1265 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1266 ah->sw_mgmt_crypto = true;
1267 } else
1268 ah->sw_mgmt_crypto = true;
1269
1270 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1271 ath9k_hw_set_delta_slope(ah, chan);
1272
1273 ath9k_hw_spur_mitigate_freq(ah, chan);
1274 ah->eep_ops->set_board_values(ah, chan);
1275
1276 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1277 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1278 | macStaId1
1279 | AR_STA_ID1_RTS_USE_DEF
1280 | (ah->config.
1281 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1282 | ah->sta_id1_defaults);
1283 ath9k_hw_set_operating_mode(ah, ah->opmode);
1284
1285 ath_hw_setbssidmask(common);
1286
1287 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1288
1289 ath9k_hw_write_associd(ah);
1290
1291 REG_WRITE(ah, AR_ISR, ~0);
1292
1293 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1294
1295 r = ath9k_hw_rf_set_freq(ah, chan);
1296 if (r)
1297 return r;
1298
1299 for (i = 0; i < AR_NUM_DCU; i++)
1300 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1301
1302 ah->intr_txqs = 0;
1303 for (i = 0; i < ah->caps.total_queues; i++)
1304 ath9k_hw_resettxqueue(ah, i);
1305
1306 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1307 ath9k_hw_init_qos(ah);
1308
1309 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1310 ath9k_enable_rfkill(ah);
1311
1312 ath9k_hw_init_global_settings(ah);
1313
1314 if (AR_SREV_9287_12_OR_LATER(ah)) {
1315 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1316 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1317 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1318 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1319 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1320 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1321
1322 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1323 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1324
1325 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1326 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1327 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1328 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1329 }
1330 if (AR_SREV_9287_12_OR_LATER(ah)) {
1331 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1332 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1333 }
1334
1335 REG_WRITE(ah, AR_STA_ID1,
1336 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1337
1338 ath9k_hw_set_dma(ah);
1339
1340 REG_WRITE(ah, AR_OBS, 8);
1341
1342 if (ah->config.rx_intr_mitigation) {
1343 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1344 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1345 }
1346
1347 ath9k_hw_init_bb(ah, chan);
1348
1349 if (!ath9k_hw_init_cal(ah, chan))
1350 return -EIO;
1351
1352 ath9k_hw_restore_chainmask(ah);
1353 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1354
1355 /*
1356 * For big endian systems turn on swapping for descriptors
1357 */
1358 if (AR_SREV_9100(ah)) {
1359 u32 mask;
1360 mask = REG_READ(ah, AR_CFG);
1361 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1362 ath_print(common, ATH_DBG_RESET,
1363 "CFG Byte Swap Set 0x%x\n", mask);
1364 } else {
1365 mask =
1366 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1367 REG_WRITE(ah, AR_CFG, mask);
1368 ath_print(common, ATH_DBG_RESET,
1369 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1370 }
1371 } else {
1372 /* Configure AR9271 target WLAN */
1373 if (AR_SREV_9271(ah))
1374 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1375 #ifdef __BIG_ENDIAN
1376 else
1377 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1378 #endif
1379 }
1380
1381 if (ah->btcoex_hw.enabled)
1382 ath9k_hw_btcoex_enable(ah);
1383
1384 return 0;
1385 }
1386 EXPORT_SYMBOL(ath9k_hw_reset);
1387
1388 /************************/
1389 /* Key Cache Management */
1390 /************************/
1391
1392 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1393 {
1394 u32 keyType;
1395
1396 if (entry >= ah->caps.keycache_size) {
1397 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1398 "keychache entry %u out of range\n", entry);
1399 return false;
1400 }
1401
1402 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1403
1404 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1405 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1406 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1407 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1408 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1409 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1410 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1411 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1412
1413 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1414 u16 micentry = entry + 64;
1415
1416 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1417 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1418 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1419 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1420
1421 }
1422
1423 return true;
1424 }
1425 EXPORT_SYMBOL(ath9k_hw_keyreset);
1426
1427 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1428 {
1429 u32 macHi, macLo;
1430
1431 if (entry >= ah->caps.keycache_size) {
1432 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1433 "keychache entry %u out of range\n", entry);
1434 return false;
1435 }
1436
1437 if (mac != NULL) {
1438 macHi = (mac[5] << 8) | mac[4];
1439 macLo = (mac[3] << 24) |
1440 (mac[2] << 16) |
1441 (mac[1] << 8) |
1442 mac[0];
1443 macLo >>= 1;
1444 macLo |= (macHi & 1) << 31;
1445 macHi >>= 1;
1446 } else {
1447 macLo = macHi = 0;
1448 }
1449 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1450 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1451
1452 return true;
1453 }
1454 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1455
1456 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1457 const struct ath9k_keyval *k,
1458 const u8 *mac)
1459 {
1460 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1461 struct ath_common *common = ath9k_hw_common(ah);
1462 u32 key0, key1, key2, key3, key4;
1463 u32 keyType;
1464
1465 if (entry >= pCap->keycache_size) {
1466 ath_print(common, ATH_DBG_FATAL,
1467 "keycache entry %u out of range\n", entry);
1468 return false;
1469 }
1470
1471 switch (k->kv_type) {
1472 case ATH9K_CIPHER_AES_OCB:
1473 keyType = AR_KEYTABLE_TYPE_AES;
1474 break;
1475 case ATH9K_CIPHER_AES_CCM:
1476 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1477 ath_print(common, ATH_DBG_ANY,
1478 "AES-CCM not supported by mac rev 0x%x\n",
1479 ah->hw_version.macRev);
1480 return false;
1481 }
1482 keyType = AR_KEYTABLE_TYPE_CCM;
1483 break;
1484 case ATH9K_CIPHER_TKIP:
1485 keyType = AR_KEYTABLE_TYPE_TKIP;
1486 if (ATH9K_IS_MIC_ENABLED(ah)
1487 && entry + 64 >= pCap->keycache_size) {
1488 ath_print(common, ATH_DBG_ANY,
1489 "entry %u inappropriate for TKIP\n", entry);
1490 return false;
1491 }
1492 break;
1493 case ATH9K_CIPHER_WEP:
1494 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1495 ath_print(common, ATH_DBG_ANY,
1496 "WEP key length %u too small\n", k->kv_len);
1497 return false;
1498 }
1499 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1500 keyType = AR_KEYTABLE_TYPE_40;
1501 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1502 keyType = AR_KEYTABLE_TYPE_104;
1503 else
1504 keyType = AR_KEYTABLE_TYPE_128;
1505 break;
1506 case ATH9K_CIPHER_CLR:
1507 keyType = AR_KEYTABLE_TYPE_CLR;
1508 break;
1509 default:
1510 ath_print(common, ATH_DBG_FATAL,
1511 "cipher %u not supported\n", k->kv_type);
1512 return false;
1513 }
1514
1515 key0 = get_unaligned_le32(k->kv_val + 0);
1516 key1 = get_unaligned_le16(k->kv_val + 4);
1517 key2 = get_unaligned_le32(k->kv_val + 6);
1518 key3 = get_unaligned_le16(k->kv_val + 10);
1519 key4 = get_unaligned_le32(k->kv_val + 12);
1520 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1521 key4 &= 0xff;
1522
1523 /*
1524 * Note: Key cache registers access special memory area that requires
1525 * two 32-bit writes to actually update the values in the internal
1526 * memory. Consequently, the exact order and pairs used here must be
1527 * maintained.
1528 */
1529
1530 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1531 u16 micentry = entry + 64;
1532
1533 /*
1534 * Write inverted key[47:0] first to avoid Michael MIC errors
1535 * on frames that could be sent or received at the same time.
1536 * The correct key will be written in the end once everything
1537 * else is ready.
1538 */
1539 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1540 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1541
1542 /* Write key[95:48] */
1543 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1544 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1545
1546 /* Write key[127:96] and key type */
1547 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1548 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1549
1550 /* Write MAC address for the entry */
1551 (void) ath9k_hw_keysetmac(ah, entry, mac);
1552
1553 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1554 /*
1555 * TKIP uses two key cache entries:
1556 * Michael MIC TX/RX keys in the same key cache entry
1557 * (idx = main index + 64):
1558 * key0 [31:0] = RX key [31:0]
1559 * key1 [15:0] = TX key [31:16]
1560 * key1 [31:16] = reserved
1561 * key2 [31:0] = RX key [63:32]
1562 * key3 [15:0] = TX key [15:0]
1563 * key3 [31:16] = reserved
1564 * key4 [31:0] = TX key [63:32]
1565 */
1566 u32 mic0, mic1, mic2, mic3, mic4;
1567
1568 mic0 = get_unaligned_le32(k->kv_mic + 0);
1569 mic2 = get_unaligned_le32(k->kv_mic + 4);
1570 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1571 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1572 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1573
1574 /* Write RX[31:0] and TX[31:16] */
1575 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1576 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1577
1578 /* Write RX[63:32] and TX[15:0] */
1579 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1580 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1581
1582 /* Write TX[63:32] and keyType(reserved) */
1583 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1584 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1585 AR_KEYTABLE_TYPE_CLR);
1586
1587 } else {
1588 /*
1589 * TKIP uses four key cache entries (two for group
1590 * keys):
1591 * Michael MIC TX/RX keys are in different key cache
1592 * entries (idx = main index + 64 for TX and
1593 * main index + 32 + 96 for RX):
1594 * key0 [31:0] = TX/RX MIC key [31:0]
1595 * key1 [31:0] = reserved
1596 * key2 [31:0] = TX/RX MIC key [63:32]
1597 * key3 [31:0] = reserved
1598 * key4 [31:0] = reserved
1599 *
1600 * Upper layer code will call this function separately
1601 * for TX and RX keys when these registers offsets are
1602 * used.
1603 */
1604 u32 mic0, mic2;
1605
1606 mic0 = get_unaligned_le32(k->kv_mic + 0);
1607 mic2 = get_unaligned_le32(k->kv_mic + 4);
1608
1609 /* Write MIC key[31:0] */
1610 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1611 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1612
1613 /* Write MIC key[63:32] */
1614 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1615 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1616
1617 /* Write TX[63:32] and keyType(reserved) */
1618 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1619 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1620 AR_KEYTABLE_TYPE_CLR);
1621 }
1622
1623 /* MAC address registers are reserved for the MIC entry */
1624 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1625 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1626
1627 /*
1628 * Write the correct (un-inverted) key[47:0] last to enable
1629 * TKIP now that all other registers are set with correct
1630 * values.
1631 */
1632 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1633 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1634 } else {
1635 /* Write key[47:0] */
1636 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1637 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1638
1639 /* Write key[95:48] */
1640 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1641 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1642
1643 /* Write key[127:96] and key type */
1644 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1645 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1646
1647 /* Write MAC address for the entry */
1648 (void) ath9k_hw_keysetmac(ah, entry, mac);
1649 }
1650
1651 return true;
1652 }
1653 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1654
1655 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1656 {
1657 if (entry < ah->caps.keycache_size) {
1658 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1659 if (val & AR_KEYTABLE_VALID)
1660 return true;
1661 }
1662 return false;
1663 }
1664 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1665
1666 /******************************/
1667 /* Power Management (Chipset) */
1668 /******************************/
1669
1670 /*
1671 * Notify Power Mgt is disabled in self-generated frames.
1672 * If requested, force chip to sleep.
1673 */
1674 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1675 {
1676 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1677 if (setChip) {
1678 /*
1679 * Clear the RTC force wake bit to allow the
1680 * mac to go to sleep.
1681 */
1682 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1683 AR_RTC_FORCE_WAKE_EN);
1684 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1685 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1686
1687 /* Shutdown chip. Active low */
1688 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1689 REG_CLR_BIT(ah, (AR_RTC_RESET),
1690 AR_RTC_RESET_EN);
1691 }
1692 }
1693
1694 /*
1695 * Notify Power Management is enabled in self-generating
1696 * frames. If request, set power mode of chip to
1697 * auto/normal. Duration in units of 128us (1/8 TU).
1698 */
1699 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1700 {
1701 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1702 if (setChip) {
1703 struct ath9k_hw_capabilities *pCap = &ah->caps;
1704
1705 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1706 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1707 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1708 AR_RTC_FORCE_WAKE_ON_INT);
1709 } else {
1710 /*
1711 * Clear the RTC force wake bit to allow the
1712 * mac to go to sleep.
1713 */
1714 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1715 AR_RTC_FORCE_WAKE_EN);
1716 }
1717 }
1718 }
1719
1720 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1721 {
1722 u32 val;
1723 int i;
1724
1725 if (setChip) {
1726 if ((REG_READ(ah, AR_RTC_STATUS) &
1727 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1728 if (ath9k_hw_set_reset_reg(ah,
1729 ATH9K_RESET_POWER_ON) != true) {
1730 return false;
1731 }
1732 if (!AR_SREV_9300_20_OR_LATER(ah))
1733 ath9k_hw_init_pll(ah, NULL);
1734 }
1735 if (AR_SREV_9100(ah))
1736 REG_SET_BIT(ah, AR_RTC_RESET,
1737 AR_RTC_RESET_EN);
1738
1739 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1740 AR_RTC_FORCE_WAKE_EN);
1741 udelay(50);
1742
1743 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1744 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1745 if (val == AR_RTC_STATUS_ON)
1746 break;
1747 udelay(50);
1748 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1749 AR_RTC_FORCE_WAKE_EN);
1750 }
1751 if (i == 0) {
1752 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1753 "Failed to wakeup in %uus\n",
1754 POWER_UP_TIME / 20);
1755 return false;
1756 }
1757 }
1758
1759 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1760
1761 return true;
1762 }
1763
1764 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1765 {
1766 struct ath_common *common = ath9k_hw_common(ah);
1767 int status = true, setChip = true;
1768 static const char *modes[] = {
1769 "AWAKE",
1770 "FULL-SLEEP",
1771 "NETWORK SLEEP",
1772 "UNDEFINED"
1773 };
1774
1775 if (ah->power_mode == mode)
1776 return status;
1777
1778 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1779 modes[ah->power_mode], modes[mode]);
1780
1781 switch (mode) {
1782 case ATH9K_PM_AWAKE:
1783 status = ath9k_hw_set_power_awake(ah, setChip);
1784 break;
1785 case ATH9K_PM_FULL_SLEEP:
1786 ath9k_set_power_sleep(ah, setChip);
1787 ah->chip_fullsleep = true;
1788 break;
1789 case ATH9K_PM_NETWORK_SLEEP:
1790 ath9k_set_power_network_sleep(ah, setChip);
1791 break;
1792 default:
1793 ath_print(common, ATH_DBG_FATAL,
1794 "Unknown power mode %u\n", mode);
1795 return false;
1796 }
1797 ah->power_mode = mode;
1798
1799 return status;
1800 }
1801 EXPORT_SYMBOL(ath9k_hw_setpower);
1802
1803 /*******************/
1804 /* Beacon Handling */
1805 /*******************/
1806
1807 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1808 {
1809 int flags = 0;
1810
1811 ah->beacon_interval = beacon_period;
1812
1813 switch (ah->opmode) {
1814 case NL80211_IFTYPE_STATION:
1815 case NL80211_IFTYPE_MONITOR:
1816 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1817 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1818 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1819 flags |= AR_TBTT_TIMER_EN;
1820 break;
1821 case NL80211_IFTYPE_ADHOC:
1822 case NL80211_IFTYPE_MESH_POINT:
1823 REG_SET_BIT(ah, AR_TXCFG,
1824 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1825 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1826 TU_TO_USEC(next_beacon +
1827 (ah->atim_window ? ah->
1828 atim_window : 1)));
1829 flags |= AR_NDP_TIMER_EN;
1830 case NL80211_IFTYPE_AP:
1831 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1832 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1833 TU_TO_USEC(next_beacon -
1834 ah->config.
1835 dma_beacon_response_time));
1836 REG_WRITE(ah, AR_NEXT_SWBA,
1837 TU_TO_USEC(next_beacon -
1838 ah->config.
1839 sw_beacon_response_time));
1840 flags |=
1841 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1842 break;
1843 default:
1844 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1845 "%s: unsupported opmode: %d\n",
1846 __func__, ah->opmode);
1847 return;
1848 break;
1849 }
1850
1851 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1852 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1853 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1854 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1855
1856 beacon_period &= ~ATH9K_BEACON_ENA;
1857 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1858 ath9k_hw_reset_tsf(ah);
1859 }
1860
1861 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1862 }
1863 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1864
1865 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1866 const struct ath9k_beacon_state *bs)
1867 {
1868 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1869 struct ath9k_hw_capabilities *pCap = &ah->caps;
1870 struct ath_common *common = ath9k_hw_common(ah);
1871
1872 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1873
1874 REG_WRITE(ah, AR_BEACON_PERIOD,
1875 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1876 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1877 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1878
1879 REG_RMW_FIELD(ah, AR_RSSI_THR,
1880 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1881
1882 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1883
1884 if (bs->bs_sleepduration > beaconintval)
1885 beaconintval = bs->bs_sleepduration;
1886
1887 dtimperiod = bs->bs_dtimperiod;
1888 if (bs->bs_sleepduration > dtimperiod)
1889 dtimperiod = bs->bs_sleepduration;
1890
1891 if (beaconintval == dtimperiod)
1892 nextTbtt = bs->bs_nextdtim;
1893 else
1894 nextTbtt = bs->bs_nexttbtt;
1895
1896 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1897 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1898 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1899 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1900
1901 REG_WRITE(ah, AR_NEXT_DTIM,
1902 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1903 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1904
1905 REG_WRITE(ah, AR_SLEEP1,
1906 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1907 | AR_SLEEP1_ASSUME_DTIM);
1908
1909 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1910 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1911 else
1912 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1913
1914 REG_WRITE(ah, AR_SLEEP2,
1915 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1916
1917 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1918 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1919
1920 REG_SET_BIT(ah, AR_TIMER_MODE,
1921 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1922 AR_DTIM_TIMER_EN);
1923
1924 /* TSF Out of Range Threshold */
1925 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1926 }
1927 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1928
1929 /*******************/
1930 /* HW Capabilities */
1931 /*******************/
1932
1933 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1934 {
1935 struct ath9k_hw_capabilities *pCap = &ah->caps;
1936 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1937 struct ath_common *common = ath9k_hw_common(ah);
1938 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1939
1940 u16 capField = 0, eeval;
1941
1942 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1943 regulatory->current_rd = eeval;
1944
1945 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1946 if (AR_SREV_9285_10_OR_LATER(ah))
1947 eeval |= AR9285_RDEXT_DEFAULT;
1948 regulatory->current_rd_ext = eeval;
1949
1950 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1951
1952 if (ah->opmode != NL80211_IFTYPE_AP &&
1953 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1954 if (regulatory->current_rd == 0x64 ||
1955 regulatory->current_rd == 0x65)
1956 regulatory->current_rd += 5;
1957 else if (regulatory->current_rd == 0x41)
1958 regulatory->current_rd = 0x43;
1959 ath_print(common, ATH_DBG_REGULATORY,
1960 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1961 }
1962
1963 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1964 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1965 ath_print(common, ATH_DBG_FATAL,
1966 "no band has been marked as supported in EEPROM.\n");
1967 return -EINVAL;
1968 }
1969
1970 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
1971
1972 if (eeval & AR5416_OPFLAGS_11A) {
1973 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
1974 if (ah->config.ht_enable) {
1975 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
1976 set_bit(ATH9K_MODE_11NA_HT20,
1977 pCap->wireless_modes);
1978 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
1979 set_bit(ATH9K_MODE_11NA_HT40PLUS,
1980 pCap->wireless_modes);
1981 set_bit(ATH9K_MODE_11NA_HT40MINUS,
1982 pCap->wireless_modes);
1983 }
1984 }
1985 }
1986
1987 if (eeval & AR5416_OPFLAGS_11G) {
1988 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
1989 if (ah->config.ht_enable) {
1990 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
1991 set_bit(ATH9K_MODE_11NG_HT20,
1992 pCap->wireless_modes);
1993 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
1994 set_bit(ATH9K_MODE_11NG_HT40PLUS,
1995 pCap->wireless_modes);
1996 set_bit(ATH9K_MODE_11NG_HT40MINUS,
1997 pCap->wireless_modes);
1998 }
1999 }
2000 }
2001
2002 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2003 /*
2004 * For AR9271 we will temporarilly uses the rx chainmax as read from
2005 * the EEPROM.
2006 */
2007 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2008 !(eeval & AR5416_OPFLAGS_11A) &&
2009 !(AR_SREV_9271(ah)))
2010 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2011 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2012 else
2013 /* Use rx_chainmask from EEPROM. */
2014 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2015
2016 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2017 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2018
2019 pCap->low_2ghz_chan = 2312;
2020 pCap->high_2ghz_chan = 2732;
2021
2022 pCap->low_5ghz_chan = 4920;
2023 pCap->high_5ghz_chan = 6100;
2024
2025 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2026 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2027 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2028
2029 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2030 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2031 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2032
2033 if (ah->config.ht_enable)
2034 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2035 else
2036 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2037
2038 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2039 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2040 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2041 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2042
2043 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2044 pCap->total_queues =
2045 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2046 else
2047 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2048
2049 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2050 pCap->keycache_size =
2051 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2052 else
2053 pCap->keycache_size = AR_KEYTABLE_SIZE;
2054
2055 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2056
2057 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2058 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2059 else
2060 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2061
2062 if (AR_SREV_9271(ah))
2063 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2064 else if (AR_SREV_9285_10_OR_LATER(ah))
2065 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2066 else if (AR_SREV_9280_10_OR_LATER(ah))
2067 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2068 else
2069 pCap->num_gpio_pins = AR_NUM_GPIO;
2070
2071 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2072 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2073 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2074 } else {
2075 pCap->rts_aggr_limit = (8 * 1024);
2076 }
2077
2078 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2079
2080 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2081 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2082 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2083 ah->rfkill_gpio =
2084 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2085 ah->rfkill_polarity =
2086 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2087
2088 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2089 }
2090 #endif
2091 if (AR_SREV_9271(ah))
2092 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2093 else
2094 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2095
2096 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2097 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2098 else
2099 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2100
2101 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2102 pCap->reg_cap =
2103 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2104 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2105 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2106 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2107 } else {
2108 pCap->reg_cap =
2109 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2110 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2111 }
2112
2113 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2114 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2115 AR_SREV_5416(ah))
2116 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2117
2118 pCap->num_antcfg_5ghz =
2119 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2120 pCap->num_antcfg_2ghz =
2121 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2122
2123 if (AR_SREV_9280_10_OR_LATER(ah) &&
2124 ath9k_hw_btcoex_supported(ah)) {
2125 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2126 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2127
2128 if (AR_SREV_9285(ah)) {
2129 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2130 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2131 } else {
2132 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2133 }
2134 } else {
2135 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2136 }
2137
2138 if (AR_SREV_9300_20_OR_LATER(ah)) {
2139 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
2140 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2141 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2142 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2143 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2144 } else {
2145 pCap->tx_desc_len = sizeof(struct ath_desc);
2146 }
2147
2148 if (AR_SREV_9300_20_OR_LATER(ah))
2149 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2150
2151 return 0;
2152 }
2153
2154 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2155 u32 capability, u32 *result)
2156 {
2157 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2158 switch (type) {
2159 case ATH9K_CAP_CIPHER:
2160 switch (capability) {
2161 case ATH9K_CIPHER_AES_CCM:
2162 case ATH9K_CIPHER_AES_OCB:
2163 case ATH9K_CIPHER_TKIP:
2164 case ATH9K_CIPHER_WEP:
2165 case ATH9K_CIPHER_MIC:
2166 case ATH9K_CIPHER_CLR:
2167 return true;
2168 default:
2169 return false;
2170 }
2171 case ATH9K_CAP_TKIP_MIC:
2172 switch (capability) {
2173 case 0:
2174 return true;
2175 case 1:
2176 return (ah->sta_id1_defaults &
2177 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2178 false;
2179 }
2180 case ATH9K_CAP_TKIP_SPLIT:
2181 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2182 false : true;
2183 case ATH9K_CAP_MCAST_KEYSRCH:
2184 switch (capability) {
2185 case 0:
2186 return true;
2187 case 1:
2188 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2189 return false;
2190 } else {
2191 return (ah->sta_id1_defaults &
2192 AR_STA_ID1_MCAST_KSRCH) ? true :
2193 false;
2194 }
2195 }
2196 return false;
2197 case ATH9K_CAP_TXPOW:
2198 switch (capability) {
2199 case 0:
2200 return 0;
2201 case 1:
2202 *result = regulatory->power_limit;
2203 return 0;
2204 case 2:
2205 *result = regulatory->max_power_level;
2206 return 0;
2207 case 3:
2208 *result = regulatory->tp_scale;
2209 return 0;
2210 }
2211 return false;
2212 case ATH9K_CAP_DS:
2213 return (AR_SREV_9280_20_OR_LATER(ah) &&
2214 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2215 ? false : true;
2216 default:
2217 return false;
2218 }
2219 }
2220 EXPORT_SYMBOL(ath9k_hw_getcapability);
2221
2222 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2223 u32 capability, u32 setting, int *status)
2224 {
2225 switch (type) {
2226 case ATH9K_CAP_TKIP_MIC:
2227 if (setting)
2228 ah->sta_id1_defaults |=
2229 AR_STA_ID1_CRPT_MIC_ENABLE;
2230 else
2231 ah->sta_id1_defaults &=
2232 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2233 return true;
2234 case ATH9K_CAP_MCAST_KEYSRCH:
2235 if (setting)
2236 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2237 else
2238 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2239 return true;
2240 default:
2241 return false;
2242 }
2243 }
2244 EXPORT_SYMBOL(ath9k_hw_setcapability);
2245
2246 /****************************/
2247 /* GPIO / RFKILL / Antennae */
2248 /****************************/
2249
2250 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2251 u32 gpio, u32 type)
2252 {
2253 int addr;
2254 u32 gpio_shift, tmp;
2255
2256 if (gpio > 11)
2257 addr = AR_GPIO_OUTPUT_MUX3;
2258 else if (gpio > 5)
2259 addr = AR_GPIO_OUTPUT_MUX2;
2260 else
2261 addr = AR_GPIO_OUTPUT_MUX1;
2262
2263 gpio_shift = (gpio % 6) * 5;
2264
2265 if (AR_SREV_9280_20_OR_LATER(ah)
2266 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2267 REG_RMW(ah, addr, (type << gpio_shift),
2268 (0x1f << gpio_shift));
2269 } else {
2270 tmp = REG_READ(ah, addr);
2271 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2272 tmp &= ~(0x1f << gpio_shift);
2273 tmp |= (type << gpio_shift);
2274 REG_WRITE(ah, addr, tmp);
2275 }
2276 }
2277
2278 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2279 {
2280 u32 gpio_shift;
2281
2282 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2283
2284 gpio_shift = gpio << 1;
2285
2286 REG_RMW(ah,
2287 AR_GPIO_OE_OUT,
2288 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2289 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2290 }
2291 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2292
2293 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2294 {
2295 #define MS_REG_READ(x, y) \
2296 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2297
2298 if (gpio >= ah->caps.num_gpio_pins)
2299 return 0xffffffff;
2300
2301 if (AR_SREV_9300_20_OR_LATER(ah))
2302 return MS_REG_READ(AR9300, gpio) != 0;
2303 else if (AR_SREV_9271(ah))
2304 return MS_REG_READ(AR9271, gpio) != 0;
2305 else if (AR_SREV_9287_10_OR_LATER(ah))
2306 return MS_REG_READ(AR9287, gpio) != 0;
2307 else if (AR_SREV_9285_10_OR_LATER(ah))
2308 return MS_REG_READ(AR9285, gpio) != 0;
2309 else if (AR_SREV_9280_10_OR_LATER(ah))
2310 return MS_REG_READ(AR928X, gpio) != 0;
2311 else
2312 return MS_REG_READ(AR, gpio) != 0;
2313 }
2314 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2315
2316 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2317 u32 ah_signal_type)
2318 {
2319 u32 gpio_shift;
2320
2321 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2322
2323 gpio_shift = 2 * gpio;
2324
2325 REG_RMW(ah,
2326 AR_GPIO_OE_OUT,
2327 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2328 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2329 }
2330 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2331
2332 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2333 {
2334 if (AR_SREV_9271(ah))
2335 val = ~val;
2336
2337 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2338 AR_GPIO_BIT(gpio));
2339 }
2340 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2341
2342 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2343 {
2344 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2345 }
2346 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2347
2348 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2349 {
2350 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2351 }
2352 EXPORT_SYMBOL(ath9k_hw_setantenna);
2353
2354 /*********************/
2355 /* General Operation */
2356 /*********************/
2357
2358 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2359 {
2360 u32 bits = REG_READ(ah, AR_RX_FILTER);
2361 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2362
2363 if (phybits & AR_PHY_ERR_RADAR)
2364 bits |= ATH9K_RX_FILTER_PHYRADAR;
2365 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2366 bits |= ATH9K_RX_FILTER_PHYERR;
2367
2368 return bits;
2369 }
2370 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2371
2372 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2373 {
2374 u32 phybits;
2375
2376 REG_WRITE(ah, AR_RX_FILTER, bits);
2377
2378 phybits = 0;
2379 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2380 phybits |= AR_PHY_ERR_RADAR;
2381 if (bits & ATH9K_RX_FILTER_PHYERR)
2382 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2383 REG_WRITE(ah, AR_PHY_ERR, phybits);
2384
2385 if (phybits)
2386 REG_WRITE(ah, AR_RXCFG,
2387 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2388 else
2389 REG_WRITE(ah, AR_RXCFG,
2390 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2391 }
2392 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2393
2394 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2395 {
2396 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2397 return false;
2398
2399 ath9k_hw_init_pll(ah, NULL);
2400 return true;
2401 }
2402 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2403
2404 bool ath9k_hw_disable(struct ath_hw *ah)
2405 {
2406 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2407 return false;
2408
2409 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2410 return false;
2411
2412 ath9k_hw_init_pll(ah, NULL);
2413 return true;
2414 }
2415 EXPORT_SYMBOL(ath9k_hw_disable);
2416
2417 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2418 {
2419 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2420 struct ath9k_channel *chan = ah->curchan;
2421 struct ieee80211_channel *channel = chan->chan;
2422
2423 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2424
2425 ah->eep_ops->set_txpower(ah, chan,
2426 ath9k_regd_get_ctl(regulatory, chan),
2427 channel->max_antenna_gain * 2,
2428 channel->max_power * 2,
2429 min((u32) MAX_RATE_POWER,
2430 (u32) regulatory->power_limit));
2431 }
2432 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2433
2434 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2435 {
2436 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2437 }
2438 EXPORT_SYMBOL(ath9k_hw_setmac);
2439
2440 void ath9k_hw_setopmode(struct ath_hw *ah)
2441 {
2442 ath9k_hw_set_operating_mode(ah, ah->opmode);
2443 }
2444 EXPORT_SYMBOL(ath9k_hw_setopmode);
2445
2446 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2447 {
2448 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2449 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2450 }
2451 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2452
2453 void ath9k_hw_write_associd(struct ath_hw *ah)
2454 {
2455 struct ath_common *common = ath9k_hw_common(ah);
2456
2457 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2458 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2459 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2460 }
2461 EXPORT_SYMBOL(ath9k_hw_write_associd);
2462
2463 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2464 {
2465 u64 tsf;
2466
2467 tsf = REG_READ(ah, AR_TSF_U32);
2468 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
2469
2470 return tsf;
2471 }
2472 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2473
2474 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2475 {
2476 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2477 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2478 }
2479 EXPORT_SYMBOL(ath9k_hw_settsf64);
2480
2481 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2482 {
2483 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2484 AH_TSF_WRITE_TIMEOUT))
2485 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2486 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2487
2488 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2489 }
2490 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2491
2492 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2493 {
2494 if (setting)
2495 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2496 else
2497 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2498 }
2499 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2500
2501 /*
2502 * Extend 15-bit time stamp from rx descriptor to
2503 * a full 64-bit TSF using the current h/w TSF.
2504 */
2505 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2506 {
2507 u64 tsf;
2508
2509 tsf = ath9k_hw_gettsf64(ah);
2510 if ((tsf & 0x7fff) < rstamp)
2511 tsf -= 0x8000;
2512 return (tsf & ~0x7fff) | rstamp;
2513 }
2514 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2515
2516 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2517 {
2518 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2519 u32 macmode;
2520
2521 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2522 macmode = AR_2040_JOINED_RX_CLEAR;
2523 else
2524 macmode = 0;
2525
2526 REG_WRITE(ah, AR_2040_MODE, macmode);
2527 }
2528
2529 /* HW Generic timers configuration */
2530
2531 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2532 {
2533 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2534 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2535 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2536 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2537 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2538 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2539 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2540 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2541 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2542 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2543 AR_NDP2_TIMER_MODE, 0x0002},
2544 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2545 AR_NDP2_TIMER_MODE, 0x0004},
2546 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2547 AR_NDP2_TIMER_MODE, 0x0008},
2548 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2549 AR_NDP2_TIMER_MODE, 0x0010},
2550 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2551 AR_NDP2_TIMER_MODE, 0x0020},
2552 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2553 AR_NDP2_TIMER_MODE, 0x0040},
2554 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2555 AR_NDP2_TIMER_MODE, 0x0080}
2556 };
2557
2558 /* HW generic timer primitives */
2559
2560 /* compute and clear index of rightmost 1 */
2561 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2562 {
2563 u32 b;
2564
2565 b = *mask;
2566 b &= (0-b);
2567 *mask &= ~b;
2568 b *= debruijn32;
2569 b >>= 27;
2570
2571 return timer_table->gen_timer_index[b];
2572 }
2573
2574 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2575 {
2576 return REG_READ(ah, AR_TSF_L32);
2577 }
2578 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2579
2580 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2581 void (*trigger)(void *),
2582 void (*overflow)(void *),
2583 void *arg,
2584 u8 timer_index)
2585 {
2586 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2587 struct ath_gen_timer *timer;
2588
2589 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2590
2591 if (timer == NULL) {
2592 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2593 "Failed to allocate memory"
2594 "for hw timer[%d]\n", timer_index);
2595 return NULL;
2596 }
2597
2598 /* allocate a hardware generic timer slot */
2599 timer_table->timers[timer_index] = timer;
2600 timer->index = timer_index;
2601 timer->trigger = trigger;
2602 timer->overflow = overflow;
2603 timer->arg = arg;
2604
2605 return timer;
2606 }
2607 EXPORT_SYMBOL(ath_gen_timer_alloc);
2608
2609 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2610 struct ath_gen_timer *timer,
2611 u32 timer_next,
2612 u32 timer_period)
2613 {
2614 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2615 u32 tsf;
2616
2617 BUG_ON(!timer_period);
2618
2619 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2620
2621 tsf = ath9k_hw_gettsf32(ah);
2622
2623 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2624 "curent tsf %x period %x"
2625 "timer_next %x\n", tsf, timer_period, timer_next);
2626
2627 /*
2628 * Pull timer_next forward if the current TSF already passed it
2629 * because of software latency
2630 */
2631 if (timer_next < tsf)
2632 timer_next = tsf + timer_period;
2633
2634 /*
2635 * Program generic timer registers
2636 */
2637 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2638 timer_next);
2639 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2640 timer_period);
2641 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2642 gen_tmr_configuration[timer->index].mode_mask);
2643
2644 /* Enable both trigger and thresh interrupt masks */
2645 REG_SET_BIT(ah, AR_IMR_S5,
2646 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2647 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2648 }
2649 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2650
2651 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2652 {
2653 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2654
2655 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2656 (timer->index >= ATH_MAX_GEN_TIMER)) {
2657 return;
2658 }
2659
2660 /* Clear generic timer enable bits. */
2661 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2662 gen_tmr_configuration[timer->index].mode_mask);
2663
2664 /* Disable both trigger and thresh interrupt masks */
2665 REG_CLR_BIT(ah, AR_IMR_S5,
2666 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2667 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2668
2669 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2670 }
2671 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2672
2673 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2674 {
2675 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2676
2677 /* free the hardware generic timer slot */
2678 timer_table->timers[timer->index] = NULL;
2679 kfree(timer);
2680 }
2681 EXPORT_SYMBOL(ath_gen_timer_free);
2682
2683 /*
2684 * Generic Timer Interrupts handling
2685 */
2686 void ath_gen_timer_isr(struct ath_hw *ah)
2687 {
2688 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2689 struct ath_gen_timer *timer;
2690 struct ath_common *common = ath9k_hw_common(ah);
2691 u32 trigger_mask, thresh_mask, index;
2692
2693 /* get hardware generic timer interrupt status */
2694 trigger_mask = ah->intr_gen_timer_trigger;
2695 thresh_mask = ah->intr_gen_timer_thresh;
2696 trigger_mask &= timer_table->timer_mask.val;
2697 thresh_mask &= timer_table->timer_mask.val;
2698
2699 trigger_mask &= ~thresh_mask;
2700
2701 while (thresh_mask) {
2702 index = rightmost_index(timer_table, &thresh_mask);
2703 timer = timer_table->timers[index];
2704 BUG_ON(!timer);
2705 ath_print(common, ATH_DBG_HWTIMER,
2706 "TSF overflow for Gen timer %d\n", index);
2707 timer->overflow(timer->arg);
2708 }
2709
2710 while (trigger_mask) {
2711 index = rightmost_index(timer_table, &trigger_mask);
2712 timer = timer_table->timers[index];
2713 BUG_ON(!timer);
2714 ath_print(common, ATH_DBG_HWTIMER,
2715 "Gen timer[%d] trigger\n", index);
2716 timer->trigger(timer->arg);
2717 }
2718 }
2719 EXPORT_SYMBOL(ath_gen_timer_isr);
2720
2721 /********/
2722 /* HTC */
2723 /********/
2724
2725 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2726 {
2727 ah->htc_reset_init = true;
2728 }
2729 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2730
2731 static struct {
2732 u32 version;
2733 const char * name;
2734 } ath_mac_bb_names[] = {
2735 /* Devices with external radios */
2736 { AR_SREV_VERSION_5416_PCI, "5416" },
2737 { AR_SREV_VERSION_5416_PCIE, "5418" },
2738 { AR_SREV_VERSION_9100, "9100" },
2739 { AR_SREV_VERSION_9160, "9160" },
2740 /* Single-chip solutions */
2741 { AR_SREV_VERSION_9280, "9280" },
2742 { AR_SREV_VERSION_9285, "9285" },
2743 { AR_SREV_VERSION_9287, "9287" },
2744 { AR_SREV_VERSION_9271, "9271" },
2745 };
2746
2747 /* For devices with external radios */
2748 static struct {
2749 u16 version;
2750 const char * name;
2751 } ath_rf_names[] = {
2752 { 0, "5133" },
2753 { AR_RAD5133_SREV_MAJOR, "5133" },
2754 { AR_RAD5122_SREV_MAJOR, "5122" },
2755 { AR_RAD2133_SREV_MAJOR, "2133" },
2756 { AR_RAD2122_SREV_MAJOR, "2122" }
2757 };
2758
2759 /*
2760 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2761 */
2762 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2763 {
2764 int i;
2765
2766 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2767 if (ath_mac_bb_names[i].version == mac_bb_version) {
2768 return ath_mac_bb_names[i].name;
2769 }
2770 }
2771
2772 return "????";
2773 }
2774
2775 /*
2776 * Return the RF name. "????" is returned if the RF is unknown.
2777 * Used for devices with external radios.
2778 */
2779 static const char *ath9k_hw_rf_name(u16 rf_version)
2780 {
2781 int i;
2782
2783 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2784 if (ath_rf_names[i].version == rf_version) {
2785 return ath_rf_names[i].name;
2786 }
2787 }
2788
2789 return "????";
2790 }
2791
2792 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2793 {
2794 int used;
2795
2796 /* chipsets >= AR9280 are single-chip */
2797 if (AR_SREV_9280_10_OR_LATER(ah)) {
2798 used = snprintf(hw_name, len,
2799 "Atheros AR%s Rev:%x",
2800 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2801 ah->hw_version.macRev);
2802 }
2803 else {
2804 used = snprintf(hw_name, len,
2805 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2806 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2807 ah->hw_version.macRev,
2808 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2809 AR_RADIO_SREV_MAJOR)),
2810 ah->hw_version.phyRev);
2811 }
2812
2813 hw_name[used] = '\0';
2814 }
2815 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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