2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
23 #include "ar9003_mac.h"
25 #define ATH9K_CLOCK_RATE_CCK 22
26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
29 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
31 MODULE_AUTHOR("Atheros Communications");
32 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
33 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
34 MODULE_LICENSE("Dual BSD/GPL");
36 static int __init
ath9k_init(void)
40 module_init(ath9k_init
);
42 static void __exit
ath9k_exit(void)
46 module_exit(ath9k_exit
);
48 /* Private hardware callbacks */
50 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
52 ath9k_hw_private_ops(ah
)->init_cal_settings(ah
);
55 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
57 ath9k_hw_private_ops(ah
)->init_mode_regs(ah
);
60 static bool ath9k_hw_macversion_supported(struct ath_hw
*ah
)
62 struct ath_hw_private_ops
*priv_ops
= ath9k_hw_private_ops(ah
);
64 return priv_ops
->macversion_supported(ah
->hw_version
.macVersion
);
67 static u32
ath9k_hw_compute_pll_control(struct ath_hw
*ah
,
68 struct ath9k_channel
*chan
)
70 return ath9k_hw_private_ops(ah
)->compute_pll_control(ah
, chan
);
73 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
75 if (!ath9k_hw_private_ops(ah
)->init_mode_gain_regs
)
78 ath9k_hw_private_ops(ah
)->init_mode_gain_regs(ah
);
81 /********************/
82 /* Helper Functions */
83 /********************/
85 static u32
ath9k_hw_mac_clks(struct ath_hw
*ah
, u32 usecs
)
87 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
89 if (!ah
->curchan
) /* should really check for CCK instead */
90 return usecs
*ATH9K_CLOCK_RATE_CCK
;
91 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
92 return usecs
*ATH9K_CLOCK_RATE_2GHZ_OFDM
;
93 return usecs
*ATH9K_CLOCK_RATE_5GHZ_OFDM
;
96 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
98 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
100 if (conf_is_ht40(conf
))
101 return ath9k_hw_mac_clks(ah
, usecs
) * 2;
103 return ath9k_hw_mac_clks(ah
, usecs
);
106 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
110 BUG_ON(timeout
< AH_TIME_QUANTUM
);
112 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
113 if ((REG_READ(ah
, reg
) & mask
) == val
)
116 udelay(AH_TIME_QUANTUM
);
119 ath_print(ath9k_hw_common(ah
), ATH_DBG_ANY
,
120 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
121 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
125 EXPORT_SYMBOL(ath9k_hw_wait
);
127 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
132 for (i
= 0, retval
= 0; i
< n
; i
++) {
133 retval
= (retval
<< 1) | (val
& 1);
139 bool ath9k_get_channel_edges(struct ath_hw
*ah
,
143 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
145 if (flags
& CHANNEL_5GHZ
) {
146 *low
= pCap
->low_5ghz_chan
;
147 *high
= pCap
->high_5ghz_chan
;
150 if ((flags
& CHANNEL_2GHZ
)) {
151 *low
= pCap
->low_2ghz_chan
;
152 *high
= pCap
->high_2ghz_chan
;
158 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
160 u32 frameLen
, u16 rateix
,
163 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
169 case WLAN_RC_PHY_CCK
:
170 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
173 numBits
= frameLen
<< 3;
174 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
176 case WLAN_RC_PHY_OFDM
:
177 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
178 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
179 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
180 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
181 txTime
= OFDM_SIFS_TIME_QUARTER
182 + OFDM_PREAMBLE_TIME_QUARTER
183 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
184 } else if (ah
->curchan
&&
185 IS_CHAN_HALF_RATE(ah
->curchan
)) {
186 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
187 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
188 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
189 txTime
= OFDM_SIFS_TIME_HALF
+
190 OFDM_PREAMBLE_TIME_HALF
191 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
193 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
194 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
195 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
196 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
197 + (numSymbols
* OFDM_SYMBOL_TIME
);
201 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
202 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
209 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
211 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
212 struct ath9k_channel
*chan
,
213 struct chan_centers
*centers
)
217 if (!IS_CHAN_HT40(chan
)) {
218 centers
->ctl_center
= centers
->ext_center
=
219 centers
->synth_center
= chan
->channel
;
223 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
224 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
225 centers
->synth_center
=
226 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
229 centers
->synth_center
=
230 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
234 centers
->ctl_center
=
235 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
236 /* 25 MHz spacing is supported by hw but not on upper layers */
237 centers
->ext_center
=
238 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
245 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
249 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
252 val
= REG_READ(ah
, AR_SREV
);
253 ah
->hw_version
.macVersion
=
254 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
255 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
256 ah
->is_pciexpress
= (val
& AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
258 if (!AR_SREV_9100(ah
))
259 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
261 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
263 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
264 ah
->is_pciexpress
= true;
268 /************************************/
269 /* HW Attach, Detach, Init Routines */
270 /************************************/
272 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
274 if (AR_SREV_9100(ah
))
277 ENABLE_REGWRITE_BUFFER(ah
);
279 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
280 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
281 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
282 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
283 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
284 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
285 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
286 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
287 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
289 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
291 REGWRITE_BUFFER_FLUSH(ah
);
292 DISABLE_REGWRITE_BUFFER(ah
);
295 /* This should work for all families including legacy */
296 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
298 struct ath_common
*common
= ath9k_hw_common(ah
);
299 u32 regAddr
[2] = { AR_STA_ID0
};
301 u32 patternData
[4] = { 0x55555555,
307 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
309 regAddr
[1] = AR_PHY_BASE
+ (8 << 2);
313 for (i
= 0; i
< loop_max
; i
++) {
314 u32 addr
= regAddr
[i
];
317 regHold
[i
] = REG_READ(ah
, addr
);
318 for (j
= 0; j
< 0x100; j
++) {
319 wrData
= (j
<< 16) | j
;
320 REG_WRITE(ah
, addr
, wrData
);
321 rdData
= REG_READ(ah
, addr
);
322 if (rdData
!= wrData
) {
323 ath_print(common
, ATH_DBG_FATAL
,
324 "address test failed "
325 "addr: 0x%08x - wr:0x%08x != "
327 addr
, wrData
, rdData
);
331 for (j
= 0; j
< 4; j
++) {
332 wrData
= patternData
[j
];
333 REG_WRITE(ah
, addr
, wrData
);
334 rdData
= REG_READ(ah
, addr
);
335 if (wrData
!= rdData
) {
336 ath_print(common
, ATH_DBG_FATAL
,
337 "address test failed "
338 "addr: 0x%08x - wr:0x%08x != "
340 addr
, wrData
, rdData
);
344 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
351 static void ath9k_hw_init_config(struct ath_hw
*ah
)
355 ah
->config
.dma_beacon_response_time
= 2;
356 ah
->config
.sw_beacon_response_time
= 10;
357 ah
->config
.additional_swba_backoff
= 0;
358 ah
->config
.ack_6mb
= 0x0;
359 ah
->config
.cwm_ignore_extcca
= 0;
360 ah
->config
.pcie_powersave_enable
= 0;
361 ah
->config
.pcie_clock_req
= 0;
362 ah
->config
.pcie_waen
= 0;
363 ah
->config
.analog_shiftreg
= 1;
364 ah
->config
.ofdm_trig_low
= 200;
365 ah
->config
.ofdm_trig_high
= 500;
366 ah
->config
.cck_trig_high
= 200;
367 ah
->config
.cck_trig_low
= 100;
370 * For now ANI is disabled for AR9003, it is still
373 if (!AR_SREV_9300_20_OR_LATER(ah
))
374 ah
->config
.enable_ani
= 1;
376 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
377 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
378 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
381 if (ah
->hw_version
.devid
!= AR2427_DEVID_PCIE
)
382 ah
->config
.ht_enable
= 1;
384 ah
->config
.ht_enable
= 0;
386 ah
->config
.rx_intr_mitigation
= true;
389 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
390 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
391 * This means we use it for all AR5416 devices, and the few
392 * minor PCI AR9280 devices out there.
394 * Serialization is required because these devices do not handle
395 * well the case of two concurrent reads/writes due to the latency
396 * involved. During one read/write another read/write can be issued
397 * on another CPU while the previous read/write may still be working
398 * on our hardware, if we hit this case the hardware poops in a loop.
399 * We prevent this by serializing reads and writes.
401 * This issue is not present on PCI-Express devices or pre-AR5416
402 * devices (legacy, 802.11abg).
404 if (num_possible_cpus() > 1)
405 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
408 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
410 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
412 regulatory
->country_code
= CTRY_DEFAULT
;
413 regulatory
->power_limit
= MAX_RATE_POWER
;
414 regulatory
->tp_scale
= ATH9K_TP_SCALE_MAX
;
416 ah
->hw_version
.magic
= AR5416_MAGIC
;
417 ah
->hw_version
.subvendorid
= 0;
420 if (!AR_SREV_9100(ah
))
421 ah
->ah_flags
= AH_USE_EEPROM
;
424 ah
->sta_id1_defaults
= AR_STA_ID1_CRPT_MIC_ENABLE
;
425 ah
->beacon_interval
= 100;
426 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
427 ah
->slottime
= (u32
) -1;
428 ah
->globaltxtimeout
= (u32
) -1;
429 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
432 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
434 struct ath_common
*common
= ath9k_hw_common(ah
);
438 u32 EEP_MAC
[] = { EEP_MAC_LSW
, EEP_MAC_MID
, EEP_MAC_MSW
};
441 for (i
= 0; i
< 3; i
++) {
442 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_MAC
[i
]);
444 common
->macaddr
[2 * i
] = eeval
>> 8;
445 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
447 if (sum
== 0 || sum
== 0xffff * 3)
448 return -EADDRNOTAVAIL
;
453 static int ath9k_hw_post_init(struct ath_hw
*ah
)
457 if (!AR_SREV_9271(ah
)) {
458 if (!ath9k_hw_chip_test(ah
))
462 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
463 ecode
= ar9002_hw_rf_claim(ah
);
468 ecode
= ath9k_hw_eeprom_init(ah
);
472 ath_print(ath9k_hw_common(ah
), ATH_DBG_CONFIG
,
473 "Eeprom VER: %d, REV: %d\n",
474 ah
->eep_ops
->get_eeprom_ver(ah
),
475 ah
->eep_ops
->get_eeprom_rev(ah
));
477 ecode
= ath9k_hw_rf_alloc_ext_banks(ah
);
479 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
480 "Failed allocating banks for "
485 if (!AR_SREV_9100(ah
)) {
486 ath9k_hw_ani_setup(ah
);
487 ath9k_hw_ani_init(ah
);
493 static void ath9k_hw_attach_ops(struct ath_hw
*ah
)
495 if (AR_SREV_9300_20_OR_LATER(ah
))
496 ar9003_hw_attach_ops(ah
);
498 ar9002_hw_attach_ops(ah
);
501 /* Called for all hardware families */
502 static int __ath9k_hw_init(struct ath_hw
*ah
)
504 struct ath_common
*common
= ath9k_hw_common(ah
);
507 if (ah
->hw_version
.devid
== AR5416_AR9100_DEVID
)
508 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
510 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
511 ath_print(common
, ATH_DBG_FATAL
,
512 "Couldn't reset chip\n");
516 ath9k_hw_init_defaults(ah
);
517 ath9k_hw_init_config(ah
);
519 ath9k_hw_attach_ops(ah
);
521 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
522 ath_print(common
, ATH_DBG_FATAL
, "Couldn't wakeup chip\n");
526 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
527 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
528 (AR_SREV_9280(ah
) && !ah
->is_pciexpress
)) {
529 ah
->config
.serialize_regmode
=
532 ah
->config
.serialize_regmode
=
537 ath_print(common
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
538 ah
->config
.serialize_regmode
);
540 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
541 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
543 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
545 if (!ath9k_hw_macversion_supported(ah
)) {
546 ath_print(common
, ATH_DBG_FATAL
,
547 "Mac Chip Rev 0x%02x.%x is not supported by "
548 "this driver\n", ah
->hw_version
.macVersion
,
549 ah
->hw_version
.macRev
);
553 if (AR_SREV_9271(ah
) || AR_SREV_9100(ah
))
554 ah
->is_pciexpress
= false;
556 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
557 ath9k_hw_init_cal_settings(ah
);
559 ah
->ani_function
= ATH9K_ANI_ALL
;
560 if (AR_SREV_9280_10_OR_LATER(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
561 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
563 ath9k_hw_init_mode_regs(ah
);
565 if (ah
->is_pciexpress
)
566 ath9k_hw_configpcipowersave(ah
, 0, 0);
568 ath9k_hw_disablepcie(ah
);
570 if (!AR_SREV_9300_20_OR_LATER(ah
))
571 ar9002_hw_cck_chan14_spread(ah
);
573 r
= ath9k_hw_post_init(ah
);
577 ath9k_hw_init_mode_gain_regs(ah
);
578 r
= ath9k_hw_fill_cap_info(ah
);
582 r
= ath9k_hw_init_macaddr(ah
);
584 ath_print(common
, ATH_DBG_FATAL
,
585 "Failed to initialize MAC address\n");
589 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
590 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
592 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
594 if (AR_SREV_9300_20_OR_LATER(ah
))
595 ar9003_hw_set_nf_limits(ah
);
597 ath9k_init_nfcal_hist_buffer(ah
);
599 common
->state
= ATH_HW_INITIALIZED
;
604 int ath9k_hw_init(struct ath_hw
*ah
)
607 struct ath_common
*common
= ath9k_hw_common(ah
);
609 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
610 switch (ah
->hw_version
.devid
) {
611 case AR5416_DEVID_PCI
:
612 case AR5416_DEVID_PCIE
:
613 case AR5416_AR9100_DEVID
:
614 case AR9160_DEVID_PCI
:
615 case AR9280_DEVID_PCI
:
616 case AR9280_DEVID_PCIE
:
617 case AR9285_DEVID_PCIE
:
618 case AR9287_DEVID_PCI
:
619 case AR9287_DEVID_PCIE
:
620 case AR2427_DEVID_PCIE
:
621 case AR9300_DEVID_PCIE
:
624 if (common
->bus_ops
->ath_bus_type
== ATH_USB
)
626 ath_print(common
, ATH_DBG_FATAL
,
627 "Hardware device ID 0x%04x not supported\n",
628 ah
->hw_version
.devid
);
632 ret
= __ath9k_hw_init(ah
);
634 ath_print(common
, ATH_DBG_FATAL
,
635 "Unable to initialize hardware; "
636 "initialization status: %d\n", ret
);
642 EXPORT_SYMBOL(ath9k_hw_init
);
644 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
646 ENABLE_REGWRITE_BUFFER(ah
);
648 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
649 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
651 REG_WRITE(ah
, AR_QOS_NO_ACK
,
652 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
653 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
654 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
656 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
657 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
658 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
659 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
660 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
662 REGWRITE_BUFFER_FLUSH(ah
);
663 DISABLE_REGWRITE_BUFFER(ah
);
666 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
667 struct ath9k_channel
*chan
)
669 u32 pll
= ath9k_hw_compute_pll_control(ah
, chan
);
671 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
673 /* Switch the core clock for ar9271 to 117Mhz */
674 if (AR_SREV_9271(ah
)) {
676 REG_WRITE(ah
, 0x50040, 0x304);
679 udelay(RTC_PLL_SETTLE_DELAY
);
681 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
684 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
685 enum nl80211_iftype opmode
)
687 u32 imr_reg
= AR_IMR_TXERR
|
693 if (AR_SREV_9300_20_OR_LATER(ah
)) {
694 imr_reg
|= AR_IMR_RXOK_HP
;
695 if (ah
->config
.rx_intr_mitigation
)
696 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
698 imr_reg
|= AR_IMR_RXOK_LP
;
701 if (ah
->config
.rx_intr_mitigation
)
702 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
704 imr_reg
|= AR_IMR_RXOK
;
707 if (ah
->config
.tx_intr_mitigation
)
708 imr_reg
|= AR_IMR_TXINTM
| AR_IMR_TXMINTR
;
710 imr_reg
|= AR_IMR_TXOK
;
712 if (opmode
== NL80211_IFTYPE_AP
)
713 imr_reg
|= AR_IMR_MIB
;
715 ENABLE_REGWRITE_BUFFER(ah
);
717 REG_WRITE(ah
, AR_IMR
, imr_reg
);
718 ah
->imrs2_reg
|= AR_IMR_S2_GTT
;
719 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
721 if (!AR_SREV_9100(ah
)) {
722 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
723 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, AR_INTR_SYNC_DEFAULT
);
724 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
727 REGWRITE_BUFFER_FLUSH(ah
);
728 DISABLE_REGWRITE_BUFFER(ah
);
730 if (AR_SREV_9300_20_OR_LATER(ah
)) {
731 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_ENABLE
, 0);
732 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_MASK
, 0);
733 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_ENABLE
, 0);
734 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_MASK
, 0);
738 static void ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
740 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
741 val
= min(val
, (u32
) 0xFFFF);
742 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, val
);
745 static void ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
747 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
748 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_ACK
));
749 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK
, val
);
752 static void ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
754 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
755 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_CTS
));
756 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_CTS
, val
);
759 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
762 ath_print(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
763 "bad global tx timeout %u\n", tu
);
764 ah
->globaltxtimeout
= (u32
) -1;
767 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
768 ah
->globaltxtimeout
= tu
;
773 void ath9k_hw_init_global_settings(struct ath_hw
*ah
)
775 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
780 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
783 if (ah
->misc_mode
!= 0)
784 REG_WRITE(ah
, AR_PCU_MISC
,
785 REG_READ(ah
, AR_PCU_MISC
) | ah
->misc_mode
);
787 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_5GHZ
)
792 /* As defined by IEEE 802.11-2007 17.3.8.6 */
793 slottime
= ah
->slottime
+ 3 * ah
->coverage_class
;
794 acktimeout
= slottime
+ sifstime
;
797 * Workaround for early ACK timeouts, add an offset to match the
798 * initval's 64us ack timeout value.
799 * This was initially only meant to work around an issue with delayed
800 * BA frames in some implementations, but it has been found to fix ACK
801 * timeout issues in other cases as well.
803 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
804 acktimeout
+= 64 - sifstime
- ah
->slottime
;
806 ath9k_hw_setslottime(ah
, slottime
);
807 ath9k_hw_set_ack_timeout(ah
, acktimeout
);
808 ath9k_hw_set_cts_timeout(ah
, acktimeout
);
809 if (ah
->globaltxtimeout
!= (u32
) -1)
810 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
812 EXPORT_SYMBOL(ath9k_hw_init_global_settings
);
814 void ath9k_hw_deinit(struct ath_hw
*ah
)
816 struct ath_common
*common
= ath9k_hw_common(ah
);
818 if (common
->state
< ATH_HW_INITIALIZED
)
821 if (!AR_SREV_9100(ah
))
822 ath9k_hw_ani_disable(ah
);
824 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
827 ath9k_hw_rf_free_ext_banks(ah
);
829 EXPORT_SYMBOL(ath9k_hw_deinit
);
835 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
)
837 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
841 else if (IS_CHAN_G(chan
))
849 /****************************************/
850 /* Reset and Channel Switching Routines */
851 /****************************************/
853 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
855 struct ath_common
*common
= ath9k_hw_common(ah
);
858 ENABLE_REGWRITE_BUFFER(ah
);
861 * set AHB_MODE not to do cacheline prefetches
863 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
864 regval
= REG_READ(ah
, AR_AHB_MODE
);
865 REG_WRITE(ah
, AR_AHB_MODE
, regval
| AR_AHB_PREFETCH_RD_EN
);
869 * let mac dma reads be in 128 byte chunks
871 regval
= REG_READ(ah
, AR_TXCFG
) & ~AR_TXCFG_DMASZ_MASK
;
872 REG_WRITE(ah
, AR_TXCFG
, regval
| AR_TXCFG_DMASZ_128B
);
874 REGWRITE_BUFFER_FLUSH(ah
);
875 DISABLE_REGWRITE_BUFFER(ah
);
878 * Restore TX Trigger Level to its pre-reset value.
879 * The initial value depends on whether aggregation is enabled, and is
880 * adjusted whenever underruns are detected.
882 if (!AR_SREV_9300_20_OR_LATER(ah
))
883 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
885 ENABLE_REGWRITE_BUFFER(ah
);
888 * let mac dma writes be in 128 byte chunks
890 regval
= REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_DMASZ_MASK
;
891 REG_WRITE(ah
, AR_RXCFG
, regval
| AR_RXCFG_DMASZ_128B
);
894 * Setup receive FIFO threshold to hold off TX activities
896 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
898 if (AR_SREV_9300_20_OR_LATER(ah
)) {
899 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_HP
, 0x1);
900 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_LP
, 0x1);
902 ath9k_hw_set_rx_bufsize(ah
, common
->rx_bufsize
-
903 ah
->caps
.rx_status_len
);
907 * reduce the number of usable entries in PCU TXBUF to avoid
908 * wrap around issues.
910 if (AR_SREV_9285(ah
)) {
911 /* For AR9285 the number of Fifos are reduced to half.
912 * So set the usable tx buf size also to half to
913 * avoid data/delimiter underruns
915 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
916 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
917 } else if (!AR_SREV_9271(ah
)) {
918 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
919 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
922 REGWRITE_BUFFER_FLUSH(ah
);
923 DISABLE_REGWRITE_BUFFER(ah
);
925 if (AR_SREV_9300_20_OR_LATER(ah
))
926 ath9k_hw_reset_txstatus_ring(ah
);
929 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
933 val
= REG_READ(ah
, AR_STA_ID1
);
934 val
&= ~(AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
);
936 case NL80211_IFTYPE_AP
:
937 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_STA_AP
938 | AR_STA_ID1_KSRCH_MODE
);
939 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
941 case NL80211_IFTYPE_ADHOC
:
942 case NL80211_IFTYPE_MESH_POINT
:
943 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_ADHOC
944 | AR_STA_ID1_KSRCH_MODE
);
945 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
947 case NL80211_IFTYPE_STATION
:
948 case NL80211_IFTYPE_MONITOR
:
949 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
954 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
955 u32
*coef_mantissa
, u32
*coef_exponent
)
957 u32 coef_exp
, coef_man
;
959 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
960 if ((coef_scaled
>> coef_exp
) & 0x1)
963 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
965 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
967 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
968 *coef_exponent
= coef_exp
- 16;
971 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
976 if (AR_SREV_9100(ah
)) {
977 u32 val
= REG_READ(ah
, AR_RTC_DERIVED_CLK
);
978 val
&= ~AR_RTC_DERIVED_CLK_PERIOD
;
979 val
|= SM(1, AR_RTC_DERIVED_CLK_PERIOD
);
980 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, val
);
981 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
984 ENABLE_REGWRITE_BUFFER(ah
);
986 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
987 AR_RTC_FORCE_WAKE_ON_INT
);
989 if (AR_SREV_9100(ah
)) {
990 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
991 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
993 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
995 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
996 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
998 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1001 if (!AR_SREV_9300_20_OR_LATER(ah
))
1003 REG_WRITE(ah
, AR_RC
, val
);
1005 } else if (!AR_SREV_9300_20_OR_LATER(ah
))
1006 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1008 rst_flags
= AR_RTC_RC_MAC_WARM
;
1009 if (type
== ATH9K_RESET_COLD
)
1010 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1013 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1015 REGWRITE_BUFFER_FLUSH(ah
);
1016 DISABLE_REGWRITE_BUFFER(ah
);
1020 REG_WRITE(ah
, AR_RTC_RC
, 0);
1021 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1022 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1023 "RTC stuck in MAC reset\n");
1027 if (!AR_SREV_9100(ah
))
1028 REG_WRITE(ah
, AR_RC
, 0);
1030 if (AR_SREV_9100(ah
))
1036 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1038 ENABLE_REGWRITE_BUFFER(ah
);
1040 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1041 AR_RTC_FORCE_WAKE_ON_INT
);
1043 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1044 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1046 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1048 REGWRITE_BUFFER_FLUSH(ah
);
1049 DISABLE_REGWRITE_BUFFER(ah
);
1051 if (!AR_SREV_9300_20_OR_LATER(ah
))
1054 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1055 REG_WRITE(ah
, AR_RC
, 0);
1057 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1059 if (!ath9k_hw_wait(ah
,
1064 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1065 "RTC not waking up\n");
1069 ath9k_hw_read_revisions(ah
);
1071 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1074 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1076 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1077 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1080 case ATH9K_RESET_POWER_ON
:
1081 return ath9k_hw_set_reset_power_on(ah
);
1082 case ATH9K_RESET_WARM
:
1083 case ATH9K_RESET_COLD
:
1084 return ath9k_hw_set_reset(ah
, type
);
1090 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1091 struct ath9k_channel
*chan
)
1093 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
1094 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1096 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1099 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1102 ah
->chip_fullsleep
= false;
1103 ath9k_hw_init_pll(ah
, chan
);
1104 ath9k_hw_set_rfmode(ah
, chan
);
1109 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1110 struct ath9k_channel
*chan
)
1112 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1113 struct ath_common
*common
= ath9k_hw_common(ah
);
1114 struct ieee80211_channel
*channel
= chan
->chan
;
1118 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1119 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1120 ath_print(common
, ATH_DBG_QUEUE
,
1121 "Transmit frames pending on "
1122 "queue %d\n", qnum
);
1127 if (!ath9k_hw_rfbus_req(ah
)) {
1128 ath_print(common
, ATH_DBG_FATAL
,
1129 "Could not kill baseband RX\n");
1133 ath9k_hw_set_channel_regs(ah
, chan
);
1135 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1137 ath_print(common
, ATH_DBG_FATAL
,
1138 "Failed to set channel\n");
1142 ah
->eep_ops
->set_txpower(ah
, chan
,
1143 ath9k_regd_get_ctl(regulatory
, chan
),
1144 channel
->max_antenna_gain
* 2,
1145 channel
->max_power
* 2,
1146 min((u32
) MAX_RATE_POWER
,
1147 (u32
) regulatory
->power_limit
));
1149 ath9k_hw_rfbus_done(ah
);
1151 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1152 ath9k_hw_set_delta_slope(ah
, chan
);
1154 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1156 if (!chan
->oneTimeCalsDone
)
1157 chan
->oneTimeCalsDone
= true;
1162 bool ath9k_hw_check_alive(struct ath_hw
*ah
)
1167 if (AR_SREV_9285_10_OR_LATER(ah
))
1171 reg
= REG_READ(ah
, AR_OBS_BUS_1
);
1173 if ((reg
& 0x7E7FFFEF) == 0x00702400)
1176 switch (reg
& 0x7E000B00) {
1184 } while (count
-- > 0);
1188 EXPORT_SYMBOL(ath9k_hw_check_alive
);
1190 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1191 bool bChannelChange
)
1193 struct ath_common
*common
= ath9k_hw_common(ah
);
1195 struct ath9k_channel
*curchan
= ah
->curchan
;
1201 ah
->txchainmask
= common
->tx_chainmask
;
1202 ah
->rxchainmask
= common
->rx_chainmask
;
1204 if (!ah
->chip_fullsleep
) {
1205 ath9k_hw_abortpcurecv(ah
);
1206 if (!ath9k_hw_stopdmarecv(ah
))
1207 ath_print(common
, ATH_DBG_XMIT
,
1208 "Failed to stop receive dma\n");
1211 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1214 if (curchan
&& !ah
->chip_fullsleep
)
1215 ath9k_hw_getnf(ah
, curchan
);
1217 if (bChannelChange
&&
1218 (ah
->chip_fullsleep
!= true) &&
1219 (ah
->curchan
!= NULL
) &&
1220 (chan
->channel
!= ah
->curchan
->channel
) &&
1221 ((chan
->channelFlags
& CHANNEL_ALL
) ==
1222 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)) &&
1223 !(AR_SREV_9280(ah
) || IS_CHAN_A_5MHZ_SPACED(chan
) ||
1224 IS_CHAN_A_5MHZ_SPACED(ah
->curchan
))) {
1226 if (ath9k_hw_channel_change(ah
, chan
)) {
1227 ath9k_hw_loadnf(ah
, ah
->curchan
);
1228 ath9k_hw_start_nfcal(ah
);
1233 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1234 if (saveDefAntenna
== 0)
1237 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1239 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1240 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1241 tsf
= ath9k_hw_gettsf64(ah
);
1243 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1244 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1245 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1247 ath9k_hw_mark_phy_inactive(ah
);
1249 /* Only required on the first reset */
1250 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1252 AR9271_RESET_POWER_DOWN_CONTROL
,
1253 AR9271_RADIO_RF_RST
);
1257 if (!ath9k_hw_chip_reset(ah
, chan
)) {
1258 ath_print(common
, ATH_DBG_FATAL
, "Chip reset failed\n");
1262 /* Only required on the first reset */
1263 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1264 ah
->htc_reset_init
= false;
1266 AR9271_RESET_POWER_DOWN_CONTROL
,
1267 AR9271_GATE_MAC_CTL
);
1272 if (tsf
&& AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1273 ath9k_hw_settsf64(ah
, tsf
);
1275 if (AR_SREV_9280_10_OR_LATER(ah
))
1276 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
1278 r
= ath9k_hw_process_ini(ah
, chan
);
1282 /* Setup MFP options for CCMP */
1283 if (AR_SREV_9280_20_OR_LATER(ah
)) {
1284 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1285 * frames when constructing CCMP AAD. */
1286 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
1288 ah
->sw_mgmt_crypto
= false;
1289 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1290 /* Disable hardware crypto for management frames */
1291 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
1292 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
1293 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1294 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
1295 ah
->sw_mgmt_crypto
= true;
1297 ah
->sw_mgmt_crypto
= true;
1299 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1300 ath9k_hw_set_delta_slope(ah
, chan
);
1302 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1303 ah
->eep_ops
->set_board_values(ah
, chan
);
1305 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
1307 ENABLE_REGWRITE_BUFFER(ah
);
1309 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(common
->macaddr
));
1310 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(common
->macaddr
+ 4)
1312 | AR_STA_ID1_RTS_USE_DEF
1314 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
1315 | ah
->sta_id1_defaults
);
1316 ath_hw_setbssidmask(common
);
1317 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
1318 ath9k_hw_write_associd(ah
);
1319 REG_WRITE(ah
, AR_ISR
, ~0);
1320 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
1322 REGWRITE_BUFFER_FLUSH(ah
);
1323 DISABLE_REGWRITE_BUFFER(ah
);
1325 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1329 ENABLE_REGWRITE_BUFFER(ah
);
1331 for (i
= 0; i
< AR_NUM_DCU
; i
++)
1332 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
1334 REGWRITE_BUFFER_FLUSH(ah
);
1335 DISABLE_REGWRITE_BUFFER(ah
);
1338 for (i
= 0; i
< ah
->caps
.total_queues
; i
++)
1339 ath9k_hw_resettxqueue(ah
, i
);
1341 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
1342 ath9k_hw_init_qos(ah
);
1344 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1345 ath9k_enable_rfkill(ah
);
1347 ath9k_hw_init_global_settings(ah
);
1349 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
1350 ar9002_hw_enable_async_fifo(ah
);
1351 ar9002_hw_enable_wep_aggregation(ah
);
1354 REG_WRITE(ah
, AR_STA_ID1
,
1355 REG_READ(ah
, AR_STA_ID1
) | AR_STA_ID1_PRESERVE_SEQNUM
);
1357 ath9k_hw_set_dma(ah
);
1359 REG_WRITE(ah
, AR_OBS
, 8);
1361 if (ah
->config
.rx_intr_mitigation
) {
1362 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
1363 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
1366 if (ah
->config
.tx_intr_mitigation
) {
1367 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_LAST
, 300);
1368 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_FIRST
, 750);
1371 ath9k_hw_init_bb(ah
, chan
);
1373 if (!ath9k_hw_init_cal(ah
, chan
))
1376 ENABLE_REGWRITE_BUFFER(ah
);
1378 ath9k_hw_restore_chainmask(ah
);
1379 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
1381 REGWRITE_BUFFER_FLUSH(ah
);
1382 DISABLE_REGWRITE_BUFFER(ah
);
1385 * For big endian systems turn on swapping for descriptors
1387 if (AR_SREV_9100(ah
)) {
1389 mask
= REG_READ(ah
, AR_CFG
);
1390 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
1391 ath_print(common
, ATH_DBG_RESET
,
1392 "CFG Byte Swap Set 0x%x\n", mask
);
1395 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
1396 REG_WRITE(ah
, AR_CFG
, mask
);
1397 ath_print(common
, ATH_DBG_RESET
,
1398 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
1401 /* Configure AR9271 target WLAN */
1402 if (AR_SREV_9271(ah
))
1403 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
1406 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1410 if (ah
->btcoex_hw
.enabled
)
1411 ath9k_hw_btcoex_enable(ah
);
1413 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1414 ath9k_hw_loadnf(ah
, curchan
);
1415 ath9k_hw_start_nfcal(ah
);
1420 EXPORT_SYMBOL(ath9k_hw_reset
);
1422 /************************/
1423 /* Key Cache Management */
1424 /************************/
1426 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
)
1430 if (entry
>= ah
->caps
.keycache_size
) {
1431 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1432 "keychache entry %u out of range\n", entry
);
1436 keyType
= REG_READ(ah
, AR_KEYTABLE_TYPE(entry
));
1438 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), 0);
1439 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), 0);
1440 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), 0);
1441 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), 0);
1442 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), 0);
1443 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), AR_KEYTABLE_TYPE_CLR
);
1444 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), 0);
1445 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), 0);
1447 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
1448 u16 micentry
= entry
+ 64;
1450 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), 0);
1451 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
1452 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), 0);
1453 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
1459 EXPORT_SYMBOL(ath9k_hw_keyreset
);
1461 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
)
1465 if (entry
>= ah
->caps
.keycache_size
) {
1466 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1467 "keychache entry %u out of range\n", entry
);
1472 macHi
= (mac
[5] << 8) | mac
[4];
1473 macLo
= (mac
[3] << 24) |
1478 macLo
|= (macHi
& 1) << 31;
1483 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), macLo
);
1484 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), macHi
| AR_KEYTABLE_VALID
);
1488 EXPORT_SYMBOL(ath9k_hw_keysetmac
);
1490 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
1491 const struct ath9k_keyval
*k
,
1494 const struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1495 struct ath_common
*common
= ath9k_hw_common(ah
);
1496 u32 key0
, key1
, key2
, key3
, key4
;
1499 if (entry
>= pCap
->keycache_size
) {
1500 ath_print(common
, ATH_DBG_FATAL
,
1501 "keycache entry %u out of range\n", entry
);
1505 switch (k
->kv_type
) {
1506 case ATH9K_CIPHER_AES_OCB
:
1507 keyType
= AR_KEYTABLE_TYPE_AES
;
1509 case ATH9K_CIPHER_AES_CCM
:
1510 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_CIPHER_AESCCM
)) {
1511 ath_print(common
, ATH_DBG_ANY
,
1512 "AES-CCM not supported by mac rev 0x%x\n",
1513 ah
->hw_version
.macRev
);
1516 keyType
= AR_KEYTABLE_TYPE_CCM
;
1518 case ATH9K_CIPHER_TKIP
:
1519 keyType
= AR_KEYTABLE_TYPE_TKIP
;
1520 if (ATH9K_IS_MIC_ENABLED(ah
)
1521 && entry
+ 64 >= pCap
->keycache_size
) {
1522 ath_print(common
, ATH_DBG_ANY
,
1523 "entry %u inappropriate for TKIP\n", entry
);
1527 case ATH9K_CIPHER_WEP
:
1528 if (k
->kv_len
< WLAN_KEY_LEN_WEP40
) {
1529 ath_print(common
, ATH_DBG_ANY
,
1530 "WEP key length %u too small\n", k
->kv_len
);
1533 if (k
->kv_len
<= WLAN_KEY_LEN_WEP40
)
1534 keyType
= AR_KEYTABLE_TYPE_40
;
1535 else if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
1536 keyType
= AR_KEYTABLE_TYPE_104
;
1538 keyType
= AR_KEYTABLE_TYPE_128
;
1540 case ATH9K_CIPHER_CLR
:
1541 keyType
= AR_KEYTABLE_TYPE_CLR
;
1544 ath_print(common
, ATH_DBG_FATAL
,
1545 "cipher %u not supported\n", k
->kv_type
);
1549 key0
= get_unaligned_le32(k
->kv_val
+ 0);
1550 key1
= get_unaligned_le16(k
->kv_val
+ 4);
1551 key2
= get_unaligned_le32(k
->kv_val
+ 6);
1552 key3
= get_unaligned_le16(k
->kv_val
+ 10);
1553 key4
= get_unaligned_le32(k
->kv_val
+ 12);
1554 if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
1558 * Note: Key cache registers access special memory area that requires
1559 * two 32-bit writes to actually update the values in the internal
1560 * memory. Consequently, the exact order and pairs used here must be
1564 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
1565 u16 micentry
= entry
+ 64;
1568 * Write inverted key[47:0] first to avoid Michael MIC errors
1569 * on frames that could be sent or received at the same time.
1570 * The correct key will be written in the end once everything
1573 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), ~key0
);
1574 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), ~key1
);
1576 /* Write key[95:48] */
1577 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
1578 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
1580 /* Write key[127:96] and key type */
1581 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
1582 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
1584 /* Write MAC address for the entry */
1585 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
1587 if (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) {
1589 * TKIP uses two key cache entries:
1590 * Michael MIC TX/RX keys in the same key cache entry
1591 * (idx = main index + 64):
1592 * key0 [31:0] = RX key [31:0]
1593 * key1 [15:0] = TX key [31:16]
1594 * key1 [31:16] = reserved
1595 * key2 [31:0] = RX key [63:32]
1596 * key3 [15:0] = TX key [15:0]
1597 * key3 [31:16] = reserved
1598 * key4 [31:0] = TX key [63:32]
1600 u32 mic0
, mic1
, mic2
, mic3
, mic4
;
1602 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
1603 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
1604 mic1
= get_unaligned_le16(k
->kv_txmic
+ 2) & 0xffff;
1605 mic3
= get_unaligned_le16(k
->kv_txmic
+ 0) & 0xffff;
1606 mic4
= get_unaligned_le32(k
->kv_txmic
+ 4);
1608 /* Write RX[31:0] and TX[31:16] */
1609 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
1610 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), mic1
);
1612 /* Write RX[63:32] and TX[15:0] */
1613 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
1614 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), mic3
);
1616 /* Write TX[63:32] and keyType(reserved) */
1617 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), mic4
);
1618 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
1619 AR_KEYTABLE_TYPE_CLR
);
1623 * TKIP uses four key cache entries (two for group
1625 * Michael MIC TX/RX keys are in different key cache
1626 * entries (idx = main index + 64 for TX and
1627 * main index + 32 + 96 for RX):
1628 * key0 [31:0] = TX/RX MIC key [31:0]
1629 * key1 [31:0] = reserved
1630 * key2 [31:0] = TX/RX MIC key [63:32]
1631 * key3 [31:0] = reserved
1632 * key4 [31:0] = reserved
1634 * Upper layer code will call this function separately
1635 * for TX and RX keys when these registers offsets are
1640 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
1641 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
1643 /* Write MIC key[31:0] */
1644 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
1645 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
1647 /* Write MIC key[63:32] */
1648 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
1649 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
1651 /* Write TX[63:32] and keyType(reserved) */
1652 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), 0);
1653 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
1654 AR_KEYTABLE_TYPE_CLR
);
1657 /* MAC address registers are reserved for the MIC entry */
1658 REG_WRITE(ah
, AR_KEYTABLE_MAC0(micentry
), 0);
1659 REG_WRITE(ah
, AR_KEYTABLE_MAC1(micentry
), 0);
1662 * Write the correct (un-inverted) key[47:0] last to enable
1663 * TKIP now that all other registers are set with correct
1666 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
1667 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
1669 /* Write key[47:0] */
1670 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
1671 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
1673 /* Write key[95:48] */
1674 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
1675 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
1677 /* Write key[127:96] and key type */
1678 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
1679 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
1681 /* Write MAC address for the entry */
1682 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
1687 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry
);
1689 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
)
1691 if (entry
< ah
->caps
.keycache_size
) {
1692 u32 val
= REG_READ(ah
, AR_KEYTABLE_MAC1(entry
));
1693 if (val
& AR_KEYTABLE_VALID
)
1698 EXPORT_SYMBOL(ath9k_hw_keyisvalid
);
1700 /******************************/
1701 /* Power Management (Chipset) */
1702 /******************************/
1705 * Notify Power Mgt is disabled in self-generated frames.
1706 * If requested, force chip to sleep.
1708 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
1710 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1713 * Clear the RTC force wake bit to allow the
1714 * mac to go to sleep.
1716 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
1717 AR_RTC_FORCE_WAKE_EN
);
1718 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1719 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1721 /* Shutdown chip. Active low */
1722 if (!AR_SREV_5416(ah
) && !AR_SREV_9271(ah
))
1723 REG_CLR_BIT(ah
, (AR_RTC_RESET
),
1729 * Notify Power Management is enabled in self-generating
1730 * frames. If request, set power mode of chip to
1731 * auto/normal. Duration in units of 128us (1/8 TU).
1733 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
1735 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1737 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1739 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
1740 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1741 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1742 AR_RTC_FORCE_WAKE_ON_INT
);
1745 * Clear the RTC force wake bit to allow the
1746 * mac to go to sleep.
1748 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
1749 AR_RTC_FORCE_WAKE_EN
);
1754 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
1760 if ((REG_READ(ah
, AR_RTC_STATUS
) &
1761 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
1762 if (ath9k_hw_set_reset_reg(ah
,
1763 ATH9K_RESET_POWER_ON
) != true) {
1766 if (!AR_SREV_9300_20_OR_LATER(ah
))
1767 ath9k_hw_init_pll(ah
, NULL
);
1769 if (AR_SREV_9100(ah
))
1770 REG_SET_BIT(ah
, AR_RTC_RESET
,
1773 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
1774 AR_RTC_FORCE_WAKE_EN
);
1777 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
1778 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
1779 if (val
== AR_RTC_STATUS_ON
)
1782 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
1783 AR_RTC_FORCE_WAKE_EN
);
1786 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1787 "Failed to wakeup in %uus\n",
1788 POWER_UP_TIME
/ 20);
1793 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1798 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
1800 struct ath_common
*common
= ath9k_hw_common(ah
);
1801 int status
= true, setChip
= true;
1802 static const char *modes
[] = {
1809 if (ah
->power_mode
== mode
)
1812 ath_print(common
, ATH_DBG_RESET
, "%s -> %s\n",
1813 modes
[ah
->power_mode
], modes
[mode
]);
1816 case ATH9K_PM_AWAKE
:
1817 status
= ath9k_hw_set_power_awake(ah
, setChip
);
1819 case ATH9K_PM_FULL_SLEEP
:
1820 ath9k_set_power_sleep(ah
, setChip
);
1821 ah
->chip_fullsleep
= true;
1823 case ATH9K_PM_NETWORK_SLEEP
:
1824 ath9k_set_power_network_sleep(ah
, setChip
);
1827 ath_print(common
, ATH_DBG_FATAL
,
1828 "Unknown power mode %u\n", mode
);
1831 ah
->power_mode
= mode
;
1835 EXPORT_SYMBOL(ath9k_hw_setpower
);
1837 /*******************/
1838 /* Beacon Handling */
1839 /*******************/
1841 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
1845 ah
->beacon_interval
= beacon_period
;
1847 ENABLE_REGWRITE_BUFFER(ah
);
1849 switch (ah
->opmode
) {
1850 case NL80211_IFTYPE_STATION
:
1851 case NL80211_IFTYPE_MONITOR
:
1852 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
1853 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
1854 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
1855 flags
|= AR_TBTT_TIMER_EN
;
1857 case NL80211_IFTYPE_ADHOC
:
1858 case NL80211_IFTYPE_MESH_POINT
:
1859 REG_SET_BIT(ah
, AR_TXCFG
,
1860 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
1861 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
,
1862 TU_TO_USEC(next_beacon
+
1863 (ah
->atim_window
? ah
->
1865 flags
|= AR_NDP_TIMER_EN
;
1866 case NL80211_IFTYPE_AP
:
1867 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
1868 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
,
1869 TU_TO_USEC(next_beacon
-
1871 dma_beacon_response_time
));
1872 REG_WRITE(ah
, AR_NEXT_SWBA
,
1873 TU_TO_USEC(next_beacon
-
1875 sw_beacon_response_time
));
1877 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
1880 ath_print(ath9k_hw_common(ah
), ATH_DBG_BEACON
,
1881 "%s: unsupported opmode: %d\n",
1882 __func__
, ah
->opmode
);
1887 REG_WRITE(ah
, AR_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
1888 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
1889 REG_WRITE(ah
, AR_SWBA_PERIOD
, TU_TO_USEC(beacon_period
));
1890 REG_WRITE(ah
, AR_NDP_PERIOD
, TU_TO_USEC(beacon_period
));
1892 REGWRITE_BUFFER_FLUSH(ah
);
1893 DISABLE_REGWRITE_BUFFER(ah
);
1895 beacon_period
&= ~ATH9K_BEACON_ENA
;
1896 if (beacon_period
& ATH9K_BEACON_RESET_TSF
) {
1897 ath9k_hw_reset_tsf(ah
);
1900 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
1902 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
1904 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
1905 const struct ath9k_beacon_state
*bs
)
1907 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
1908 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1909 struct ath_common
*common
= ath9k_hw_common(ah
);
1911 ENABLE_REGWRITE_BUFFER(ah
);
1913 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
1915 REG_WRITE(ah
, AR_BEACON_PERIOD
,
1916 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
1917 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
1918 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
1920 REGWRITE_BUFFER_FLUSH(ah
);
1921 DISABLE_REGWRITE_BUFFER(ah
);
1923 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
1924 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
1926 beaconintval
= bs
->bs_intval
& ATH9K_BEACON_PERIOD
;
1928 if (bs
->bs_sleepduration
> beaconintval
)
1929 beaconintval
= bs
->bs_sleepduration
;
1931 dtimperiod
= bs
->bs_dtimperiod
;
1932 if (bs
->bs_sleepduration
> dtimperiod
)
1933 dtimperiod
= bs
->bs_sleepduration
;
1935 if (beaconintval
== dtimperiod
)
1936 nextTbtt
= bs
->bs_nextdtim
;
1938 nextTbtt
= bs
->bs_nexttbtt
;
1940 ath_print(common
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
1941 ath_print(common
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
1942 ath_print(common
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
1943 ath_print(common
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
1945 ENABLE_REGWRITE_BUFFER(ah
);
1947 REG_WRITE(ah
, AR_NEXT_DTIM
,
1948 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
1949 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
1951 REG_WRITE(ah
, AR_SLEEP1
,
1952 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
1953 | AR_SLEEP1_ASSUME_DTIM
);
1955 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
1956 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
1958 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
1960 REG_WRITE(ah
, AR_SLEEP2
,
1961 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
1963 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
1964 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
1966 REGWRITE_BUFFER_FLUSH(ah
);
1967 DISABLE_REGWRITE_BUFFER(ah
);
1969 REG_SET_BIT(ah
, AR_TIMER_MODE
,
1970 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
1973 /* TSF Out of Range Threshold */
1974 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
1976 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
1978 /*******************/
1979 /* HW Capabilities */
1980 /*******************/
1982 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
1984 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1985 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1986 struct ath_common
*common
= ath9k_hw_common(ah
);
1987 struct ath_btcoex_hw
*btcoex_hw
= &ah
->btcoex_hw
;
1989 u16 capField
= 0, eeval
;
1991 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
1992 regulatory
->current_rd
= eeval
;
1994 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_1
);
1995 if (AR_SREV_9285_10_OR_LATER(ah
))
1996 eeval
|= AR9285_RDEXT_DEFAULT
;
1997 regulatory
->current_rd_ext
= eeval
;
1999 capField
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_CAP
);
2001 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
2002 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
2003 if (regulatory
->current_rd
== 0x64 ||
2004 regulatory
->current_rd
== 0x65)
2005 regulatory
->current_rd
+= 5;
2006 else if (regulatory
->current_rd
== 0x41)
2007 regulatory
->current_rd
= 0x43;
2008 ath_print(common
, ATH_DBG_REGULATORY
,
2009 "regdomain mapped to 0x%x\n", regulatory
->current_rd
);
2012 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
2013 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
2014 ath_print(common
, ATH_DBG_FATAL
,
2015 "no band has been marked as supported in EEPROM.\n");
2019 bitmap_zero(pCap
->wireless_modes
, ATH9K_MODE_MAX
);
2021 if (eeval
& AR5416_OPFLAGS_11A
) {
2022 set_bit(ATH9K_MODE_11A
, pCap
->wireless_modes
);
2023 if (ah
->config
.ht_enable
) {
2024 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT20
))
2025 set_bit(ATH9K_MODE_11NA_HT20
,
2026 pCap
->wireless_modes
);
2027 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT40
)) {
2028 set_bit(ATH9K_MODE_11NA_HT40PLUS
,
2029 pCap
->wireless_modes
);
2030 set_bit(ATH9K_MODE_11NA_HT40MINUS
,
2031 pCap
->wireless_modes
);
2036 if (eeval
& AR5416_OPFLAGS_11G
) {
2037 set_bit(ATH9K_MODE_11G
, pCap
->wireless_modes
);
2038 if (ah
->config
.ht_enable
) {
2039 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT20
))
2040 set_bit(ATH9K_MODE_11NG_HT20
,
2041 pCap
->wireless_modes
);
2042 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT40
)) {
2043 set_bit(ATH9K_MODE_11NG_HT40PLUS
,
2044 pCap
->wireless_modes
);
2045 set_bit(ATH9K_MODE_11NG_HT40MINUS
,
2046 pCap
->wireless_modes
);
2051 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
2053 * For AR9271 we will temporarilly uses the rx chainmax as read from
2056 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
2057 !(eeval
& AR5416_OPFLAGS_11A
) &&
2058 !(AR_SREV_9271(ah
)))
2059 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2060 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
2062 /* Use rx_chainmask from EEPROM. */
2063 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
2065 if (!(AR_SREV_9280(ah
) && (ah
->hw_version
.macRev
== 0)))
2066 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
2068 pCap
->low_2ghz_chan
= 2312;
2069 pCap
->high_2ghz_chan
= 2732;
2071 pCap
->low_5ghz_chan
= 4920;
2072 pCap
->high_5ghz_chan
= 6100;
2074 pCap
->hw_caps
&= ~ATH9K_HW_CAP_CIPHER_CKIP
;
2075 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_TKIP
;
2076 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_AESCCM
;
2078 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MIC_CKIP
;
2079 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_TKIP
;
2080 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_AESCCM
;
2082 if (ah
->config
.ht_enable
)
2083 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
2085 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
2087 pCap
->hw_caps
|= ATH9K_HW_CAP_GTT
;
2088 pCap
->hw_caps
|= ATH9K_HW_CAP_VEOL
;
2089 pCap
->hw_caps
|= ATH9K_HW_CAP_BSSIDMASK
;
2090 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MCAST_KEYSEARCH
;
2092 if (capField
& AR_EEPROM_EEPCAP_MAXQCU
)
2093 pCap
->total_queues
=
2094 MS(capField
, AR_EEPROM_EEPCAP_MAXQCU
);
2096 pCap
->total_queues
= ATH9K_NUM_TX_QUEUES
;
2098 if (capField
& AR_EEPROM_EEPCAP_KC_ENTRIES
)
2099 pCap
->keycache_size
=
2100 1 << MS(capField
, AR_EEPROM_EEPCAP_KC_ENTRIES
);
2102 pCap
->keycache_size
= AR_KEYTABLE_SIZE
;
2104 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCC
;
2106 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
2107 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
>> 1;
2109 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
;
2111 if (AR_SREV_9271(ah
))
2112 pCap
->num_gpio_pins
= AR9271_NUM_GPIO
;
2113 else if (AR_SREV_9285_10_OR_LATER(ah
))
2114 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
2115 else if (AR_SREV_9280_10_OR_LATER(ah
))
2116 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
2118 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
2120 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
2121 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
2122 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
2124 pCap
->rts_aggr_limit
= (8 * 1024);
2127 pCap
->hw_caps
|= ATH9K_HW_CAP_ENHANCEDPM
;
2129 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2130 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
2131 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
2133 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
2134 ah
->rfkill_polarity
=
2135 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
2137 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
2140 if (AR_SREV_9271(ah
))
2141 pCap
->hw_caps
|= ATH9K_HW_CAP_AUTOSLEEP
;
2143 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
2145 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
2146 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
2148 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
2150 if (regulatory
->current_rd_ext
& (1 << REG_EXT_JAPAN_MIDBAND
)) {
2152 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
2153 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
|
2154 AR_EEPROM_EEREGCAP_EN_KK_U2
|
2155 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
;
2158 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
2159 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
;
2162 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2163 if (regulatory
->current_rd_ext
& (1 << REG_EXT_FCC_MIDBAND
) &&
2165 pCap
->reg_cap
|= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
;
2167 pCap
->num_antcfg_5ghz
=
2168 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_5GHZ
);
2169 pCap
->num_antcfg_2ghz
=
2170 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_2GHZ
);
2172 if (AR_SREV_9280_10_OR_LATER(ah
) &&
2173 ath9k_hw_btcoex_supported(ah
)) {
2174 btcoex_hw
->btactive_gpio
= ATH_BTACTIVE_GPIO
;
2175 btcoex_hw
->wlanactive_gpio
= ATH_WLANACTIVE_GPIO
;
2177 if (AR_SREV_9285(ah
)) {
2178 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_3WIRE
;
2179 btcoex_hw
->btpriority_gpio
= ATH_BTPRIORITY_GPIO
;
2181 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_2WIRE
;
2184 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_NONE
;
2187 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2188 pCap
->hw_caps
|= ATH9K_HW_CAP_EDMA
| ATH9K_HW_CAP_LDPC
;
2189 pCap
->rx_hp_qdepth
= ATH9K_HW_RX_HP_QDEPTH
;
2190 pCap
->rx_lp_qdepth
= ATH9K_HW_RX_LP_QDEPTH
;
2191 pCap
->rx_status_len
= sizeof(struct ar9003_rxs
);
2192 pCap
->tx_desc_len
= sizeof(struct ar9003_txc
);
2193 pCap
->txs_len
= sizeof(struct ar9003_txs
);
2195 pCap
->tx_desc_len
= sizeof(struct ath_desc
);
2198 if (AR_SREV_9300_20_OR_LATER(ah
))
2199 pCap
->hw_caps
|= ATH9K_HW_CAP_RAC_SUPPORTED
;
2204 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
2205 u32 capability
, u32
*result
)
2207 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2209 case ATH9K_CAP_CIPHER
:
2210 switch (capability
) {
2211 case ATH9K_CIPHER_AES_CCM
:
2212 case ATH9K_CIPHER_AES_OCB
:
2213 case ATH9K_CIPHER_TKIP
:
2214 case ATH9K_CIPHER_WEP
:
2215 case ATH9K_CIPHER_MIC
:
2216 case ATH9K_CIPHER_CLR
:
2221 case ATH9K_CAP_TKIP_MIC
:
2222 switch (capability
) {
2226 return (ah
->sta_id1_defaults
&
2227 AR_STA_ID1_CRPT_MIC_ENABLE
) ? true :
2230 case ATH9K_CAP_TKIP_SPLIT
:
2231 return (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) ?
2233 case ATH9K_CAP_MCAST_KEYSRCH
:
2234 switch (capability
) {
2238 if (REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_ADHOC
) {
2241 return (ah
->sta_id1_defaults
&
2242 AR_STA_ID1_MCAST_KSRCH
) ? true :
2247 case ATH9K_CAP_TXPOW
:
2248 switch (capability
) {
2252 *result
= regulatory
->power_limit
;
2255 *result
= regulatory
->max_power_level
;
2258 *result
= regulatory
->tp_scale
;
2263 return (AR_SREV_9280_20_OR_LATER(ah
) &&
2264 (ah
->eep_ops
->get_eeprom(ah
, EEP_RC_CHAIN_MASK
) == 1))
2270 EXPORT_SYMBOL(ath9k_hw_getcapability
);
2272 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
2273 u32 capability
, u32 setting
, int *status
)
2276 case ATH9K_CAP_TKIP_MIC
:
2278 ah
->sta_id1_defaults
|=
2279 AR_STA_ID1_CRPT_MIC_ENABLE
;
2281 ah
->sta_id1_defaults
&=
2282 ~AR_STA_ID1_CRPT_MIC_ENABLE
;
2284 case ATH9K_CAP_MCAST_KEYSRCH
:
2286 ah
->sta_id1_defaults
|= AR_STA_ID1_MCAST_KSRCH
;
2288 ah
->sta_id1_defaults
&= ~AR_STA_ID1_MCAST_KSRCH
;
2294 EXPORT_SYMBOL(ath9k_hw_setcapability
);
2296 /****************************/
2297 /* GPIO / RFKILL / Antennae */
2298 /****************************/
2300 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
2304 u32 gpio_shift
, tmp
;
2307 addr
= AR_GPIO_OUTPUT_MUX3
;
2309 addr
= AR_GPIO_OUTPUT_MUX2
;
2311 addr
= AR_GPIO_OUTPUT_MUX1
;
2313 gpio_shift
= (gpio
% 6) * 5;
2315 if (AR_SREV_9280_20_OR_LATER(ah
)
2316 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
2317 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
2318 (0x1f << gpio_shift
));
2320 tmp
= REG_READ(ah
, addr
);
2321 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
2322 tmp
&= ~(0x1f << gpio_shift
);
2323 tmp
|= (type
<< gpio_shift
);
2324 REG_WRITE(ah
, addr
, tmp
);
2328 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
2332 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
2334 gpio_shift
= gpio
<< 1;
2338 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
2339 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2341 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
2343 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
2345 #define MS_REG_READ(x, y) \
2346 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2348 if (gpio
>= ah
->caps
.num_gpio_pins
)
2351 if (AR_SREV_9300_20_OR_LATER(ah
))
2352 return MS_REG_READ(AR9300
, gpio
) != 0;
2353 else if (AR_SREV_9271(ah
))
2354 return MS_REG_READ(AR9271
, gpio
) != 0;
2355 else if (AR_SREV_9287_10_OR_LATER(ah
))
2356 return MS_REG_READ(AR9287
, gpio
) != 0;
2357 else if (AR_SREV_9285_10_OR_LATER(ah
))
2358 return MS_REG_READ(AR9285
, gpio
) != 0;
2359 else if (AR_SREV_9280_10_OR_LATER(ah
))
2360 return MS_REG_READ(AR928X
, gpio
) != 0;
2362 return MS_REG_READ(AR
, gpio
) != 0;
2364 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
2366 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
2371 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
2373 gpio_shift
= 2 * gpio
;
2377 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
2378 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2380 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
2382 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
2384 if (AR_SREV_9271(ah
))
2387 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
2390 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
2392 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
2394 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
2396 EXPORT_SYMBOL(ath9k_hw_getdefantenna
);
2398 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
2400 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
2402 EXPORT_SYMBOL(ath9k_hw_setantenna
);
2404 /*********************/
2405 /* General Operation */
2406 /*********************/
2408 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
2410 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
2411 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
2413 if (phybits
& AR_PHY_ERR_RADAR
)
2414 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
2415 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
2416 bits
|= ATH9K_RX_FILTER_PHYERR
;
2420 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
2422 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
2426 ENABLE_REGWRITE_BUFFER(ah
);
2428 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
2431 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
2432 phybits
|= AR_PHY_ERR_RADAR
;
2433 if (bits
& ATH9K_RX_FILTER_PHYERR
)
2434 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
2435 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
2438 REG_WRITE(ah
, AR_RXCFG
,
2439 REG_READ(ah
, AR_RXCFG
) | AR_RXCFG_ZLFDMA
);
2441 REG_WRITE(ah
, AR_RXCFG
,
2442 REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_ZLFDMA
);
2444 REGWRITE_BUFFER_FLUSH(ah
);
2445 DISABLE_REGWRITE_BUFFER(ah
);
2447 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
2449 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
2451 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
2454 ath9k_hw_init_pll(ah
, NULL
);
2457 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
2459 bool ath9k_hw_disable(struct ath_hw
*ah
)
2461 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
2464 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
2467 ath9k_hw_init_pll(ah
, NULL
);
2470 EXPORT_SYMBOL(ath9k_hw_disable
);
2472 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
)
2474 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2475 struct ath9k_channel
*chan
= ah
->curchan
;
2476 struct ieee80211_channel
*channel
= chan
->chan
;
2478 regulatory
->power_limit
= min(limit
, (u32
) MAX_RATE_POWER
);
2480 ah
->eep_ops
->set_txpower(ah
, chan
,
2481 ath9k_regd_get_ctl(regulatory
, chan
),
2482 channel
->max_antenna_gain
* 2,
2483 channel
->max_power
* 2,
2484 min((u32
) MAX_RATE_POWER
,
2485 (u32
) regulatory
->power_limit
));
2487 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
2489 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
)
2491 memcpy(ath9k_hw_common(ah
)->macaddr
, mac
, ETH_ALEN
);
2493 EXPORT_SYMBOL(ath9k_hw_setmac
);
2495 void ath9k_hw_setopmode(struct ath_hw
*ah
)
2497 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2499 EXPORT_SYMBOL(ath9k_hw_setopmode
);
2501 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
2503 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
2504 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
2506 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
2508 void ath9k_hw_write_associd(struct ath_hw
*ah
)
2510 struct ath_common
*common
= ath9k_hw_common(ah
);
2512 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
2513 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
2514 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
2516 EXPORT_SYMBOL(ath9k_hw_write_associd
);
2518 #define ATH9K_MAX_TSF_READ 10
2520 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
2522 u32 tsf_lower
, tsf_upper1
, tsf_upper2
;
2525 tsf_upper1
= REG_READ(ah
, AR_TSF_U32
);
2526 for (i
= 0; i
< ATH9K_MAX_TSF_READ
; i
++) {
2527 tsf_lower
= REG_READ(ah
, AR_TSF_L32
);
2528 tsf_upper2
= REG_READ(ah
, AR_TSF_U32
);
2529 if (tsf_upper2
== tsf_upper1
)
2531 tsf_upper1
= tsf_upper2
;
2534 WARN_ON( i
== ATH9K_MAX_TSF_READ
);
2536 return (((u64
)tsf_upper1
<< 32) | tsf_lower
);
2538 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
2540 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
2542 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
2543 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
2545 EXPORT_SYMBOL(ath9k_hw_settsf64
);
2547 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
2549 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
2550 AH_TSF_WRITE_TIMEOUT
))
2551 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
2552 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2554 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
2556 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
2558 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
2561 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
2563 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
2565 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
2568 * Extend 15-bit time stamp from rx descriptor to
2569 * a full 64-bit TSF using the current h/w TSF.
2571 u64
ath9k_hw_extend_tsf(struct ath_hw
*ah
, u32 rstamp
)
2575 tsf
= ath9k_hw_gettsf64(ah
);
2576 if ((tsf
& 0x7fff) < rstamp
)
2578 return (tsf
& ~0x7fff) | rstamp
;
2580 EXPORT_SYMBOL(ath9k_hw_extend_tsf
);
2582 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
)
2584 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
2587 if (conf_is_ht40(conf
) && !ah
->config
.cwm_ignore_extcca
)
2588 macmode
= AR_2040_JOINED_RX_CLEAR
;
2592 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
2595 /* HW Generic timers configuration */
2597 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
2599 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2600 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2601 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2602 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2603 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2604 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2605 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2606 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2607 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
2608 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
2609 AR_NDP2_TIMER_MODE
, 0x0002},
2610 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
2611 AR_NDP2_TIMER_MODE
, 0x0004},
2612 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
2613 AR_NDP2_TIMER_MODE
, 0x0008},
2614 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
2615 AR_NDP2_TIMER_MODE
, 0x0010},
2616 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
2617 AR_NDP2_TIMER_MODE
, 0x0020},
2618 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
2619 AR_NDP2_TIMER_MODE
, 0x0040},
2620 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
2621 AR_NDP2_TIMER_MODE
, 0x0080}
2624 /* HW generic timer primitives */
2626 /* compute and clear index of rightmost 1 */
2627 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
2637 return timer_table
->gen_timer_index
[b
];
2640 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
2642 return REG_READ(ah
, AR_TSF_L32
);
2644 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
2646 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
2647 void (*trigger
)(void *),
2648 void (*overflow
)(void *),
2652 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2653 struct ath_gen_timer
*timer
;
2655 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
2657 if (timer
== NULL
) {
2658 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2659 "Failed to allocate memory"
2660 "for hw timer[%d]\n", timer_index
);
2664 /* allocate a hardware generic timer slot */
2665 timer_table
->timers
[timer_index
] = timer
;
2666 timer
->index
= timer_index
;
2667 timer
->trigger
= trigger
;
2668 timer
->overflow
= overflow
;
2673 EXPORT_SYMBOL(ath_gen_timer_alloc
);
2675 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
2676 struct ath_gen_timer
*timer
,
2680 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2683 BUG_ON(!timer_period
);
2685 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
2687 tsf
= ath9k_hw_gettsf32(ah
);
2689 ath_print(ath9k_hw_common(ah
), ATH_DBG_HWTIMER
,
2690 "curent tsf %x period %x"
2691 "timer_next %x\n", tsf
, timer_period
, timer_next
);
2694 * Pull timer_next forward if the current TSF already passed it
2695 * because of software latency
2697 if (timer_next
< tsf
)
2698 timer_next
= tsf
+ timer_period
;
2701 * Program generic timer registers
2703 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
2705 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
2707 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2708 gen_tmr_configuration
[timer
->index
].mode_mask
);
2710 /* Enable both trigger and thresh interrupt masks */
2711 REG_SET_BIT(ah
, AR_IMR_S5
,
2712 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
2713 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
2715 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
2717 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
2719 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2721 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
2722 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
2726 /* Clear generic timer enable bits. */
2727 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2728 gen_tmr_configuration
[timer
->index
].mode_mask
);
2730 /* Disable both trigger and thresh interrupt masks */
2731 REG_CLR_BIT(ah
, AR_IMR_S5
,
2732 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
2733 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
2735 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
2737 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
2739 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
2741 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2743 /* free the hardware generic timer slot */
2744 timer_table
->timers
[timer
->index
] = NULL
;
2747 EXPORT_SYMBOL(ath_gen_timer_free
);
2750 * Generic Timer Interrupts handling
2752 void ath_gen_timer_isr(struct ath_hw
*ah
)
2754 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2755 struct ath_gen_timer
*timer
;
2756 struct ath_common
*common
= ath9k_hw_common(ah
);
2757 u32 trigger_mask
, thresh_mask
, index
;
2759 /* get hardware generic timer interrupt status */
2760 trigger_mask
= ah
->intr_gen_timer_trigger
;
2761 thresh_mask
= ah
->intr_gen_timer_thresh
;
2762 trigger_mask
&= timer_table
->timer_mask
.val
;
2763 thresh_mask
&= timer_table
->timer_mask
.val
;
2765 trigger_mask
&= ~thresh_mask
;
2767 while (thresh_mask
) {
2768 index
= rightmost_index(timer_table
, &thresh_mask
);
2769 timer
= timer_table
->timers
[index
];
2771 ath_print(common
, ATH_DBG_HWTIMER
,
2772 "TSF overflow for Gen timer %d\n", index
);
2773 timer
->overflow(timer
->arg
);
2776 while (trigger_mask
) {
2777 index
= rightmost_index(timer_table
, &trigger_mask
);
2778 timer
= timer_table
->timers
[index
];
2780 ath_print(common
, ATH_DBG_HWTIMER
,
2781 "Gen timer[%d] trigger\n", index
);
2782 timer
->trigger(timer
->arg
);
2785 EXPORT_SYMBOL(ath_gen_timer_isr
);
2791 void ath9k_hw_htc_resetinit(struct ath_hw
*ah
)
2793 ah
->htc_reset_init
= true;
2795 EXPORT_SYMBOL(ath9k_hw_htc_resetinit
);
2800 } ath_mac_bb_names
[] = {
2801 /* Devices with external radios */
2802 { AR_SREV_VERSION_5416_PCI
, "5416" },
2803 { AR_SREV_VERSION_5416_PCIE
, "5418" },
2804 { AR_SREV_VERSION_9100
, "9100" },
2805 { AR_SREV_VERSION_9160
, "9160" },
2806 /* Single-chip solutions */
2807 { AR_SREV_VERSION_9280
, "9280" },
2808 { AR_SREV_VERSION_9285
, "9285" },
2809 { AR_SREV_VERSION_9287
, "9287" },
2810 { AR_SREV_VERSION_9271
, "9271" },
2811 { AR_SREV_VERSION_9300
, "9300" },
2814 /* For devices with external radios */
2818 } ath_rf_names
[] = {
2820 { AR_RAD5133_SREV_MAJOR
, "5133" },
2821 { AR_RAD5122_SREV_MAJOR
, "5122" },
2822 { AR_RAD2133_SREV_MAJOR
, "2133" },
2823 { AR_RAD2122_SREV_MAJOR
, "2122" }
2827 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2829 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
2833 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
2834 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
2835 return ath_mac_bb_names
[i
].name
;
2843 * Return the RF name. "????" is returned if the RF is unknown.
2844 * Used for devices with external radios.
2846 static const char *ath9k_hw_rf_name(u16 rf_version
)
2850 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
2851 if (ath_rf_names
[i
].version
== rf_version
) {
2852 return ath_rf_names
[i
].name
;
2859 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
2863 /* chipsets >= AR9280 are single-chip */
2864 if (AR_SREV_9280_10_OR_LATER(ah
)) {
2865 used
= snprintf(hw_name
, len
,
2866 "Atheros AR%s Rev:%x",
2867 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
2868 ah
->hw_version
.macRev
);
2871 used
= snprintf(hw_name
, len
,
2872 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2873 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
2874 ah
->hw_version
.macRev
,
2875 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
&
2876 AR_RADIO_SREV_MAJOR
)),
2877 ah
->hw_version
.phyRev
);
2880 hw_name
[used
] = '\0';
2882 EXPORT_SYMBOL(ath9k_hw_name
);