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ath9k_hw: start building an abstraction layer for hardware routines
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "hw-ops.h"
22 #include "rc.h"
23 #include "initvals.h"
24
25 #define ATH9K_CLOCK_RATE_CCK 22
26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28
29 static void ar9002_hw_attach_ops(struct ath_hw *ah);
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
33
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
38
39 static int __init ath9k_init(void)
40 {
41 return 0;
42 }
43 module_init(ath9k_init);
44
45 static void __exit ath9k_exit(void)
46 {
47 return;
48 }
49 module_exit(ath9k_exit);
50
51 /* Private hardware callbacks */
52
53 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
54 {
55 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
56 }
57
58 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
59 {
60 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
61 }
62
63 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
64 {
65 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
66
67 return priv_ops->macversion_supported(ah->hw_version.macVersion);
68 }
69
70 /********************/
71 /* Helper Functions */
72 /********************/
73
74 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
75 {
76 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
77
78 if (!ah->curchan) /* should really check for CCK instead */
79 return usecs *ATH9K_CLOCK_RATE_CCK;
80 if (conf->channel->band == IEEE80211_BAND_2GHZ)
81 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
82 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
83 }
84
85 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
86 {
87 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
88
89 if (conf_is_ht40(conf))
90 return ath9k_hw_mac_clks(ah, usecs) * 2;
91 else
92 return ath9k_hw_mac_clks(ah, usecs);
93 }
94
95 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
96 {
97 int i;
98
99 BUG_ON(timeout < AH_TIME_QUANTUM);
100
101 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
102 if ((REG_READ(ah, reg) & mask) == val)
103 return true;
104
105 udelay(AH_TIME_QUANTUM);
106 }
107
108 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
109 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
110 timeout, reg, REG_READ(ah, reg), mask, val);
111
112 return false;
113 }
114 EXPORT_SYMBOL(ath9k_hw_wait);
115
116 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
117 {
118 u32 retval;
119 int i;
120
121 for (i = 0, retval = 0; i < n; i++) {
122 retval = (retval << 1) | (val & 1);
123 val >>= 1;
124 }
125 return retval;
126 }
127
128 bool ath9k_get_channel_edges(struct ath_hw *ah,
129 u16 flags, u16 *low,
130 u16 *high)
131 {
132 struct ath9k_hw_capabilities *pCap = &ah->caps;
133
134 if (flags & CHANNEL_5GHZ) {
135 *low = pCap->low_5ghz_chan;
136 *high = pCap->high_5ghz_chan;
137 return true;
138 }
139 if ((flags & CHANNEL_2GHZ)) {
140 *low = pCap->low_2ghz_chan;
141 *high = pCap->high_2ghz_chan;
142 return true;
143 }
144 return false;
145 }
146
147 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
148 u8 phy, int kbps,
149 u32 frameLen, u16 rateix,
150 bool shortPreamble)
151 {
152 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
153
154 if (kbps == 0)
155 return 0;
156
157 switch (phy) {
158 case WLAN_RC_PHY_CCK:
159 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
160 if (shortPreamble)
161 phyTime >>= 1;
162 numBits = frameLen << 3;
163 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
164 break;
165 case WLAN_RC_PHY_OFDM:
166 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
167 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
168 numBits = OFDM_PLCP_BITS + (frameLen << 3);
169 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
170 txTime = OFDM_SIFS_TIME_QUARTER
171 + OFDM_PREAMBLE_TIME_QUARTER
172 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
173 } else if (ah->curchan &&
174 IS_CHAN_HALF_RATE(ah->curchan)) {
175 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
176 numBits = OFDM_PLCP_BITS + (frameLen << 3);
177 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
178 txTime = OFDM_SIFS_TIME_HALF +
179 OFDM_PREAMBLE_TIME_HALF
180 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
181 } else {
182 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
183 numBits = OFDM_PLCP_BITS + (frameLen << 3);
184 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
185 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
186 + (numSymbols * OFDM_SYMBOL_TIME);
187 }
188 break;
189 default:
190 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
191 "Unknown phy %u (rate ix %u)\n", phy, rateix);
192 txTime = 0;
193 break;
194 }
195
196 return txTime;
197 }
198 EXPORT_SYMBOL(ath9k_hw_computetxtime);
199
200 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
201 struct ath9k_channel *chan,
202 struct chan_centers *centers)
203 {
204 int8_t extoff;
205
206 if (!IS_CHAN_HT40(chan)) {
207 centers->ctl_center = centers->ext_center =
208 centers->synth_center = chan->channel;
209 return;
210 }
211
212 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
213 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
214 centers->synth_center =
215 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
216 extoff = 1;
217 } else {
218 centers->synth_center =
219 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
220 extoff = -1;
221 }
222
223 centers->ctl_center =
224 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
225 /* 25 MHz spacing is supported by hw but not on upper layers */
226 centers->ext_center =
227 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
228 }
229
230 /******************/
231 /* Chip Revisions */
232 /******************/
233
234 static void ath9k_hw_read_revisions(struct ath_hw *ah)
235 {
236 u32 val;
237
238 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
239
240 if (val == 0xFF) {
241 val = REG_READ(ah, AR_SREV);
242 ah->hw_version.macVersion =
243 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
244 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
245 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
246 } else {
247 if (!AR_SREV_9100(ah))
248 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
249
250 ah->hw_version.macRev = val & AR_SREV_REVISION;
251
252 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
253 ah->is_pciexpress = true;
254 }
255 }
256
257 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
258 {
259 u32 val;
260 int i;
261
262 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
263
264 for (i = 0; i < 8; i++)
265 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
266 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
267 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
268
269 return ath9k_hw_reverse_bits(val, 8);
270 }
271
272 /************************************/
273 /* HW Attach, Detach, Init Routines */
274 /************************************/
275
276 static void ath9k_hw_disablepcie(struct ath_hw *ah)
277 {
278 if (AR_SREV_9100(ah))
279 return;
280
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
290
291 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
292 }
293
294 static bool ath9k_hw_chip_test(struct ath_hw *ah)
295 {
296 struct ath_common *common = ath9k_hw_common(ah);
297 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
298 u32 regHold[2];
299 u32 patternData[4] = { 0x55555555,
300 0xaaaaaaaa,
301 0x66666666,
302 0x99999999 };
303 int i, j;
304
305 for (i = 0; i < 2; i++) {
306 u32 addr = regAddr[i];
307 u32 wrData, rdData;
308
309 regHold[i] = REG_READ(ah, addr);
310 for (j = 0; j < 0x100; j++) {
311 wrData = (j << 16) | j;
312 REG_WRITE(ah, addr, wrData);
313 rdData = REG_READ(ah, addr);
314 if (rdData != wrData) {
315 ath_print(common, ATH_DBG_FATAL,
316 "address test failed "
317 "addr: 0x%08x - wr:0x%08x != "
318 "rd:0x%08x\n",
319 addr, wrData, rdData);
320 return false;
321 }
322 }
323 for (j = 0; j < 4; j++) {
324 wrData = patternData[j];
325 REG_WRITE(ah, addr, wrData);
326 rdData = REG_READ(ah, addr);
327 if (wrData != rdData) {
328 ath_print(common, ATH_DBG_FATAL,
329 "address test failed "
330 "addr: 0x%08x - wr:0x%08x != "
331 "rd:0x%08x\n",
332 addr, wrData, rdData);
333 return false;
334 }
335 }
336 REG_WRITE(ah, regAddr[i], regHold[i]);
337 }
338 udelay(100);
339
340 return true;
341 }
342
343 static void ath9k_hw_init_config(struct ath_hw *ah)
344 {
345 int i;
346
347 ah->config.dma_beacon_response_time = 2;
348 ah->config.sw_beacon_response_time = 10;
349 ah->config.additional_swba_backoff = 0;
350 ah->config.ack_6mb = 0x0;
351 ah->config.cwm_ignore_extcca = 0;
352 ah->config.pcie_powersave_enable = 0;
353 ah->config.pcie_clock_req = 0;
354 ah->config.pcie_waen = 0;
355 ah->config.analog_shiftreg = 1;
356 ah->config.ofdm_trig_low = 200;
357 ah->config.ofdm_trig_high = 500;
358 ah->config.cck_trig_high = 200;
359 ah->config.cck_trig_low = 100;
360 ah->config.enable_ani = 1;
361
362 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
363 ah->config.spurchans[i][0] = AR_NO_SPUR;
364 ah->config.spurchans[i][1] = AR_NO_SPUR;
365 }
366
367 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
368 ah->config.ht_enable = 1;
369 else
370 ah->config.ht_enable = 0;
371
372 ah->config.rx_intr_mitigation = true;
373
374 /*
375 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
376 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
377 * This means we use it for all AR5416 devices, and the few
378 * minor PCI AR9280 devices out there.
379 *
380 * Serialization is required because these devices do not handle
381 * well the case of two concurrent reads/writes due to the latency
382 * involved. During one read/write another read/write can be issued
383 * on another CPU while the previous read/write may still be working
384 * on our hardware, if we hit this case the hardware poops in a loop.
385 * We prevent this by serializing reads and writes.
386 *
387 * This issue is not present on PCI-Express devices or pre-AR5416
388 * devices (legacy, 802.11abg).
389 */
390 if (num_possible_cpus() > 1)
391 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
392 }
393
394 static void ath9k_hw_init_defaults(struct ath_hw *ah)
395 {
396 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
397
398 regulatory->country_code = CTRY_DEFAULT;
399 regulatory->power_limit = MAX_RATE_POWER;
400 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
401
402 ah->hw_version.magic = AR5416_MAGIC;
403 ah->hw_version.subvendorid = 0;
404
405 ah->ah_flags = 0;
406 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
407 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
408 if (!AR_SREV_9100(ah))
409 ah->ah_flags = AH_USE_EEPROM;
410
411 ah->atim_window = 0;
412 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
413 ah->beacon_interval = 100;
414 ah->enable_32kHz_clock = DONT_USE_32KHZ;
415 ah->slottime = (u32) -1;
416 ah->globaltxtimeout = (u32) -1;
417 ah->power_mode = ATH9K_PM_UNDEFINED;
418 }
419
420 static int ath9k_hw_rf_claim(struct ath_hw *ah)
421 {
422 u32 val;
423
424 REG_WRITE(ah, AR_PHY(0), 0x00000007);
425
426 val = ath9k_hw_get_radiorev(ah);
427 switch (val & AR_RADIO_SREV_MAJOR) {
428 case 0:
429 val = AR_RAD5133_SREV_MAJOR;
430 break;
431 case AR_RAD5133_SREV_MAJOR:
432 case AR_RAD5122_SREV_MAJOR:
433 case AR_RAD2133_SREV_MAJOR:
434 case AR_RAD2122_SREV_MAJOR:
435 break;
436 default:
437 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
438 "Radio Chip Rev 0x%02X not supported\n",
439 val & AR_RADIO_SREV_MAJOR);
440 return -EOPNOTSUPP;
441 }
442
443 ah->hw_version.analog5GhzRev = val;
444
445 return 0;
446 }
447
448 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
449 {
450 struct ath_common *common = ath9k_hw_common(ah);
451 u32 sum;
452 int i;
453 u16 eeval;
454
455 sum = 0;
456 for (i = 0; i < 3; i++) {
457 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
458 sum += eeval;
459 common->macaddr[2 * i] = eeval >> 8;
460 common->macaddr[2 * i + 1] = eeval & 0xff;
461 }
462 if (sum == 0 || sum == 0xffff * 3)
463 return -EADDRNOTAVAIL;
464
465 return 0;
466 }
467
468 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
469 {
470 u32 rxgain_type;
471
472 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
473 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
474
475 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
476 INIT_INI_ARRAY(&ah->iniModesRxGain,
477 ar9280Modes_backoff_13db_rxgain_9280_2,
478 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
479 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
480 INIT_INI_ARRAY(&ah->iniModesRxGain,
481 ar9280Modes_backoff_23db_rxgain_9280_2,
482 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
483 else
484 INIT_INI_ARRAY(&ah->iniModesRxGain,
485 ar9280Modes_original_rxgain_9280_2,
486 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
487 } else {
488 INIT_INI_ARRAY(&ah->iniModesRxGain,
489 ar9280Modes_original_rxgain_9280_2,
490 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
491 }
492 }
493
494 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
495 {
496 u32 txgain_type;
497
498 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
499 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
500
501 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
502 INIT_INI_ARRAY(&ah->iniModesTxGain,
503 ar9280Modes_high_power_tx_gain_9280_2,
504 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
505 else
506 INIT_INI_ARRAY(&ah->iniModesTxGain,
507 ar9280Modes_original_tx_gain_9280_2,
508 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
509 } else {
510 INIT_INI_ARRAY(&ah->iniModesTxGain,
511 ar9280Modes_original_tx_gain_9280_2,
512 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
513 }
514 }
515
516 static int ath9k_hw_post_init(struct ath_hw *ah)
517 {
518 int ecode;
519
520 if (!AR_SREV_9271(ah)) {
521 if (!ath9k_hw_chip_test(ah))
522 return -ENODEV;
523 }
524
525 ecode = ath9k_hw_rf_claim(ah);
526 if (ecode != 0)
527 return ecode;
528
529 ecode = ath9k_hw_eeprom_init(ah);
530 if (ecode != 0)
531 return ecode;
532
533 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
534 "Eeprom VER: %d, REV: %d\n",
535 ah->eep_ops->get_eeprom_ver(ah),
536 ah->eep_ops->get_eeprom_rev(ah));
537
538 if (!AR_SREV_9280_10_OR_LATER(ah)) {
539 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
540 if (ecode) {
541 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
542 "Failed allocating banks for "
543 "external radio\n");
544 return ecode;
545 }
546 }
547
548 if (!AR_SREV_9100(ah)) {
549 ath9k_hw_ani_setup(ah);
550 ath9k_hw_ani_init(ah);
551 }
552
553 return 0;
554 }
555
556 static bool ar9002_hw_macversion_supported(u32 macversion)
557 {
558 switch (macversion) {
559 case AR_SREV_VERSION_5416_PCI:
560 case AR_SREV_VERSION_5416_PCIE:
561 case AR_SREV_VERSION_9160:
562 case AR_SREV_VERSION_9100:
563 case AR_SREV_VERSION_9280:
564 case AR_SREV_VERSION_9285:
565 case AR_SREV_VERSION_9287:
566 case AR_SREV_VERSION_9271:
567 return true;
568 default:
569 break;
570 }
571 return false;
572 }
573
574 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
575 {
576 if (AR_SREV_9160_10_OR_LATER(ah)) {
577 if (AR_SREV_9280_10_OR_LATER(ah)) {
578 ah->iq_caldata.calData = &iq_cal_single_sample;
579 ah->adcgain_caldata.calData =
580 &adc_gain_cal_single_sample;
581 ah->adcdc_caldata.calData =
582 &adc_dc_cal_single_sample;
583 ah->adcdc_calinitdata.calData =
584 &adc_init_dc_cal;
585 } else {
586 ah->iq_caldata.calData = &iq_cal_multi_sample;
587 ah->adcgain_caldata.calData =
588 &adc_gain_cal_multi_sample;
589 ah->adcdc_caldata.calData =
590 &adc_dc_cal_multi_sample;
591 ah->adcdc_calinitdata.calData =
592 &adc_init_dc_cal;
593 }
594 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
595 }
596 }
597
598 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
599 {
600 if (AR_SREV_9271(ah)) {
601 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
602 ARRAY_SIZE(ar9271Modes_9271), 6);
603 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
604 ARRAY_SIZE(ar9271Common_9271), 2);
605 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
606 ar9271Common_normal_cck_fir_coeff_9271,
607 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
608 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
609 ar9271Common_japan_2484_cck_fir_coeff_9271,
610 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
611 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
612 ar9271Modes_9271_1_0_only,
613 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
614 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
615 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
616 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
617 ar9271Modes_high_power_tx_gain_9271,
618 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
619 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
620 ar9271Modes_normal_power_tx_gain_9271,
621 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
622 return;
623 }
624
625 if (AR_SREV_9287_11_OR_LATER(ah)) {
626 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
627 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
628 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
629 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
630 if (ah->config.pcie_clock_req)
631 INIT_INI_ARRAY(&ah->iniPcieSerdes,
632 ar9287PciePhy_clkreq_off_L1_9287_1_1,
633 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
634 else
635 INIT_INI_ARRAY(&ah->iniPcieSerdes,
636 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
637 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
638 2);
639 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
640 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
641 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
642 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
643 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
644
645 if (ah->config.pcie_clock_req)
646 INIT_INI_ARRAY(&ah->iniPcieSerdes,
647 ar9287PciePhy_clkreq_off_L1_9287_1_0,
648 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
649 else
650 INIT_INI_ARRAY(&ah->iniPcieSerdes,
651 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
652 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
653 2);
654 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
655
656
657 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
658 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
659 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
660 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
661
662 if (ah->config.pcie_clock_req) {
663 INIT_INI_ARRAY(&ah->iniPcieSerdes,
664 ar9285PciePhy_clkreq_off_L1_9285_1_2,
665 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
666 } else {
667 INIT_INI_ARRAY(&ah->iniPcieSerdes,
668 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
669 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
670 2);
671 }
672 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
673 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
674 ARRAY_SIZE(ar9285Modes_9285), 6);
675 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
676 ARRAY_SIZE(ar9285Common_9285), 2);
677
678 if (ah->config.pcie_clock_req) {
679 INIT_INI_ARRAY(&ah->iniPcieSerdes,
680 ar9285PciePhy_clkreq_off_L1_9285,
681 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
682 } else {
683 INIT_INI_ARRAY(&ah->iniPcieSerdes,
684 ar9285PciePhy_clkreq_always_on_L1_9285,
685 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
686 }
687 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
688 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
689 ARRAY_SIZE(ar9280Modes_9280_2), 6);
690 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
691 ARRAY_SIZE(ar9280Common_9280_2), 2);
692
693 if (ah->config.pcie_clock_req) {
694 INIT_INI_ARRAY(&ah->iniPcieSerdes,
695 ar9280PciePhy_clkreq_off_L1_9280,
696 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
697 } else {
698 INIT_INI_ARRAY(&ah->iniPcieSerdes,
699 ar9280PciePhy_clkreq_always_on_L1_9280,
700 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
701 }
702 INIT_INI_ARRAY(&ah->iniModesAdditional,
703 ar9280Modes_fast_clock_9280_2,
704 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
705 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
706 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
707 ARRAY_SIZE(ar9280Modes_9280), 6);
708 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
709 ARRAY_SIZE(ar9280Common_9280), 2);
710 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
711 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
712 ARRAY_SIZE(ar5416Modes_9160), 6);
713 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
714 ARRAY_SIZE(ar5416Common_9160), 2);
715 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
716 ARRAY_SIZE(ar5416Bank0_9160), 2);
717 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
718 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
719 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
720 ARRAY_SIZE(ar5416Bank1_9160), 2);
721 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
722 ARRAY_SIZE(ar5416Bank2_9160), 2);
723 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
724 ARRAY_SIZE(ar5416Bank3_9160), 3);
725 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
726 ARRAY_SIZE(ar5416Bank6_9160), 3);
727 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
728 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
729 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
730 ARRAY_SIZE(ar5416Bank7_9160), 2);
731 if (AR_SREV_9160_11(ah)) {
732 INIT_INI_ARRAY(&ah->iniAddac,
733 ar5416Addac_91601_1,
734 ARRAY_SIZE(ar5416Addac_91601_1), 2);
735 } else {
736 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
737 ARRAY_SIZE(ar5416Addac_9160), 2);
738 }
739 } else if (AR_SREV_9100_OR_LATER(ah)) {
740 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
741 ARRAY_SIZE(ar5416Modes_9100), 6);
742 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
743 ARRAY_SIZE(ar5416Common_9100), 2);
744 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
745 ARRAY_SIZE(ar5416Bank0_9100), 2);
746 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
747 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
748 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
749 ARRAY_SIZE(ar5416Bank1_9100), 2);
750 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
751 ARRAY_SIZE(ar5416Bank2_9100), 2);
752 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
753 ARRAY_SIZE(ar5416Bank3_9100), 3);
754 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
755 ARRAY_SIZE(ar5416Bank6_9100), 3);
756 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
757 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
758 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
759 ARRAY_SIZE(ar5416Bank7_9100), 2);
760 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
761 ARRAY_SIZE(ar5416Addac_9100), 2);
762 } else {
763 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
764 ARRAY_SIZE(ar5416Modes), 6);
765 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
766 ARRAY_SIZE(ar5416Common), 2);
767 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
768 ARRAY_SIZE(ar5416Bank0), 2);
769 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
770 ARRAY_SIZE(ar5416BB_RfGain), 3);
771 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
772 ARRAY_SIZE(ar5416Bank1), 2);
773 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
774 ARRAY_SIZE(ar5416Bank2), 2);
775 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
776 ARRAY_SIZE(ar5416Bank3), 3);
777 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
778 ARRAY_SIZE(ar5416Bank6), 3);
779 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
780 ARRAY_SIZE(ar5416Bank6TPC), 3);
781 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
782 ARRAY_SIZE(ar5416Bank7), 2);
783 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
784 ARRAY_SIZE(ar5416Addac), 2);
785 }
786 }
787
788 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
789 {
790 if (AR_SREV_9287_11_OR_LATER(ah))
791 INIT_INI_ARRAY(&ah->iniModesRxGain,
792 ar9287Modes_rx_gain_9287_1_1,
793 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
794 else if (AR_SREV_9287_10(ah))
795 INIT_INI_ARRAY(&ah->iniModesRxGain,
796 ar9287Modes_rx_gain_9287_1_0,
797 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
798 else if (AR_SREV_9280_20(ah))
799 ath9k_hw_init_rxgain_ini(ah);
800
801 if (AR_SREV_9287_11_OR_LATER(ah)) {
802 INIT_INI_ARRAY(&ah->iniModesTxGain,
803 ar9287Modes_tx_gain_9287_1_1,
804 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
805 } else if (AR_SREV_9287_10(ah)) {
806 INIT_INI_ARRAY(&ah->iniModesTxGain,
807 ar9287Modes_tx_gain_9287_1_0,
808 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
809 } else if (AR_SREV_9280_20(ah)) {
810 ath9k_hw_init_txgain_ini(ah);
811 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
812 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
813
814 /* txgain table */
815 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
816 if (AR_SREV_9285E_20(ah)) {
817 INIT_INI_ARRAY(&ah->iniModesTxGain,
818 ar9285Modes_XE2_0_high_power,
819 ARRAY_SIZE(
820 ar9285Modes_XE2_0_high_power), 6);
821 } else {
822 INIT_INI_ARRAY(&ah->iniModesTxGain,
823 ar9285Modes_high_power_tx_gain_9285_1_2,
824 ARRAY_SIZE(
825 ar9285Modes_high_power_tx_gain_9285_1_2), 6);
826 }
827 } else {
828 if (AR_SREV_9285E_20(ah)) {
829 INIT_INI_ARRAY(&ah->iniModesTxGain,
830 ar9285Modes_XE2_0_normal_power,
831 ARRAY_SIZE(
832 ar9285Modes_XE2_0_normal_power), 6);
833 } else {
834 INIT_INI_ARRAY(&ah->iniModesTxGain,
835 ar9285Modes_original_tx_gain_9285_1_2,
836 ARRAY_SIZE(
837 ar9285Modes_original_tx_gain_9285_1_2), 6);
838 }
839 }
840 }
841 }
842
843 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
844 {
845 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
846 struct ath_common *common = ath9k_hw_common(ah);
847
848 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
849 (ah->eep_map != EEP_MAP_4KBITS) &&
850 ((pBase->version & 0xff) > 0x0a) &&
851 (pBase->pwdclkind == 0);
852
853 if (ah->need_an_top2_fixup)
854 ath_print(common, ATH_DBG_EEPROM,
855 "needs fixup for AR_AN_TOP2 register\n");
856 }
857
858 /* Called for all hardware families */
859 static int __ath9k_hw_init(struct ath_hw *ah)
860 {
861 struct ath_common *common = ath9k_hw_common(ah);
862 int r = 0;
863
864 ath9k_hw_init_defaults(ah);
865 ath9k_hw_init_config(ah);
866
867 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
868 ath_print(common, ATH_DBG_FATAL,
869 "Couldn't reset chip\n");
870 return -EIO;
871 }
872
873 ar9002_hw_attach_ops(ah);
874
875 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
876 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
877 return -EIO;
878 }
879
880 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
881 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
882 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
883 ah->config.serialize_regmode =
884 SER_REG_MODE_ON;
885 } else {
886 ah->config.serialize_regmode =
887 SER_REG_MODE_OFF;
888 }
889 }
890
891 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
892 ah->config.serialize_regmode);
893
894 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
895 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
896 else
897 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
898
899 if (!ath9k_hw_macversion_supported(ah)) {
900 ath_print(common, ATH_DBG_FATAL,
901 "Mac Chip Rev 0x%02x.%x is not supported by "
902 "this driver\n", ah->hw_version.macVersion,
903 ah->hw_version.macRev);
904 return -EOPNOTSUPP;
905 }
906
907 if (AR_SREV_9100(ah)) {
908 ah->iq_caldata.calData = &iq_cal_multi_sample;
909 ah->supp_cals = IQ_MISMATCH_CAL;
910 ah->is_pciexpress = false;
911 }
912
913 if (AR_SREV_9271(ah))
914 ah->is_pciexpress = false;
915
916 /* XXX: move this to its own hw op */
917 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
918
919 ath9k_hw_init_cal_settings(ah);
920
921 ah->ani_function = ATH9K_ANI_ALL;
922 if (AR_SREV_9280_10_OR_LATER(ah)) {
923 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
924 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
925 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
926 } else {
927 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
928 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
929 }
930
931 ath9k_hw_init_mode_regs(ah);
932
933 if (ah->is_pciexpress)
934 ath9k_hw_configpcipowersave(ah, 0, 0);
935 else
936 ath9k_hw_disablepcie(ah);
937
938 /* Support for Japan ch.14 (2484) spread */
939 if (AR_SREV_9287_11_OR_LATER(ah)) {
940 INIT_INI_ARRAY(&ah->iniCckfirNormal,
941 ar9287Common_normal_cck_fir_coeff_92871_1,
942 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
943 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
944 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
945 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
946 }
947
948 r = ath9k_hw_post_init(ah);
949 if (r)
950 return r;
951
952 ath9k_hw_init_mode_gain_regs(ah);
953 r = ath9k_hw_fill_cap_info(ah);
954 if (r)
955 return r;
956
957 ath9k_hw_init_eeprom_fix(ah);
958
959 r = ath9k_hw_init_macaddr(ah);
960 if (r) {
961 ath_print(common, ATH_DBG_FATAL,
962 "Failed to initialize MAC address\n");
963 return r;
964 }
965
966 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
967 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
968 else
969 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
970
971 ath9k_init_nfcal_hist_buffer(ah);
972
973 common->state = ATH_HW_INITIALIZED;
974
975 return 0;
976 }
977
978 int ath9k_hw_init(struct ath_hw *ah)
979 {
980 int ret;
981 struct ath_common *common = ath9k_hw_common(ah);
982
983 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
984 switch (ah->hw_version.devid) {
985 case AR5416_DEVID_PCI:
986 case AR5416_DEVID_PCIE:
987 case AR5416_AR9100_DEVID:
988 case AR9160_DEVID_PCI:
989 case AR9280_DEVID_PCI:
990 case AR9280_DEVID_PCIE:
991 case AR9285_DEVID_PCIE:
992 case AR5416_DEVID_AR9287_PCI:
993 case AR5416_DEVID_AR9287_PCIE:
994 case AR2427_DEVID_PCIE:
995 break;
996 default:
997 if (common->bus_ops->ath_bus_type == ATH_USB)
998 break;
999 ath_print(common, ATH_DBG_FATAL,
1000 "Hardware device ID 0x%04x not supported\n",
1001 ah->hw_version.devid);
1002 return -EOPNOTSUPP;
1003 }
1004
1005 ret = __ath9k_hw_init(ah);
1006 if (ret) {
1007 ath_print(common, ATH_DBG_FATAL,
1008 "Unable to initialize hardware; "
1009 "initialization status: %d\n", ret);
1010 return ret;
1011 }
1012
1013 return 0;
1014 }
1015 EXPORT_SYMBOL(ath9k_hw_init);
1016
1017 static void ath9k_hw_init_bb(struct ath_hw *ah,
1018 struct ath9k_channel *chan)
1019 {
1020 u32 synthDelay;
1021
1022 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1023 if (IS_CHAN_B(chan))
1024 synthDelay = (4 * synthDelay) / 22;
1025 else
1026 synthDelay /= 10;
1027
1028 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1029
1030 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1031 }
1032
1033 static void ath9k_hw_init_qos(struct ath_hw *ah)
1034 {
1035 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1036 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1037
1038 REG_WRITE(ah, AR_QOS_NO_ACK,
1039 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1040 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1041 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1042
1043 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1044 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1045 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1046 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1047 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1048 }
1049
1050 static void ath9k_hw_init_pll(struct ath_hw *ah,
1051 struct ath9k_channel *chan)
1052 {
1053 u32 pll;
1054
1055 if (AR_SREV_9100(ah)) {
1056 if (chan && IS_CHAN_5GHZ(chan))
1057 pll = 0x1450;
1058 else
1059 pll = 0x1458;
1060 } else {
1061 if (AR_SREV_9280_10_OR_LATER(ah)) {
1062 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1063
1064 if (chan && IS_CHAN_HALF_RATE(chan))
1065 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1066 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1067 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1068
1069 if (chan && IS_CHAN_5GHZ(chan)) {
1070 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1071
1072
1073 if (AR_SREV_9280_20(ah)) {
1074 if (((chan->channel % 20) == 0)
1075 || ((chan->channel % 10) == 0))
1076 pll = 0x2850;
1077 else
1078 pll = 0x142c;
1079 }
1080 } else {
1081 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1082 }
1083
1084 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1085
1086 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1087
1088 if (chan && IS_CHAN_HALF_RATE(chan))
1089 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1090 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1091 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1092
1093 if (chan && IS_CHAN_5GHZ(chan))
1094 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1095 else
1096 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1097 } else {
1098 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1099
1100 if (chan && IS_CHAN_HALF_RATE(chan))
1101 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1102 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1103 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1104
1105 if (chan && IS_CHAN_5GHZ(chan))
1106 pll |= SM(0xa, AR_RTC_PLL_DIV);
1107 else
1108 pll |= SM(0xb, AR_RTC_PLL_DIV);
1109 }
1110 }
1111 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1112
1113 /* Switch the core clock for ar9271 to 117Mhz */
1114 if (AR_SREV_9271(ah)) {
1115 udelay(500);
1116 REG_WRITE(ah, 0x50040, 0x304);
1117 }
1118
1119 udelay(RTC_PLL_SETTLE_DELAY);
1120
1121 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1122 }
1123
1124 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1125 {
1126 int rx_chainmask, tx_chainmask;
1127
1128 rx_chainmask = ah->rxchainmask;
1129 tx_chainmask = ah->txchainmask;
1130
1131 switch (rx_chainmask) {
1132 case 0x5:
1133 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1134 AR_PHY_SWAP_ALT_CHAIN);
1135 case 0x3:
1136 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1137 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1138 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1139 break;
1140 }
1141 case 0x1:
1142 case 0x2:
1143 case 0x7:
1144 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1145 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1146 break;
1147 default:
1148 break;
1149 }
1150
1151 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1152 if (tx_chainmask == 0x5) {
1153 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1154 AR_PHY_SWAP_ALT_CHAIN);
1155 }
1156 if (AR_SREV_9100(ah))
1157 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1158 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1159 }
1160
1161 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1162 enum nl80211_iftype opmode)
1163 {
1164 u32 imr_reg = AR_IMR_TXERR |
1165 AR_IMR_TXURN |
1166 AR_IMR_RXERR |
1167 AR_IMR_RXORN |
1168 AR_IMR_BCNMISC;
1169
1170 if (ah->config.rx_intr_mitigation)
1171 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1172 else
1173 imr_reg |= AR_IMR_RXOK;
1174
1175 imr_reg |= AR_IMR_TXOK;
1176
1177 if (opmode == NL80211_IFTYPE_AP)
1178 imr_reg |= AR_IMR_MIB;
1179
1180 REG_WRITE(ah, AR_IMR, imr_reg);
1181 ah->imrs2_reg |= AR_IMR_S2_GTT;
1182 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1183
1184 if (!AR_SREV_9100(ah)) {
1185 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1186 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1187 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1188 }
1189 }
1190
1191 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1192 {
1193 u32 val = ath9k_hw_mac_to_clks(ah, us);
1194 val = min(val, (u32) 0xFFFF);
1195 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1196 }
1197
1198 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1199 {
1200 u32 val = ath9k_hw_mac_to_clks(ah, us);
1201 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1202 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1203 }
1204
1205 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1206 {
1207 u32 val = ath9k_hw_mac_to_clks(ah, us);
1208 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1209 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1210 }
1211
1212 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1213 {
1214 if (tu > 0xFFFF) {
1215 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1216 "bad global tx timeout %u\n", tu);
1217 ah->globaltxtimeout = (u32) -1;
1218 return false;
1219 } else {
1220 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1221 ah->globaltxtimeout = tu;
1222 return true;
1223 }
1224 }
1225
1226 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1227 {
1228 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1229 int acktimeout;
1230 int slottime;
1231 int sifstime;
1232
1233 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1234 ah->misc_mode);
1235
1236 if (ah->misc_mode != 0)
1237 REG_WRITE(ah, AR_PCU_MISC,
1238 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1239
1240 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1241 sifstime = 16;
1242 else
1243 sifstime = 10;
1244
1245 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1246 slottime = ah->slottime + 3 * ah->coverage_class;
1247 acktimeout = slottime + sifstime;
1248
1249 /*
1250 * Workaround for early ACK timeouts, add an offset to match the
1251 * initval's 64us ack timeout value.
1252 * This was initially only meant to work around an issue with delayed
1253 * BA frames in some implementations, but it has been found to fix ACK
1254 * timeout issues in other cases as well.
1255 */
1256 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1257 acktimeout += 64 - sifstime - ah->slottime;
1258
1259 ath9k_hw_setslottime(ah, slottime);
1260 ath9k_hw_set_ack_timeout(ah, acktimeout);
1261 ath9k_hw_set_cts_timeout(ah, acktimeout);
1262 if (ah->globaltxtimeout != (u32) -1)
1263 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1264 }
1265 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1266
1267 void ath9k_hw_deinit(struct ath_hw *ah)
1268 {
1269 struct ath_common *common = ath9k_hw_common(ah);
1270
1271 if (common->state < ATH_HW_INITIALIZED)
1272 goto free_hw;
1273
1274 if (!AR_SREV_9100(ah))
1275 ath9k_hw_ani_disable(ah);
1276
1277 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1278
1279 free_hw:
1280 if (!AR_SREV_9280_10_OR_LATER(ah))
1281 ath9k_hw_rf_free_ext_banks(ah);
1282 }
1283 EXPORT_SYMBOL(ath9k_hw_deinit);
1284
1285 /*******/
1286 /* INI */
1287 /*******/
1288
1289 static void ath9k_hw_override_ini(struct ath_hw *ah,
1290 struct ath9k_channel *chan)
1291 {
1292 u32 val;
1293
1294 /*
1295 * Set the RX_ABORT and RX_DIS and clear if off only after
1296 * RXE is set for MAC. This prevents frames with corrupted
1297 * descriptor status.
1298 */
1299 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1300
1301 if (AR_SREV_9280_10_OR_LATER(ah)) {
1302 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1303
1304 if (!AR_SREV_9271(ah))
1305 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1306
1307 if (AR_SREV_9287_10_OR_LATER(ah))
1308 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1309
1310 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1311 }
1312
1313 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1314 AR_SREV_9280_10_OR_LATER(ah))
1315 return;
1316 /*
1317 * Disable BB clock gating
1318 * Necessary to avoid issues on AR5416 2.0
1319 */
1320 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1321
1322 /*
1323 * Disable RIFS search on some chips to avoid baseband
1324 * hang issues.
1325 */
1326 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1327 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1328 val &= ~AR_PHY_RIFS_INIT_DELAY;
1329 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1330 }
1331 }
1332
1333 static void ath9k_olc_init(struct ath_hw *ah)
1334 {
1335 u32 i;
1336
1337 if (OLC_FOR_AR9287_10_LATER) {
1338 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1339 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1340 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1341 AR9287_AN_TXPC0_TXPCMODE,
1342 AR9287_AN_TXPC0_TXPCMODE_S,
1343 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1344 udelay(100);
1345 } else {
1346 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1347 ah->originalGain[i] =
1348 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1349 AR_PHY_TX_GAIN);
1350 ah->PDADCdelta = 0;
1351 }
1352 }
1353
1354 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1355 struct ath9k_channel *chan)
1356 {
1357 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1358
1359 if (IS_CHAN_B(chan))
1360 ctl |= CTL_11B;
1361 else if (IS_CHAN_G(chan))
1362 ctl |= CTL_11G;
1363 else
1364 ctl |= CTL_11A;
1365
1366 return ctl;
1367 }
1368
1369 static int ath9k_hw_process_ini(struct ath_hw *ah,
1370 struct ath9k_channel *chan)
1371 {
1372 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1373 int i, regWrites = 0;
1374 struct ieee80211_channel *channel = chan->chan;
1375 u32 modesIndex, freqIndex;
1376
1377 switch (chan->chanmode) {
1378 case CHANNEL_A:
1379 case CHANNEL_A_HT20:
1380 modesIndex = 1;
1381 freqIndex = 1;
1382 break;
1383 case CHANNEL_A_HT40PLUS:
1384 case CHANNEL_A_HT40MINUS:
1385 modesIndex = 2;
1386 freqIndex = 1;
1387 break;
1388 case CHANNEL_G:
1389 case CHANNEL_G_HT20:
1390 case CHANNEL_B:
1391 modesIndex = 4;
1392 freqIndex = 2;
1393 break;
1394 case CHANNEL_G_HT40PLUS:
1395 case CHANNEL_G_HT40MINUS:
1396 modesIndex = 3;
1397 freqIndex = 2;
1398 break;
1399
1400 default:
1401 return -EINVAL;
1402 }
1403
1404 /* Set correct baseband to analog shift setting to access analog chips */
1405 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1406
1407 /* Write ADDAC shifts */
1408 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1409 ah->eep_ops->set_addac(ah, chan);
1410
1411 if (AR_SREV_5416_22_OR_LATER(ah)) {
1412 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1413 } else {
1414 struct ar5416IniArray temp;
1415 u32 addacSize =
1416 sizeof(u32) * ah->iniAddac.ia_rows *
1417 ah->iniAddac.ia_columns;
1418
1419 /* For AR5416 2.0/2.1 */
1420 memcpy(ah->addac5416_21,
1421 ah->iniAddac.ia_array, addacSize);
1422
1423 /* override CLKDRV value at [row, column] = [31, 1] */
1424 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1425
1426 temp.ia_array = ah->addac5416_21;
1427 temp.ia_columns = ah->iniAddac.ia_columns;
1428 temp.ia_rows = ah->iniAddac.ia_rows;
1429 REG_WRITE_ARRAY(&temp, 1, regWrites);
1430 }
1431
1432 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1433
1434 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1435 u32 reg = INI_RA(&ah->iniModes, i, 0);
1436 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1437
1438 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1439 val &= ~AR_AN_TOP2_PWDCLKIND;
1440
1441 REG_WRITE(ah, reg, val);
1442
1443 if (reg >= 0x7800 && reg < 0x78a0
1444 && ah->config.analog_shiftreg) {
1445 udelay(100);
1446 }
1447
1448 DO_DELAY(regWrites);
1449 }
1450
1451 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1452 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1453
1454 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1455 AR_SREV_9287_10_OR_LATER(ah))
1456 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1457
1458 if (AR_SREV_9271_10(ah))
1459 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1460 modesIndex, regWrites);
1461
1462 /* Write common array parameters */
1463 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1464 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1465 u32 val = INI_RA(&ah->iniCommon, i, 1);
1466
1467 REG_WRITE(ah, reg, val);
1468
1469 if (reg >= 0x7800 && reg < 0x78a0
1470 && ah->config.analog_shiftreg) {
1471 udelay(100);
1472 }
1473
1474 DO_DELAY(regWrites);
1475 }
1476
1477 if (AR_SREV_9271(ah)) {
1478 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1479 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1480 modesIndex, regWrites);
1481 else
1482 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1483 modesIndex, regWrites);
1484 }
1485
1486 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1487
1488 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1489 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1490 regWrites);
1491 }
1492
1493 ath9k_hw_override_ini(ah, chan);
1494 ath9k_hw_set_regs(ah, chan);
1495 ath9k_hw_init_chain_masks(ah);
1496
1497 if (OLC_FOR_AR9280_20_LATER)
1498 ath9k_olc_init(ah);
1499
1500 /* Set TX power */
1501 ah->eep_ops->set_txpower(ah, chan,
1502 ath9k_regd_get_ctl(regulatory, chan),
1503 channel->max_antenna_gain * 2,
1504 channel->max_power * 2,
1505 min((u32) MAX_RATE_POWER,
1506 (u32) regulatory->power_limit));
1507
1508 /* Write analog registers */
1509 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1510 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1511 "ar5416SetRfRegs failed\n");
1512 return -EIO;
1513 }
1514
1515 return 0;
1516 }
1517
1518 /****************************************/
1519 /* Reset and Channel Switching Routines */
1520 /****************************************/
1521
1522 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1523 {
1524 u32 rfMode = 0;
1525
1526 if (chan == NULL)
1527 return;
1528
1529 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1530 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1531
1532 if (!AR_SREV_9280_10_OR_LATER(ah))
1533 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1534 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1535
1536 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1537 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1538
1539 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1540 }
1541
1542 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1543 {
1544 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1545 }
1546
1547 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1548 {
1549 u32 regval;
1550
1551 /*
1552 * set AHB_MODE not to do cacheline prefetches
1553 */
1554 regval = REG_READ(ah, AR_AHB_MODE);
1555 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1556
1557 /*
1558 * let mac dma reads be in 128 byte chunks
1559 */
1560 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1561 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1562
1563 /*
1564 * Restore TX Trigger Level to its pre-reset value.
1565 * The initial value depends on whether aggregation is enabled, and is
1566 * adjusted whenever underruns are detected.
1567 */
1568 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1569
1570 /*
1571 * let mac dma writes be in 128 byte chunks
1572 */
1573 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1574 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1575
1576 /*
1577 * Setup receive FIFO threshold to hold off TX activities
1578 */
1579 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1580
1581 /*
1582 * reduce the number of usable entries in PCU TXBUF to avoid
1583 * wrap around issues.
1584 */
1585 if (AR_SREV_9285(ah)) {
1586 /* For AR9285 the number of Fifos are reduced to half.
1587 * So set the usable tx buf size also to half to
1588 * avoid data/delimiter underruns
1589 */
1590 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1591 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1592 } else if (!AR_SREV_9271(ah)) {
1593 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1594 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1595 }
1596 }
1597
1598 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1599 {
1600 u32 val;
1601
1602 val = REG_READ(ah, AR_STA_ID1);
1603 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1604 switch (opmode) {
1605 case NL80211_IFTYPE_AP:
1606 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1607 | AR_STA_ID1_KSRCH_MODE);
1608 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1609 break;
1610 case NL80211_IFTYPE_ADHOC:
1611 case NL80211_IFTYPE_MESH_POINT:
1612 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1613 | AR_STA_ID1_KSRCH_MODE);
1614 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1615 break;
1616 case NL80211_IFTYPE_STATION:
1617 case NL80211_IFTYPE_MONITOR:
1618 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1619 break;
1620 }
1621 }
1622
1623 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1624 u32 coef_scaled,
1625 u32 *coef_mantissa,
1626 u32 *coef_exponent)
1627 {
1628 u32 coef_exp, coef_man;
1629
1630 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1631 if ((coef_scaled >> coef_exp) & 0x1)
1632 break;
1633
1634 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1635
1636 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1637
1638 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1639 *coef_exponent = coef_exp - 16;
1640 }
1641
1642 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1643 struct ath9k_channel *chan)
1644 {
1645 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1646 u32 clockMhzScaled = 0x64000000;
1647 struct chan_centers centers;
1648
1649 if (IS_CHAN_HALF_RATE(chan))
1650 clockMhzScaled = clockMhzScaled >> 1;
1651 else if (IS_CHAN_QUARTER_RATE(chan))
1652 clockMhzScaled = clockMhzScaled >> 2;
1653
1654 ath9k_hw_get_channel_centers(ah, chan, &centers);
1655 coef_scaled = clockMhzScaled / centers.synth_center;
1656
1657 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1658 &ds_coef_exp);
1659
1660 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1661 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1662 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1663 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1664
1665 coef_scaled = (9 * coef_scaled) / 10;
1666
1667 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1668 &ds_coef_exp);
1669
1670 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1671 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1672 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1673 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1674 }
1675
1676 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1677 {
1678 u32 rst_flags;
1679 u32 tmpReg;
1680
1681 if (AR_SREV_9100(ah)) {
1682 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1683 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1684 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1685 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1686 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1687 }
1688
1689 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1690 AR_RTC_FORCE_WAKE_ON_INT);
1691
1692 if (AR_SREV_9100(ah)) {
1693 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1694 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1695 } else {
1696 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1697 if (tmpReg &
1698 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1699 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1700 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1701 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1702 } else {
1703 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1704 }
1705
1706 rst_flags = AR_RTC_RC_MAC_WARM;
1707 if (type == ATH9K_RESET_COLD)
1708 rst_flags |= AR_RTC_RC_MAC_COLD;
1709 }
1710
1711 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1712 udelay(50);
1713
1714 REG_WRITE(ah, AR_RTC_RC, 0);
1715 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1716 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1717 "RTC stuck in MAC reset\n");
1718 return false;
1719 }
1720
1721 if (!AR_SREV_9100(ah))
1722 REG_WRITE(ah, AR_RC, 0);
1723
1724 if (AR_SREV_9100(ah))
1725 udelay(50);
1726
1727 return true;
1728 }
1729
1730 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1731 {
1732 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1733 AR_RTC_FORCE_WAKE_ON_INT);
1734
1735 if (!AR_SREV_9100(ah))
1736 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1737
1738 REG_WRITE(ah, AR_RTC_RESET, 0);
1739 udelay(2);
1740
1741 if (!AR_SREV_9100(ah))
1742 REG_WRITE(ah, AR_RC, 0);
1743
1744 REG_WRITE(ah, AR_RTC_RESET, 1);
1745
1746 if (!ath9k_hw_wait(ah,
1747 AR_RTC_STATUS,
1748 AR_RTC_STATUS_M,
1749 AR_RTC_STATUS_ON,
1750 AH_WAIT_TIMEOUT)) {
1751 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1752 "RTC not waking up\n");
1753 return false;
1754 }
1755
1756 ath9k_hw_read_revisions(ah);
1757
1758 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1759 }
1760
1761 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1762 {
1763 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1764 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1765
1766 switch (type) {
1767 case ATH9K_RESET_POWER_ON:
1768 return ath9k_hw_set_reset_power_on(ah);
1769 case ATH9K_RESET_WARM:
1770 case ATH9K_RESET_COLD:
1771 return ath9k_hw_set_reset(ah, type);
1772 default:
1773 return false;
1774 }
1775 }
1776
1777 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1778 {
1779 u32 phymode;
1780 u32 enableDacFifo = 0;
1781
1782 if (AR_SREV_9285_10_OR_LATER(ah))
1783 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1784 AR_PHY_FC_ENABLE_DAC_FIFO);
1785
1786 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1787 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1788
1789 if (IS_CHAN_HT40(chan)) {
1790 phymode |= AR_PHY_FC_DYN2040_EN;
1791
1792 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1793 (chan->chanmode == CHANNEL_G_HT40PLUS))
1794 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1795
1796 }
1797 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1798
1799 ath9k_hw_set11nmac2040(ah);
1800
1801 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1802 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1803 }
1804
1805 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1806 struct ath9k_channel *chan)
1807 {
1808 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1809 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1810 return false;
1811 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1812 return false;
1813
1814 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1815 return false;
1816
1817 ah->chip_fullsleep = false;
1818 ath9k_hw_init_pll(ah, chan);
1819 ath9k_hw_set_rfmode(ah, chan);
1820
1821 return true;
1822 }
1823
1824 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1825 struct ath9k_channel *chan)
1826 {
1827 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1828 struct ath_common *common = ath9k_hw_common(ah);
1829 struct ieee80211_channel *channel = chan->chan;
1830 u32 synthDelay, qnum;
1831 int r;
1832
1833 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1834 if (ath9k_hw_numtxpending(ah, qnum)) {
1835 ath_print(common, ATH_DBG_QUEUE,
1836 "Transmit frames pending on "
1837 "queue %d\n", qnum);
1838 return false;
1839 }
1840 }
1841
1842 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1843 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1844 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1845 ath_print(common, ATH_DBG_FATAL,
1846 "Could not kill baseband RX\n");
1847 return false;
1848 }
1849
1850 ath9k_hw_set_regs(ah, chan);
1851
1852 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1853 if (r) {
1854 ath_print(common, ATH_DBG_FATAL,
1855 "Failed to set channel\n");
1856 return false;
1857 }
1858
1859 ah->eep_ops->set_txpower(ah, chan,
1860 ath9k_regd_get_ctl(regulatory, chan),
1861 channel->max_antenna_gain * 2,
1862 channel->max_power * 2,
1863 min((u32) MAX_RATE_POWER,
1864 (u32) regulatory->power_limit));
1865
1866 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1867 if (IS_CHAN_B(chan))
1868 synthDelay = (4 * synthDelay) / 22;
1869 else
1870 synthDelay /= 10;
1871
1872 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1873
1874 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1875
1876 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1877 ath9k_hw_set_delta_slope(ah, chan);
1878
1879 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1880
1881 if (!chan->oneTimeCalsDone)
1882 chan->oneTimeCalsDone = true;
1883
1884 return true;
1885 }
1886
1887 static void ath9k_enable_rfkill(struct ath_hw *ah)
1888 {
1889 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1890 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1891
1892 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1893 AR_GPIO_INPUT_MUX2_RFSILENT);
1894
1895 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1896 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1897 }
1898
1899 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1900 bool bChannelChange)
1901 {
1902 struct ath_common *common = ath9k_hw_common(ah);
1903 u32 saveLedState;
1904 struct ath9k_channel *curchan = ah->curchan;
1905 u32 saveDefAntenna;
1906 u32 macStaId1;
1907 u64 tsf = 0;
1908 int i, rx_chainmask, r;
1909
1910 ah->txchainmask = common->tx_chainmask;
1911 ah->rxchainmask = common->rx_chainmask;
1912
1913 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1914 return -EIO;
1915
1916 if (curchan && !ah->chip_fullsleep)
1917 ath9k_hw_getnf(ah, curchan);
1918
1919 if (bChannelChange &&
1920 (ah->chip_fullsleep != true) &&
1921 (ah->curchan != NULL) &&
1922 (chan->channel != ah->curchan->channel) &&
1923 ((chan->channelFlags & CHANNEL_ALL) ==
1924 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1925 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1926 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1927
1928 if (ath9k_hw_channel_change(ah, chan)) {
1929 ath9k_hw_loadnf(ah, ah->curchan);
1930 ath9k_hw_start_nfcal(ah);
1931 return 0;
1932 }
1933 }
1934
1935 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1936 if (saveDefAntenna == 0)
1937 saveDefAntenna = 1;
1938
1939 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1940
1941 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1942 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1943 tsf = ath9k_hw_gettsf64(ah);
1944
1945 saveLedState = REG_READ(ah, AR_CFG_LED) &
1946 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1947 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1948
1949 ath9k_hw_mark_phy_inactive(ah);
1950
1951 /* Only required on the first reset */
1952 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1953 REG_WRITE(ah,
1954 AR9271_RESET_POWER_DOWN_CONTROL,
1955 AR9271_RADIO_RF_RST);
1956 udelay(50);
1957 }
1958
1959 if (!ath9k_hw_chip_reset(ah, chan)) {
1960 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1961 return -EINVAL;
1962 }
1963
1964 /* Only required on the first reset */
1965 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1966 ah->htc_reset_init = false;
1967 REG_WRITE(ah,
1968 AR9271_RESET_POWER_DOWN_CONTROL,
1969 AR9271_GATE_MAC_CTL);
1970 udelay(50);
1971 }
1972
1973 /* Restore TSF */
1974 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1975 ath9k_hw_settsf64(ah, tsf);
1976
1977 if (AR_SREV_9280_10_OR_LATER(ah))
1978 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1979
1980 if (AR_SREV_9287_12_OR_LATER(ah)) {
1981 /* Enable ASYNC FIFO */
1982 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1983 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1984 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1985 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1986 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1987 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1988 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1989 }
1990 r = ath9k_hw_process_ini(ah, chan);
1991 if (r)
1992 return r;
1993
1994 /* Setup MFP options for CCMP */
1995 if (AR_SREV_9280_20_OR_LATER(ah)) {
1996 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1997 * frames when constructing CCMP AAD. */
1998 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1999 0xc7ff);
2000 ah->sw_mgmt_crypto = false;
2001 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2002 /* Disable hardware crypto for management frames */
2003 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2004 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2005 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2006 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2007 ah->sw_mgmt_crypto = true;
2008 } else
2009 ah->sw_mgmt_crypto = true;
2010
2011 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2012 ath9k_hw_set_delta_slope(ah, chan);
2013
2014 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2015 ah->eep_ops->set_board_values(ah, chan);
2016
2017 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2018 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2019 | macStaId1
2020 | AR_STA_ID1_RTS_USE_DEF
2021 | (ah->config.
2022 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2023 | ah->sta_id1_defaults);
2024 ath9k_hw_set_operating_mode(ah, ah->opmode);
2025
2026 ath_hw_setbssidmask(common);
2027
2028 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2029
2030 ath9k_hw_write_associd(ah);
2031
2032 REG_WRITE(ah, AR_ISR, ~0);
2033
2034 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2035
2036 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2037 if (r)
2038 return r;
2039
2040 for (i = 0; i < AR_NUM_DCU; i++)
2041 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2042
2043 ah->intr_txqs = 0;
2044 for (i = 0; i < ah->caps.total_queues; i++)
2045 ath9k_hw_resettxqueue(ah, i);
2046
2047 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2048 ath9k_hw_init_qos(ah);
2049
2050 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2051 ath9k_enable_rfkill(ah);
2052
2053 ath9k_hw_init_global_settings(ah);
2054
2055 if (AR_SREV_9287_12_OR_LATER(ah)) {
2056 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2057 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2058 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2059 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2060 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2061 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2062
2063 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2064 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2065
2066 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2067 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2068 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2069 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2070 }
2071 if (AR_SREV_9287_12_OR_LATER(ah)) {
2072 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2073 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2074 }
2075
2076 REG_WRITE(ah, AR_STA_ID1,
2077 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2078
2079 ath9k_hw_set_dma(ah);
2080
2081 REG_WRITE(ah, AR_OBS, 8);
2082
2083 if (ah->config.rx_intr_mitigation) {
2084 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2085 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2086 }
2087
2088 ath9k_hw_init_bb(ah, chan);
2089
2090 if (!ath9k_hw_init_cal(ah, chan))
2091 return -EIO;
2092
2093 rx_chainmask = ah->rxchainmask;
2094 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2095 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2096 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2097 }
2098
2099 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2100
2101 /*
2102 * For big endian systems turn on swapping for descriptors
2103 */
2104 if (AR_SREV_9100(ah)) {
2105 u32 mask;
2106 mask = REG_READ(ah, AR_CFG);
2107 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2108 ath_print(common, ATH_DBG_RESET,
2109 "CFG Byte Swap Set 0x%x\n", mask);
2110 } else {
2111 mask =
2112 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2113 REG_WRITE(ah, AR_CFG, mask);
2114 ath_print(common, ATH_DBG_RESET,
2115 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2116 }
2117 } else {
2118 /* Configure AR9271 target WLAN */
2119 if (AR_SREV_9271(ah))
2120 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2121 #ifdef __BIG_ENDIAN
2122 else
2123 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2124 #endif
2125 }
2126
2127 if (ah->btcoex_hw.enabled)
2128 ath9k_hw_btcoex_enable(ah);
2129
2130 return 0;
2131 }
2132 EXPORT_SYMBOL(ath9k_hw_reset);
2133
2134 /************************/
2135 /* Key Cache Management */
2136 /************************/
2137
2138 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2139 {
2140 u32 keyType;
2141
2142 if (entry >= ah->caps.keycache_size) {
2143 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2144 "keychache entry %u out of range\n", entry);
2145 return false;
2146 }
2147
2148 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2149
2150 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2151 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2152 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2153 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2154 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2155 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2156 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2157 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2158
2159 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2160 u16 micentry = entry + 64;
2161
2162 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2163 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2164 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2165 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2166
2167 }
2168
2169 return true;
2170 }
2171 EXPORT_SYMBOL(ath9k_hw_keyreset);
2172
2173 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2174 {
2175 u32 macHi, macLo;
2176
2177 if (entry >= ah->caps.keycache_size) {
2178 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2179 "keychache entry %u out of range\n", entry);
2180 return false;
2181 }
2182
2183 if (mac != NULL) {
2184 macHi = (mac[5] << 8) | mac[4];
2185 macLo = (mac[3] << 24) |
2186 (mac[2] << 16) |
2187 (mac[1] << 8) |
2188 mac[0];
2189 macLo >>= 1;
2190 macLo |= (macHi & 1) << 31;
2191 macHi >>= 1;
2192 } else {
2193 macLo = macHi = 0;
2194 }
2195 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2196 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2197
2198 return true;
2199 }
2200 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2201
2202 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2203 const struct ath9k_keyval *k,
2204 const u8 *mac)
2205 {
2206 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2207 struct ath_common *common = ath9k_hw_common(ah);
2208 u32 key0, key1, key2, key3, key4;
2209 u32 keyType;
2210
2211 if (entry >= pCap->keycache_size) {
2212 ath_print(common, ATH_DBG_FATAL,
2213 "keycache entry %u out of range\n", entry);
2214 return false;
2215 }
2216
2217 switch (k->kv_type) {
2218 case ATH9K_CIPHER_AES_OCB:
2219 keyType = AR_KEYTABLE_TYPE_AES;
2220 break;
2221 case ATH9K_CIPHER_AES_CCM:
2222 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2223 ath_print(common, ATH_DBG_ANY,
2224 "AES-CCM not supported by mac rev 0x%x\n",
2225 ah->hw_version.macRev);
2226 return false;
2227 }
2228 keyType = AR_KEYTABLE_TYPE_CCM;
2229 break;
2230 case ATH9K_CIPHER_TKIP:
2231 keyType = AR_KEYTABLE_TYPE_TKIP;
2232 if (ATH9K_IS_MIC_ENABLED(ah)
2233 && entry + 64 >= pCap->keycache_size) {
2234 ath_print(common, ATH_DBG_ANY,
2235 "entry %u inappropriate for TKIP\n", entry);
2236 return false;
2237 }
2238 break;
2239 case ATH9K_CIPHER_WEP:
2240 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2241 ath_print(common, ATH_DBG_ANY,
2242 "WEP key length %u too small\n", k->kv_len);
2243 return false;
2244 }
2245 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2246 keyType = AR_KEYTABLE_TYPE_40;
2247 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2248 keyType = AR_KEYTABLE_TYPE_104;
2249 else
2250 keyType = AR_KEYTABLE_TYPE_128;
2251 break;
2252 case ATH9K_CIPHER_CLR:
2253 keyType = AR_KEYTABLE_TYPE_CLR;
2254 break;
2255 default:
2256 ath_print(common, ATH_DBG_FATAL,
2257 "cipher %u not supported\n", k->kv_type);
2258 return false;
2259 }
2260
2261 key0 = get_unaligned_le32(k->kv_val + 0);
2262 key1 = get_unaligned_le16(k->kv_val + 4);
2263 key2 = get_unaligned_le32(k->kv_val + 6);
2264 key3 = get_unaligned_le16(k->kv_val + 10);
2265 key4 = get_unaligned_le32(k->kv_val + 12);
2266 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2267 key4 &= 0xff;
2268
2269 /*
2270 * Note: Key cache registers access special memory area that requires
2271 * two 32-bit writes to actually update the values in the internal
2272 * memory. Consequently, the exact order and pairs used here must be
2273 * maintained.
2274 */
2275
2276 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2277 u16 micentry = entry + 64;
2278
2279 /*
2280 * Write inverted key[47:0] first to avoid Michael MIC errors
2281 * on frames that could be sent or received at the same time.
2282 * The correct key will be written in the end once everything
2283 * else is ready.
2284 */
2285 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2286 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2287
2288 /* Write key[95:48] */
2289 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2290 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2291
2292 /* Write key[127:96] and key type */
2293 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2294 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2295
2296 /* Write MAC address for the entry */
2297 (void) ath9k_hw_keysetmac(ah, entry, mac);
2298
2299 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2300 /*
2301 * TKIP uses two key cache entries:
2302 * Michael MIC TX/RX keys in the same key cache entry
2303 * (idx = main index + 64):
2304 * key0 [31:0] = RX key [31:0]
2305 * key1 [15:0] = TX key [31:16]
2306 * key1 [31:16] = reserved
2307 * key2 [31:0] = RX key [63:32]
2308 * key3 [15:0] = TX key [15:0]
2309 * key3 [31:16] = reserved
2310 * key4 [31:0] = TX key [63:32]
2311 */
2312 u32 mic0, mic1, mic2, mic3, mic4;
2313
2314 mic0 = get_unaligned_le32(k->kv_mic + 0);
2315 mic2 = get_unaligned_le32(k->kv_mic + 4);
2316 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2317 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2318 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2319
2320 /* Write RX[31:0] and TX[31:16] */
2321 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2322 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2323
2324 /* Write RX[63:32] and TX[15:0] */
2325 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2326 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2327
2328 /* Write TX[63:32] and keyType(reserved) */
2329 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2330 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2331 AR_KEYTABLE_TYPE_CLR);
2332
2333 } else {
2334 /*
2335 * TKIP uses four key cache entries (two for group
2336 * keys):
2337 * Michael MIC TX/RX keys are in different key cache
2338 * entries (idx = main index + 64 for TX and
2339 * main index + 32 + 96 for RX):
2340 * key0 [31:0] = TX/RX MIC key [31:0]
2341 * key1 [31:0] = reserved
2342 * key2 [31:0] = TX/RX MIC key [63:32]
2343 * key3 [31:0] = reserved
2344 * key4 [31:0] = reserved
2345 *
2346 * Upper layer code will call this function separately
2347 * for TX and RX keys when these registers offsets are
2348 * used.
2349 */
2350 u32 mic0, mic2;
2351
2352 mic0 = get_unaligned_le32(k->kv_mic + 0);
2353 mic2 = get_unaligned_le32(k->kv_mic + 4);
2354
2355 /* Write MIC key[31:0] */
2356 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2357 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2358
2359 /* Write MIC key[63:32] */
2360 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2361 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2362
2363 /* Write TX[63:32] and keyType(reserved) */
2364 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2365 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2366 AR_KEYTABLE_TYPE_CLR);
2367 }
2368
2369 /* MAC address registers are reserved for the MIC entry */
2370 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2371 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2372
2373 /*
2374 * Write the correct (un-inverted) key[47:0] last to enable
2375 * TKIP now that all other registers are set with correct
2376 * values.
2377 */
2378 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2379 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2380 } else {
2381 /* Write key[47:0] */
2382 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2383 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2384
2385 /* Write key[95:48] */
2386 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2387 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2388
2389 /* Write key[127:96] and key type */
2390 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2391 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2392
2393 /* Write MAC address for the entry */
2394 (void) ath9k_hw_keysetmac(ah, entry, mac);
2395 }
2396
2397 return true;
2398 }
2399 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2400
2401 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2402 {
2403 if (entry < ah->caps.keycache_size) {
2404 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2405 if (val & AR_KEYTABLE_VALID)
2406 return true;
2407 }
2408 return false;
2409 }
2410 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2411
2412 /******************************/
2413 /* Power Management (Chipset) */
2414 /******************************/
2415
2416 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2417 {
2418 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2419 if (setChip) {
2420 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2421 AR_RTC_FORCE_WAKE_EN);
2422 if (!AR_SREV_9100(ah))
2423 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2424
2425 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2426 REG_CLR_BIT(ah, (AR_RTC_RESET),
2427 AR_RTC_RESET_EN);
2428 }
2429 }
2430
2431 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2432 {
2433 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2434 if (setChip) {
2435 struct ath9k_hw_capabilities *pCap = &ah->caps;
2436
2437 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2438 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2439 AR_RTC_FORCE_WAKE_ON_INT);
2440 } else {
2441 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2442 AR_RTC_FORCE_WAKE_EN);
2443 }
2444 }
2445 }
2446
2447 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2448 {
2449 u32 val;
2450 int i;
2451
2452 if (setChip) {
2453 if ((REG_READ(ah, AR_RTC_STATUS) &
2454 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2455 if (ath9k_hw_set_reset_reg(ah,
2456 ATH9K_RESET_POWER_ON) != true) {
2457 return false;
2458 }
2459 ath9k_hw_init_pll(ah, NULL);
2460 }
2461 if (AR_SREV_9100(ah))
2462 REG_SET_BIT(ah, AR_RTC_RESET,
2463 AR_RTC_RESET_EN);
2464
2465 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2466 AR_RTC_FORCE_WAKE_EN);
2467 udelay(50);
2468
2469 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2470 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2471 if (val == AR_RTC_STATUS_ON)
2472 break;
2473 udelay(50);
2474 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2475 AR_RTC_FORCE_WAKE_EN);
2476 }
2477 if (i == 0) {
2478 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2479 "Failed to wakeup in %uus\n",
2480 POWER_UP_TIME / 20);
2481 return false;
2482 }
2483 }
2484
2485 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2486
2487 return true;
2488 }
2489
2490 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2491 {
2492 struct ath_common *common = ath9k_hw_common(ah);
2493 int status = true, setChip = true;
2494 static const char *modes[] = {
2495 "AWAKE",
2496 "FULL-SLEEP",
2497 "NETWORK SLEEP",
2498 "UNDEFINED"
2499 };
2500
2501 if (ah->power_mode == mode)
2502 return status;
2503
2504 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2505 modes[ah->power_mode], modes[mode]);
2506
2507 switch (mode) {
2508 case ATH9K_PM_AWAKE:
2509 status = ath9k_hw_set_power_awake(ah, setChip);
2510 break;
2511 case ATH9K_PM_FULL_SLEEP:
2512 ath9k_set_power_sleep(ah, setChip);
2513 ah->chip_fullsleep = true;
2514 break;
2515 case ATH9K_PM_NETWORK_SLEEP:
2516 ath9k_set_power_network_sleep(ah, setChip);
2517 break;
2518 default:
2519 ath_print(common, ATH_DBG_FATAL,
2520 "Unknown power mode %u\n", mode);
2521 return false;
2522 }
2523 ah->power_mode = mode;
2524
2525 return status;
2526 }
2527 EXPORT_SYMBOL(ath9k_hw_setpower);
2528
2529 /*
2530 * Helper for ASPM support.
2531 *
2532 * Disable PLL when in L0s as well as receiver clock when in L1.
2533 * This power saving option must be enabled through the SerDes.
2534 *
2535 * Programming the SerDes must go through the same 288 bit serial shift
2536 * register as the other analog registers. Hence the 9 writes.
2537 */
2538 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
2539 int restore,
2540 int power_off)
2541 {
2542 u8 i;
2543 u32 val;
2544
2545 if (ah->is_pciexpress != true)
2546 return;
2547
2548 /* Do not touch SerDes registers */
2549 if (ah->config.pcie_powersave_enable == 2)
2550 return;
2551
2552 /* Nothing to do on restore for 11N */
2553 if (!restore) {
2554 if (AR_SREV_9280_20_OR_LATER(ah)) {
2555 /*
2556 * AR9280 2.0 or later chips use SerDes values from the
2557 * initvals.h initialized depending on chipset during
2558 * __ath9k_hw_init()
2559 */
2560 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2561 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2562 INI_RA(&ah->iniPcieSerdes, i, 1));
2563 }
2564 } else if (AR_SREV_9280(ah) &&
2565 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2566 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2567 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2568
2569 /* RX shut off when elecidle is asserted */
2570 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2571 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2572 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2573
2574 /* Shut off CLKREQ active in L1 */
2575 if (ah->config.pcie_clock_req)
2576 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2577 else
2578 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2579
2580 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2581 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2582 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2583
2584 /* Load the new settings */
2585 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2586
2587 } else {
2588 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2589 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2590
2591 /* RX shut off when elecidle is asserted */
2592 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2593 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2594 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2595
2596 /*
2597 * Ignore ah->ah_config.pcie_clock_req setting for
2598 * pre-AR9280 11n
2599 */
2600 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2601
2602 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2603 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2604 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2605
2606 /* Load the new settings */
2607 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2608 }
2609
2610 udelay(1000);
2611
2612 /* set bit 19 to allow forcing of pcie core into L1 state */
2613 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2614
2615 /* Several PCIe massages to ensure proper behaviour */
2616 if (ah->config.pcie_waen) {
2617 val = ah->config.pcie_waen;
2618 if (!power_off)
2619 val &= (~AR_WA_D3_L1_DISABLE);
2620 } else {
2621 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2622 AR_SREV_9287(ah)) {
2623 val = AR9285_WA_DEFAULT;
2624 if (!power_off)
2625 val &= (~AR_WA_D3_L1_DISABLE);
2626 } else if (AR_SREV_9280(ah)) {
2627 /*
2628 * On AR9280 chips bit 22 of 0x4004 needs to be
2629 * set otherwise card may disappear.
2630 */
2631 val = AR9280_WA_DEFAULT;
2632 if (!power_off)
2633 val &= (~AR_WA_D3_L1_DISABLE);
2634 } else
2635 val = AR_WA_DEFAULT;
2636 }
2637
2638 REG_WRITE(ah, AR_WA, val);
2639 }
2640
2641 if (power_off) {
2642 /*
2643 * Set PCIe workaround bits
2644 * bit 14 in WA register (disable L1) should only
2645 * be set when device enters D3 and be cleared
2646 * when device comes back to D0.
2647 */
2648 if (ah->config.pcie_waen) {
2649 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2650 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2651 } else {
2652 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2653 AR_SREV_9287(ah)) &&
2654 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2655 (AR_SREV_9280(ah) &&
2656 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2657 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2658 }
2659 }
2660 }
2661 }
2662
2663 /**********************/
2664 /* Interrupt Handling */
2665 /**********************/
2666
2667 bool ath9k_hw_intrpend(struct ath_hw *ah)
2668 {
2669 u32 host_isr;
2670
2671 if (AR_SREV_9100(ah))
2672 return true;
2673
2674 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2675 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2676 return true;
2677
2678 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2679 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2680 && (host_isr != AR_INTR_SPURIOUS))
2681 return true;
2682
2683 return false;
2684 }
2685 EXPORT_SYMBOL(ath9k_hw_intrpend);
2686
2687 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2688 {
2689 u32 isr = 0;
2690 u32 mask2 = 0;
2691 struct ath9k_hw_capabilities *pCap = &ah->caps;
2692 u32 sync_cause = 0;
2693 bool fatal_int = false;
2694 struct ath_common *common = ath9k_hw_common(ah);
2695
2696 if (!AR_SREV_9100(ah)) {
2697 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2698 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2699 == AR_RTC_STATUS_ON) {
2700 isr = REG_READ(ah, AR_ISR);
2701 }
2702 }
2703
2704 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2705 AR_INTR_SYNC_DEFAULT;
2706
2707 *masked = 0;
2708
2709 if (!isr && !sync_cause)
2710 return false;
2711 } else {
2712 *masked = 0;
2713 isr = REG_READ(ah, AR_ISR);
2714 }
2715
2716 if (isr) {
2717 if (isr & AR_ISR_BCNMISC) {
2718 u32 isr2;
2719 isr2 = REG_READ(ah, AR_ISR_S2);
2720 if (isr2 & AR_ISR_S2_TIM)
2721 mask2 |= ATH9K_INT_TIM;
2722 if (isr2 & AR_ISR_S2_DTIM)
2723 mask2 |= ATH9K_INT_DTIM;
2724 if (isr2 & AR_ISR_S2_DTIMSYNC)
2725 mask2 |= ATH9K_INT_DTIMSYNC;
2726 if (isr2 & (AR_ISR_S2_CABEND))
2727 mask2 |= ATH9K_INT_CABEND;
2728 if (isr2 & AR_ISR_S2_GTT)
2729 mask2 |= ATH9K_INT_GTT;
2730 if (isr2 & AR_ISR_S2_CST)
2731 mask2 |= ATH9K_INT_CST;
2732 if (isr2 & AR_ISR_S2_TSFOOR)
2733 mask2 |= ATH9K_INT_TSFOOR;
2734 }
2735
2736 isr = REG_READ(ah, AR_ISR_RAC);
2737 if (isr == 0xffffffff) {
2738 *masked = 0;
2739 return false;
2740 }
2741
2742 *masked = isr & ATH9K_INT_COMMON;
2743
2744 if (ah->config.rx_intr_mitigation) {
2745 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2746 *masked |= ATH9K_INT_RX;
2747 }
2748
2749 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2750 *masked |= ATH9K_INT_RX;
2751 if (isr &
2752 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2753 AR_ISR_TXEOL)) {
2754 u32 s0_s, s1_s;
2755
2756 *masked |= ATH9K_INT_TX;
2757
2758 s0_s = REG_READ(ah, AR_ISR_S0_S);
2759 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2760 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2761
2762 s1_s = REG_READ(ah, AR_ISR_S1_S);
2763 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2764 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2765 }
2766
2767 if (isr & AR_ISR_RXORN) {
2768 ath_print(common, ATH_DBG_INTERRUPT,
2769 "receive FIFO overrun interrupt\n");
2770 }
2771
2772 if (!AR_SREV_9100(ah)) {
2773 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2774 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2775 if (isr5 & AR_ISR_S5_TIM_TIMER)
2776 *masked |= ATH9K_INT_TIM_TIMER;
2777 }
2778 }
2779
2780 *masked |= mask2;
2781 }
2782
2783 if (AR_SREV_9100(ah))
2784 return true;
2785
2786 if (isr & AR_ISR_GENTMR) {
2787 u32 s5_s;
2788
2789 s5_s = REG_READ(ah, AR_ISR_S5_S);
2790 if (isr & AR_ISR_GENTMR) {
2791 ah->intr_gen_timer_trigger =
2792 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2793
2794 ah->intr_gen_timer_thresh =
2795 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2796
2797 if (ah->intr_gen_timer_trigger)
2798 *masked |= ATH9K_INT_GENTIMER;
2799
2800 }
2801 }
2802
2803 if (sync_cause) {
2804 fatal_int =
2805 (sync_cause &
2806 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2807 ? true : false;
2808
2809 if (fatal_int) {
2810 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2811 ath_print(common, ATH_DBG_ANY,
2812 "received PCI FATAL interrupt\n");
2813 }
2814 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2815 ath_print(common, ATH_DBG_ANY,
2816 "received PCI PERR interrupt\n");
2817 }
2818 *masked |= ATH9K_INT_FATAL;
2819 }
2820 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2821 ath_print(common, ATH_DBG_INTERRUPT,
2822 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2823 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2824 REG_WRITE(ah, AR_RC, 0);
2825 *masked |= ATH9K_INT_FATAL;
2826 }
2827 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2828 ath_print(common, ATH_DBG_INTERRUPT,
2829 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2830 }
2831
2832 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2833 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2834 }
2835
2836 return true;
2837 }
2838 EXPORT_SYMBOL(ath9k_hw_getisr);
2839
2840 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2841 {
2842 enum ath9k_int omask = ah->imask;
2843 u32 mask, mask2;
2844 struct ath9k_hw_capabilities *pCap = &ah->caps;
2845 struct ath_common *common = ath9k_hw_common(ah);
2846
2847 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2848
2849 if (omask & ATH9K_INT_GLOBAL) {
2850 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2851 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2852 (void) REG_READ(ah, AR_IER);
2853 if (!AR_SREV_9100(ah)) {
2854 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2855 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2856
2857 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2858 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2859 }
2860 }
2861
2862 mask = ints & ATH9K_INT_COMMON;
2863 mask2 = 0;
2864
2865 if (ints & ATH9K_INT_TX) {
2866 if (ah->txok_interrupt_mask)
2867 mask |= AR_IMR_TXOK;
2868 if (ah->txdesc_interrupt_mask)
2869 mask |= AR_IMR_TXDESC;
2870 if (ah->txerr_interrupt_mask)
2871 mask |= AR_IMR_TXERR;
2872 if (ah->txeol_interrupt_mask)
2873 mask |= AR_IMR_TXEOL;
2874 }
2875 if (ints & ATH9K_INT_RX) {
2876 mask |= AR_IMR_RXERR;
2877 if (ah->config.rx_intr_mitigation)
2878 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2879 else
2880 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2881 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2882 mask |= AR_IMR_GENTMR;
2883 }
2884
2885 if (ints & (ATH9K_INT_BMISC)) {
2886 mask |= AR_IMR_BCNMISC;
2887 if (ints & ATH9K_INT_TIM)
2888 mask2 |= AR_IMR_S2_TIM;
2889 if (ints & ATH9K_INT_DTIM)
2890 mask2 |= AR_IMR_S2_DTIM;
2891 if (ints & ATH9K_INT_DTIMSYNC)
2892 mask2 |= AR_IMR_S2_DTIMSYNC;
2893 if (ints & ATH9K_INT_CABEND)
2894 mask2 |= AR_IMR_S2_CABEND;
2895 if (ints & ATH9K_INT_TSFOOR)
2896 mask2 |= AR_IMR_S2_TSFOOR;
2897 }
2898
2899 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2900 mask |= AR_IMR_BCNMISC;
2901 if (ints & ATH9K_INT_GTT)
2902 mask2 |= AR_IMR_S2_GTT;
2903 if (ints & ATH9K_INT_CST)
2904 mask2 |= AR_IMR_S2_CST;
2905 }
2906
2907 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2908 REG_WRITE(ah, AR_IMR, mask);
2909 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2910 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2911 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2912 ah->imrs2_reg |= mask2;
2913 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2914
2915 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2916 if (ints & ATH9K_INT_TIM_TIMER)
2917 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2918 else
2919 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2920 }
2921
2922 if (ints & ATH9K_INT_GLOBAL) {
2923 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2924 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2925 if (!AR_SREV_9100(ah)) {
2926 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2927 AR_INTR_MAC_IRQ);
2928 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2929
2930
2931 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2932 AR_INTR_SYNC_DEFAULT);
2933 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2934 AR_INTR_SYNC_DEFAULT);
2935 }
2936 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2937 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2938 }
2939
2940 return omask;
2941 }
2942 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2943
2944 /*******************/
2945 /* Beacon Handling */
2946 /*******************/
2947
2948 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2949 {
2950 int flags = 0;
2951
2952 ah->beacon_interval = beacon_period;
2953
2954 switch (ah->opmode) {
2955 case NL80211_IFTYPE_STATION:
2956 case NL80211_IFTYPE_MONITOR:
2957 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2958 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2959 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2960 flags |= AR_TBTT_TIMER_EN;
2961 break;
2962 case NL80211_IFTYPE_ADHOC:
2963 case NL80211_IFTYPE_MESH_POINT:
2964 REG_SET_BIT(ah, AR_TXCFG,
2965 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2966 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2967 TU_TO_USEC(next_beacon +
2968 (ah->atim_window ? ah->
2969 atim_window : 1)));
2970 flags |= AR_NDP_TIMER_EN;
2971 case NL80211_IFTYPE_AP:
2972 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2973 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2974 TU_TO_USEC(next_beacon -
2975 ah->config.
2976 dma_beacon_response_time));
2977 REG_WRITE(ah, AR_NEXT_SWBA,
2978 TU_TO_USEC(next_beacon -
2979 ah->config.
2980 sw_beacon_response_time));
2981 flags |=
2982 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2983 break;
2984 default:
2985 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2986 "%s: unsupported opmode: %d\n",
2987 __func__, ah->opmode);
2988 return;
2989 break;
2990 }
2991
2992 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2993 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2994 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2995 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2996
2997 beacon_period &= ~ATH9K_BEACON_ENA;
2998 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2999 ath9k_hw_reset_tsf(ah);
3000 }
3001
3002 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3003 }
3004 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3005
3006 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3007 const struct ath9k_beacon_state *bs)
3008 {
3009 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3010 struct ath9k_hw_capabilities *pCap = &ah->caps;
3011 struct ath_common *common = ath9k_hw_common(ah);
3012
3013 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3014
3015 REG_WRITE(ah, AR_BEACON_PERIOD,
3016 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3017 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3018 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3019
3020 REG_RMW_FIELD(ah, AR_RSSI_THR,
3021 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3022
3023 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3024
3025 if (bs->bs_sleepduration > beaconintval)
3026 beaconintval = bs->bs_sleepduration;
3027
3028 dtimperiod = bs->bs_dtimperiod;
3029 if (bs->bs_sleepduration > dtimperiod)
3030 dtimperiod = bs->bs_sleepduration;
3031
3032 if (beaconintval == dtimperiod)
3033 nextTbtt = bs->bs_nextdtim;
3034 else
3035 nextTbtt = bs->bs_nexttbtt;
3036
3037 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3038 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3039 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3040 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3041
3042 REG_WRITE(ah, AR_NEXT_DTIM,
3043 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3044 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3045
3046 REG_WRITE(ah, AR_SLEEP1,
3047 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3048 | AR_SLEEP1_ASSUME_DTIM);
3049
3050 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3051 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3052 else
3053 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3054
3055 REG_WRITE(ah, AR_SLEEP2,
3056 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3057
3058 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3059 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3060
3061 REG_SET_BIT(ah, AR_TIMER_MODE,
3062 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3063 AR_DTIM_TIMER_EN);
3064
3065 /* TSF Out of Range Threshold */
3066 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3067 }
3068 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3069
3070 /*******************/
3071 /* HW Capabilities */
3072 /*******************/
3073
3074 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3075 {
3076 struct ath9k_hw_capabilities *pCap = &ah->caps;
3077 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3078 struct ath_common *common = ath9k_hw_common(ah);
3079 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3080
3081 u16 capField = 0, eeval;
3082
3083 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3084 regulatory->current_rd = eeval;
3085
3086 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3087 if (AR_SREV_9285_10_OR_LATER(ah))
3088 eeval |= AR9285_RDEXT_DEFAULT;
3089 regulatory->current_rd_ext = eeval;
3090
3091 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3092
3093 if (ah->opmode != NL80211_IFTYPE_AP &&
3094 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3095 if (regulatory->current_rd == 0x64 ||
3096 regulatory->current_rd == 0x65)
3097 regulatory->current_rd += 5;
3098 else if (regulatory->current_rd == 0x41)
3099 regulatory->current_rd = 0x43;
3100 ath_print(common, ATH_DBG_REGULATORY,
3101 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3102 }
3103
3104 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3105 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3106 ath_print(common, ATH_DBG_FATAL,
3107 "no band has been marked as supported in EEPROM.\n");
3108 return -EINVAL;
3109 }
3110
3111 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3112
3113 if (eeval & AR5416_OPFLAGS_11A) {
3114 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3115 if (ah->config.ht_enable) {
3116 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3117 set_bit(ATH9K_MODE_11NA_HT20,
3118 pCap->wireless_modes);
3119 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3120 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3121 pCap->wireless_modes);
3122 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3123 pCap->wireless_modes);
3124 }
3125 }
3126 }
3127
3128 if (eeval & AR5416_OPFLAGS_11G) {
3129 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3130 if (ah->config.ht_enable) {
3131 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3132 set_bit(ATH9K_MODE_11NG_HT20,
3133 pCap->wireless_modes);
3134 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3135 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3136 pCap->wireless_modes);
3137 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3138 pCap->wireless_modes);
3139 }
3140 }
3141 }
3142
3143 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3144 /*
3145 * For AR9271 we will temporarilly uses the rx chainmax as read from
3146 * the EEPROM.
3147 */
3148 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3149 !(eeval & AR5416_OPFLAGS_11A) &&
3150 !(AR_SREV_9271(ah)))
3151 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3152 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3153 else
3154 /* Use rx_chainmask from EEPROM. */
3155 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3156
3157 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3158 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3159
3160 pCap->low_2ghz_chan = 2312;
3161 pCap->high_2ghz_chan = 2732;
3162
3163 pCap->low_5ghz_chan = 4920;
3164 pCap->high_5ghz_chan = 6100;
3165
3166 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3167 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3168 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3169
3170 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3171 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3172 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3173
3174 if (ah->config.ht_enable)
3175 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3176 else
3177 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3178
3179 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3180 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3181 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3182 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3183
3184 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3185 pCap->total_queues =
3186 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3187 else
3188 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3189
3190 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3191 pCap->keycache_size =
3192 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3193 else
3194 pCap->keycache_size = AR_KEYTABLE_SIZE;
3195
3196 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3197
3198 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3199 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3200 else
3201 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3202
3203 if (AR_SREV_9271(ah))
3204 pCap->num_gpio_pins = AR9271_NUM_GPIO;
3205 else if (AR_SREV_9285_10_OR_LATER(ah))
3206 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3207 else if (AR_SREV_9280_10_OR_LATER(ah))
3208 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3209 else
3210 pCap->num_gpio_pins = AR_NUM_GPIO;
3211
3212 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3213 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3214 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3215 } else {
3216 pCap->rts_aggr_limit = (8 * 1024);
3217 }
3218
3219 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3220
3221 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3222 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3223 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3224 ah->rfkill_gpio =
3225 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3226 ah->rfkill_polarity =
3227 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3228
3229 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3230 }
3231 #endif
3232 if (AR_SREV_9271(ah))
3233 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3234 else
3235 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3236
3237 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3238 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3239 else
3240 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3241
3242 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3243 pCap->reg_cap =
3244 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3245 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3246 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3247 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3248 } else {
3249 pCap->reg_cap =
3250 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3251 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3252 }
3253
3254 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3255 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3256 AR_SREV_5416(ah))
3257 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3258
3259 pCap->num_antcfg_5ghz =
3260 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3261 pCap->num_antcfg_2ghz =
3262 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3263
3264 if (AR_SREV_9280_10_OR_LATER(ah) &&
3265 ath9k_hw_btcoex_supported(ah)) {
3266 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3267 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3268
3269 if (AR_SREV_9285(ah)) {
3270 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3271 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3272 } else {
3273 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3274 }
3275 } else {
3276 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3277 }
3278
3279 return 0;
3280 }
3281
3282 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3283 u32 capability, u32 *result)
3284 {
3285 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3286 switch (type) {
3287 case ATH9K_CAP_CIPHER:
3288 switch (capability) {
3289 case ATH9K_CIPHER_AES_CCM:
3290 case ATH9K_CIPHER_AES_OCB:
3291 case ATH9K_CIPHER_TKIP:
3292 case ATH9K_CIPHER_WEP:
3293 case ATH9K_CIPHER_MIC:
3294 case ATH9K_CIPHER_CLR:
3295 return true;
3296 default:
3297 return false;
3298 }
3299 case ATH9K_CAP_TKIP_MIC:
3300 switch (capability) {
3301 case 0:
3302 return true;
3303 case 1:
3304 return (ah->sta_id1_defaults &
3305 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3306 false;
3307 }
3308 case ATH9K_CAP_TKIP_SPLIT:
3309 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3310 false : true;
3311 case ATH9K_CAP_DIVERSITY:
3312 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3313 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3314 true : false;
3315 case ATH9K_CAP_MCAST_KEYSRCH:
3316 switch (capability) {
3317 case 0:
3318 return true;
3319 case 1:
3320 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3321 return false;
3322 } else {
3323 return (ah->sta_id1_defaults &
3324 AR_STA_ID1_MCAST_KSRCH) ? true :
3325 false;
3326 }
3327 }
3328 return false;
3329 case ATH9K_CAP_TXPOW:
3330 switch (capability) {
3331 case 0:
3332 return 0;
3333 case 1:
3334 *result = regulatory->power_limit;
3335 return 0;
3336 case 2:
3337 *result = regulatory->max_power_level;
3338 return 0;
3339 case 3:
3340 *result = regulatory->tp_scale;
3341 return 0;
3342 }
3343 return false;
3344 case ATH9K_CAP_DS:
3345 return (AR_SREV_9280_20_OR_LATER(ah) &&
3346 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3347 ? false : true;
3348 default:
3349 return false;
3350 }
3351 }
3352 EXPORT_SYMBOL(ath9k_hw_getcapability);
3353
3354 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3355 u32 capability, u32 setting, int *status)
3356 {
3357 u32 v;
3358
3359 switch (type) {
3360 case ATH9K_CAP_TKIP_MIC:
3361 if (setting)
3362 ah->sta_id1_defaults |=
3363 AR_STA_ID1_CRPT_MIC_ENABLE;
3364 else
3365 ah->sta_id1_defaults &=
3366 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3367 return true;
3368 case ATH9K_CAP_DIVERSITY:
3369 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3370 if (setting)
3371 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3372 else
3373 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3374 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3375 return true;
3376 case ATH9K_CAP_MCAST_KEYSRCH:
3377 if (setting)
3378 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3379 else
3380 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3381 return true;
3382 default:
3383 return false;
3384 }
3385 }
3386 EXPORT_SYMBOL(ath9k_hw_setcapability);
3387
3388 /****************************/
3389 /* GPIO / RFKILL / Antennae */
3390 /****************************/
3391
3392 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3393 u32 gpio, u32 type)
3394 {
3395 int addr;
3396 u32 gpio_shift, tmp;
3397
3398 if (gpio > 11)
3399 addr = AR_GPIO_OUTPUT_MUX3;
3400 else if (gpio > 5)
3401 addr = AR_GPIO_OUTPUT_MUX2;
3402 else
3403 addr = AR_GPIO_OUTPUT_MUX1;
3404
3405 gpio_shift = (gpio % 6) * 5;
3406
3407 if (AR_SREV_9280_20_OR_LATER(ah)
3408 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3409 REG_RMW(ah, addr, (type << gpio_shift),
3410 (0x1f << gpio_shift));
3411 } else {
3412 tmp = REG_READ(ah, addr);
3413 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3414 tmp &= ~(0x1f << gpio_shift);
3415 tmp |= (type << gpio_shift);
3416 REG_WRITE(ah, addr, tmp);
3417 }
3418 }
3419
3420 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3421 {
3422 u32 gpio_shift;
3423
3424 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3425
3426 gpio_shift = gpio << 1;
3427
3428 REG_RMW(ah,
3429 AR_GPIO_OE_OUT,
3430 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3431 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3432 }
3433 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3434
3435 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3436 {
3437 #define MS_REG_READ(x, y) \
3438 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3439
3440 if (gpio >= ah->caps.num_gpio_pins)
3441 return 0xffffffff;
3442
3443 if (AR_SREV_9271(ah))
3444 return MS_REG_READ(AR9271, gpio) != 0;
3445 else if (AR_SREV_9287_10_OR_LATER(ah))
3446 return MS_REG_READ(AR9287, gpio) != 0;
3447 else if (AR_SREV_9285_10_OR_LATER(ah))
3448 return MS_REG_READ(AR9285, gpio) != 0;
3449 else if (AR_SREV_9280_10_OR_LATER(ah))
3450 return MS_REG_READ(AR928X, gpio) != 0;
3451 else
3452 return MS_REG_READ(AR, gpio) != 0;
3453 }
3454 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3455
3456 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3457 u32 ah_signal_type)
3458 {
3459 u32 gpio_shift;
3460
3461 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3462
3463 gpio_shift = 2 * gpio;
3464
3465 REG_RMW(ah,
3466 AR_GPIO_OE_OUT,
3467 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3468 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3469 }
3470 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3471
3472 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3473 {
3474 if (AR_SREV_9271(ah))
3475 val = ~val;
3476
3477 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3478 AR_GPIO_BIT(gpio));
3479 }
3480 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3481
3482 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3483 {
3484 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3485 }
3486 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3487
3488 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3489 {
3490 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3491 }
3492 EXPORT_SYMBOL(ath9k_hw_setantenna);
3493
3494 /*********************/
3495 /* General Operation */
3496 /*********************/
3497
3498 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3499 {
3500 u32 bits = REG_READ(ah, AR_RX_FILTER);
3501 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3502
3503 if (phybits & AR_PHY_ERR_RADAR)
3504 bits |= ATH9K_RX_FILTER_PHYRADAR;
3505 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3506 bits |= ATH9K_RX_FILTER_PHYERR;
3507
3508 return bits;
3509 }
3510 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3511
3512 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3513 {
3514 u32 phybits;
3515
3516 REG_WRITE(ah, AR_RX_FILTER, bits);
3517
3518 phybits = 0;
3519 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3520 phybits |= AR_PHY_ERR_RADAR;
3521 if (bits & ATH9K_RX_FILTER_PHYERR)
3522 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3523 REG_WRITE(ah, AR_PHY_ERR, phybits);
3524
3525 if (phybits)
3526 REG_WRITE(ah, AR_RXCFG,
3527 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3528 else
3529 REG_WRITE(ah, AR_RXCFG,
3530 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3531 }
3532 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3533
3534 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3535 {
3536 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3537 return false;
3538
3539 ath9k_hw_init_pll(ah, NULL);
3540 return true;
3541 }
3542 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3543
3544 bool ath9k_hw_disable(struct ath_hw *ah)
3545 {
3546 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3547 return false;
3548
3549 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3550 return false;
3551
3552 ath9k_hw_init_pll(ah, NULL);
3553 return true;
3554 }
3555 EXPORT_SYMBOL(ath9k_hw_disable);
3556
3557 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3558 {
3559 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3560 struct ath9k_channel *chan = ah->curchan;
3561 struct ieee80211_channel *channel = chan->chan;
3562
3563 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3564
3565 ah->eep_ops->set_txpower(ah, chan,
3566 ath9k_regd_get_ctl(regulatory, chan),
3567 channel->max_antenna_gain * 2,
3568 channel->max_power * 2,
3569 min((u32) MAX_RATE_POWER,
3570 (u32) regulatory->power_limit));
3571 }
3572 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3573
3574 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3575 {
3576 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3577 }
3578 EXPORT_SYMBOL(ath9k_hw_setmac);
3579
3580 void ath9k_hw_setopmode(struct ath_hw *ah)
3581 {
3582 ath9k_hw_set_operating_mode(ah, ah->opmode);
3583 }
3584 EXPORT_SYMBOL(ath9k_hw_setopmode);
3585
3586 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3587 {
3588 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3589 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3590 }
3591 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3592
3593 void ath9k_hw_write_associd(struct ath_hw *ah)
3594 {
3595 struct ath_common *common = ath9k_hw_common(ah);
3596
3597 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3598 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3599 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3600 }
3601 EXPORT_SYMBOL(ath9k_hw_write_associd);
3602
3603 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3604 {
3605 u64 tsf;
3606
3607 tsf = REG_READ(ah, AR_TSF_U32);
3608 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3609
3610 return tsf;
3611 }
3612 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3613
3614 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3615 {
3616 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3617 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3618 }
3619 EXPORT_SYMBOL(ath9k_hw_settsf64);
3620
3621 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3622 {
3623 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3624 AH_TSF_WRITE_TIMEOUT))
3625 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3626 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3627
3628 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3629 }
3630 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3631
3632 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3633 {
3634 if (setting)
3635 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3636 else
3637 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3638 }
3639 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3640
3641 /*
3642 * Extend 15-bit time stamp from rx descriptor to
3643 * a full 64-bit TSF using the current h/w TSF.
3644 */
3645 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3646 {
3647 u64 tsf;
3648
3649 tsf = ath9k_hw_gettsf64(ah);
3650 if ((tsf & 0x7fff) < rstamp)
3651 tsf -= 0x8000;
3652 return (tsf & ~0x7fff) | rstamp;
3653 }
3654 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3655
3656 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3657 {
3658 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3659 u32 macmode;
3660
3661 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3662 macmode = AR_2040_JOINED_RX_CLEAR;
3663 else
3664 macmode = 0;
3665
3666 REG_WRITE(ah, AR_2040_MODE, macmode);
3667 }
3668
3669 /* HW Generic timers configuration */
3670
3671 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3672 {
3673 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3674 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3675 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3676 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3677 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3678 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3679 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3680 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3681 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3682 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3683 AR_NDP2_TIMER_MODE, 0x0002},
3684 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3685 AR_NDP2_TIMER_MODE, 0x0004},
3686 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3687 AR_NDP2_TIMER_MODE, 0x0008},
3688 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3689 AR_NDP2_TIMER_MODE, 0x0010},
3690 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3691 AR_NDP2_TIMER_MODE, 0x0020},
3692 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3693 AR_NDP2_TIMER_MODE, 0x0040},
3694 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3695 AR_NDP2_TIMER_MODE, 0x0080}
3696 };
3697
3698 /* HW generic timer primitives */
3699
3700 /* compute and clear index of rightmost 1 */
3701 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3702 {
3703 u32 b;
3704
3705 b = *mask;
3706 b &= (0-b);
3707 *mask &= ~b;
3708 b *= debruijn32;
3709 b >>= 27;
3710
3711 return timer_table->gen_timer_index[b];
3712 }
3713
3714 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3715 {
3716 return REG_READ(ah, AR_TSF_L32);
3717 }
3718 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3719
3720 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3721 void (*trigger)(void *),
3722 void (*overflow)(void *),
3723 void *arg,
3724 u8 timer_index)
3725 {
3726 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3727 struct ath_gen_timer *timer;
3728
3729 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3730
3731 if (timer == NULL) {
3732 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3733 "Failed to allocate memory"
3734 "for hw timer[%d]\n", timer_index);
3735 return NULL;
3736 }
3737
3738 /* allocate a hardware generic timer slot */
3739 timer_table->timers[timer_index] = timer;
3740 timer->index = timer_index;
3741 timer->trigger = trigger;
3742 timer->overflow = overflow;
3743 timer->arg = arg;
3744
3745 return timer;
3746 }
3747 EXPORT_SYMBOL(ath_gen_timer_alloc);
3748
3749 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3750 struct ath_gen_timer *timer,
3751 u32 timer_next,
3752 u32 timer_period)
3753 {
3754 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3755 u32 tsf;
3756
3757 BUG_ON(!timer_period);
3758
3759 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3760
3761 tsf = ath9k_hw_gettsf32(ah);
3762
3763 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3764 "curent tsf %x period %x"
3765 "timer_next %x\n", tsf, timer_period, timer_next);
3766
3767 /*
3768 * Pull timer_next forward if the current TSF already passed it
3769 * because of software latency
3770 */
3771 if (timer_next < tsf)
3772 timer_next = tsf + timer_period;
3773
3774 /*
3775 * Program generic timer registers
3776 */
3777 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3778 timer_next);
3779 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3780 timer_period);
3781 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3782 gen_tmr_configuration[timer->index].mode_mask);
3783
3784 /* Enable both trigger and thresh interrupt masks */
3785 REG_SET_BIT(ah, AR_IMR_S5,
3786 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3787 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3788 }
3789 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3790
3791 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3792 {
3793 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3794
3795 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3796 (timer->index >= ATH_MAX_GEN_TIMER)) {
3797 return;
3798 }
3799
3800 /* Clear generic timer enable bits. */
3801 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3802 gen_tmr_configuration[timer->index].mode_mask);
3803
3804 /* Disable both trigger and thresh interrupt masks */
3805 REG_CLR_BIT(ah, AR_IMR_S5,
3806 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3807 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3808
3809 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3810 }
3811 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3812
3813 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3814 {
3815 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3816
3817 /* free the hardware generic timer slot */
3818 timer_table->timers[timer->index] = NULL;
3819 kfree(timer);
3820 }
3821 EXPORT_SYMBOL(ath_gen_timer_free);
3822
3823 /*
3824 * Generic Timer Interrupts handling
3825 */
3826 void ath_gen_timer_isr(struct ath_hw *ah)
3827 {
3828 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3829 struct ath_gen_timer *timer;
3830 struct ath_common *common = ath9k_hw_common(ah);
3831 u32 trigger_mask, thresh_mask, index;
3832
3833 /* get hardware generic timer interrupt status */
3834 trigger_mask = ah->intr_gen_timer_trigger;
3835 thresh_mask = ah->intr_gen_timer_thresh;
3836 trigger_mask &= timer_table->timer_mask.val;
3837 thresh_mask &= timer_table->timer_mask.val;
3838
3839 trigger_mask &= ~thresh_mask;
3840
3841 while (thresh_mask) {
3842 index = rightmost_index(timer_table, &thresh_mask);
3843 timer = timer_table->timers[index];
3844 BUG_ON(!timer);
3845 ath_print(common, ATH_DBG_HWTIMER,
3846 "TSF overflow for Gen timer %d\n", index);
3847 timer->overflow(timer->arg);
3848 }
3849
3850 while (trigger_mask) {
3851 index = rightmost_index(timer_table, &trigger_mask);
3852 timer = timer_table->timers[index];
3853 BUG_ON(!timer);
3854 ath_print(common, ATH_DBG_HWTIMER,
3855 "Gen timer[%d] trigger\n", index);
3856 timer->trigger(timer->arg);
3857 }
3858 }
3859 EXPORT_SYMBOL(ath_gen_timer_isr);
3860
3861 /********/
3862 /* HTC */
3863 /********/
3864
3865 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3866 {
3867 ah->htc_reset_init = true;
3868 }
3869 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3870
3871 static struct {
3872 u32 version;
3873 const char * name;
3874 } ath_mac_bb_names[] = {
3875 /* Devices with external radios */
3876 { AR_SREV_VERSION_5416_PCI, "5416" },
3877 { AR_SREV_VERSION_5416_PCIE, "5418" },
3878 { AR_SREV_VERSION_9100, "9100" },
3879 { AR_SREV_VERSION_9160, "9160" },
3880 /* Single-chip solutions */
3881 { AR_SREV_VERSION_9280, "9280" },
3882 { AR_SREV_VERSION_9285, "9285" },
3883 { AR_SREV_VERSION_9287, "9287" },
3884 { AR_SREV_VERSION_9271, "9271" },
3885 };
3886
3887 /* For devices with external radios */
3888 static struct {
3889 u16 version;
3890 const char * name;
3891 } ath_rf_names[] = {
3892 { 0, "5133" },
3893 { AR_RAD5133_SREV_MAJOR, "5133" },
3894 { AR_RAD5122_SREV_MAJOR, "5122" },
3895 { AR_RAD2133_SREV_MAJOR, "2133" },
3896 { AR_RAD2122_SREV_MAJOR, "2122" }
3897 };
3898
3899 /*
3900 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3901 */
3902 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3903 {
3904 int i;
3905
3906 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3907 if (ath_mac_bb_names[i].version == mac_bb_version) {
3908 return ath_mac_bb_names[i].name;
3909 }
3910 }
3911
3912 return "????";
3913 }
3914
3915 /*
3916 * Return the RF name. "????" is returned if the RF is unknown.
3917 * Used for devices with external radios.
3918 */
3919 static const char *ath9k_hw_rf_name(u16 rf_version)
3920 {
3921 int i;
3922
3923 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3924 if (ath_rf_names[i].version == rf_version) {
3925 return ath_rf_names[i].name;
3926 }
3927 }
3928
3929 return "????";
3930 }
3931
3932 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3933 {
3934 int used;
3935
3936 /* chipsets >= AR9280 are single-chip */
3937 if (AR_SREV_9280_10_OR_LATER(ah)) {
3938 used = snprintf(hw_name, len,
3939 "Atheros AR%s Rev:%x",
3940 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3941 ah->hw_version.macRev);
3942 }
3943 else {
3944 used = snprintf(hw_name, len,
3945 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3946 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3947 ah->hw_version.macRev,
3948 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3949 AR_RADIO_SREV_MAJOR)),
3950 ah->hw_version.phyRev);
3951 }
3952
3953 hw_name[used] = '\0';
3954 }
3955 EXPORT_SYMBOL(ath9k_hw_name);
3956
3957 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
3958 static void ar9002_hw_attach_ops(struct ath_hw *ah)
3959 {
3960 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3961 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
3962
3963 priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
3964 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
3965 priv_ops->macversion_supported = ar9002_hw_macversion_supported;
3966
3967 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
3968 }
Linux kernel - Deliverables
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