drivers/net/wireless/ath/ath9k/hw.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef HW_H
  18 #define HW_H
  19
  20 #include <linux/if_ether.h>
  21 #include <linux/delay.h>
  22 #include <linux/io.h>
  23
  24 #include "mac.h"
  25 #include "ani.h"
  26 #include "eeprom.h"
  27 #include "calib.h"
  28 #include "reg.h"
  29 #include "phy.h"
  30 #include "btcoex.h"
  31
  32 #include "../regd.h"
  33
  34 #define ATHEROS_VENDOR_ID       0x168c
  35 #define AR5416_DEVID_PCI        0x0023
  36 #define AR5416_DEVID_PCIE       0x0024
  37 #define AR9160_DEVID_PCI        0x0027
  38 #define AR9280_DEVID_PCI        0x0029
  39 #define AR9280_DEVID_PCIE       0x002a
  40 #define AR9285_DEVID_PCIE       0x002b
  41 #define AR5416_AR9100_DEVID     0x000b
  42 #define AR_SUBVENDOR_ID_NOG     0x0e11
  43 #define AR_SUBVENDOR_ID_NEW_A   0x7065
  44 #define AR5416_MAGIC            0x19641014
  45
  46 #define AR5416_DEVID_AR9287_PCI  0x002D
  47 #define AR5416_DEVID_AR9287_PCIE 0x002E
  48
  49 #define AR9280_COEX2WIRE_SUBSYSID       0x309b
  50 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
  51 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
  52
  53 /* Register read/write primitives */
  54 #define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
  55 #define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
  56
  57 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
  58 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
  59 #define REG_RMW(_a, _r, _set, _clr)    \
  60         REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
  61 #define REG_RMW_FIELD(_a, _r, _f, _v) \
  62         REG_WRITE(_a, _r, \
  63         (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
  64 #define REG_SET_BIT(_a, _r, _f) \
  65         REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
  66 #define REG_CLR_BIT(_a, _r, _f) \
  67         REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
  68
  69 #define DO_DELAY(x) do {                        \
  70                 if ((++(x) % 64) == 0)          \
  71                         udelay(1);              \
  72         } while (0)
  73
  74 #define REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
  75                 int r;                                                  \
  76                 for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
  77                         REG_WRITE(ah, INI_RA((iniarray), (r), 0),       \
  78                                   INI_RA((iniarray), r, (column)));     \
  79                         DO_DELAY(regWr);                                \
  80                 }                                                       \
  81         } while (0)
  82
  83 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
  84 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
  85 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
  86 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
  87 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
  88 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
  89 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
  90
  91 #define AR_GPIOD_MASK               0x00001FFF
  92 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
  93
  94 #define BASE_ACTIVATE_DELAY         100
  95 #define RTC_PLL_SETTLE_DELAY        1000
  96 #define COEF_SCALE_S                24
  97 #define HT40_CHANNEL_CENTER_SHIFT   10
  98
  99 #define ATH9K_ANTENNA0_CHAINMASK    0x1
 100 #define ATH9K_ANTENNA1_CHAINMASK    0x2
 101
 102 #define ATH9K_NUM_DMA_DEBUG_REGS    8
 103 #define ATH9K_NUM_QUEUES            10
 104
 105 #define MAX_RATE_POWER              63
 106 #define AH_WAIT_TIMEOUT             100000 /* (us) */
 107 #define AH_TSF_WRITE_TIMEOUT        100    /* (us) */
 108 #define AH_TIME_QUANTUM             10
 109 #define AR_KEYTABLE_SIZE            128
 110 #define POWER_UP_TIME               10000
 111 #define SPUR_RSSI_THRESH            40
 112
 113 #define CAB_TIMEOUT_VAL             10
 114 #define BEACON_TIMEOUT_VAL          10
 115 #define MIN_BEACON_TIMEOUT_VAL      1
 116 #define SLEEP_SLOP                  3
 117
 118 #define INIT_CONFIG_STATUS          0x00000000
 119 #define INIT_RSSI_THR               0x00000700
 120 #define INIT_BCON_CNTRL_REG         0x00000000
 121
 122 #define TU_TO_USEC(_tu)             ((_tu) << 10)
 123
 124 enum wireless_mode {
 125         ATH9K_MODE_11A = 0,
 126         ATH9K_MODE_11G,
 127         ATH9K_MODE_11NA_HT20,
 128         ATH9K_MODE_11NG_HT20,
 129         ATH9K_MODE_11NA_HT40PLUS,
 130         ATH9K_MODE_11NA_HT40MINUS,
 131         ATH9K_MODE_11NG_HT40PLUS,
 132         ATH9K_MODE_11NG_HT40MINUS,
 133         ATH9K_MODE_MAX,
 134 };
 135
 136 enum ath9k_ant_setting {
 137         ATH9K_ANT_VARIABLE = 0,
 138         ATH9K_ANT_FIXED_A,
 139         ATH9K_ANT_FIXED_B
 140 };
 141
 142 enum ath9k_hw_caps {
 143         ATH9K_HW_CAP_MIC_AESCCM                 = BIT(0),
 144         ATH9K_HW_CAP_MIC_CKIP                   = BIT(1),
 145         ATH9K_HW_CAP_MIC_TKIP                   = BIT(2),
 146         ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(3),
 147         ATH9K_HW_CAP_CIPHER_CKIP                = BIT(4),
 148         ATH9K_HW_CAP_CIPHER_TKIP                = BIT(5),
 149         ATH9K_HW_CAP_VEOL                       = BIT(6),
 150         ATH9K_HW_CAP_BSSIDMASK                  = BIT(7),
 151         ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(8),
 152         ATH9K_HW_CAP_HT                         = BIT(9),
 153         ATH9K_HW_CAP_GTT                        = BIT(10),
 154         ATH9K_HW_CAP_FASTCC                     = BIT(11),
 155         ATH9K_HW_CAP_RFSILENT                   = BIT(12),
 156         ATH9K_HW_CAP_CST                        = BIT(13),
 157         ATH9K_HW_CAP_ENHANCEDPM                 = BIT(14),
 158         ATH9K_HW_CAP_AUTOSLEEP                  = BIT(15),
 159         ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(16),
 160 };
 161
 162 enum ath9k_capability_type {
 163         ATH9K_CAP_CIPHER = 0,
 164         ATH9K_CAP_TKIP_MIC,
 165         ATH9K_CAP_TKIP_SPLIT,
 166         ATH9K_CAP_DIVERSITY,
 167         ATH9K_CAP_TXPOW,
 168         ATH9K_CAP_MCAST_KEYSRCH,
 169         ATH9K_CAP_DS
 170 };
 171
 172 struct ath9k_hw_capabilities {
 173         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
 174         DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
 175         u16 total_queues;
 176         u16 keycache_size;
 177         u16 low_5ghz_chan, high_5ghz_chan;
 178         u16 low_2ghz_chan, high_2ghz_chan;
 179         u16 rts_aggr_limit;
 180         u8 tx_chainmask;
 181         u8 rx_chainmask;
 182         u16 tx_triglevel_max;
 183         u16 reg_cap;
 184         u8 num_gpio_pins;
 185         u8 num_antcfg_2ghz;
 186         u8 num_antcfg_5ghz;
 187 };
 188
 189 struct ath9k_ops_config {
 190         int dma_beacon_response_time;
 191         int sw_beacon_response_time;
 192         int additional_swba_backoff;
 193         int ack_6mb;
 194         int cwm_ignore_extcca;
 195         u8 pcie_powersave_enable;
 196         u8 pcie_clock_req;
 197         u32 pcie_waen;
 198         u8 analog_shiftreg;
 199         u8 ht_enable;
 200         u32 ofdm_trig_low;
 201         u32 ofdm_trig_high;
 202         u32 cck_trig_high;
 203         u32 cck_trig_low;
 204         u32 enable_ani;
 205         enum ath9k_ant_setting diversity_control;
 206         u16 antenna_switch_swap;
 207         int serialize_regmode;
 208         bool intr_mitigation;
 209 #define SPUR_DISABLE            0
 210 #define SPUR_ENABLE_IOCTL       1
 211 #define SPUR_ENABLE_EEPROM      2
 212 #define AR_EEPROM_MODAL_SPURS   5
 213 #define AR_SPUR_5413_1          1640
 214 #define AR_SPUR_5413_2          1200
 215 #define AR_NO_SPUR              0x8000
 216 #define AR_BASE_FREQ_2GHZ       2300
 217 #define AR_BASE_FREQ_5GHZ       4900
 218 #define AR_SPUR_FEEQ_BOUND_HT40 19
 219 #define AR_SPUR_FEEQ_BOUND_HT20 10
 220         int spurmode;
 221         u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
 222 };
 223
 224 enum ath9k_int {
 225         ATH9K_INT_RX = 0x00000001,
 226         ATH9K_INT_RXDESC = 0x00000002,
 227         ATH9K_INT_RXNOFRM = 0x00000008,
 228         ATH9K_INT_RXEOL = 0x00000010,
 229         ATH9K_INT_RXORN = 0x00000020,
 230         ATH9K_INT_TX = 0x00000040,
 231         ATH9K_INT_TXDESC = 0x00000080,
 232         ATH9K_INT_TIM_TIMER = 0x00000100,
 233         ATH9K_INT_TXURN = 0x00000800,
 234         ATH9K_INT_MIB = 0x00001000,
 235         ATH9K_INT_RXPHY = 0x00004000,
 236         ATH9K_INT_RXKCM = 0x00008000,
 237         ATH9K_INT_SWBA = 0x00010000,
 238         ATH9K_INT_BMISS = 0x00040000,
 239         ATH9K_INT_BNR = 0x00100000,
 240         ATH9K_INT_TIM = 0x00200000,
 241         ATH9K_INT_DTIM = 0x00400000,
 242         ATH9K_INT_DTIMSYNC = 0x00800000,
 243         ATH9K_INT_GPIO = 0x01000000,
 244         ATH9K_INT_CABEND = 0x02000000,
 245         ATH9K_INT_TSFOOR = 0x04000000,
 246         ATH9K_INT_GENTIMER = 0x08000000,
 247         ATH9K_INT_CST = 0x10000000,
 248         ATH9K_INT_GTT = 0x20000000,
 249         ATH9K_INT_FATAL = 0x40000000,
 250         ATH9K_INT_GLOBAL = 0x80000000,
 251         ATH9K_INT_BMISC = ATH9K_INT_TIM |
 252                 ATH9K_INT_DTIM |
 253                 ATH9K_INT_DTIMSYNC |
 254                 ATH9K_INT_TSFOOR |
 255                 ATH9K_INT_CABEND,
 256         ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
 257                 ATH9K_INT_RXDESC |
 258                 ATH9K_INT_RXEOL |
 259                 ATH9K_INT_RXORN |
 260                 ATH9K_INT_TXURN |
 261                 ATH9K_INT_TXDESC |
 262                 ATH9K_INT_MIB |
 263                 ATH9K_INT_RXPHY |
 264                 ATH9K_INT_RXKCM |
 265                 ATH9K_INT_SWBA |
 266                 ATH9K_INT_BMISS |
 267                 ATH9K_INT_GPIO,
 268         ATH9K_INT_NOCARD = 0xffffffff
 269 };
 270
 271 #define CHANNEL_CW_INT    0x00002
 272 #define CHANNEL_CCK       0x00020
 273 #define CHANNEL_OFDM      0x00040
 274 #define CHANNEL_2GHZ      0x00080
 275 #define CHANNEL_5GHZ      0x00100
 276 #define CHANNEL_PASSIVE   0x00200
 277 #define CHANNEL_DYN       0x00400
 278 #define CHANNEL_HALF      0x04000
 279 #define CHANNEL_QUARTER   0x08000
 280 #define CHANNEL_HT20      0x10000
 281 #define CHANNEL_HT40PLUS  0x20000
 282 #define CHANNEL_HT40MINUS 0x40000
 283
 284 #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
 285 #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
 286 #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
 287 #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
 288 #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
 289 #define CHANNEL_G_HT40PLUS  (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
 290 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
 291 #define CHANNEL_A_HT40PLUS  (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
 292 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
 293 #define CHANNEL_ALL                             \
 294         (CHANNEL_OFDM|                          \
 295          CHANNEL_CCK|                           \
 296          CHANNEL_2GHZ |                         \
 297          CHANNEL_5GHZ |                         \
 298          CHANNEL_HT20 |                         \
 299          CHANNEL_HT40PLUS |                     \
 300          CHANNEL_HT40MINUS)
 301
 302 struct ath9k_channel {
 303         struct ieee80211_channel *chan;
 304         u16 channel;
 305         u32 channelFlags;
 306         u32 chanmode;
 307         int32_t CalValid;
 308         bool oneTimeCalsDone;
 309         int8_t iCoff;
 310         int8_t qCoff;
 311         int16_t rawNoiseFloor;
 312 };
 313
 314 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
 315        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
 316        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
 317        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
 318 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
 319 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
 320 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
 321 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
 322 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
 323 #define IS_CHAN_A_5MHZ_SPACED(_c)                       \
 324         ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&  \
 325          (((_c)->channel % 20) != 0) &&                 \
 326          (((_c)->channel % 10) != 0))
 327
 328 /* These macros check chanmode and not channelFlags */
 329 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
 330 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
 331                           ((_c)->chanmode == CHANNEL_G_HT20))
 332 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||     \
 333                           ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||    \
 334                           ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||     \
 335                           ((_c)->chanmode == CHANNEL_G_HT40MINUS))
 336 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
 337
 338 enum ath9k_power_mode {
 339         ATH9K_PM_AWAKE = 0,
 340         ATH9K_PM_FULL_SLEEP,
 341         ATH9K_PM_NETWORK_SLEEP,
 342         ATH9K_PM_UNDEFINED
 343 };
 344
 345 enum ath9k_tp_scale {
 346         ATH9K_TP_SCALE_MAX = 0,
 347         ATH9K_TP_SCALE_50,
 348         ATH9K_TP_SCALE_25,
 349         ATH9K_TP_SCALE_12,
 350         ATH9K_TP_SCALE_MIN
 351 };
 352
 353 enum ser_reg_mode {
 354         SER_REG_MODE_OFF = 0,
 355         SER_REG_MODE_ON = 1,
 356         SER_REG_MODE_AUTO = 2,
 357 };
 358
 359 struct ath9k_beacon_state {
 360         u32 bs_nexttbtt;
 361         u32 bs_nextdtim;
 362         u32 bs_intval;
 363 #define ATH9K_BEACON_PERIOD       0x0000ffff
 364 #define ATH9K_BEACON_ENA          0x00800000
 365 #define ATH9K_BEACON_RESET_TSF    0x01000000
 366 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
 367         u32 bs_dtimperiod;
 368         u16 bs_cfpperiod;
 369         u16 bs_cfpmaxduration;
 370         u32 bs_cfpnext;
 371         u16 bs_timoffset;
 372         u16 bs_bmissthreshold;
 373         u32 bs_sleepduration;
 374         u32 bs_tsfoor_threshold;
 375 };
 376
 377 struct chan_centers {
 378         u16 synth_center;
 379         u16 ctl_center;
 380         u16 ext_center;
 381 };
 382
 383 enum {
 384         ATH9K_RESET_POWER_ON,
 385         ATH9K_RESET_WARM,
 386         ATH9K_RESET_COLD,
 387 };
 388
 389 struct ath9k_hw_version {
 390         u32 magic;
 391         u16 devid;
 392         u16 subvendorid;
 393         u32 macVersion;
 394         u16 macRev;
 395         u16 phyRev;
 396         u16 analog5GhzRev;
 397         u16 analog2GhzRev;
 398         u16 subsysid;
 399 };
 400
 401 /* Generic TSF timer definitions */
 402
 403 #define ATH_MAX_GEN_TIMER       16
 404
 405 #define AR_GENTMR_BIT(_index)   (1 << (_index))
 406
 407 /*
 408  * Using de Bruijin sequence to to look up 1's index in a 32 bit number
 409  * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
 410  */
 411 #define debruijn32 0x077CB531UL
 412
 413 struct ath_gen_timer_configuration {
 414         u32 next_addr;
 415         u32 period_addr;
 416         u32 mode_addr;
 417         u32 mode_mask;
 418 };
 419
 420 struct ath_gen_timer {
 421         void (*trigger)(void *arg);
 422         void (*overflow)(void *arg);
 423         void *arg;
 424         u8 index;
 425 };
 426
 427 struct ath_gen_timer_table {
 428         u32 gen_timer_index[32];
 429         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
 430         union {
 431                 unsigned long timer_bits;
 432                 u16 val;
 433         } timer_mask;
 434 };
 435
 436 struct ath_hw {
 437         struct ath_softc *ah_sc;
 438         struct ath9k_hw_version hw_version;
 439         struct ath9k_ops_config config;
 440         struct ath9k_hw_capabilities caps;
 441         struct ath9k_channel channels[38];
 442         struct ath9k_channel *curchan;
 443
 444         union {
 445                 struct ar5416_eeprom_def def;
 446                 struct ar5416_eeprom_4k map4k;
 447                 struct ar9287_eeprom map9287;
 448         } eeprom;
 449         const struct eeprom_ops *eep_ops;
 450         enum ath9k_eep_map eep_map;
 451
 452         bool sw_mgmt_crypto;
 453         bool is_pciexpress;
 454         u8 macaddr[ETH_ALEN];
 455         u16 tx_trig_level;
 456         u16 rfsilent;
 457         u32 rfkill_gpio;
 458         u32 rfkill_polarity;
 459         u32 ah_flags;
 460
 461         bool htc_reset_init;
 462
 463         enum nl80211_iftype opmode;
 464         enum ath9k_power_mode power_mode;
 465
 466         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 467         struct ath9k_pacal_info pacal_info;
 468         struct ar5416Stats stats;
 469         struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
 470
 471         int16_t curchan_rad_index;
 472         u32 mask_reg;
 473         u32 txok_interrupt_mask;
 474         u32 txerr_interrupt_mask;
 475         u32 txdesc_interrupt_mask;
 476         u32 txeol_interrupt_mask;
 477         u32 txurn_interrupt_mask;
 478         bool chip_fullsleep;
 479         u32 atim_window;
 480
 481         /* Calibration */
 482         enum ath9k_cal_types supp_cals;
 483         struct ath9k_cal_list iq_caldata;
 484         struct ath9k_cal_list adcgain_caldata;
 485         struct ath9k_cal_list adcdc_calinitdata;
 486         struct ath9k_cal_list adcdc_caldata;
 487         struct ath9k_cal_list *cal_list;
 488         struct ath9k_cal_list *cal_list_last;
 489         struct ath9k_cal_list *cal_list_curr;
 490 #define totalPowerMeasI meas0.unsign
 491 #define totalPowerMeasQ meas1.unsign
 492 #define totalIqCorrMeas meas2.sign
 493 #define totalAdcIOddPhase  meas0.unsign
 494 #define totalAdcIEvenPhase meas1.unsign
 495 #define totalAdcQOddPhase  meas2.unsign
 496 #define totalAdcQEvenPhase meas3.unsign
 497 #define totalAdcDcOffsetIOddPhase  meas0.sign
 498 #define totalAdcDcOffsetIEvenPhase meas1.sign
 499 #define totalAdcDcOffsetQOddPhase  meas2.sign
 500 #define totalAdcDcOffsetQEvenPhase meas3.sign
 501         union {
 502                 u32 unsign[AR5416_MAX_CHAINS];
 503                 int32_t sign[AR5416_MAX_CHAINS];
 504         } meas0;
 505         union {
 506                 u32 unsign[AR5416_MAX_CHAINS];
 507                 int32_t sign[AR5416_MAX_CHAINS];
 508         } meas1;
 509         union {
 510                 u32 unsign[AR5416_MAX_CHAINS];
 511                 int32_t sign[AR5416_MAX_CHAINS];
 512         } meas2;
 513         union {
 514                 u32 unsign[AR5416_MAX_CHAINS];
 515                 int32_t sign[AR5416_MAX_CHAINS];
 516         } meas3;
 517         u16 cal_samples;
 518
 519         u32 sta_id1_defaults;
 520         u32 misc_mode;
 521         enum {
 522                 AUTO_32KHZ,
 523                 USE_32KHZ,
 524                 DONT_USE_32KHZ,
 525         } enable_32kHz_clock;
 526
 527         /* RF */
 528         u32 *analogBank0Data;
 529         u32 *analogBank1Data;
 530         u32 *analogBank2Data;
 531         u32 *analogBank3Data;
 532         u32 *analogBank6Data;
 533         u32 *analogBank6TPCData;
 534         u32 *analogBank7Data;
 535         u32 *addac5416_21;
 536         u32 *bank6Temp;
 537
 538         int16_t txpower_indexoffset;
 539         u32 beacon_interval;
 540         u32 slottime;
 541         u32 acktimeout;
 542         u32 ctstimeout;
 543         u32 globaltxtimeout;
 544         u8 gbeacon_rate;
 545
 546         /* ANI */
 547         u32 proc_phyerr;
 548         u32 aniperiod;
 549         struct ar5416AniState *curani;
 550         struct ar5416AniState ani[255];
 551         int totalSizeDesired[5];
 552         int coarse_high[5];
 553         int coarse_low[5];
 554         int firpwr[5];
 555         enum ath9k_ani_cmd ani_function;
 556
 557         /* Bluetooth coexistance */
 558         struct ath_btcoex_hw btcoex_hw;
 559
 560         u32 intr_txqs;
 561         enum ath9k_ht_extprotspacing extprotspacing;
 562         u8 txchainmask;
 563         u8 rxchainmask;
 564
 565         u32 originalGain[22];
 566         int initPDADC;
 567         int PDADCdelta;
 568         u8 led_pin;
 569
 570         struct ar5416IniArray iniModes;
 571         struct ar5416IniArray iniCommon;
 572         struct ar5416IniArray iniBank0;
 573         struct ar5416IniArray iniBB_RfGain;
 574         struct ar5416IniArray iniBank1;
 575         struct ar5416IniArray iniBank2;
 576         struct ar5416IniArray iniBank3;
 577         struct ar5416IniArray iniBank6;
 578         struct ar5416IniArray iniBank6TPC;
 579         struct ar5416IniArray iniBank7;
 580         struct ar5416IniArray iniAddac;
 581         struct ar5416IniArray iniPcieSerdes;
 582         struct ar5416IniArray iniModesAdditional;
 583         struct ar5416IniArray iniModesRxGain;
 584         struct ar5416IniArray iniModesTxGain;
 585
 586         u32 intr_gen_timer_trigger;
 587         u32 intr_gen_timer_thresh;
 588         struct ath_gen_timer_table hw_gen_timers;
 589 };
 590
 591 /* Initialization, Detach, Reset */
 592 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
 593 void ath9k_hw_detach(struct ath_hw *ah);
 594 int ath9k_hw_init(struct ath_hw *ah);
 595 void ath9k_hw_rf_free(struct ath_hw *ah);
 596 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 597                    bool bChannelChange);
 598 void ath9k_hw_fill_cap_info(struct ath_hw *ah);
 599 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
 600                             u32 capability, u32 *result);
 601 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
 602                             u32 capability, u32 setting, int *status);
 603
 604 /* Key Cache Management */
 605 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
 606 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
 607 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
 608                                  const struct ath9k_keyval *k,
 609                                  const u8 *mac);
 610 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
 611
 612 /* GPIO / RFKILL / Antennae */
 613 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
 614 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
 615 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
 616                          u32 ah_signal_type);
 617 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
 618 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
 619 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
 620 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
 621                                enum ath9k_ant_setting settings,
 622                                struct ath9k_channel *chan,
 623                                u8 *tx_chainmask, u8 *rx_chainmask,
 624                                u8 *antenna_cfgd);
 625
 626 /* General Operation */
 627 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
 628 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
 629 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
 630 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 631                            const struct ath_rate_table *rates,
 632                            u32 frameLen, u16 rateix, bool shortPreamble);
 633 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 634                                   struct ath9k_channel *chan,
 635                                   struct chan_centers *centers);
 636 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
 637 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
 638 bool ath9k_hw_phy_disable(struct ath_hw *ah);
 639 bool ath9k_hw_disable(struct ath_hw *ah);
 640 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
 641 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
 642 void ath9k_hw_setopmode(struct ath_hw *ah);
 643 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
 644 void ath9k_hw_setbssidmask(struct ath_softc *sc);
 645 void ath9k_hw_write_associd(struct ath_softc *sc);
 646 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
 647 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
 648 void ath9k_hw_reset_tsf(struct ath_hw *ah);
 649 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
 650 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
 651 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
 652 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
 653 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
 654                                     const struct ath9k_beacon_state *bs);
 655
 656 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
 657
 658 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
 659
 660 /* Interrupt Handling */
 661 bool ath9k_hw_intrpend(struct ath_hw *ah);
 662 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
 663 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
 664
 665 /* Generic hw timer primitives */
 666 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
 667                                           void (*trigger)(void *),
 668                                           void (*overflow)(void *),
 669                                           void *arg,
 670                                           u8 timer_index);
 671 void ath_gen_timer_start(struct ath_hw *ah, struct ath_gen_timer *timer,
 672                          u32 timer_next, u32 timer_period);
 673 void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
 674 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
 675 void ath_gen_timer_isr(struct ath_hw *hw);
 676 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 677
 678 #define ATH_PCIE_CAP_LINK_CTRL  0x70
 679 #define ATH_PCIE_CAP_LINK_L0S   1
 680 #define ATH_PCIE_CAP_LINK_L1    2
 681
 682 void ath_pcie_aspm_disable(struct ath_softc *sc);
 683 #endif