drivers/net/wireless/ath/ath9k/hw.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef HW_H
  18 #define HW_H
  19
  20 #include <linux/if_ether.h>
  21 #include <linux/delay.h>
  22 #include <linux/io.h>
  23
  24 #include "mac.h"
  25 #include "ani.h"
  26 #include "eeprom.h"
  27 #include "calib.h"
  28 #include "reg.h"
  29 #include "phy.h"
  30 #include "btcoex.h"
  31
  32 #include "../regd.h"
  33 #include "../debug.h"
  34
  35 #define ATHEROS_VENDOR_ID       0x168c
  36
  37 #define AR5416_DEVID_PCI        0x0023
  38 #define AR5416_DEVID_PCIE       0x0024
  39 #define AR9160_DEVID_PCI        0x0027
  40 #define AR9280_DEVID_PCI        0x0029
  41 #define AR9280_DEVID_PCIE       0x002a
  42 #define AR9285_DEVID_PCIE       0x002b
  43
  44 #define AR5416_AR9100_DEVID     0x000b
  45
  46 #define AR9271_USB             0x9271
  47
  48 #define AR_SUBVENDOR_ID_NOG     0x0e11
  49 #define AR_SUBVENDOR_ID_NEW_A   0x7065
  50 #define AR5416_MAGIC            0x19641014
  51
  52 #define AR5416_DEVID_AR9287_PCI  0x002D
  53 #define AR5416_DEVID_AR9287_PCIE 0x002E
  54
  55 #define AR9280_COEX2WIRE_SUBSYSID       0x309b
  56 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
  57 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
  58
  59 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
  60
  61 #define ATH_DEFAULT_NOISE_FLOOR -95
  62
  63 #define ATH9K_RSSI_BAD                  0x80
  64
  65 /* Register read/write primitives */
  66 #define REG_WRITE(_ah, _reg, _val) \
  67         ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
  68
  69 #define REG_READ(_ah, _reg) \
  70         ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
  71
  72 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
  73 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
  74 #define REG_RMW(_a, _r, _set, _clr)    \
  75         REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
  76 #define REG_RMW_FIELD(_a, _r, _f, _v) \
  77         REG_WRITE(_a, _r, \
  78         (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
  79 #define REG_SET_BIT(_a, _r, _f) \
  80         REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
  81 #define REG_CLR_BIT(_a, _r, _f) \
  82         REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
  83
  84 #define DO_DELAY(x) do {                        \
  85                 if ((++(x) % 64) == 0)          \
  86                         udelay(1);              \
  87         } while (0)
  88
  89 #define REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
  90                 int r;                                                  \
  91                 for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
  92                         REG_WRITE(ah, INI_RA((iniarray), (r), 0),       \
  93                                   INI_RA((iniarray), r, (column)));     \
  94                         DO_DELAY(regWr);                                \
  95                 }                                                       \
  96         } while (0)
  97
  98 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
  99 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
 100 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
 101 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
 102 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
 103 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
 104 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
 105
 106 #define AR_GPIOD_MASK               0x00001FFF
 107 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
 108
 109 #define BASE_ACTIVATE_DELAY         100
 110 #define RTC_PLL_SETTLE_DELAY        100
 111 #define COEF_SCALE_S                24
 112 #define HT40_CHANNEL_CENTER_SHIFT   10
 113
 114 #define ATH9K_ANTENNA0_CHAINMASK    0x1
 115 #define ATH9K_ANTENNA1_CHAINMASK    0x2
 116
 117 #define ATH9K_NUM_DMA_DEBUG_REGS    8
 118 #define ATH9K_NUM_QUEUES            10
 119
 120 #define MAX_RATE_POWER              63
 121 #define AH_WAIT_TIMEOUT             100000 /* (us) */
 122 #define AH_TSF_WRITE_TIMEOUT        100    /* (us) */
 123 #define AH_TIME_QUANTUM             10
 124 #define AR_KEYTABLE_SIZE            128
 125 #define POWER_UP_TIME               10000
 126 #define SPUR_RSSI_THRESH            40
 127
 128 #define CAB_TIMEOUT_VAL             10
 129 #define BEACON_TIMEOUT_VAL          10
 130 #define MIN_BEACON_TIMEOUT_VAL      1
 131 #define SLEEP_SLOP                  3
 132
 133 #define INIT_CONFIG_STATUS          0x00000000
 134 #define INIT_RSSI_THR               0x00000700
 135 #define INIT_BCON_CNTRL_REG         0x00000000
 136
 137 #define TU_TO_USEC(_tu)             ((_tu) << 10)
 138
 139 enum wireless_mode {
 140         ATH9K_MODE_11A = 0,
 141         ATH9K_MODE_11G,
 142         ATH9K_MODE_11NA_HT20,
 143         ATH9K_MODE_11NG_HT20,
 144         ATH9K_MODE_11NA_HT40PLUS,
 145         ATH9K_MODE_11NA_HT40MINUS,
 146         ATH9K_MODE_11NG_HT40PLUS,
 147         ATH9K_MODE_11NG_HT40MINUS,
 148         ATH9K_MODE_MAX,
 149 };
 150
 151 /**
 152  * ath9k_ant_setting - transmit antenna settings
 153  *
 154  * Configures the antenna setting to use for transmit.
 155  *
 156  * @ATH9K_ANT_VARIABLE: this means transmit on all active antennas
 157  * @ATH9K_ANT_FIXED_A: this means transmit on the first antenna only
 158  * @ATH9K_ANT_FIXED_B: this means transmit on the second antenna only
 159  */
 160 enum ath9k_ant_setting {
 161         ATH9K_ANT_VARIABLE = 0,
 162         ATH9K_ANT_FIXED_A,
 163         ATH9K_ANT_FIXED_B
 164 };
 165
 166 enum ath9k_hw_caps {
 167         ATH9K_HW_CAP_MIC_AESCCM                 = BIT(0),
 168         ATH9K_HW_CAP_MIC_CKIP                   = BIT(1),
 169         ATH9K_HW_CAP_MIC_TKIP                   = BIT(2),
 170         ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(3),
 171         ATH9K_HW_CAP_CIPHER_CKIP                = BIT(4),
 172         ATH9K_HW_CAP_CIPHER_TKIP                = BIT(5),
 173         ATH9K_HW_CAP_VEOL                       = BIT(6),
 174         ATH9K_HW_CAP_BSSIDMASK                  = BIT(7),
 175         ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(8),
 176         ATH9K_HW_CAP_HT                         = BIT(9),
 177         ATH9K_HW_CAP_GTT                        = BIT(10),
 178         ATH9K_HW_CAP_FASTCC                     = BIT(11),
 179         ATH9K_HW_CAP_RFSILENT                   = BIT(12),
 180         ATH9K_HW_CAP_CST                        = BIT(13),
 181         ATH9K_HW_CAP_ENHANCEDPM                 = BIT(14),
 182         ATH9K_HW_CAP_AUTOSLEEP                  = BIT(15),
 183         ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(16),
 184 };
 185
 186 enum ath9k_capability_type {
 187         ATH9K_CAP_CIPHER = 0,
 188         ATH9K_CAP_TKIP_MIC,
 189         ATH9K_CAP_TKIP_SPLIT,
 190         ATH9K_CAP_DIVERSITY,
 191         ATH9K_CAP_TXPOW,
 192         ATH9K_CAP_MCAST_KEYSRCH,
 193         ATH9K_CAP_DS
 194 };
 195
 196 struct ath9k_hw_capabilities {
 197         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
 198         DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
 199         u16 total_queues;
 200         u16 keycache_size;
 201         u16 low_5ghz_chan, high_5ghz_chan;
 202         u16 low_2ghz_chan, high_2ghz_chan;
 203         u16 rts_aggr_limit;
 204         u8 tx_chainmask;
 205         u8 rx_chainmask;
 206         u16 tx_triglevel_max;
 207         u16 reg_cap;
 208         u8 num_gpio_pins;
 209         u8 num_antcfg_2ghz;
 210         u8 num_antcfg_5ghz;
 211 };
 212
 213 struct ath9k_ops_config {
 214         int dma_beacon_response_time;
 215         int sw_beacon_response_time;
 216         int additional_swba_backoff;
 217         int ack_6mb;
 218         int cwm_ignore_extcca;
 219         u8 pcie_powersave_enable;
 220         u8 pcie_clock_req;
 221         u32 pcie_waen;
 222         u8 analog_shiftreg;
 223         u8 ht_enable;
 224         u32 ofdm_trig_low;
 225         u32 ofdm_trig_high;
 226         u32 cck_trig_high;
 227         u32 cck_trig_low;
 228         u32 enable_ani;
 229         enum ath9k_ant_setting diversity_control;
 230         u16 antenna_switch_swap;
 231         int serialize_regmode;
 232         bool intr_mitigation;
 233 #define SPUR_DISABLE            0
 234 #define SPUR_ENABLE_IOCTL       1
 235 #define SPUR_ENABLE_EEPROM      2
 236 #define AR_EEPROM_MODAL_SPURS   5
 237 #define AR_SPUR_5413_1          1640
 238 #define AR_SPUR_5413_2          1200
 239 #define AR_NO_SPUR              0x8000
 240 #define AR_BASE_FREQ_2GHZ       2300
 241 #define AR_BASE_FREQ_5GHZ       4900
 242 #define AR_SPUR_FEEQ_BOUND_HT40 19
 243 #define AR_SPUR_FEEQ_BOUND_HT20 10
 244         int spurmode;
 245         u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
 246 };
 247
 248 enum ath9k_int {
 249         ATH9K_INT_RX = 0x00000001,
 250         ATH9K_INT_RXDESC = 0x00000002,
 251         ATH9K_INT_RXNOFRM = 0x00000008,
 252         ATH9K_INT_RXEOL = 0x00000010,
 253         ATH9K_INT_RXORN = 0x00000020,
 254         ATH9K_INT_TX = 0x00000040,
 255         ATH9K_INT_TXDESC = 0x00000080,
 256         ATH9K_INT_TIM_TIMER = 0x00000100,
 257         ATH9K_INT_TXURN = 0x00000800,
 258         ATH9K_INT_MIB = 0x00001000,
 259         ATH9K_INT_RXPHY = 0x00004000,
 260         ATH9K_INT_RXKCM = 0x00008000,
 261         ATH9K_INT_SWBA = 0x00010000,
 262         ATH9K_INT_BMISS = 0x00040000,
 263         ATH9K_INT_BNR = 0x00100000,
 264         ATH9K_INT_TIM = 0x00200000,
 265         ATH9K_INT_DTIM = 0x00400000,
 266         ATH9K_INT_DTIMSYNC = 0x00800000,
 267         ATH9K_INT_GPIO = 0x01000000,
 268         ATH9K_INT_CABEND = 0x02000000,
 269         ATH9K_INT_TSFOOR = 0x04000000,
 270         ATH9K_INT_GENTIMER = 0x08000000,
 271         ATH9K_INT_CST = 0x10000000,
 272         ATH9K_INT_GTT = 0x20000000,
 273         ATH9K_INT_FATAL = 0x40000000,
 274         ATH9K_INT_GLOBAL = 0x80000000,
 275         ATH9K_INT_BMISC = ATH9K_INT_TIM |
 276                 ATH9K_INT_DTIM |
 277                 ATH9K_INT_DTIMSYNC |
 278                 ATH9K_INT_TSFOOR |
 279                 ATH9K_INT_CABEND,
 280         ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
 281                 ATH9K_INT_RXDESC |
 282                 ATH9K_INT_RXEOL |
 283                 ATH9K_INT_RXORN |
 284                 ATH9K_INT_TXURN |
 285                 ATH9K_INT_TXDESC |
 286                 ATH9K_INT_MIB |
 287                 ATH9K_INT_RXPHY |
 288                 ATH9K_INT_RXKCM |
 289                 ATH9K_INT_SWBA |
 290                 ATH9K_INT_BMISS |
 291                 ATH9K_INT_GPIO,
 292         ATH9K_INT_NOCARD = 0xffffffff
 293 };
 294
 295 #define CHANNEL_CW_INT    0x00002
 296 #define CHANNEL_CCK       0x00020
 297 #define CHANNEL_OFDM      0x00040
 298 #define CHANNEL_2GHZ      0x00080
 299 #define CHANNEL_5GHZ      0x00100
 300 #define CHANNEL_PASSIVE   0x00200
 301 #define CHANNEL_DYN       0x00400
 302 #define CHANNEL_HALF      0x04000
 303 #define CHANNEL_QUARTER   0x08000
 304 #define CHANNEL_HT20      0x10000
 305 #define CHANNEL_HT40PLUS  0x20000
 306 #define CHANNEL_HT40MINUS 0x40000
 307
 308 #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
 309 #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
 310 #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
 311 #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
 312 #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
 313 #define CHANNEL_G_HT40PLUS  (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
 314 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
 315 #define CHANNEL_A_HT40PLUS  (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
 316 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
 317 #define CHANNEL_ALL                             \
 318         (CHANNEL_OFDM|                          \
 319          CHANNEL_CCK|                           \
 320          CHANNEL_2GHZ |                         \
 321          CHANNEL_5GHZ |                         \
 322          CHANNEL_HT20 |                         \
 323          CHANNEL_HT40PLUS |                     \
 324          CHANNEL_HT40MINUS)
 325
 326 struct ath9k_channel {
 327         struct ieee80211_channel *chan;
 328         u16 channel;
 329         u32 channelFlags;
 330         u32 chanmode;
 331         int32_t CalValid;
 332         bool oneTimeCalsDone;
 333         int8_t iCoff;
 334         int8_t qCoff;
 335         int16_t rawNoiseFloor;
 336 };
 337
 338 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
 339        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
 340        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
 341        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
 342 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
 343 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
 344 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
 345 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
 346 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
 347 #define IS_CHAN_A_5MHZ_SPACED(_c)                       \
 348         ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&  \
 349          (((_c)->channel % 20) != 0) &&                 \
 350          (((_c)->channel % 10) != 0))
 351
 352 /* These macros check chanmode and not channelFlags */
 353 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
 354 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
 355                           ((_c)->chanmode == CHANNEL_G_HT20))
 356 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||     \
 357                           ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||    \
 358                           ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||     \
 359                           ((_c)->chanmode == CHANNEL_G_HT40MINUS))
 360 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
 361
 362 enum ath9k_power_mode {
 363         ATH9K_PM_AWAKE = 0,
 364         ATH9K_PM_FULL_SLEEP,
 365         ATH9K_PM_NETWORK_SLEEP,
 366         ATH9K_PM_UNDEFINED
 367 };
 368
 369 enum ath9k_tp_scale {
 370         ATH9K_TP_SCALE_MAX = 0,
 371         ATH9K_TP_SCALE_50,
 372         ATH9K_TP_SCALE_25,
 373         ATH9K_TP_SCALE_12,
 374         ATH9K_TP_SCALE_MIN
 375 };
 376
 377 enum ser_reg_mode {
 378         SER_REG_MODE_OFF = 0,
 379         SER_REG_MODE_ON = 1,
 380         SER_REG_MODE_AUTO = 2,
 381 };
 382
 383 struct ath9k_beacon_state {
 384         u32 bs_nexttbtt;
 385         u32 bs_nextdtim;
 386         u32 bs_intval;
 387 #define ATH9K_BEACON_PERIOD       0x0000ffff
 388 #define ATH9K_BEACON_ENA          0x00800000
 389 #define ATH9K_BEACON_RESET_TSF    0x01000000
 390 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
 391         u32 bs_dtimperiod;
 392         u16 bs_cfpperiod;
 393         u16 bs_cfpmaxduration;
 394         u32 bs_cfpnext;
 395         u16 bs_timoffset;
 396         u16 bs_bmissthreshold;
 397         u32 bs_sleepduration;
 398         u32 bs_tsfoor_threshold;
 399 };
 400
 401 struct chan_centers {
 402         u16 synth_center;
 403         u16 ctl_center;
 404         u16 ext_center;
 405 };
 406
 407 enum {
 408         ATH9K_RESET_POWER_ON,
 409         ATH9K_RESET_WARM,
 410         ATH9K_RESET_COLD,
 411 };
 412
 413 struct ath9k_hw_version {
 414         u32 magic;
 415         u16 devid;
 416         u16 subvendorid;
 417         u32 macVersion;
 418         u16 macRev;
 419         u16 phyRev;
 420         u16 analog5GhzRev;
 421         u16 analog2GhzRev;
 422         u16 subsysid;
 423 };
 424
 425 /* Generic TSF timer definitions */
 426
 427 #define ATH_MAX_GEN_TIMER       16
 428
 429 #define AR_GENTMR_BIT(_index)   (1 << (_index))
 430
 431 /*
 432  * Using de Bruijin sequence to to look up 1's index in a 32 bit number
 433  * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
 434  */
 435 #define debruijn32 0x077CB531UL
 436
 437 struct ath_gen_timer_configuration {
 438         u32 next_addr;
 439         u32 period_addr;
 440         u32 mode_addr;
 441         u32 mode_mask;
 442 };
 443
 444 struct ath_gen_timer {
 445         void (*trigger)(void *arg);
 446         void (*overflow)(void *arg);
 447         void *arg;
 448         u8 index;
 449 };
 450
 451 struct ath_gen_timer_table {
 452         u32 gen_timer_index[32];
 453         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
 454         union {
 455                 unsigned long timer_bits;
 456                 u16 val;
 457         } timer_mask;
 458 };
 459
 460 struct ath_hw {
 461         struct ieee80211_hw *hw;
 462         struct ath_common common;
 463         struct ath9k_hw_version hw_version;
 464         struct ath9k_ops_config config;
 465         struct ath9k_hw_capabilities caps;
 466         struct ath9k_channel channels[38];
 467         struct ath9k_channel *curchan;
 468
 469         union {
 470                 struct ar5416_eeprom_def def;
 471                 struct ar5416_eeprom_4k map4k;
 472                 struct ar9287_eeprom map9287;
 473         } eeprom;
 474         const struct eeprom_ops *eep_ops;
 475         enum ath9k_eep_map eep_map;
 476
 477         bool sw_mgmt_crypto;
 478         bool is_pciexpress;
 479         u16 tx_trig_level;
 480         u16 rfsilent;
 481         u32 rfkill_gpio;
 482         u32 rfkill_polarity;
 483         u32 ah_flags;
 484
 485         bool htc_reset_init;
 486
 487         enum nl80211_iftype opmode;
 488         enum ath9k_power_mode power_mode;
 489
 490         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 491         struct ath9k_pacal_info pacal_info;
 492         struct ar5416Stats stats;
 493         struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
 494
 495         int16_t curchan_rad_index;
 496         u32 mask_reg;
 497         u32 txok_interrupt_mask;
 498         u32 txerr_interrupt_mask;
 499         u32 txdesc_interrupt_mask;
 500         u32 txeol_interrupt_mask;
 501         u32 txurn_interrupt_mask;
 502         bool chip_fullsleep;
 503         u32 atim_window;
 504
 505         /* Calibration */
 506         enum ath9k_cal_types supp_cals;
 507         struct ath9k_cal_list iq_caldata;
 508         struct ath9k_cal_list adcgain_caldata;
 509         struct ath9k_cal_list adcdc_calinitdata;
 510         struct ath9k_cal_list adcdc_caldata;
 511         struct ath9k_cal_list *cal_list;
 512         struct ath9k_cal_list *cal_list_last;
 513         struct ath9k_cal_list *cal_list_curr;
 514 #define totalPowerMeasI meas0.unsign
 515 #define totalPowerMeasQ meas1.unsign
 516 #define totalIqCorrMeas meas2.sign
 517 #define totalAdcIOddPhase  meas0.unsign
 518 #define totalAdcIEvenPhase meas1.unsign
 519 #define totalAdcQOddPhase  meas2.unsign
 520 #define totalAdcQEvenPhase meas3.unsign
 521 #define totalAdcDcOffsetIOddPhase  meas0.sign
 522 #define totalAdcDcOffsetIEvenPhase meas1.sign
 523 #define totalAdcDcOffsetQOddPhase  meas2.sign
 524 #define totalAdcDcOffsetQEvenPhase meas3.sign
 525         union {
 526                 u32 unsign[AR5416_MAX_CHAINS];
 527                 int32_t sign[AR5416_MAX_CHAINS];
 528         } meas0;
 529         union {
 530                 u32 unsign[AR5416_MAX_CHAINS];
 531                 int32_t sign[AR5416_MAX_CHAINS];
 532         } meas1;
 533         union {
 534                 u32 unsign[AR5416_MAX_CHAINS];
 535                 int32_t sign[AR5416_MAX_CHAINS];
 536         } meas2;
 537         union {
 538                 u32 unsign[AR5416_MAX_CHAINS];
 539                 int32_t sign[AR5416_MAX_CHAINS];
 540         } meas3;
 541         u16 cal_samples;
 542
 543         u32 sta_id1_defaults;
 544         u32 misc_mode;
 545         enum {
 546                 AUTO_32KHZ,
 547                 USE_32KHZ,
 548                 DONT_USE_32KHZ,
 549         } enable_32kHz_clock;
 550
 551         /* RF */
 552         u32 *analogBank0Data;
 553         u32 *analogBank1Data;
 554         u32 *analogBank2Data;
 555         u32 *analogBank3Data;
 556         u32 *analogBank6Data;
 557         u32 *analogBank6TPCData;
 558         u32 *analogBank7Data;
 559         u32 *addac5416_21;
 560         u32 *bank6Temp;
 561
 562         int16_t txpower_indexoffset;
 563         u32 beacon_interval;
 564         u32 slottime;
 565         u32 acktimeout;
 566         u32 ctstimeout;
 567         u32 globaltxtimeout;
 568         u8 gbeacon_rate;
 569
 570         /* ANI */
 571         u32 proc_phyerr;
 572         u32 aniperiod;
 573         struct ar5416AniState *curani;
 574         struct ar5416AniState ani[255];
 575         int totalSizeDesired[5];
 576         int coarse_high[5];
 577         int coarse_low[5];
 578         int firpwr[5];
 579         enum ath9k_ani_cmd ani_function;
 580
 581         /* Bluetooth coexistance */
 582         struct ath_btcoex_hw btcoex_hw;
 583
 584         u32 intr_txqs;
 585         u8 txchainmask;
 586         u8 rxchainmask;
 587
 588         u32 originalGain[22];
 589         int initPDADC;
 590         int PDADCdelta;
 591         u8 led_pin;
 592
 593         struct ar5416IniArray iniModes;
 594         struct ar5416IniArray iniCommon;
 595         struct ar5416IniArray iniBank0;
 596         struct ar5416IniArray iniBB_RfGain;
 597         struct ar5416IniArray iniBank1;
 598         struct ar5416IniArray iniBank2;
 599         struct ar5416IniArray iniBank3;
 600         struct ar5416IniArray iniBank6;
 601         struct ar5416IniArray iniBank6TPC;
 602         struct ar5416IniArray iniBank7;
 603         struct ar5416IniArray iniAddac;
 604         struct ar5416IniArray iniPcieSerdes;
 605         struct ar5416IniArray iniModesAdditional;
 606         struct ar5416IniArray iniModesRxGain;
 607         struct ar5416IniArray iniModesTxGain;
 608         struct ar5416IniArray iniModes_9271_1_0_only;
 609         struct ar5416IniArray iniCckfirNormal;
 610         struct ar5416IniArray iniCckfirJapan2484;
 611
 612         u32 intr_gen_timer_trigger;
 613         u32 intr_gen_timer_thresh;
 614         struct ath_gen_timer_table hw_gen_timers;
 615 };
 616
 617 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
 618 {
 619         return &ah->common;
 620 }
 621
 622 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
 623 {
 624         return &(ath9k_hw_common(ah)->regulatory);
 625 }
 626
 627 /* Initialization, Detach, Reset */
 628 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
 629 void ath9k_hw_detach(struct ath_hw *ah);
 630 int ath9k_hw_init(struct ath_hw *ah);
 631 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 632                    bool bChannelChange);
 633 void ath9k_hw_fill_cap_info(struct ath_hw *ah);
 634 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
 635                             u32 capability, u32 *result);
 636 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
 637                             u32 capability, u32 setting, int *status);
 638
 639 /* Key Cache Management */
 640 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
 641 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
 642 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
 643                                  const struct ath9k_keyval *k,
 644                                  const u8 *mac);
 645 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
 646
 647 /* GPIO / RFKILL / Antennae */
 648 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
 649 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
 650 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
 651                          u32 ah_signal_type);
 652 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
 653 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
 654 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
 655 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
 656                                enum ath9k_ant_setting settings,
 657                                struct ath9k_channel *chan,
 658                                u8 *tx_chainmask, u8 *rx_chainmask,
 659                                u8 *antenna_cfgd);
 660
 661 /* General Operation */
 662 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
 663 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
 664 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
 665 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 666                            const struct ath_rate_table *rates,
 667                            u32 frameLen, u16 rateix, bool shortPreamble);
 668 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 669                                   struct ath9k_channel *chan,
 670                                   struct chan_centers *centers);
 671 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
 672 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
 673 bool ath9k_hw_phy_disable(struct ath_hw *ah);
 674 bool ath9k_hw_disable(struct ath_hw *ah);
 675 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
 676 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
 677 void ath9k_hw_setopmode(struct ath_hw *ah);
 678 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
 679 void ath9k_hw_setbssidmask(struct ath_hw *ah);
 680 void ath9k_hw_write_associd(struct ath_hw *ah);
 681 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
 682 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
 683 void ath9k_hw_reset_tsf(struct ath_hw *ah);
 684 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
 685 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
 686 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
 687 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
 688 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
 689                                     const struct ath9k_beacon_state *bs);
 690
 691 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
 692
 693 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
 694
 695 /* Interrupt Handling */
 696 bool ath9k_hw_intrpend(struct ath_hw *ah);
 697 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
 698 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
 699
 700 /* Generic hw timer primitives */
 701 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
 702                                           void (*trigger)(void *),
 703                                           void (*overflow)(void *),
 704                                           void *arg,
 705                                           u8 timer_index);
 706 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
 707                               struct ath_gen_timer *timer,
 708                               u32 timer_next,
 709                               u32 timer_period);
 710 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
 711
 712 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
 713 void ath_gen_timer_isr(struct ath_hw *hw);
 714 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 715
 716 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
 717
 718 #define ATH_PCIE_CAP_LINK_CTRL  0x70
 719 #define ATH_PCIE_CAP_LINK_L0S   1
 720 #define ATH_PCIE_CAP_LINK_L1    2
 721
 722 #endif