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ath9k: initialize hw prior to debugfs
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / mac.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18
19 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
20 struct ath9k_tx_queue_info *qi)
21 {
22 ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
24 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
26 ah->txurn_interrupt_mask);
27
28 REG_WRITE(ah, AR_IMR_S0,
29 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
30 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
31 REG_WRITE(ah, AR_IMR_S1,
32 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
33 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
34 REG_RMW_FIELD(ah, AR_IMR_S2,
35 AR_IMR_S2_QCU_TXURN, ah->txurn_interrupt_mask);
36 }
37
38 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
39 {
40 return REG_READ(ah, AR_QTXDP(q));
41 }
42 EXPORT_SYMBOL(ath9k_hw_gettxbuf);
43
44 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
45 {
46 REG_WRITE(ah, AR_QTXDP(q), txdp);
47 }
48 EXPORT_SYMBOL(ath9k_hw_puttxbuf);
49
50 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
51 {
52 ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
53 "Enable TXE on queue: %u\n", q);
54 REG_WRITE(ah, AR_Q_TXE, 1 << q);
55 }
56 EXPORT_SYMBOL(ath9k_hw_txstart);
57
58 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
59 {
60 u32 npend;
61
62 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
63 if (npend == 0) {
64
65 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
66 npend = 1;
67 }
68
69 return npend;
70 }
71 EXPORT_SYMBOL(ath9k_hw_numtxpending);
72
73 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
74 {
75 u32 txcfg, curLevel, newLevel;
76 enum ath9k_int omask;
77
78 if (ah->tx_trig_level >= MAX_TX_FIFO_THRESHOLD)
79 return false;
80
81 omask = ath9k_hw_set_interrupts(ah, ah->mask_reg & ~ATH9K_INT_GLOBAL);
82
83 txcfg = REG_READ(ah, AR_TXCFG);
84 curLevel = MS(txcfg, AR_FTRIG);
85 newLevel = curLevel;
86 if (bIncTrigLevel) {
87 if (curLevel < MAX_TX_FIFO_THRESHOLD)
88 newLevel++;
89 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
90 newLevel--;
91 if (newLevel != curLevel)
92 REG_WRITE(ah, AR_TXCFG,
93 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
94
95 ath9k_hw_set_interrupts(ah, omask);
96
97 ah->tx_trig_level = newLevel;
98
99 return newLevel != curLevel;
100 }
101 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
102
103 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
104 {
105 #define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
106 #define ATH9K_TIME_QUANTUM 100 /* usec */
107 struct ath_common *common = ath9k_hw_common(ah);
108 struct ath9k_hw_capabilities *pCap = &ah->caps;
109 struct ath9k_tx_queue_info *qi;
110 u32 tsfLow, j, wait;
111 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
112
113 if (q >= pCap->total_queues) {
114 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
115 "invalid queue: %u\n", q);
116 return false;
117 }
118
119 qi = &ah->txq[q];
120 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
121 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
122 "inactive queue: %u\n", q);
123 return false;
124 }
125
126 REG_WRITE(ah, AR_Q_TXD, 1 << q);
127
128 for (wait = wait_time; wait != 0; wait--) {
129 if (ath9k_hw_numtxpending(ah, q) == 0)
130 break;
131 udelay(ATH9K_TIME_QUANTUM);
132 }
133
134 if (ath9k_hw_numtxpending(ah, q)) {
135 ath_print(common, ATH_DBG_QUEUE,
136 "%s: Num of pending TX Frames %d on Q %d\n",
137 __func__, ath9k_hw_numtxpending(ah, q), q);
138
139 for (j = 0; j < 2; j++) {
140 tsfLow = REG_READ(ah, AR_TSF_L32);
141 REG_WRITE(ah, AR_QUIET2,
142 SM(10, AR_QUIET2_QUIET_DUR));
143 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
144 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
145 REG_SET_BIT(ah, AR_TIMER_MODE,
146 AR_QUIET_TIMER_EN);
147
148 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
149 break;
150
151 ath_print(common, ATH_DBG_QUEUE,
152 "TSF has moved while trying to set "
153 "quiet time TSF: 0x%08x\n", tsfLow);
154 }
155
156 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
157
158 udelay(200);
159 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
160
161 wait = wait_time;
162 while (ath9k_hw_numtxpending(ah, q)) {
163 if ((--wait) == 0) {
164 ath_print(common, ATH_DBG_QUEUE,
165 "Failed to stop TX DMA in 100 "
166 "msec after killing last frame\n");
167 break;
168 }
169 udelay(ATH9K_TIME_QUANTUM);
170 }
171
172 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
173 }
174
175 REG_WRITE(ah, AR_Q_TXD, 0);
176 return wait != 0;
177
178 #undef ATH9K_TX_STOP_DMA_TIMEOUT
179 #undef ATH9K_TIME_QUANTUM
180 }
181 EXPORT_SYMBOL(ath9k_hw_stoptxdma);
182
183 void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
184 u32 segLen, bool firstSeg,
185 bool lastSeg, const struct ath_desc *ds0)
186 {
187 struct ar5416_desc *ads = AR5416DESC(ds);
188
189 if (firstSeg) {
190 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
191 } else if (lastSeg) {
192 ads->ds_ctl0 = 0;
193 ads->ds_ctl1 = segLen;
194 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
195 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
196 } else {
197 ads->ds_ctl0 = 0;
198 ads->ds_ctl1 = segLen | AR_TxMore;
199 ads->ds_ctl2 = 0;
200 ads->ds_ctl3 = 0;
201 }
202 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
203 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
204 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
205 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
206 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
207 }
208 EXPORT_SYMBOL(ath9k_hw_filltxdesc);
209
210 void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
211 {
212 struct ar5416_desc *ads = AR5416DESC(ds);
213
214 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
215 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
216 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
217 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
218 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
219 }
220 EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
221
222 int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds)
223 {
224 struct ar5416_desc *ads = AR5416DESC(ds);
225
226 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
227 return -EINPROGRESS;
228
229 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
230 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
231 ds->ds_txstat.ts_status = 0;
232 ds->ds_txstat.ts_flags = 0;
233
234 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
235 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
236 if (ads->ds_txstatus1 & AR_Filtered)
237 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
238 if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
239 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
240 ath9k_hw_updatetxtriglevel(ah, true);
241 }
242 if (ads->ds_txstatus9 & AR_TxOpExceeded)
243 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
244 if (ads->ds_txstatus1 & AR_TxTimerExpired)
245 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
246
247 if (ads->ds_txstatus1 & AR_DescCfgErr)
248 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
249 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
250 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
251 ath9k_hw_updatetxtriglevel(ah, true);
252 }
253 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
254 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
255 ath9k_hw_updatetxtriglevel(ah, true);
256 }
257 if (ads->ds_txstatus0 & AR_TxBaStatus) {
258 ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
259 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
260 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
261 }
262
263 ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
264 switch (ds->ds_txstat.ts_rateindex) {
265 case 0:
266 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
267 break;
268 case 1:
269 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
270 break;
271 case 2:
272 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
273 break;
274 case 3:
275 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
276 break;
277 }
278
279 ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
280 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
281 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
282 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
283 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
284 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
285 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
286 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
287 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
288 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
289 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
290 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
291 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
292 ds->ds_txstat.ts_antenna = 0;
293
294 return 0;
295 }
296 EXPORT_SYMBOL(ath9k_hw_txprocdesc);
297
298 void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
299 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
300 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
301 {
302 struct ar5416_desc *ads = AR5416DESC(ds);
303
304 txPower += ah->txpower_indexoffset;
305 if (txPower > 63)
306 txPower = 63;
307
308 ads->ds_ctl0 = (pktLen & AR_FrameLen)
309 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
310 | SM(txPower, AR_XmitPower)
311 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
312 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
313 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
314 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
315
316 ads->ds_ctl1 =
317 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
318 | SM(type, AR_FrameType)
319 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
320 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
321 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
322
323 ads->ds_ctl6 = SM(keyType, AR_EncrType);
324
325 if (AR_SREV_9285(ah)) {
326 ads->ds_ctl8 = 0;
327 ads->ds_ctl9 = 0;
328 ads->ds_ctl10 = 0;
329 ads->ds_ctl11 = 0;
330 }
331 }
332 EXPORT_SYMBOL(ath9k_hw_set11n_txdesc);
333
334 void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
335 struct ath_desc *lastds,
336 u32 durUpdateEn, u32 rtsctsRate,
337 u32 rtsctsDuration,
338 struct ath9k_11n_rate_series series[],
339 u32 nseries, u32 flags)
340 {
341 struct ar5416_desc *ads = AR5416DESC(ds);
342 struct ar5416_desc *last_ads = AR5416DESC(lastds);
343 u32 ds_ctl0;
344
345 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
346 ds_ctl0 = ads->ds_ctl0;
347
348 if (flags & ATH9K_TXDESC_RTSENA) {
349 ds_ctl0 &= ~AR_CTSEnable;
350 ds_ctl0 |= AR_RTSEnable;
351 } else {
352 ds_ctl0 &= ~AR_RTSEnable;
353 ds_ctl0 |= AR_CTSEnable;
354 }
355
356 ads->ds_ctl0 = ds_ctl0;
357 } else {
358 ads->ds_ctl0 =
359 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
360 }
361
362 ads->ds_ctl2 = set11nTries(series, 0)
363 | set11nTries(series, 1)
364 | set11nTries(series, 2)
365 | set11nTries(series, 3)
366 | (durUpdateEn ? AR_DurUpdateEna : 0)
367 | SM(0, AR_BurstDur);
368
369 ads->ds_ctl3 = set11nRate(series, 0)
370 | set11nRate(series, 1)
371 | set11nRate(series, 2)
372 | set11nRate(series, 3);
373
374 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
375 | set11nPktDurRTSCTS(series, 1);
376
377 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
378 | set11nPktDurRTSCTS(series, 3);
379
380 ads->ds_ctl7 = set11nRateFlags(series, 0)
381 | set11nRateFlags(series, 1)
382 | set11nRateFlags(series, 2)
383 | set11nRateFlags(series, 3)
384 | SM(rtsctsRate, AR_RTSCTSRate);
385 last_ads->ds_ctl2 = ads->ds_ctl2;
386 last_ads->ds_ctl3 = ads->ds_ctl3;
387 }
388 EXPORT_SYMBOL(ath9k_hw_set11n_ratescenario);
389
390 void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
391 u32 aggrLen)
392 {
393 struct ar5416_desc *ads = AR5416DESC(ds);
394
395 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
396 ads->ds_ctl6 &= ~AR_AggrLen;
397 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
398 }
399 EXPORT_SYMBOL(ath9k_hw_set11n_aggr_first);
400
401 void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
402 u32 numDelims)
403 {
404 struct ar5416_desc *ads = AR5416DESC(ds);
405 unsigned int ctl6;
406
407 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
408
409 ctl6 = ads->ds_ctl6;
410 ctl6 &= ~AR_PadDelim;
411 ctl6 |= SM(numDelims, AR_PadDelim);
412 ads->ds_ctl6 = ctl6;
413 }
414 EXPORT_SYMBOL(ath9k_hw_set11n_aggr_middle);
415
416 void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
417 {
418 struct ar5416_desc *ads = AR5416DESC(ds);
419
420 ads->ds_ctl1 |= AR_IsAggr;
421 ads->ds_ctl1 &= ~AR_MoreAggr;
422 ads->ds_ctl6 &= ~AR_PadDelim;
423 }
424 EXPORT_SYMBOL(ath9k_hw_set11n_aggr_last);
425
426 void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
427 {
428 struct ar5416_desc *ads = AR5416DESC(ds);
429
430 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
431 }
432 EXPORT_SYMBOL(ath9k_hw_clr11n_aggr);
433
434 void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
435 u32 burstDuration)
436 {
437 struct ar5416_desc *ads = AR5416DESC(ds);
438
439 ads->ds_ctl2 &= ~AR_BurstDur;
440 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
441 }
442 EXPORT_SYMBOL(ath9k_hw_set11n_burstduration);
443
444 void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
445 u32 vmf)
446 {
447 struct ar5416_desc *ads = AR5416DESC(ds);
448
449 if (vmf)
450 ads->ds_ctl0 |= AR_VirtMoreFrag;
451 else
452 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
453 }
454
455 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
456 {
457 *txqs &= ah->intr_txqs;
458 ah->intr_txqs &= ~(*txqs);
459 }
460 EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs);
461
462 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
463 const struct ath9k_tx_queue_info *qinfo)
464 {
465 u32 cw;
466 struct ath_common *common = ath9k_hw_common(ah);
467 struct ath9k_hw_capabilities *pCap = &ah->caps;
468 struct ath9k_tx_queue_info *qi;
469
470 if (q >= pCap->total_queues) {
471 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
472 "invalid queue: %u\n", q);
473 return false;
474 }
475
476 qi = &ah->txq[q];
477 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
478 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
479 "inactive queue: %u\n", q);
480 return false;
481 }
482
483 ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
484
485 qi->tqi_ver = qinfo->tqi_ver;
486 qi->tqi_subtype = qinfo->tqi_subtype;
487 qi->tqi_qflags = qinfo->tqi_qflags;
488 qi->tqi_priority = qinfo->tqi_priority;
489 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
490 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
491 else
492 qi->tqi_aifs = INIT_AIFS;
493 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
494 cw = min(qinfo->tqi_cwmin, 1024U);
495 qi->tqi_cwmin = 1;
496 while (qi->tqi_cwmin < cw)
497 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
498 } else
499 qi->tqi_cwmin = qinfo->tqi_cwmin;
500 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
501 cw = min(qinfo->tqi_cwmax, 1024U);
502 qi->tqi_cwmax = 1;
503 while (qi->tqi_cwmax < cw)
504 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
505 } else
506 qi->tqi_cwmax = INIT_CWMAX;
507
508 if (qinfo->tqi_shretry != 0)
509 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
510 else
511 qi->tqi_shretry = INIT_SH_RETRY;
512 if (qinfo->tqi_lgretry != 0)
513 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
514 else
515 qi->tqi_lgretry = INIT_LG_RETRY;
516 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
517 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
518 qi->tqi_burstTime = qinfo->tqi_burstTime;
519 qi->tqi_readyTime = qinfo->tqi_readyTime;
520
521 switch (qinfo->tqi_subtype) {
522 case ATH9K_WME_UPSD:
523 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
524 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
525 break;
526 default:
527 break;
528 }
529
530 return true;
531 }
532 EXPORT_SYMBOL(ath9k_hw_set_txq_props);
533
534 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
535 struct ath9k_tx_queue_info *qinfo)
536 {
537 struct ath_common *common = ath9k_hw_common(ah);
538 struct ath9k_hw_capabilities *pCap = &ah->caps;
539 struct ath9k_tx_queue_info *qi;
540
541 if (q >= pCap->total_queues) {
542 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
543 "invalid queue: %u\n", q);
544 return false;
545 }
546
547 qi = &ah->txq[q];
548 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
549 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
550 "inactive queue: %u\n", q);
551 return false;
552 }
553
554 qinfo->tqi_qflags = qi->tqi_qflags;
555 qinfo->tqi_ver = qi->tqi_ver;
556 qinfo->tqi_subtype = qi->tqi_subtype;
557 qinfo->tqi_qflags = qi->tqi_qflags;
558 qinfo->tqi_priority = qi->tqi_priority;
559 qinfo->tqi_aifs = qi->tqi_aifs;
560 qinfo->tqi_cwmin = qi->tqi_cwmin;
561 qinfo->tqi_cwmax = qi->tqi_cwmax;
562 qinfo->tqi_shretry = qi->tqi_shretry;
563 qinfo->tqi_lgretry = qi->tqi_lgretry;
564 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
565 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
566 qinfo->tqi_burstTime = qi->tqi_burstTime;
567 qinfo->tqi_readyTime = qi->tqi_readyTime;
568
569 return true;
570 }
571 EXPORT_SYMBOL(ath9k_hw_get_txq_props);
572
573 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
574 const struct ath9k_tx_queue_info *qinfo)
575 {
576 struct ath_common *common = ath9k_hw_common(ah);
577 struct ath9k_tx_queue_info *qi;
578 struct ath9k_hw_capabilities *pCap = &ah->caps;
579 int q;
580
581 switch (type) {
582 case ATH9K_TX_QUEUE_BEACON:
583 q = pCap->total_queues - 1;
584 break;
585 case ATH9K_TX_QUEUE_CAB:
586 q = pCap->total_queues - 2;
587 break;
588 case ATH9K_TX_QUEUE_PSPOLL:
589 q = 1;
590 break;
591 case ATH9K_TX_QUEUE_UAPSD:
592 q = pCap->total_queues - 3;
593 break;
594 case ATH9K_TX_QUEUE_DATA:
595 for (q = 0; q < pCap->total_queues; q++)
596 if (ah->txq[q].tqi_type ==
597 ATH9K_TX_QUEUE_INACTIVE)
598 break;
599 if (q == pCap->total_queues) {
600 ath_print(common, ATH_DBG_FATAL,
601 "No available TX queue\n");
602 return -1;
603 }
604 break;
605 default:
606 ath_print(common, ATH_DBG_FATAL,
607 "Invalid TX queue type: %u\n", type);
608 return -1;
609 }
610
611 ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
612
613 qi = &ah->txq[q];
614 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
615 ath_print(common, ATH_DBG_FATAL,
616 "TX queue: %u already active\n", q);
617 return -1;
618 }
619 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
620 qi->tqi_type = type;
621 if (qinfo == NULL) {
622 qi->tqi_qflags =
623 TXQ_FLAG_TXOKINT_ENABLE
624 | TXQ_FLAG_TXERRINT_ENABLE
625 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
626 qi->tqi_aifs = INIT_AIFS;
627 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
628 qi->tqi_cwmax = INIT_CWMAX;
629 qi->tqi_shretry = INIT_SH_RETRY;
630 qi->tqi_lgretry = INIT_LG_RETRY;
631 qi->tqi_physCompBuf = 0;
632 } else {
633 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
634 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
635 }
636
637 return q;
638 }
639 EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
640
641 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
642 {
643 struct ath9k_hw_capabilities *pCap = &ah->caps;
644 struct ath_common *common = ath9k_hw_common(ah);
645 struct ath9k_tx_queue_info *qi;
646
647 if (q >= pCap->total_queues) {
648 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
649 "invalid queue: %u\n", q);
650 return false;
651 }
652 qi = &ah->txq[q];
653 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
654 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
655 "inactive queue: %u\n", q);
656 return false;
657 }
658
659 ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
660
661 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
662 ah->txok_interrupt_mask &= ~(1 << q);
663 ah->txerr_interrupt_mask &= ~(1 << q);
664 ah->txdesc_interrupt_mask &= ~(1 << q);
665 ah->txeol_interrupt_mask &= ~(1 << q);
666 ah->txurn_interrupt_mask &= ~(1 << q);
667 ath9k_hw_set_txq_interrupts(ah, qi);
668
669 return true;
670 }
671 EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
672
673 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
674 {
675 struct ath9k_hw_capabilities *pCap = &ah->caps;
676 struct ath_common *common = ath9k_hw_common(ah);
677 struct ath9k_channel *chan = ah->curchan;
678 struct ath9k_tx_queue_info *qi;
679 u32 cwMin, chanCwMin, value;
680
681 if (q >= pCap->total_queues) {
682 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
683 "invalid queue: %u\n", q);
684 return false;
685 }
686
687 qi = &ah->txq[q];
688 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
689 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
690 "inactive queue: %u\n", q);
691 return true;
692 }
693
694 ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
695
696 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
697 if (chan && IS_CHAN_B(chan))
698 chanCwMin = INIT_CWMIN_11B;
699 else
700 chanCwMin = INIT_CWMIN;
701
702 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
703 } else
704 cwMin = qi->tqi_cwmin;
705
706 REG_WRITE(ah, AR_DLCL_IFS(q),
707 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
708 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
709 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
710
711 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
712 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
713 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
714 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
715
716 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
717 REG_WRITE(ah, AR_DMISC(q),
718 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
719
720 if (qi->tqi_cbrPeriod) {
721 REG_WRITE(ah, AR_QCBRCFG(q),
722 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
723 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
724 REG_WRITE(ah, AR_QMISC(q),
725 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
726 (qi->tqi_cbrOverflowLimit ?
727 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
728 }
729 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
730 REG_WRITE(ah, AR_QRDYTIMECFG(q),
731 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
732 AR_Q_RDYTIMECFG_EN);
733 }
734
735 REG_WRITE(ah, AR_DCHNTIME(q),
736 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
737 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
738
739 if (qi->tqi_burstTime
740 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
741 REG_WRITE(ah, AR_QMISC(q),
742 REG_READ(ah, AR_QMISC(q)) |
743 AR_Q_MISC_RDYTIME_EXP_POLICY);
744
745 }
746
747 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
748 REG_WRITE(ah, AR_DMISC(q),
749 REG_READ(ah, AR_DMISC(q)) |
750 AR_D_MISC_POST_FR_BKOFF_DIS);
751 }
752 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
753 REG_WRITE(ah, AR_DMISC(q),
754 REG_READ(ah, AR_DMISC(q)) |
755 AR_D_MISC_FRAG_BKOFF_EN);
756 }
757 switch (qi->tqi_type) {
758 case ATH9K_TX_QUEUE_BEACON:
759 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
760 | AR_Q_MISC_FSP_DBA_GATED
761 | AR_Q_MISC_BEACON_USE
762 | AR_Q_MISC_CBR_INCR_DIS1);
763
764 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
765 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
766 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
767 | AR_D_MISC_BEACON_USE
768 | AR_D_MISC_POST_FR_BKOFF_DIS);
769 break;
770 case ATH9K_TX_QUEUE_CAB:
771 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
772 | AR_Q_MISC_FSP_DBA_GATED
773 | AR_Q_MISC_CBR_INCR_DIS1
774 | AR_Q_MISC_CBR_INCR_DIS0);
775 value = (qi->tqi_readyTime -
776 (ah->config.sw_beacon_response_time -
777 ah->config.dma_beacon_response_time) -
778 ah->config.additional_swba_backoff) * 1024;
779 REG_WRITE(ah, AR_QRDYTIMECFG(q),
780 value | AR_Q_RDYTIMECFG_EN);
781 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
782 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
783 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
784 break;
785 case ATH9K_TX_QUEUE_PSPOLL:
786 REG_WRITE(ah, AR_QMISC(q),
787 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
788 break;
789 case ATH9K_TX_QUEUE_UAPSD:
790 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
791 AR_D_MISC_POST_FR_BKOFF_DIS);
792 break;
793 default:
794 break;
795 }
796
797 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
798 REG_WRITE(ah, AR_DMISC(q),
799 REG_READ(ah, AR_DMISC(q)) |
800 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
801 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
802 AR_D_MISC_POST_FR_BKOFF_DIS);
803 }
804
805 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
806 ah->txok_interrupt_mask |= 1 << q;
807 else
808 ah->txok_interrupt_mask &= ~(1 << q);
809 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
810 ah->txerr_interrupt_mask |= 1 << q;
811 else
812 ah->txerr_interrupt_mask &= ~(1 << q);
813 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
814 ah->txdesc_interrupt_mask |= 1 << q;
815 else
816 ah->txdesc_interrupt_mask &= ~(1 << q);
817 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
818 ah->txeol_interrupt_mask |= 1 << q;
819 else
820 ah->txeol_interrupt_mask &= ~(1 << q);
821 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
822 ah->txurn_interrupt_mask |= 1 << q;
823 else
824 ah->txurn_interrupt_mask &= ~(1 << q);
825 ath9k_hw_set_txq_interrupts(ah, qi);
826
827 return true;
828 }
829 EXPORT_SYMBOL(ath9k_hw_resettxqueue);
830
831 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
832 u32 pa, struct ath_desc *nds, u64 tsf)
833 {
834 struct ar5416_desc ads;
835 struct ar5416_desc *adsp = AR5416DESC(ds);
836 u32 phyerr;
837
838 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
839 return -EINPROGRESS;
840
841 ads.u.rx = adsp->u.rx;
842
843 ds->ds_rxstat.rs_status = 0;
844 ds->ds_rxstat.rs_flags = 0;
845
846 ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
847 ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp;
848
849 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
850 ds->ds_rxstat.rs_rssi = ATH9K_RSSI_BAD;
851 ds->ds_rxstat.rs_rssi_ctl0 = ATH9K_RSSI_BAD;
852 ds->ds_rxstat.rs_rssi_ctl1 = ATH9K_RSSI_BAD;
853 ds->ds_rxstat.rs_rssi_ctl2 = ATH9K_RSSI_BAD;
854 ds->ds_rxstat.rs_rssi_ext0 = ATH9K_RSSI_BAD;
855 ds->ds_rxstat.rs_rssi_ext1 = ATH9K_RSSI_BAD;
856 ds->ds_rxstat.rs_rssi_ext2 = ATH9K_RSSI_BAD;
857 } else {
858 ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
859 ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
860 AR_RxRSSIAnt00);
861 ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
862 AR_RxRSSIAnt01);
863 ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
864 AR_RxRSSIAnt02);
865 ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4,
866 AR_RxRSSIAnt10);
867 ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4,
868 AR_RxRSSIAnt11);
869 ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4,
870 AR_RxRSSIAnt12);
871 }
872 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
873 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
874 else
875 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID;
876
877 ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
878 ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
879
880 ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
881 ds->ds_rxstat.rs_moreaggr =
882 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
883 ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
884 ds->ds_rxstat.rs_flags =
885 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
886 ds->ds_rxstat.rs_flags |=
887 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
888
889 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
890 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
891 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
892 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
893 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
894 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
895
896 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
897 if (ads.ds_rxstatus8 & AR_CRCErr)
898 ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
899 else if (ads.ds_rxstatus8 & AR_PHYErr) {
900 ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
901 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
902 ds->ds_rxstat.rs_phyerr = phyerr;
903 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
904 ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
905 else if (ads.ds_rxstatus8 & AR_MichaelErr)
906 ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
907 }
908
909 return 0;
910 }
911 EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
912
913 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
914 u32 size, u32 flags)
915 {
916 struct ar5416_desc *ads = AR5416DESC(ds);
917 struct ath9k_hw_capabilities *pCap = &ah->caps;
918
919 ads->ds_ctl1 = size & AR_BufLen;
920 if (flags & ATH9K_RXDESC_INTREQ)
921 ads->ds_ctl1 |= AR_RxIntrReq;
922
923 ads->ds_rxstatus8 &= ~AR_RxDone;
924 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
925 memset(&(ads->u), 0, sizeof(ads->u));
926 }
927 EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
928
929 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
930 {
931 u32 reg;
932
933 if (set) {
934 REG_SET_BIT(ah, AR_DIAG_SW,
935 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
936
937 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
938 0, AH_WAIT_TIMEOUT)) {
939 REG_CLR_BIT(ah, AR_DIAG_SW,
940 (AR_DIAG_RX_DIS |
941 AR_DIAG_RX_ABORT));
942
943 reg = REG_READ(ah, AR_OBS_BUS_1);
944 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
945 "RX failed to go idle in 10 ms RXSM=0x%x\n",
946 reg);
947
948 return false;
949 }
950 } else {
951 REG_CLR_BIT(ah, AR_DIAG_SW,
952 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
953 }
954
955 return true;
956 }
957 EXPORT_SYMBOL(ath9k_hw_setrxabort);
958
959 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
960 {
961 REG_WRITE(ah, AR_RXDP, rxdp);
962 }
963 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
964
965 void ath9k_hw_rxena(struct ath_hw *ah)
966 {
967 REG_WRITE(ah, AR_CR, AR_CR_RXE);
968 }
969 EXPORT_SYMBOL(ath9k_hw_rxena);
970
971 void ath9k_hw_startpcureceive(struct ath_hw *ah)
972 {
973 ath9k_enable_mib_counters(ah);
974
975 ath9k_ani_reset(ah);
976
977 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
978 }
979 EXPORT_SYMBOL(ath9k_hw_startpcureceive);
980
981 void ath9k_hw_stoppcurecv(struct ath_hw *ah)
982 {
983 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
984
985 ath9k_hw_disable_mib_counters(ah);
986 }
987 EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
988
989 bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
990 {
991 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
992 #define AH_RX_TIME_QUANTUM 100 /* usec */
993 struct ath_common *common = ath9k_hw_common(ah);
994 int i;
995
996 REG_WRITE(ah, AR_CR, AR_CR_RXD);
997
998 /* Wait for rx enable bit to go low */
999 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
1000 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
1001 break;
1002 udelay(AH_TIME_QUANTUM);
1003 }
1004
1005 if (i == 0) {
1006 ath_print(common, ATH_DBG_FATAL,
1007 "DMA failed to stop in %d ms "
1008 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
1009 AH_RX_STOP_DMA_TIMEOUT / 1000,
1010 REG_READ(ah, AR_CR),
1011 REG_READ(ah, AR_DIAG_SW));
1012 return false;
1013 } else {
1014 return true;
1015 }
1016
1017 #undef AH_RX_TIME_QUANTUM
1018 #undef AH_RX_STOP_DMA_TIMEOUT
1019 }
1020 EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
Linux kernel - Deliverables
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