2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/pci.h>
21 static struct pci_device_id ath_pci_id_table
[] __devinitdata
= {
22 { PCI_VDEVICE(ATHEROS
, 0x0023) }, /* PCI */
23 { PCI_VDEVICE(ATHEROS
, 0x0024) }, /* PCI-E */
24 { PCI_VDEVICE(ATHEROS
, 0x0027) }, /* PCI */
25 { PCI_VDEVICE(ATHEROS
, 0x0029) }, /* PCI */
26 { PCI_VDEVICE(ATHEROS
, 0x002A) }, /* PCI-E */
27 { PCI_VDEVICE(ATHEROS
, 0x002B) }, /* PCI-E */
28 { PCI_VDEVICE(ATHEROS
, 0x002D) }, /* PCI */
29 { PCI_VDEVICE(ATHEROS
, 0x002E) }, /* PCI-E */
33 /* return bus cachesize in 4B word units */
34 static void ath_pci_read_cachesize(struct ath_common
*common
, int *csz
)
36 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
39 pci_read_config_byte(to_pci_dev(sc
->dev
), PCI_CACHE_LINE_SIZE
, &u8tmp
);
43 * This check was put in to avoid "unplesant" consequences if
44 * the bootrom has not fully initialized all PCI devices.
45 * Sometimes the cache line size register is not set
49 *csz
= DEFAULT_CACHELINE
>> 2; /* Use the default size */
52 static void ath_pci_cleanup(struct ath_common
*common
)
54 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
55 struct pci_dev
*pdev
= to_pci_dev(sc
->dev
);
57 pci_iounmap(pdev
, sc
->mem
);
58 pci_disable_device(pdev
);
59 pci_release_region(pdev
, 0);
62 static bool ath_pci_eeprom_read(struct ath_common
*common
, u32 off
, u16
*data
)
64 struct ath_hw
*ah
= (struct ath_hw
*) common
->ah
;
66 common
->ops
->read(ah
, AR5416_EEPROM_OFFSET
+ (off
<< AR5416_EEPROM_S
));
68 if (!ath9k_hw_wait(ah
,
69 AR_EEPROM_STATUS_DATA
,
70 AR_EEPROM_STATUS_DATA_BUSY
|
71 AR_EEPROM_STATUS_DATA_PROT_ACCESS
, 0,
76 *data
= MS(common
->ops
->read(ah
, AR_EEPROM_STATUS_DATA
),
77 AR_EEPROM_STATUS_DATA_VAL
);
83 * Bluetooth coexistance requires disabling ASPM.
85 static void ath_pci_bt_coex_prep(struct ath_common
*common
)
87 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
88 struct pci_dev
*pdev
= to_pci_dev(sc
->dev
);
94 pci_read_config_byte(pdev
, ATH_PCIE_CAP_LINK_CTRL
, &aspm
);
95 aspm
&= ~(ATH_PCIE_CAP_LINK_L0S
| ATH_PCIE_CAP_LINK_L1
);
96 pci_write_config_byte(pdev
, ATH_PCIE_CAP_LINK_CTRL
, aspm
);
99 const static struct ath_bus_ops ath_pci_bus_ops
= {
100 .read_cachesize
= ath_pci_read_cachesize
,
101 .cleanup
= ath_pci_cleanup
,
102 .eeprom_read
= ath_pci_eeprom_read
,
103 .bt_coex_prep
= ath_pci_bt_coex_prep
,
106 static int ath_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
109 struct ath_wiphy
*aphy
;
110 struct ath_softc
*sc
;
111 struct ieee80211_hw
*hw
;
118 if (pci_enable_device(pdev
))
121 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
124 printk(KERN_ERR
"ath9k: 32-bit DMA not available\n");
128 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
131 printk(KERN_ERR
"ath9k: 32-bit DMA consistent "
132 "DMA enable failed\n");
137 * Cache line size is used to size and align various
138 * structures used to communicate with the hardware.
140 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
143 * Linux 2.4.18 (at least) writes the cache line size
144 * register as a 16-bit wide register which is wrong.
145 * We must have this setup properly for rx buffer
146 * DMA to work so force a reasonable value here if it
149 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
150 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
153 * The default setting of latency timer yields poor results,
154 * set it to the value used by other systems. It may be worth
155 * tweaking this setting more.
157 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
159 pci_set_master(pdev
);
162 * Disable the RETRY_TIMEOUT register (0x41) to keep
163 * PCI Tx retries from interfering with C3 CPU state.
165 pci_read_config_dword(pdev
, 0x40, &val
);
166 if ((val
& 0x0000ff00) != 0)
167 pci_write_config_dword(pdev
, 0x40, val
& 0xffff00ff);
169 ret
= pci_request_region(pdev
, 0, "ath9k");
171 dev_err(&pdev
->dev
, "PCI memory region reserve error\n");
176 mem
= pci_iomap(pdev
, 0, 0);
178 printk(KERN_ERR
"PCI memory map error\n") ;
183 hw
= ieee80211_alloc_hw(sizeof(struct ath_wiphy
) +
184 sizeof(struct ath_softc
), &ath9k_ops
);
186 dev_err(&pdev
->dev
, "no memory for ieee80211_hw\n");
191 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
192 pci_set_drvdata(pdev
, hw
);
195 sc
= (struct ath_softc
*) (aphy
+ 1);
198 sc
->pri_wiphy
= aphy
;
200 sc
->dev
= &pdev
->dev
;
203 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &subsysid
);
204 ret
= ath_init_device(id
->device
, sc
, subsysid
, &ath_pci_bus_ops
);
206 dev_err(&pdev
->dev
, "failed to initialize device\n");
210 /* setup interrupt service routine */
212 ret
= request_irq(pdev
->irq
, ath_isr
, IRQF_SHARED
, "ath9k", sc
);
214 dev_err(&pdev
->dev
, "request_irq failed\n");
222 "%s: Atheros AR%s MAC/BB Rev:%x "
223 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
224 wiphy_name(hw
->wiphy
),
225 ath_mac_bb_name(ah
->hw_version
.macVersion
),
226 ah
->hw_version
.macRev
,
227 ath_rf_name((ah
->hw_version
.analog5GhzRev
& AR_RADIO_SREV_MAJOR
)),
228 ah
->hw_version
.phyRev
,
229 (unsigned long)mem
, pdev
->irq
);
235 ieee80211_free_hw(hw
);
237 pci_iounmap(pdev
, mem
);
239 pci_release_region(pdev
, 0);
241 pci_disable_device(pdev
);
245 static void ath_pci_remove(struct pci_dev
*pdev
)
247 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
248 struct ath_wiphy
*aphy
= hw
->priv
;
249 struct ath_softc
*sc
= aphy
->sc
;
256 static int ath_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
258 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
259 struct ath_wiphy
*aphy
= hw
->priv
;
260 struct ath_softc
*sc
= aphy
->sc
;
262 ath9k_hw_set_gpio(sc
->sc_ah
, sc
->sc_ah
->led_pin
, 1);
264 pci_save_state(pdev
);
265 pci_disable_device(pdev
);
266 pci_set_power_state(pdev
, PCI_D3hot
);
271 static int ath_pci_resume(struct pci_dev
*pdev
)
273 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
274 struct ath_wiphy
*aphy
= hw
->priv
;
275 struct ath_softc
*sc
= aphy
->sc
;
279 pci_restore_state(pdev
);
281 err
= pci_enable_device(pdev
);
286 * Suspend/Resume resets the PCI configuration space, so we have to
287 * re-disable the RETRY_TIMEOUT register (0x41) to keep
288 * PCI Tx retries from interfering with C3 CPU state
290 pci_read_config_dword(pdev
, 0x40, &val
);
291 if ((val
& 0x0000ff00) != 0)
292 pci_write_config_dword(pdev
, 0x40, val
& 0xffff00ff);
295 ath9k_hw_cfg_output(sc
->sc_ah
, sc
->sc_ah
->led_pin
,
296 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
297 ath9k_hw_set_gpio(sc
->sc_ah
, sc
->sc_ah
->led_pin
, 1);
302 #endif /* CONFIG_PM */
304 MODULE_DEVICE_TABLE(pci
, ath_pci_id_table
);
306 static struct pci_driver ath_pci_driver
= {
308 .id_table
= ath_pci_id_table
,
309 .probe
= ath_pci_probe
,
310 .remove
= ath_pci_remove
,
312 .suspend
= ath_pci_suspend
,
313 .resume
= ath_pci_resume
,
314 #endif /* CONFIG_PM */
317 int ath_pci_init(void)
319 return pci_register_driver(&ath_pci_driver
);
322 void ath_pci_exit(void)
324 pci_unregister_driver(&ath_pci_driver
);