drivers/net/wireless/ath/ath9k/pci.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/nl80211.h>
  20 #include <linux/pci.h>
  21 #include <linux/pci-aspm.h>
  22 #include <linux/ath9k_platform.h>
  23 #include <linux/module.h>
  24 #include "ath9k.h"
  25
  26 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
  27         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  28         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  29         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  30         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  31         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  32         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  33         { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
  34         { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
  36         { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
  37         { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
  38         { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E  AR9580 */
  39         { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E  AR9462 */
  40         { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E  AR1111/AR9485 */
  41         { 0 }
  42 };
  43
  44
  45 /* return bus cachesize in 4B word units */
  46 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
  47 {
  48         struct ath_softc *sc = (struct ath_softc *) common->priv;
  49         u8 u8tmp;
  50
  51         pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
  52         *csz = (int)u8tmp;
  53
  54         /*
  55          * This check was put in to avoid "unpleasant" consequences if
  56          * the bootrom has not fully initialized all PCI devices.
  57          * Sometimes the cache line size register is not set
  58          */
  59
  60         if (*csz == 0)
  61                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  62 }
  63
  64 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
  65 {
  66         struct ath_softc *sc = (struct ath_softc *) common->priv;
  67         struct ath9k_platform_data *pdata = sc->dev->platform_data;
  68
  69         if (pdata) {
  70                 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
  71                         ath_err(common,
  72                                 "%s: eeprom read failed, offset %08x is out of range\n",
  73                                 __func__, off);
  74                 }
  75
  76                 *data = pdata->eeprom_data[off];
  77         } else {
  78                 struct ath_hw *ah = (struct ath_hw *) common->ah;
  79
  80                 common->ops->read(ah, AR5416_EEPROM_OFFSET +
  81                                       (off << AR5416_EEPROM_S));
  82
  83                 if (!ath9k_hw_wait(ah,
  84                                    AR_EEPROM_STATUS_DATA,
  85                                    AR_EEPROM_STATUS_DATA_BUSY |
  86                                    AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  87                                    AH_WAIT_TIMEOUT)) {
  88                         return false;
  89                 }
  90
  91                 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
  92                            AR_EEPROM_STATUS_DATA_VAL);
  93         }
  94
  95         return true;
  96 }
  97
  98 static void ath_pci_extn_synch_enable(struct ath_common *common)
  99 {
 100         struct ath_softc *sc = (struct ath_softc *) common->priv;
 101         struct pci_dev *pdev = to_pci_dev(sc->dev);
 102         u8 lnkctl;
 103
 104         pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
 105         lnkctl |= PCI_EXP_LNKCTL_ES;
 106         pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
 107 }
 108
 109 /* Need to be called after we discover btcoex capabilities */
 110 static void ath_pci_aspm_init(struct ath_common *common)
 111 {
 112         struct ath_softc *sc = (struct ath_softc *) common->priv;
 113         struct ath_hw *ah = sc->sc_ah;
 114         struct pci_dev *pdev = to_pci_dev(sc->dev);
 115         struct pci_dev *parent;
 116         u16 aspm;
 117
 118         if (!ah->is_pciexpress)
 119                 return;
 120
 121         parent = pdev->bus->self;
 122         if (!parent)
 123                 return;
 124
 125         if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) {
 126                 /* Bluetooth coexistance requires disabling ASPM. */
 127                 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
 128                         PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
 129
 130                 /*
 131                  * Both upstream and downstream PCIe components should
 132                  * have the same ASPM settings.
 133                  */
 134                 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
 135                         PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
 136
 137                 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
 138                 return;
 139         }
 140
 141         pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
 142         if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
 143                 ah->aspm_enabled = true;
 144                 /* Initialize PCIe PM and SERDES registers. */
 145                 ath9k_hw_configpcipowersave(ah, false);
 146                 ath_info(common, "ASPM enabled: 0x%x\n", aspm);
 147         }
 148 }
 149
 150 static const struct ath_bus_ops ath_pci_bus_ops = {
 151         .ath_bus_type = ATH_PCI,
 152         .read_cachesize = ath_pci_read_cachesize,
 153         .eeprom_read = ath_pci_eeprom_read,
 154         .extn_synch_en = ath_pci_extn_synch_enable,
 155         .aspm_init = ath_pci_aspm_init,
 156 };
 157
 158 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 159 {
 160         void __iomem *mem;
 161         struct ath_softc *sc;
 162         struct ieee80211_hw *hw;
 163         u8 csz;
 164         u32 val;
 165         int ret = 0;
 166         char hw_name[64];
 167
 168         if (pci_enable_device(pdev))
 169                 return -EIO;
 170
 171         ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 172         if (ret) {
 173                 pr_err("32-bit DMA not available\n");
 174                 goto err_dma;
 175         }
 176
 177         ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 178         if (ret) {
 179                 pr_err("32-bit DMA consistent DMA enable failed\n");
 180                 goto err_dma;
 181         }
 182
 183         /*
 184          * Cache line size is used to size and align various
 185          * structures used to communicate with the hardware.
 186          */
 187         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 188         if (csz == 0) {
 189                 /*
 190                  * Linux 2.4.18 (at least) writes the cache line size
 191                  * register as a 16-bit wide register which is wrong.
 192                  * We must have this setup properly for rx buffer
 193                  * DMA to work so force a reasonable value here if it
 194                  * comes up zero.
 195                  */
 196                 csz = L1_CACHE_BYTES / sizeof(u32);
 197                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 198         }
 199         /*
 200          * The default setting of latency timer yields poor results,
 201          * set it to the value used by other systems. It may be worth
 202          * tweaking this setting more.
 203          */
 204         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 205
 206         pci_set_master(pdev);
 207
 208         /*
 209          * Disable the RETRY_TIMEOUT register (0x41) to keep
 210          * PCI Tx retries from interfering with C3 CPU state.
 211          */
 212         pci_read_config_dword(pdev, 0x40, &val);
 213         if ((val & 0x0000ff00) != 0)
 214                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 215
 216         ret = pci_request_region(pdev, 0, "ath9k");
 217         if (ret) {
 218                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
 219                 ret = -ENODEV;
 220                 goto err_region;
 221         }
 222
 223         mem = pci_iomap(pdev, 0, 0);
 224         if (!mem) {
 225                 pr_err("PCI memory map error\n") ;
 226                 ret = -EIO;
 227                 goto err_iomap;
 228         }
 229
 230         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
 231         if (!hw) {
 232                 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
 233                 ret = -ENOMEM;
 234                 goto err_alloc_hw;
 235         }
 236
 237         SET_IEEE80211_DEV(hw, &pdev->dev);
 238         pci_set_drvdata(pdev, hw);
 239
 240         sc = hw->priv;
 241         sc->hw = hw;
 242         sc->dev = &pdev->dev;
 243         sc->mem = mem;
 244
 245         /* Will be cleared in ath9k_start() */
 246         set_bit(SC_OP_INVALID, &sc->sc_flags);
 247
 248         ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
 249         if (ret) {
 250                 dev_err(&pdev->dev, "request_irq failed\n");
 251                 goto err_irq;
 252         }
 253
 254         sc->irq = pdev->irq;
 255
 256         ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
 257         if (ret) {
 258                 dev_err(&pdev->dev, "Failed to initialize device\n");
 259                 goto err_init;
 260         }
 261
 262         ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
 263         wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
 264                    hw_name, (unsigned long)mem, pdev->irq);
 265
 266         return 0;
 267
 268 err_init:
 269         free_irq(sc->irq, sc);
 270 err_irq:
 271         ieee80211_free_hw(hw);
 272 err_alloc_hw:
 273         pci_iounmap(pdev, mem);
 274 err_iomap:
 275         pci_release_region(pdev, 0);
 276 err_region:
 277         /* Nothing */
 278 err_dma:
 279         pci_disable_device(pdev);
 280         return ret;
 281 }
 282
 283 static void ath_pci_remove(struct pci_dev *pdev)
 284 {
 285         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 286         struct ath_softc *sc = hw->priv;
 287         void __iomem *mem = sc->mem;
 288
 289         if (!is_ath9k_unloaded)
 290                 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
 291         ath9k_deinit_device(sc);
 292         free_irq(sc->irq, sc);
 293         ieee80211_free_hw(sc->hw);
 294
 295         pci_iounmap(pdev, mem);
 296         pci_disable_device(pdev);
 297         pci_release_region(pdev, 0);
 298 }
 299
 300 #ifdef CONFIG_PM
 301
 302 static int ath_pci_suspend(struct device *device)
 303 {
 304         struct pci_dev *pdev = to_pci_dev(device);
 305         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 306         struct ath_softc *sc = hw->priv;
 307
 308         if (sc->wow_enabled)
 309                 return 0;
 310
 311         /* The device has to be moved to FULLSLEEP forcibly.
 312          * Otherwise the chip never moved to full sleep,
 313          * when no interface is up.
 314          */
 315         ath9k_stop_btcoex(sc);
 316         ath9k_hw_disable(sc->sc_ah);
 317         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 318
 319         return 0;
 320 }
 321
 322 static int ath_pci_resume(struct device *device)
 323 {
 324         struct pci_dev *pdev = to_pci_dev(device);
 325         u32 val;
 326
 327         /*
 328          * Suspend/Resume resets the PCI configuration space, so we have to
 329          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 330          * PCI Tx retries from interfering with C3 CPU state
 331          */
 332         pci_read_config_dword(pdev, 0x40, &val);
 333         if ((val & 0x0000ff00) != 0)
 334                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 335
 336         return 0;
 337 }
 338
 339 static const struct dev_pm_ops ath9k_pm_ops = {
 340         .suspend = ath_pci_suspend,
 341         .resume = ath_pci_resume,
 342         .freeze = ath_pci_suspend,
 343         .thaw = ath_pci_resume,
 344         .poweroff = ath_pci_suspend,
 345         .restore = ath_pci_resume,
 346 };
 347
 348 #define ATH9K_PM_OPS    (&ath9k_pm_ops)
 349
 350 #else /* !CONFIG_PM */
 351
 352 #define ATH9K_PM_OPS    NULL
 353
 354 #endif /* !CONFIG_PM */
 355
 356
 357 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 358
 359 static struct pci_driver ath_pci_driver = {
 360         .name       = "ath9k",
 361         .id_table   = ath_pci_id_table,
 362         .probe      = ath_pci_probe,
 363         .remove     = ath_pci_remove,
 364         .driver.pm  = ATH9K_PM_OPS,
 365 };
 366
 367 int ath_pci_init(void)
 368 {
 369         return pci_register_driver(&ath_pci_driver);
 370 }
 371
 372 void ath_pci_exit(void)
 373 {
 374         pci_unregister_driver(&ath_pci_driver);
 375 }