2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 ath9k_hw_write_regs(struct ath_hw
*ah
, u32 modesIndex
, u32 freqIndex
,
23 REG_WRITE_ARRAY(&ah
->iniBB_RfGain
, freqIndex
, regWrites
);
27 ath9k_hw_set_channel(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
29 struct ath_common
*common
= ath9k_hw_common(ah
);
35 struct chan_centers centers
;
37 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
38 freq
= centers
.synth_center
;
43 if (((freq
- 2192) % 5) == 0) {
44 channelSel
= ((freq
- 672) * 2 - 3040) / 10;
46 } else if (((freq
- 2224) % 5) == 0) {
47 channelSel
= ((freq
- 704) * 2 - 3040) / 10;
50 ath_print(common
, ATH_DBG_FATAL
,
51 "Invalid channel %u MHz\n", freq
);
55 channelSel
= (channelSel
<< 2) & 0xff;
56 channelSel
= ath9k_hw_reverse_bits(channelSel
, 8);
58 txctl
= REG_READ(ah
, AR_PHY_CCK_TX_CTRL
);
61 REG_WRITE(ah
, AR_PHY_CCK_TX_CTRL
,
62 txctl
| AR_PHY_CCK_TX_CTRL_JAPAN
);
64 REG_WRITE(ah
, AR_PHY_CCK_TX_CTRL
,
65 txctl
& ~AR_PHY_CCK_TX_CTRL_JAPAN
);
68 } else if ((freq
% 20) == 0 && freq
>= 5120) {
70 ath9k_hw_reverse_bits(((freq
- 4800) / 20 << 2), 8);
71 aModeRefSel
= ath9k_hw_reverse_bits(1, 2);
72 } else if ((freq
% 10) == 0) {
74 ath9k_hw_reverse_bits(((freq
- 4800) / 10 << 1), 8);
75 if (AR_SREV_9100(ah
) || AR_SREV_9160_10_OR_LATER(ah
))
76 aModeRefSel
= ath9k_hw_reverse_bits(2, 2);
78 aModeRefSel
= ath9k_hw_reverse_bits(1, 2);
79 } else if ((freq
% 5) == 0) {
80 channelSel
= ath9k_hw_reverse_bits((freq
- 4800) / 5, 8);
81 aModeRefSel
= ath9k_hw_reverse_bits(1, 2);
83 ath_print(common
, ATH_DBG_FATAL
,
84 "Invalid channel %u MHz\n", freq
);
89 (channelSel
<< 8) | (aModeRefSel
<< 2) | (bModeSynth
<< 1) |
92 REG_WRITE(ah
, AR_PHY(0x37), reg32
);
95 ah
->curchan_rad_index
= -1;
100 void ath9k_hw_ar9280_set_channel(struct ath_hw
*ah
,
101 struct ath9k_channel
*chan
)
103 u16 bMode
, fracMode
, aModeRefSel
= 0;
104 u32 freq
, ndiv
, channelSel
= 0, channelFrac
= 0, reg32
= 0;
105 struct chan_centers centers
;
108 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
109 freq
= centers
.synth_center
;
111 reg32
= REG_READ(ah
, AR_PHY_SYNTH_CONTROL
);
121 channelSel
= (freq
* 0x10000) / 15;
123 if (AR_SREV_9287_11_OR_LATER(ah
)) {
125 REG_WRITE_ARRAY(&ah
->iniCckfirJapan2484
,
128 REG_WRITE_ARRAY(&ah
->iniCckfirNormal
,
132 txctl
= REG_READ(ah
, AR_PHY_CCK_TX_CTRL
);
134 /* Enable channel spreading for channel 14 */
135 REG_WRITE(ah
, AR_PHY_CCK_TX_CTRL
,
136 txctl
| AR_PHY_CCK_TX_CTRL_JAPAN
);
138 REG_WRITE(ah
, AR_PHY_CCK_TX_CTRL
,
139 txctl
&~ AR_PHY_CCK_TX_CTRL_JAPAN
);
146 switch(ah
->eep_ops
->get_eeprom(ah
, EEP_FRAC_N_5G
)) {
148 if ((freq
% 20) == 0) {
150 } else if ((freq
% 10) == 0) {
160 channelSel
= (freq
* 0x8000) / 15;
162 REG_RMW_FIELD(ah
, AR_AN_SYNTH9
,
163 AR_AN_SYNTH9_REFDIVA
, refDivA
);
168 ndiv
= (freq
* (refDivA
>> aModeRefSel
)) / 60;
169 channelSel
= ndiv
& 0x1ff;
170 channelFrac
= (ndiv
& 0xfffffe00) * 2;
171 channelSel
= (channelSel
<< 17) | channelFrac
;
177 (fracMode
<< 28) | (aModeRefSel
<< 26) | (channelSel
);
179 REG_WRITE(ah
, AR_PHY_SYNTH_CONTROL
, reg32
);
182 ah
->curchan_rad_index
= -1;
186 ath9k_phy_modify_rx_buffer(u32
*rfBuf
, u32 reg32
,
187 u32 numBits
, u32 firstBit
,
190 u32 tmp32
, mask
, arrayEntry
, lastBit
;
191 int32_t bitPosition
, bitsLeft
;
193 tmp32
= ath9k_hw_reverse_bits(reg32
, numBits
);
194 arrayEntry
= (firstBit
- 1) / 8;
195 bitPosition
= (firstBit
- 1) % 8;
197 while (bitsLeft
> 0) {
198 lastBit
= (bitPosition
+ bitsLeft
> 8) ?
199 8 : bitPosition
+ bitsLeft
;
200 mask
= (((1 << lastBit
) - 1) ^ ((1 << bitPosition
) - 1)) <<
202 rfBuf
[arrayEntry
] &= ~mask
;
203 rfBuf
[arrayEntry
] |= ((tmp32
<< bitPosition
) <<
204 (column
* 8)) & mask
;
205 bitsLeft
-= 8 - bitPosition
;
206 tmp32
= tmp32
>> (8 - bitPosition
);
213 ath9k_hw_set_rf_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
217 u32 ob5GHz
= 0, db5GHz
= 0;
218 u32 ob2GHz
= 0, db2GHz
= 0;
221 if (AR_SREV_9280_10_OR_LATER(ah
))
224 eepMinorRev
= ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
);
226 RF_BANK_SETUP(ah
->analogBank0Data
, &ah
->iniBank0
, 1);
228 RF_BANK_SETUP(ah
->analogBank1Data
, &ah
->iniBank1
, 1);
230 RF_BANK_SETUP(ah
->analogBank2Data
, &ah
->iniBank2
, 1);
232 RF_BANK_SETUP(ah
->analogBank3Data
, &ah
->iniBank3
,
236 for (i
= 0; i
< ah
->iniBank6TPC
.ia_rows
; i
++) {
237 ah
->analogBank6Data
[i
] =
238 INI_RA(&ah
->iniBank6TPC
, i
, modesIndex
);
242 if (eepMinorRev
>= 2) {
243 if (IS_CHAN_2GHZ(chan
)) {
244 ob2GHz
= ah
->eep_ops
->get_eeprom(ah
, EEP_OB_2
);
245 db2GHz
= ah
->eep_ops
->get_eeprom(ah
, EEP_DB_2
);
246 ath9k_phy_modify_rx_buffer(ah
->analogBank6Data
,
248 ath9k_phy_modify_rx_buffer(ah
->analogBank6Data
,
251 ob5GHz
= ah
->eep_ops
->get_eeprom(ah
, EEP_OB_5
);
252 db5GHz
= ah
->eep_ops
->get_eeprom(ah
, EEP_DB_5
);
253 ath9k_phy_modify_rx_buffer(ah
->analogBank6Data
,
255 ath9k_phy_modify_rx_buffer(ah
->analogBank6Data
,
260 RF_BANK_SETUP(ah
->analogBank7Data
, &ah
->iniBank7
, 1);
262 REG_WRITE_RF_ARRAY(&ah
->iniBank0
, ah
->analogBank0Data
,
264 REG_WRITE_RF_ARRAY(&ah
->iniBank1
, ah
->analogBank1Data
,
266 REG_WRITE_RF_ARRAY(&ah
->iniBank2
, ah
->analogBank2Data
,
268 REG_WRITE_RF_ARRAY(&ah
->iniBank3
, ah
->analogBank3Data
,
270 REG_WRITE_RF_ARRAY(&ah
->iniBank6TPC
, ah
->analogBank6Data
,
272 REG_WRITE_RF_ARRAY(&ah
->iniBank7
, ah
->analogBank7Data
,
279 ath9k_hw_rf_free(struct ath_hw
*ah
)
281 #define ATH_FREE_BANK(bank) do { \
286 ATH_FREE_BANK(ah
->analogBank0Data
);
287 ATH_FREE_BANK(ah
->analogBank1Data
);
288 ATH_FREE_BANK(ah
->analogBank2Data
);
289 ATH_FREE_BANK(ah
->analogBank3Data
);
290 ATH_FREE_BANK(ah
->analogBank6Data
);
291 ATH_FREE_BANK(ah
->analogBank6TPCData
);
292 ATH_FREE_BANK(ah
->analogBank7Data
);
293 ATH_FREE_BANK(ah
->addac5416_21
);
294 ATH_FREE_BANK(ah
->bank6Temp
);
298 bool ath9k_hw_init_rf(struct ath_hw
*ah
, int *status
)
300 struct ath_common
*common
= ath9k_hw_common(ah
);
302 if (!AR_SREV_9280_10_OR_LATER(ah
)) {
303 ah
->analogBank0Data
=
304 kzalloc((sizeof(u32
) *
305 ah
->iniBank0
.ia_rows
), GFP_KERNEL
);
306 ah
->analogBank1Data
=
307 kzalloc((sizeof(u32
) *
308 ah
->iniBank1
.ia_rows
), GFP_KERNEL
);
309 ah
->analogBank2Data
=
310 kzalloc((sizeof(u32
) *
311 ah
->iniBank2
.ia_rows
), GFP_KERNEL
);
312 ah
->analogBank3Data
=
313 kzalloc((sizeof(u32
) *
314 ah
->iniBank3
.ia_rows
), GFP_KERNEL
);
315 ah
->analogBank6Data
=
316 kzalloc((sizeof(u32
) *
317 ah
->iniBank6
.ia_rows
), GFP_KERNEL
);
318 ah
->analogBank6TPCData
=
319 kzalloc((sizeof(u32
) *
320 ah
->iniBank6TPC
.ia_rows
), GFP_KERNEL
);
321 ah
->analogBank7Data
=
322 kzalloc((sizeof(u32
) *
323 ah
->iniBank7
.ia_rows
), GFP_KERNEL
);
325 if (ah
->analogBank0Data
== NULL
326 || ah
->analogBank1Data
== NULL
327 || ah
->analogBank2Data
== NULL
328 || ah
->analogBank3Data
== NULL
329 || ah
->analogBank6Data
== NULL
330 || ah
->analogBank6TPCData
== NULL
331 || ah
->analogBank7Data
== NULL
) {
332 ath_print(common
, ATH_DBG_FATAL
,
333 "Cannot allocate RF banks\n");
339 kzalloc((sizeof(u32
) *
340 ah
->iniAddac
.ia_rows
*
341 ah
->iniAddac
.ia_columns
), GFP_KERNEL
);
342 if (ah
->addac5416_21
== NULL
) {
343 ath_print(common
, ATH_DBG_FATAL
,
344 "Cannot allocate addac5416_21\n");
350 kzalloc((sizeof(u32
) *
351 ah
->iniBank6
.ia_rows
), GFP_KERNEL
);
352 if (ah
->bank6Temp
== NULL
) {
353 ath_print(common
, ATH_DBG_FATAL
,
354 "Cannot allocate bank6Temp\n");
364 ath9k_hw_decrease_chain_power(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
366 int i
, regWrites
= 0;
368 u32
*bank6Temp
= ah
->bank6Temp
;
370 switch (ah
->config
.diversity_control
) {
371 case ATH9K_ANT_FIXED_A
:
373 (ah
->config
.antenna_switch_swap
& ANTSWAP_AB
) ?
374 REDUCE_CHAIN_0
: REDUCE_CHAIN_1
;
376 case ATH9K_ANT_FIXED_B
:
378 (ah
->config
.antenna_switch_swap
& ANTSWAP_AB
) ?
379 REDUCE_CHAIN_1
: REDUCE_CHAIN_0
;
381 case ATH9K_ANT_VARIABLE
:
389 for (i
= 0; i
< ah
->iniBank6
.ia_rows
; i
++)
390 bank6Temp
[i
] = ah
->analogBank6Data
[i
];
392 REG_WRITE(ah
, AR_PHY_BASE
+ 0xD8, bank6SelMask
);
394 ath9k_phy_modify_rx_buffer(bank6Temp
, 1, 1, 189, 0);
395 ath9k_phy_modify_rx_buffer(bank6Temp
, 1, 1, 190, 0);
396 ath9k_phy_modify_rx_buffer(bank6Temp
, 1, 1, 191, 0);
397 ath9k_phy_modify_rx_buffer(bank6Temp
, 1, 1, 192, 0);
398 ath9k_phy_modify_rx_buffer(bank6Temp
, 1, 1, 193, 0);
399 ath9k_phy_modify_rx_buffer(bank6Temp
, 1, 1, 222, 0);
400 ath9k_phy_modify_rx_buffer(bank6Temp
, 1, 1, 245, 0);
401 ath9k_phy_modify_rx_buffer(bank6Temp
, 1, 1, 246, 0);
402 ath9k_phy_modify_rx_buffer(bank6Temp
, 1, 1, 247, 0);
404 REG_WRITE_RF_ARRAY(&ah
->iniBank6
, bank6Temp
, regWrites
);
406 REG_WRITE(ah
, AR_PHY_BASE
+ 0xD8, 0x00000053);
408 REG_WRITE(ah
, PHY_SWITCH_CHAIN_0
,
409 (REG_READ(ah
, PHY_SWITCH_CHAIN_0
) & ~0x38)
410 | ((REG_READ(ah
, PHY_SWITCH_CHAIN_0
) >> 3) & 0x38));
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