drivers/net/wireless/ath/ath9k/phy.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 /**
  18  * DOC: Programming Atheros 802.11n analog front end radios
  19  *
  20  * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
  21  * devices have either an external AR2133 analog front end radio for single
  22  * band 2.4 GHz communication or an AR5133 analog front end radio for dual
  23  * band 2.4 GHz / 5 GHz communication.
  24  *
  25  * All devices after the AR5416 and AR5418 family starting with the AR9280
  26  * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
  27  * into a single-chip and require less programming.
  28  *
  29  * The following single-chips exist with a respective embedded radio:
  30  *
  31  * AR9280 - 11n dual-band 2x2 MIMO for PCIe
  32  * AR9281 - 11n single-band 1x2 MIMO for PCIe
  33  * AR9285 - 11n single-band 1x1 for PCIe
  34  * AR9287 - 11n single-band 2x2 MIMO for PCIe
  35  *
  36  * AR9220 - 11n dual-band 2x2 MIMO for PCI
  37  * AR9223 - 11n single-band 2x2 MIMO for PCI
  38  *
  39  * AR9287 - 11n single-band 1x1 MIMO for USB
  40  */
  41
  42 #include "hw.h"
  43
  44 /**
  45  * ath9k_hw_write_regs - ??
  46  *
  47  * @ah: atheros hardware structure
  48  * @modesIndex:
  49  * @freqIndex:
  50  * @regWrites:
  51  *
  52  * Used for both the chipsets with an external AR2133/AR5133 radios and
  53  * single-chip devices.
  54  */
  55 void
  56 ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
  57                     int regWrites)
  58 {
  59         REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
  60 }
  61
  62 /**
  63  * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
  64  * @ah: atheros hardware stucture
  65  * @chan:
  66  *
  67  * For the external AR2133/AR5133 radios, takes the MHz channel value and set
  68  * the channel value. Assumes writes enabled to analog bus and bank6 register
  69  * cache in ah->analogBank6Data.
  70  */
  71 bool
  72 ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  73 {
  74         struct ath_common *common = ath9k_hw_common(ah);
  75         u32 channelSel = 0;
  76         u32 bModeSynth = 0;
  77         u32 aModeRefSel = 0;
  78         u32 reg32 = 0;
  79         u16 freq;
  80         struct chan_centers centers;
  81
  82         ath9k_hw_get_channel_centers(ah, chan, &centers);
  83         freq = centers.synth_center;
  84
  85         if (freq < 4800) {
  86                 u32 txctl;
  87
  88                 if (((freq - 2192) % 5) == 0) {
  89                         channelSel = ((freq - 672) * 2 - 3040) / 10;
  90                         bModeSynth = 0;
  91                 } else if (((freq - 2224) % 5) == 0) {
  92                         channelSel = ((freq - 704) * 2 - 3040) / 10;
  93                         bModeSynth = 1;
  94                 } else {
  95                         ath_print(common, ATH_DBG_FATAL,
  96                                   "Invalid channel %u MHz\n", freq);
  97                         return false;
  98                 }
  99
 100                 channelSel = (channelSel << 2) & 0xff;
 101                 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
 102
 103                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
 104                 if (freq == 2484) {
 105
 106                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 107                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
 108                 } else {
 109                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 110                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
 111                 }
 112
 113         } else if ((freq % 20) == 0 && freq >= 5120) {
 114                 channelSel =
 115                     ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
 116                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 117         } else if ((freq % 10) == 0) {
 118                 channelSel =
 119                     ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
 120                 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
 121                         aModeRefSel = ath9k_hw_reverse_bits(2, 2);
 122                 else
 123                         aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 124         } else if ((freq % 5) == 0) {
 125                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
 126                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 127         } else {
 128                 ath_print(common, ATH_DBG_FATAL,
 129                           "Invalid channel %u MHz\n", freq);
 130                 return false;
 131         }
 132
 133         reg32 =
 134             (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
 135             (1 << 5) | 0x1;
 136
 137         REG_WRITE(ah, AR_PHY(0x37), reg32);
 138
 139         ah->curchan = chan;
 140         ah->curchan_rad_index = -1;
 141
 142         return true;
 143 }
 144
 145 /**
 146  * ath9k_hw_ar9280_set_channel - set channel on single-chip device
 147  * @ah: atheros hardware structure
 148  * @chan:
 149  *
 150  * This is the function to change channel on single-chip devices, that is
 151  * all devices after ar9280.
 152  *
 153  * This function takes the channel value in MHz and sets
 154  * hardware channel value. Assumes writes have been enabled to analog bus.
 155  *
 156  * Actual Expression,
 157  *
 158  * For 2GHz channel,
 159  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
 160  * (freq_ref = 40MHz)
 161  *
 162  * For 5GHz channel,
 163  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
 164  * (freq_ref = 40MHz/(24>>amodeRefSel))
 165  */
 166 void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
 167                                  struct ath9k_channel *chan)
 168 {
 169         u16 bMode, fracMode, aModeRefSel = 0;
 170         u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
 171         struct chan_centers centers;
 172         u32 refDivA = 24;
 173
 174         ath9k_hw_get_channel_centers(ah, chan, &centers);
 175         freq = centers.synth_center;
 176
 177         reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
 178         reg32 &= 0xc0000000;
 179
 180         if (freq < 4800) { /* 2 GHz, fractional mode */
 181                 u32 txctl;
 182                 int regWrites = 0;
 183
 184                 bMode = 1;
 185                 fracMode = 1;
 186                 aModeRefSel = 0;
 187                 channelSel = (freq * 0x10000) / 15;
 188
 189                 if (AR_SREV_9287_11_OR_LATER(ah)) {
 190                         if (freq == 2484) {
 191                                 /* Enable channel spreading for channel 14 */
 192                                 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
 193                                                 1, regWrites);
 194                         } else {
 195                                 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
 196                                                 1, regWrites);
 197                         }
 198                 } else {
 199                         txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
 200                         if (freq == 2484) {
 201                                 /* Enable channel spreading for channel 14 */
 202                                 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 203                                           txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
 204                         } else {
 205                                 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 206                                           txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
 207                         }
 208                 }
 209         } else {
 210                 bMode = 0;
 211                 fracMode = 0;
 212
 213                 switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
 214                 case 0:
 215                         if ((freq % 20) == 0) {
 216                                 aModeRefSel = 3;
 217                         } else if ((freq % 10) == 0) {
 218                                 aModeRefSel = 2;
 219                         }
 220                         if (aModeRefSel)
 221                                 break;
 222                 case 1:
 223                 default:
 224                         aModeRefSel = 0;
 225                         /*
 226                          * Enable 2G (fractional) mode for channels
 227                          * which are 5MHz spaced.
 228                          */
 229                         fracMode = 1;
 230                         refDivA = 1;
 231                         channelSel = (freq * 0x8000) / 15;
 232
 233                         /* RefDivA setting */
 234                         REG_RMW_FIELD(ah, AR_AN_SYNTH9,
 235                                       AR_AN_SYNTH9_REFDIVA, refDivA);
 236
 237                 }
 238
 239                 if (!fracMode) {
 240                         ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
 241                         channelSel = ndiv & 0x1ff;
 242                         channelFrac = (ndiv & 0xfffffe00) * 2;
 243                         channelSel = (channelSel << 17) | channelFrac;
 244                 }
 245         }
 246
 247         reg32 = reg32 |
 248             (bMode << 29) |
 249             (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
 250
 251         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 252
 253         ah->curchan = chan;
 254         ah->curchan_rad_index = -1;
 255 }
 256
 257 /**
 258  * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
 259  * @rfbuf:
 260  * @reg32:
 261  * @numBits:
 262  * @firstBit:
 263  * @column:
 264  *
 265  * Performs analog "swizzling" of parameters into their location.
 266  * Used on external AR2133/AR5133 radios.
 267  */
 268 static void
 269 ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
 270                            u32 numBits, u32 firstBit,
 271                            u32 column)
 272 {
 273         u32 tmp32, mask, arrayEntry, lastBit;
 274         int32_t bitPosition, bitsLeft;
 275
 276         tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
 277         arrayEntry = (firstBit - 1) / 8;
 278         bitPosition = (firstBit - 1) % 8;
 279         bitsLeft = numBits;
 280         while (bitsLeft > 0) {
 281                 lastBit = (bitPosition + bitsLeft > 8) ?
 282                     8 : bitPosition + bitsLeft;
 283                 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
 284                     (column * 8);
 285                 rfBuf[arrayEntry] &= ~mask;
 286                 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
 287                                       (column * 8)) & mask;
 288                 bitsLeft -= 8 - bitPosition;
 289                 tmp32 = tmp32 >> (8 - bitPosition);
 290                 bitPosition = 0;
 291                 arrayEntry++;
 292         }
 293 }
 294
 295 /* *
 296  * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
 297  * @ah: atheros hardware structure
 298  * @chan:
 299  * @modesIndex:
 300  *
 301  * Used for the external AR2133/AR5133 radios.
 302  *
 303  * Reads the EEPROM header info from the device structure and programs
 304  * all rf registers. This routine requires access to the analog
 305  * rf device. This is not required for single-chip devices.
 306  */
 307 bool
 308 ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
 309                      u16 modesIndex)
 310 {
 311         u32 eepMinorRev;
 312         u32 ob5GHz = 0, db5GHz = 0;
 313         u32 ob2GHz = 0, db2GHz = 0;
 314         int regWrites = 0;
 315
 316         /*
 317          * Software does not need to program bank data
 318          * for single chip devices, that is AR9280 or anything
 319          * after that.
 320          */
 321         if (AR_SREV_9280_10_OR_LATER(ah))
 322                 return true;
 323
 324         /* Setup rf parameters */
 325         eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
 326
 327         /* Setup Bank 0 Write */
 328         RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
 329
 330         /* Setup Bank 1 Write */
 331         RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
 332
 333         /* Setup Bank 2 Write */
 334         RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
 335
 336         /* Setup Bank 6 Write */
 337         RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
 338                       modesIndex);
 339         {
 340                 int i;
 341                 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
 342                         ah->analogBank6Data[i] =
 343                             INI_RA(&ah->iniBank6TPC, i, modesIndex);
 344                 }
 345         }
 346
 347         /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
 348         if (eepMinorRev >= 2) {
 349                 if (IS_CHAN_2GHZ(chan)) {
 350                         ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
 351                         db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
 352                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 353                                                    ob2GHz, 3, 197, 0);
 354                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 355                                                    db2GHz, 3, 194, 0);
 356                 } else {
 357                         ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
 358                         db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
 359                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 360                                                    ob5GHz, 3, 203, 0);
 361                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 362                                                    db5GHz, 3, 200, 0);
 363                 }
 364         }
 365
 366         /* Setup Bank 7 Setup */
 367         RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
 368
 369         /* Write Analog registers */
 370         REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
 371                            regWrites);
 372         REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
 373                            regWrites);
 374         REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
 375                            regWrites);
 376         REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
 377                            regWrites);
 378         REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
 379                            regWrites);
 380         REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
 381                            regWrites);
 382
 383         return true;
 384 }
 385
 386 /**
 387  * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
 388  * @ah: atheros hardware struture
 389  * For the external AR2133/AR5133 radios banks.
 390  */
 391 void
 392 ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
 393 {
 394 #define ATH_FREE_BANK(bank) do { \
 395                 kfree(bank); \
 396                 bank = NULL; \
 397         } while (0);
 398
 399         BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
 400
 401         ATH_FREE_BANK(ah->analogBank0Data);
 402         ATH_FREE_BANK(ah->analogBank1Data);
 403         ATH_FREE_BANK(ah->analogBank2Data);
 404         ATH_FREE_BANK(ah->analogBank3Data);
 405         ATH_FREE_BANK(ah->analogBank6Data);
 406         ATH_FREE_BANK(ah->analogBank6TPCData);
 407         ATH_FREE_BANK(ah->analogBank7Data);
 408         ATH_FREE_BANK(ah->addac5416_21);
 409         ATH_FREE_BANK(ah->bank6Temp);
 410
 411 #undef ATH_FREE_BANK
 412 }
 413
 414 /**
 415  * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
 416  * @ah: atheros hardware structure
 417  *
 418  * Only required for older devices with external AR2133/AR5133 radios.
 419  */
 420 int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
 421 {
 422 #define ATH_ALLOC_BANK(bank, size) do { \
 423                 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
 424                 if (!bank) { \
 425                         ath_print(common, ATH_DBG_FATAL, \
 426                                   "Cannot allocate RF banks\n"); \
 427                         return -ENOMEM; \
 428                 } \
 429         } while (0);
 430
 431         struct ath_common *common = ath9k_hw_common(ah);
 432
 433         BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
 434
 435         ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
 436         ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
 437         ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
 438         ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
 439         ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
 440         ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
 441         ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
 442         ATH_ALLOC_BANK(ah->addac5416_21,
 443                        ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
 444         ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
 445
 446         return 0;
 447 #undef ATH_ALLOC_BANK
 448 }
 449
 450 /**
 451  * ath9k_hw_decrease_chain_power()
 452  *
 453  * @ah: atheros hardware structure
 454  * @chan:
 455  *
 456  * Only used on the AR5416 and AR5418 with the external AR2133/AR5133 radios.
 457  *
 458  * Sets a chain internal RF path to the lowest output power. Any
 459  * further writes to bank6 after this setting will override these
 460  * changes. Thus this function must be the last function in the
 461  * sequence to modify bank 6.
 462  *
 463  * This function must be called after ar5416SetRfRegs() which is
 464  * called from ath9k_hw_process_ini() due to swizzling of bank 6.
 465  * Depends on ah->analogBank6Data being initialized by
 466  * ath9k_hw_set_rf_regs()
 467  *
 468  * Additional additive reduction in power -
 469  * change chain's switch table so chain's tx state is actually the rx
 470  * state value. May produce different results in 2GHz/5GHz as well as
 471  * board to board but in general should be a reduction.
 472  *
 473  * Activated by #ifdef ALTER_SWITCH.  Not tried yet.  If so, must be
 474  * called after ah->eep_ops->set_board_values() due to RMW of
 475  * PHY_SWITCH_CHAIN_0.
 476  */
 477 void
 478 ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
 479 {
 480         int i, regWrites = 0;
 481         u32 bank6SelMask;
 482         u32 *bank6Temp = ah->bank6Temp;
 483
 484         switch (ah->config.diversity_control) {
 485         case ATH9K_ANT_FIXED_A:
 486                 bank6SelMask =
 487                     (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
 488                         REDUCE_CHAIN_0 : /* swapped, reduce chain 0 */
 489                         REDUCE_CHAIN_1; /* normal, select chain 1/2 to reduce */
 490                 break;
 491         case ATH9K_ANT_FIXED_B:
 492                 bank6SelMask =
 493                     (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
 494                         REDUCE_CHAIN_1 : /* swapped, reduce chain 1/2 */
 495                         REDUCE_CHAIN_0; /* normal, select chain 0 to reduce */
 496                 break;
 497         case ATH9K_ANT_VARIABLE:
 498                 return; /* do not change anything */
 499                 break;
 500         default:
 501                 return; /* do not change anything */
 502                 break;
 503         }
 504
 505         for (i = 0; i < ah->iniBank6.ia_rows; i++)
 506                 bank6Temp[i] = ah->analogBank6Data[i];
 507
 508         /* Write Bank 5 to switch Bank 6 write to selected chain only */
 509         REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
 510
 511         /*
 512          * Modify Bank6 selected chain to use lowest amplification.
 513          * Modifies the parameters to a value of 1.
 514          * Depends on existing bank 6 values to be cached in
 515          * ah->analogBank6Data
 516          */
 517         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
 518         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
 519         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
 520         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
 521         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
 522         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
 523         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
 524         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
 525         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
 526
 527         REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
 528
 529         REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
 530 #ifdef ALTER_SWITCH
 531         REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
 532                   (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
 533                   | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
 534 #endif
 535 }