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ath9k: Enable TSF Out of Range Interrupt
[deliverable/linux.git] / drivers / net / wireless / ath9k / hw.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val)
88 {
89 int i;
90
91 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
92 if ((REG_READ(ah, reg) & mask) == val)
93 return true;
94
95 udelay(AH_TIME_QUANTUM);
96 }
97
98 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
99 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
100 reg, REG_READ(ah, reg), mask, val);
101
102 return false;
103 }
104
105 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
106 {
107 u32 retval;
108 int i;
109
110 for (i = 0, retval = 0; i < n; i++) {
111 retval = (retval << 1) | (val & 1);
112 val >>= 1;
113 }
114 return retval;
115 }
116
117 bool ath9k_get_channel_edges(struct ath_hw *ah,
118 u16 flags, u16 *low,
119 u16 *high)
120 {
121 struct ath9k_hw_capabilities *pCap = &ah->caps;
122
123 if (flags & CHANNEL_5GHZ) {
124 *low = pCap->low_5ghz_chan;
125 *high = pCap->high_5ghz_chan;
126 return true;
127 }
128 if ((flags & CHANNEL_2GHZ)) {
129 *low = pCap->low_2ghz_chan;
130 *high = pCap->high_2ghz_chan;
131 return true;
132 }
133 return false;
134 }
135
136 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
137 struct ath_rate_table *rates,
138 u32 frameLen, u16 rateix,
139 bool shortPreamble)
140 {
141 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
142 u32 kbps;
143
144 kbps = rates->info[rateix].ratekbps;
145
146 if (kbps == 0)
147 return 0;
148
149 switch (rates->info[rateix].phy) {
150 case WLAN_RC_PHY_CCK:
151 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
152 if (shortPreamble && rates->info[rateix].short_preamble)
153 phyTime >>= 1;
154 numBits = frameLen << 3;
155 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
156 break;
157 case WLAN_RC_PHY_OFDM:
158 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
159 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
160 numBits = OFDM_PLCP_BITS + (frameLen << 3);
161 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
162 txTime = OFDM_SIFS_TIME_QUARTER
163 + OFDM_PREAMBLE_TIME_QUARTER
164 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
165 } else if (ah->curchan &&
166 IS_CHAN_HALF_RATE(ah->curchan)) {
167 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
168 numBits = OFDM_PLCP_BITS + (frameLen << 3);
169 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
170 txTime = OFDM_SIFS_TIME_HALF +
171 OFDM_PREAMBLE_TIME_HALF
172 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
173 } else {
174 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
175 numBits = OFDM_PLCP_BITS + (frameLen << 3);
176 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
177 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
178 + (numSymbols * OFDM_SYMBOL_TIME);
179 }
180 break;
181 default:
182 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
183 "Unknown phy %u (rate ix %u)\n",
184 rates->info[rateix].phy, rateix);
185 txTime = 0;
186 break;
187 }
188
189 return txTime;
190 }
191
192 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
193 struct ath9k_channel *chan,
194 struct chan_centers *centers)
195 {
196 int8_t extoff;
197
198 if (!IS_CHAN_HT40(chan)) {
199 centers->ctl_center = centers->ext_center =
200 centers->synth_center = chan->channel;
201 return;
202 }
203
204 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
205 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
206 centers->synth_center =
207 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
208 extoff = 1;
209 } else {
210 centers->synth_center =
211 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
212 extoff = -1;
213 }
214
215 centers->ctl_center =
216 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
217 centers->ext_center =
218 centers->synth_center + (extoff *
219 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
220 HT40_CHANNEL_CENTER_SHIFT : 15));
221 }
222
223 /******************/
224 /* Chip Revisions */
225 /******************/
226
227 static void ath9k_hw_read_revisions(struct ath_hw *ah)
228 {
229 u32 val;
230
231 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
232
233 if (val == 0xFF) {
234 val = REG_READ(ah, AR_SREV);
235 ah->hw_version.macVersion =
236 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
238 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
239 } else {
240 if (!AR_SREV_9100(ah))
241 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
242
243 ah->hw_version.macRev = val & AR_SREV_REVISION;
244
245 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
246 ah->is_pciexpress = true;
247 }
248 }
249
250 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
251 {
252 u32 val;
253 int i;
254
255 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
256
257 for (i = 0; i < 8; i++)
258 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
259 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
260 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
261
262 return ath9k_hw_reverse_bits(val, 8);
263 }
264
265 /************************************/
266 /* HW Attach, Detach, Init Routines */
267 /************************************/
268
269 static void ath9k_hw_disablepcie(struct ath_hw *ah)
270 {
271 if (AR_SREV_9100(ah))
272 return;
273
274 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
275 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
283
284 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
285 }
286
287 static bool ath9k_hw_chip_test(struct ath_hw *ah)
288 {
289 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
290 u32 regHold[2];
291 u32 patternData[4] = { 0x55555555,
292 0xaaaaaaaa,
293 0x66666666,
294 0x99999999 };
295 int i, j;
296
297 for (i = 0; i < 2; i++) {
298 u32 addr = regAddr[i];
299 u32 wrData, rdData;
300
301 regHold[i] = REG_READ(ah, addr);
302 for (j = 0; j < 0x100; j++) {
303 wrData = (j << 16) | j;
304 REG_WRITE(ah, addr, wrData);
305 rdData = REG_READ(ah, addr);
306 if (rdData != wrData) {
307 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
308 "address test failed "
309 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
310 addr, wrData, rdData);
311 return false;
312 }
313 }
314 for (j = 0; j < 4; j++) {
315 wrData = patternData[j];
316 REG_WRITE(ah, addr, wrData);
317 rdData = REG_READ(ah, addr);
318 if (wrData != rdData) {
319 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
320 "address test failed "
321 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
322 addr, wrData, rdData);
323 return false;
324 }
325 }
326 REG_WRITE(ah, regAddr[i], regHold[i]);
327 }
328 udelay(100);
329
330 return true;
331 }
332
333 static const char *ath9k_hw_devname(u16 devid)
334 {
335 switch (devid) {
336 case AR5416_DEVID_PCI:
337 return "Atheros 5416";
338 case AR5416_DEVID_PCIE:
339 return "Atheros 5418";
340 case AR9160_DEVID_PCI:
341 return "Atheros 9160";
342 case AR5416_AR9100_DEVID:
343 return "Atheros 9100";
344 case AR9280_DEVID_PCI:
345 case AR9280_DEVID_PCIE:
346 return "Atheros 9280";
347 case AR9285_DEVID_PCIE:
348 return "Atheros 9285";
349 }
350
351 return NULL;
352 }
353
354 static void ath9k_hw_set_defaults(struct ath_hw *ah)
355 {
356 int i;
357
358 ah->config.dma_beacon_response_time = 2;
359 ah->config.sw_beacon_response_time = 10;
360 ah->config.additional_swba_backoff = 0;
361 ah->config.ack_6mb = 0x0;
362 ah->config.cwm_ignore_extcca = 0;
363 ah->config.pcie_powersave_enable = 0;
364 ah->config.pcie_l1skp_enable = 0;
365 ah->config.pcie_clock_req = 0;
366 ah->config.pcie_power_reset = 0x100;
367 ah->config.pcie_restore = 0;
368 ah->config.pcie_waen = 0;
369 ah->config.analog_shiftreg = 1;
370 ah->config.ht_enable = 1;
371 ah->config.ofdm_trig_low = 200;
372 ah->config.ofdm_trig_high = 500;
373 ah->config.cck_trig_high = 200;
374 ah->config.cck_trig_low = 100;
375 ah->config.enable_ani = 1;
376 ah->config.noise_immunity_level = 4;
377 ah->config.ofdm_weaksignal_det = 1;
378 ah->config.cck_weaksignal_thr = 0;
379 ah->config.spur_immunity_level = 2;
380 ah->config.firstep_level = 0;
381 ah->config.rssi_thr_high = 40;
382 ah->config.rssi_thr_low = 7;
383 ah->config.diversity_control = 0;
384 ah->config.antenna_switch_swap = 0;
385
386 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
387 ah->config.spurchans[i][0] = AR_NO_SPUR;
388 ah->config.spurchans[i][1] = AR_NO_SPUR;
389 }
390
391 ah->config.intr_mitigation = 1;
392 }
393
394 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
395 int *status)
396 {
397 struct ath_hw *ah;
398
399 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
400 if (ah == NULL) {
401 DPRINTF(sc, ATH_DBG_FATAL,
402 "Cannot allocate memory for state block\n");
403 *status = -ENOMEM;
404 return NULL;
405 }
406
407 ah->ah_sc = sc;
408 ah->hw_version.magic = AR5416_MAGIC;
409 ah->regulatory.country_code = CTRY_DEFAULT;
410 ah->hw_version.devid = devid;
411 ah->hw_version.subvendorid = 0;
412
413 ah->ah_flags = 0;
414 if ((devid == AR5416_AR9100_DEVID))
415 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
416 if (!AR_SREV_9100(ah))
417 ah->ah_flags = AH_USE_EEPROM;
418
419 ah->regulatory.power_limit = MAX_RATE_POWER;
420 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
421 ah->atim_window = 0;
422 ah->diversity_control = ah->config.diversity_control;
423 ah->antenna_switch_swap =
424 ah->config.antenna_switch_swap;
425 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
426 ah->beacon_interval = 100;
427 ah->enable_32kHz_clock = DONT_USE_32KHZ;
428 ah->slottime = (u32) -1;
429 ah->acktimeout = (u32) -1;
430 ah->ctstimeout = (u32) -1;
431 ah->globaltxtimeout = (u32) -1;
432
433 ah->gbeacon_rate = 0;
434
435 return ah;
436 }
437
438 static int ath9k_hw_rfattach(struct ath_hw *ah)
439 {
440 bool rfStatus = false;
441 int ecode = 0;
442
443 rfStatus = ath9k_hw_init_rf(ah, &ecode);
444 if (!rfStatus) {
445 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
446 "RF setup failed, status %u\n", ecode);
447 return ecode;
448 }
449
450 return 0;
451 }
452
453 static int ath9k_hw_rf_claim(struct ath_hw *ah)
454 {
455 u32 val;
456
457 REG_WRITE(ah, AR_PHY(0), 0x00000007);
458
459 val = ath9k_hw_get_radiorev(ah);
460 switch (val & AR_RADIO_SREV_MAJOR) {
461 case 0:
462 val = AR_RAD5133_SREV_MAJOR;
463 break;
464 case AR_RAD5133_SREV_MAJOR:
465 case AR_RAD5122_SREV_MAJOR:
466 case AR_RAD2133_SREV_MAJOR:
467 case AR_RAD2122_SREV_MAJOR:
468 break;
469 default:
470 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
471 "5G Radio Chip Rev 0x%02X is not "
472 "supported by this driver\n",
473 ah->hw_version.analog5GhzRev);
474 return -EOPNOTSUPP;
475 }
476
477 ah->hw_version.analog5GhzRev = val;
478
479 return 0;
480 }
481
482 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
483 {
484 u32 sum;
485 int i;
486 u16 eeval;
487
488 sum = 0;
489 for (i = 0; i < 3; i++) {
490 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
491 sum += eeval;
492 ah->macaddr[2 * i] = eeval >> 8;
493 ah->macaddr[2 * i + 1] = eeval & 0xff;
494 }
495 if (sum == 0 || sum == 0xffff * 3) {
496 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
497 "mac address read failed: %pM\n",
498 ah->macaddr);
499 return -EADDRNOTAVAIL;
500 }
501
502 return 0;
503 }
504
505 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
506 {
507 u32 rxgain_type;
508
509 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
510 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
511
512 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
513 INIT_INI_ARRAY(&ah->iniModesRxGain,
514 ar9280Modes_backoff_13db_rxgain_9280_2,
515 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
516 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
517 INIT_INI_ARRAY(&ah->iniModesRxGain,
518 ar9280Modes_backoff_23db_rxgain_9280_2,
519 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
520 else
521 INIT_INI_ARRAY(&ah->iniModesRxGain,
522 ar9280Modes_original_rxgain_9280_2,
523 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
524 } else {
525 INIT_INI_ARRAY(&ah->iniModesRxGain,
526 ar9280Modes_original_rxgain_9280_2,
527 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
528 }
529 }
530
531 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
532 {
533 u32 txgain_type;
534
535 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
536 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
537
538 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
539 INIT_INI_ARRAY(&ah->iniModesTxGain,
540 ar9280Modes_high_power_tx_gain_9280_2,
541 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
542 else
543 INIT_INI_ARRAY(&ah->iniModesTxGain,
544 ar9280Modes_original_tx_gain_9280_2,
545 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
546 } else {
547 INIT_INI_ARRAY(&ah->iniModesTxGain,
548 ar9280Modes_original_tx_gain_9280_2,
549 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
550 }
551 }
552
553 static int ath9k_hw_post_attach(struct ath_hw *ah)
554 {
555 int ecode;
556
557 if (!ath9k_hw_chip_test(ah)) {
558 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
559 "hardware self-test failed\n");
560 return -ENODEV;
561 }
562
563 ecode = ath9k_hw_rf_claim(ah);
564 if (ecode != 0)
565 return ecode;
566
567 ecode = ath9k_hw_eeprom_attach(ah);
568 if (ecode != 0)
569 return ecode;
570 ecode = ath9k_hw_rfattach(ah);
571 if (ecode != 0)
572 return ecode;
573
574 if (!AR_SREV_9100(ah)) {
575 ath9k_hw_ani_setup(ah);
576 ath9k_hw_ani_attach(ah);
577 }
578
579 return 0;
580 }
581
582 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
583 int *status)
584 {
585 struct ath_hw *ah;
586 int ecode;
587 u32 i, j;
588
589 ah = ath9k_hw_newstate(devid, sc, status);
590 if (ah == NULL)
591 return NULL;
592
593 ath9k_hw_set_defaults(ah);
594
595 if (ah->config.intr_mitigation != 0)
596 ah->intr_mitigation = true;
597
598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
599 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
600 ecode = -EIO;
601 goto bad;
602 }
603
604 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
605 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
606 ecode = -EIO;
607 goto bad;
608 }
609
610 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
611 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
612 ah->config.serialize_regmode =
613 SER_REG_MODE_ON;
614 } else {
615 ah->config.serialize_regmode =
616 SER_REG_MODE_OFF;
617 }
618 }
619
620 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
621 ah->config.serialize_regmode);
622
623 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
624 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
625 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
626 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
627 DPRINTF(sc, ATH_DBG_RESET,
628 "Mac Chip Rev 0x%02x.%x is not supported by "
629 "this driver\n", ah->hw_version.macVersion,
630 ah->hw_version.macRev);
631 ecode = -EOPNOTSUPP;
632 goto bad;
633 }
634
635 if (AR_SREV_9100(ah)) {
636 ah->iq_caldata.calData = &iq_cal_multi_sample;
637 ah->supp_cals = IQ_MISMATCH_CAL;
638 ah->is_pciexpress = false;
639 }
640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
641
642 if (AR_SREV_9160_10_OR_LATER(ah)) {
643 if (AR_SREV_9280_10_OR_LATER(ah)) {
644 ah->iq_caldata.calData = &iq_cal_single_sample;
645 ah->adcgain_caldata.calData =
646 &adc_gain_cal_single_sample;
647 ah->adcdc_caldata.calData =
648 &adc_dc_cal_single_sample;
649 ah->adcdc_calinitdata.calData =
650 &adc_init_dc_cal;
651 } else {
652 ah->iq_caldata.calData = &iq_cal_multi_sample;
653 ah->adcgain_caldata.calData =
654 &adc_gain_cal_multi_sample;
655 ah->adcdc_caldata.calData =
656 &adc_dc_cal_multi_sample;
657 ah->adcdc_calinitdata.calData =
658 &adc_init_dc_cal;
659 }
660 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
661 }
662
663 if (AR_SREV_9160(ah)) {
664 ah->config.enable_ani = 1;
665 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
666 ATH9K_ANI_FIRSTEP_LEVEL);
667 } else {
668 ah->ani_function = ATH9K_ANI_ALL;
669 if (AR_SREV_9280_10_OR_LATER(ah)) {
670 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
671 }
672 }
673
674 DPRINTF(sc, ATH_DBG_RESET,
675 "This Mac Chip Rev 0x%02x.%x is \n",
676 ah->hw_version.macVersion, ah->hw_version.macRev);
677
678 if (AR_SREV_9285_12_OR_LATER(ah)) {
679 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
680 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
681 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
682 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
683
684 if (ah->config.pcie_clock_req) {
685 INIT_INI_ARRAY(&ah->iniPcieSerdes,
686 ar9285PciePhy_clkreq_off_L1_9285_1_2,
687 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
688 } else {
689 INIT_INI_ARRAY(&ah->iniPcieSerdes,
690 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
691 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
692 2);
693 }
694 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
695 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
696 ARRAY_SIZE(ar9285Modes_9285), 6);
697 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
698 ARRAY_SIZE(ar9285Common_9285), 2);
699
700 if (ah->config.pcie_clock_req) {
701 INIT_INI_ARRAY(&ah->iniPcieSerdes,
702 ar9285PciePhy_clkreq_off_L1_9285,
703 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
704 } else {
705 INIT_INI_ARRAY(&ah->iniPcieSerdes,
706 ar9285PciePhy_clkreq_always_on_L1_9285,
707 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
708 }
709 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
710 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
711 ARRAY_SIZE(ar9280Modes_9280_2), 6);
712 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
713 ARRAY_SIZE(ar9280Common_9280_2), 2);
714
715 if (ah->config.pcie_clock_req) {
716 INIT_INI_ARRAY(&ah->iniPcieSerdes,
717 ar9280PciePhy_clkreq_off_L1_9280,
718 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
719 } else {
720 INIT_INI_ARRAY(&ah->iniPcieSerdes,
721 ar9280PciePhy_clkreq_always_on_L1_9280,
722 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
723 }
724 INIT_INI_ARRAY(&ah->iniModesAdditional,
725 ar9280Modes_fast_clock_9280_2,
726 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
727 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
728 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
729 ARRAY_SIZE(ar9280Modes_9280), 6);
730 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
731 ARRAY_SIZE(ar9280Common_9280), 2);
732 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
733 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
734 ARRAY_SIZE(ar5416Modes_9160), 6);
735 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
736 ARRAY_SIZE(ar5416Common_9160), 2);
737 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
738 ARRAY_SIZE(ar5416Bank0_9160), 2);
739 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
740 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
741 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
742 ARRAY_SIZE(ar5416Bank1_9160), 2);
743 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
744 ARRAY_SIZE(ar5416Bank2_9160), 2);
745 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
746 ARRAY_SIZE(ar5416Bank3_9160), 3);
747 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
748 ARRAY_SIZE(ar5416Bank6_9160), 3);
749 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
750 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
751 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
752 ARRAY_SIZE(ar5416Bank7_9160), 2);
753 if (AR_SREV_9160_11(ah)) {
754 INIT_INI_ARRAY(&ah->iniAddac,
755 ar5416Addac_91601_1,
756 ARRAY_SIZE(ar5416Addac_91601_1), 2);
757 } else {
758 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
759 ARRAY_SIZE(ar5416Addac_9160), 2);
760 }
761 } else if (AR_SREV_9100_OR_LATER(ah)) {
762 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
763 ARRAY_SIZE(ar5416Modes_9100), 6);
764 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
765 ARRAY_SIZE(ar5416Common_9100), 2);
766 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
767 ARRAY_SIZE(ar5416Bank0_9100), 2);
768 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
769 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
770 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
771 ARRAY_SIZE(ar5416Bank1_9100), 2);
772 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
773 ARRAY_SIZE(ar5416Bank2_9100), 2);
774 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
775 ARRAY_SIZE(ar5416Bank3_9100), 3);
776 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
777 ARRAY_SIZE(ar5416Bank6_9100), 3);
778 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
779 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
780 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
781 ARRAY_SIZE(ar5416Bank7_9100), 2);
782 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
783 ARRAY_SIZE(ar5416Addac_9100), 2);
784 } else {
785 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
786 ARRAY_SIZE(ar5416Modes), 6);
787 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
788 ARRAY_SIZE(ar5416Common), 2);
789 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
790 ARRAY_SIZE(ar5416Bank0), 2);
791 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
792 ARRAY_SIZE(ar5416BB_RfGain), 3);
793 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
794 ARRAY_SIZE(ar5416Bank1), 2);
795 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
796 ARRAY_SIZE(ar5416Bank2), 2);
797 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
798 ARRAY_SIZE(ar5416Bank3), 3);
799 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
800 ARRAY_SIZE(ar5416Bank6), 3);
801 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
802 ARRAY_SIZE(ar5416Bank6TPC), 3);
803 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
804 ARRAY_SIZE(ar5416Bank7), 2);
805 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
806 ARRAY_SIZE(ar5416Addac), 2);
807 }
808
809 if (ah->is_pciexpress)
810 ath9k_hw_configpcipowersave(ah, 0);
811 else
812 ath9k_hw_disablepcie(ah);
813
814 ecode = ath9k_hw_post_attach(ah);
815 if (ecode != 0)
816 goto bad;
817
818 /* rxgain table */
819 if (AR_SREV_9280_20(ah))
820 ath9k_hw_init_rxgain_ini(ah);
821
822 /* txgain table */
823 if (AR_SREV_9280_20(ah))
824 ath9k_hw_init_txgain_ini(ah);
825
826 if (!ath9k_hw_fill_cap_info(ah)) {
827 DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
828 ecode = -EINVAL;
829 goto bad;
830 }
831
832 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
833 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
834
835 /* EEPROM Fixup */
836 for (i = 0; i < ah->iniModes.ia_rows; i++) {
837 u32 reg = INI_RA(&ah->iniModes, i, 0);
838
839 for (j = 1; j < ah->iniModes.ia_columns; j++) {
840 u32 val = INI_RA(&ah->iniModes, i, j);
841
842 INI_RA(&ah->iniModes, i, j) =
843 ath9k_hw_ini_fixup(ah,
844 &ah->eeprom.def,
845 reg, val);
846 }
847 }
848 }
849
850 ecode = ath9k_hw_init_macaddr(ah);
851 if (ecode != 0) {
852 DPRINTF(sc, ATH_DBG_RESET,
853 "failed initializing mac address\n");
854 goto bad;
855 }
856
857 if (AR_SREV_9285(ah))
858 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
859 else
860 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
861
862 ath9k_init_nfcal_hist_buffer(ah);
863
864 return ah;
865 bad:
866 if (ah)
867 ath9k_hw_detach(ah);
868 if (status)
869 *status = ecode;
870
871 return NULL;
872 }
873
874 static void ath9k_hw_init_bb(struct ath_hw *ah,
875 struct ath9k_channel *chan)
876 {
877 u32 synthDelay;
878
879 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
880 if (IS_CHAN_B(chan))
881 synthDelay = (4 * synthDelay) / 22;
882 else
883 synthDelay /= 10;
884
885 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
886
887 udelay(synthDelay + BASE_ACTIVATE_DELAY);
888 }
889
890 static void ath9k_hw_init_qos(struct ath_hw *ah)
891 {
892 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
893 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
894
895 REG_WRITE(ah, AR_QOS_NO_ACK,
896 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
897 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
898 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
899
900 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
901 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
902 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
903 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
904 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
905 }
906
907 static void ath9k_hw_init_pll(struct ath_hw *ah,
908 struct ath9k_channel *chan)
909 {
910 u32 pll;
911
912 if (AR_SREV_9100(ah)) {
913 if (chan && IS_CHAN_5GHZ(chan))
914 pll = 0x1450;
915 else
916 pll = 0x1458;
917 } else {
918 if (AR_SREV_9280_10_OR_LATER(ah)) {
919 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
920
921 if (chan && IS_CHAN_HALF_RATE(chan))
922 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
923 else if (chan && IS_CHAN_QUARTER_RATE(chan))
924 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
925
926 if (chan && IS_CHAN_5GHZ(chan)) {
927 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
928
929
930 if (AR_SREV_9280_20(ah)) {
931 if (((chan->channel % 20) == 0)
932 || ((chan->channel % 10) == 0))
933 pll = 0x2850;
934 else
935 pll = 0x142c;
936 }
937 } else {
938 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
939 }
940
941 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
942
943 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
944
945 if (chan && IS_CHAN_HALF_RATE(chan))
946 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
947 else if (chan && IS_CHAN_QUARTER_RATE(chan))
948 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
949
950 if (chan && IS_CHAN_5GHZ(chan))
951 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
952 else
953 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
954 } else {
955 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
956
957 if (chan && IS_CHAN_HALF_RATE(chan))
958 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
959 else if (chan && IS_CHAN_QUARTER_RATE(chan))
960 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
961
962 if (chan && IS_CHAN_5GHZ(chan))
963 pll |= SM(0xa, AR_RTC_PLL_DIV);
964 else
965 pll |= SM(0xb, AR_RTC_PLL_DIV);
966 }
967 }
968 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
969
970 udelay(RTC_PLL_SETTLE_DELAY);
971
972 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
973 }
974
975 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
976 {
977 int rx_chainmask, tx_chainmask;
978
979 rx_chainmask = ah->rxchainmask;
980 tx_chainmask = ah->txchainmask;
981
982 switch (rx_chainmask) {
983 case 0x5:
984 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
985 AR_PHY_SWAP_ALT_CHAIN);
986 case 0x3:
987 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
988 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
989 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
990 break;
991 }
992 case 0x1:
993 case 0x2:
994 case 0x7:
995 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
996 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
997 break;
998 default:
999 break;
1000 }
1001
1002 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1003 if (tx_chainmask == 0x5) {
1004 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1005 AR_PHY_SWAP_ALT_CHAIN);
1006 }
1007 if (AR_SREV_9100(ah))
1008 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1009 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1010 }
1011
1012 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1013 enum nl80211_iftype opmode)
1014 {
1015 ah->mask_reg = AR_IMR_TXERR |
1016 AR_IMR_TXURN |
1017 AR_IMR_RXERR |
1018 AR_IMR_RXORN |
1019 AR_IMR_BCNMISC;
1020
1021 if (ah->intr_mitigation)
1022 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1023 else
1024 ah->mask_reg |= AR_IMR_RXOK;
1025
1026 ah->mask_reg |= AR_IMR_TXOK;
1027
1028 if (opmode == NL80211_IFTYPE_AP)
1029 ah->mask_reg |= AR_IMR_MIB;
1030
1031 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1032 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1033
1034 if (!AR_SREV_9100(ah)) {
1035 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1036 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1037 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1038 }
1039 }
1040
1041 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1042 {
1043 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1044 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1045 ah->acktimeout = (u32) -1;
1046 return false;
1047 } else {
1048 REG_RMW_FIELD(ah, AR_TIME_OUT,
1049 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1050 ah->acktimeout = us;
1051 return true;
1052 }
1053 }
1054
1055 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1056 {
1057 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1058 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1059 ah->ctstimeout = (u32) -1;
1060 return false;
1061 } else {
1062 REG_RMW_FIELD(ah, AR_TIME_OUT,
1063 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1064 ah->ctstimeout = us;
1065 return true;
1066 }
1067 }
1068
1069 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1070 {
1071 if (tu > 0xFFFF) {
1072 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1073 "bad global tx timeout %u\n", tu);
1074 ah->globaltxtimeout = (u32) -1;
1075 return false;
1076 } else {
1077 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1078 ah->globaltxtimeout = tu;
1079 return true;
1080 }
1081 }
1082
1083 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1084 {
1085 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1086 ah->misc_mode);
1087
1088 if (ah->misc_mode != 0)
1089 REG_WRITE(ah, AR_PCU_MISC,
1090 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1091 if (ah->slottime != (u32) -1)
1092 ath9k_hw_setslottime(ah, ah->slottime);
1093 if (ah->acktimeout != (u32) -1)
1094 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1095 if (ah->ctstimeout != (u32) -1)
1096 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1097 if (ah->globaltxtimeout != (u32) -1)
1098 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1099 }
1100
1101 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1102 {
1103 return vendorid == ATHEROS_VENDOR_ID ?
1104 ath9k_hw_devname(devid) : NULL;
1105 }
1106
1107 void ath9k_hw_detach(struct ath_hw *ah)
1108 {
1109 if (!AR_SREV_9100(ah))
1110 ath9k_hw_ani_detach(ah);
1111
1112 ath9k_hw_rfdetach(ah);
1113 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1114 kfree(ah);
1115 }
1116
1117 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1118 {
1119 struct ath_hw *ah = NULL;
1120
1121 switch (devid) {
1122 case AR5416_DEVID_PCI:
1123 case AR5416_DEVID_PCIE:
1124 case AR5416_AR9100_DEVID:
1125 case AR9160_DEVID_PCI:
1126 case AR9280_DEVID_PCI:
1127 case AR9280_DEVID_PCIE:
1128 case AR9285_DEVID_PCIE:
1129 ah = ath9k_hw_do_attach(devid, sc, error);
1130 break;
1131 default:
1132 *error = -ENXIO;
1133 break;
1134 }
1135
1136 return ah;
1137 }
1138
1139 /*******/
1140 /* INI */
1141 /*******/
1142
1143 static void ath9k_hw_override_ini(struct ath_hw *ah,
1144 struct ath9k_channel *chan)
1145 {
1146 /*
1147 * Set the RX_ABORT and RX_DIS and clear if off only after
1148 * RXE is set for MAC. This prevents frames with corrupted
1149 * descriptor status.
1150 */
1151 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1152
1153
1154 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1155 AR_SREV_9280_10_OR_LATER(ah))
1156 return;
1157
1158 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1159 }
1160
1161 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1162 struct ar5416_eeprom_def *pEepData,
1163 u32 reg, u32 value)
1164 {
1165 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1166
1167 switch (ah->hw_version.devid) {
1168 case AR9280_DEVID_PCI:
1169 if (reg == 0x7894) {
1170 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1171 "ini VAL: %x EEPROM: %x\n", value,
1172 (pBase->version & 0xff));
1173
1174 if ((pBase->version & 0xff) > 0x0a) {
1175 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1176 "PWDCLKIND: %d\n",
1177 pBase->pwdclkind);
1178 value &= ~AR_AN_TOP2_PWDCLKIND;
1179 value |= AR_AN_TOP2_PWDCLKIND &
1180 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1181 } else {
1182 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1183 "PWDCLKIND Earlier Rev\n");
1184 }
1185
1186 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1187 "final ini VAL: %x\n", value);
1188 }
1189 break;
1190 }
1191
1192 return value;
1193 }
1194
1195 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1196 struct ar5416_eeprom_def *pEepData,
1197 u32 reg, u32 value)
1198 {
1199 if (ah->eep_map == EEP_MAP_4KBITS)
1200 return value;
1201 else
1202 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1203 }
1204
1205 static int ath9k_hw_process_ini(struct ath_hw *ah,
1206 struct ath9k_channel *chan,
1207 enum ath9k_ht_macmode macmode)
1208 {
1209 int i, regWrites = 0;
1210 struct ieee80211_channel *channel = chan->chan;
1211 u32 modesIndex, freqIndex;
1212 int status;
1213
1214 switch (chan->chanmode) {
1215 case CHANNEL_A:
1216 case CHANNEL_A_HT20:
1217 modesIndex = 1;
1218 freqIndex = 1;
1219 break;
1220 case CHANNEL_A_HT40PLUS:
1221 case CHANNEL_A_HT40MINUS:
1222 modesIndex = 2;
1223 freqIndex = 1;
1224 break;
1225 case CHANNEL_G:
1226 case CHANNEL_G_HT20:
1227 case CHANNEL_B:
1228 modesIndex = 4;
1229 freqIndex = 2;
1230 break;
1231 case CHANNEL_G_HT40PLUS:
1232 case CHANNEL_G_HT40MINUS:
1233 modesIndex = 3;
1234 freqIndex = 2;
1235 break;
1236
1237 default:
1238 return -EINVAL;
1239 }
1240
1241 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1242 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1243 ah->eep_ops->set_addac(ah, chan);
1244
1245 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1246 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1247 } else {
1248 struct ar5416IniArray temp;
1249 u32 addacSize =
1250 sizeof(u32) * ah->iniAddac.ia_rows *
1251 ah->iniAddac.ia_columns;
1252
1253 memcpy(ah->addac5416_21,
1254 ah->iniAddac.ia_array, addacSize);
1255
1256 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1257
1258 temp.ia_array = ah->addac5416_21;
1259 temp.ia_columns = ah->iniAddac.ia_columns;
1260 temp.ia_rows = ah->iniAddac.ia_rows;
1261 REG_WRITE_ARRAY(&temp, 1, regWrites);
1262 }
1263
1264 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1265
1266 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1267 u32 reg = INI_RA(&ah->iniModes, i, 0);
1268 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1269
1270 REG_WRITE(ah, reg, val);
1271
1272 if (reg >= 0x7800 && reg < 0x78a0
1273 && ah->config.analog_shiftreg) {
1274 udelay(100);
1275 }
1276
1277 DO_DELAY(regWrites);
1278 }
1279
1280 if (AR_SREV_9280(ah))
1281 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1282
1283 if (AR_SREV_9280(ah))
1284 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1285
1286 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1287 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1288 u32 val = INI_RA(&ah->iniCommon, i, 1);
1289
1290 REG_WRITE(ah, reg, val);
1291
1292 if (reg >= 0x7800 && reg < 0x78a0
1293 && ah->config.analog_shiftreg) {
1294 udelay(100);
1295 }
1296
1297 DO_DELAY(regWrites);
1298 }
1299
1300 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1301
1302 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1303 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1304 regWrites);
1305 }
1306
1307 ath9k_hw_override_ini(ah, chan);
1308 ath9k_hw_set_regs(ah, chan, macmode);
1309 ath9k_hw_init_chain_masks(ah);
1310
1311 status = ah->eep_ops->set_txpower(ah, chan,
1312 ath9k_regd_get_ctl(ah, chan),
1313 channel->max_antenna_gain * 2,
1314 channel->max_power * 2,
1315 min((u32) MAX_RATE_POWER,
1316 (u32) ah->regulatory.power_limit));
1317 if (status != 0) {
1318 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1319 "error init'ing transmit power\n");
1320 return -EIO;
1321 }
1322
1323 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1324 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1325 "ar5416SetRfRegs failed\n");
1326 return -EIO;
1327 }
1328
1329 return 0;
1330 }
1331
1332 /****************************************/
1333 /* Reset and Channel Switching Routines */
1334 /****************************************/
1335
1336 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1337 {
1338 u32 rfMode = 0;
1339
1340 if (chan == NULL)
1341 return;
1342
1343 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1344 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1345
1346 if (!AR_SREV_9280_10_OR_LATER(ah))
1347 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1348 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1349
1350 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1351 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1352
1353 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1354 }
1355
1356 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1357 {
1358 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1359 }
1360
1361 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1362 {
1363 u32 regval;
1364
1365 regval = REG_READ(ah, AR_AHB_MODE);
1366 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1367
1368 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1369 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1370
1371 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1372
1373 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1374 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1375
1376 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1377
1378 if (AR_SREV_9285(ah)) {
1379 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1380 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1381 } else {
1382 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1383 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1384 }
1385 }
1386
1387 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1388 {
1389 u32 val;
1390
1391 val = REG_READ(ah, AR_STA_ID1);
1392 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1393 switch (opmode) {
1394 case NL80211_IFTYPE_AP:
1395 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1396 | AR_STA_ID1_KSRCH_MODE);
1397 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1398 break;
1399 case NL80211_IFTYPE_ADHOC:
1400 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1401 | AR_STA_ID1_KSRCH_MODE);
1402 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1403 break;
1404 case NL80211_IFTYPE_STATION:
1405 case NL80211_IFTYPE_MONITOR:
1406 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1407 break;
1408 }
1409 }
1410
1411 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1412 u32 coef_scaled,
1413 u32 *coef_mantissa,
1414 u32 *coef_exponent)
1415 {
1416 u32 coef_exp, coef_man;
1417
1418 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1419 if ((coef_scaled >> coef_exp) & 0x1)
1420 break;
1421
1422 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1423
1424 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1425
1426 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1427 *coef_exponent = coef_exp - 16;
1428 }
1429
1430 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1431 struct ath9k_channel *chan)
1432 {
1433 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1434 u32 clockMhzScaled = 0x64000000;
1435 struct chan_centers centers;
1436
1437 if (IS_CHAN_HALF_RATE(chan))
1438 clockMhzScaled = clockMhzScaled >> 1;
1439 else if (IS_CHAN_QUARTER_RATE(chan))
1440 clockMhzScaled = clockMhzScaled >> 2;
1441
1442 ath9k_hw_get_channel_centers(ah, chan, &centers);
1443 coef_scaled = clockMhzScaled / centers.synth_center;
1444
1445 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1446 &ds_coef_exp);
1447
1448 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1449 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1450 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1451 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1452
1453 coef_scaled = (9 * coef_scaled) / 10;
1454
1455 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1456 &ds_coef_exp);
1457
1458 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1459 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1460 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1461 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1462 }
1463
1464 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1465 {
1466 u32 rst_flags;
1467 u32 tmpReg;
1468
1469 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1470 AR_RTC_FORCE_WAKE_ON_INT);
1471
1472 if (AR_SREV_9100(ah)) {
1473 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1474 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1475 } else {
1476 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1477 if (tmpReg &
1478 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1479 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1480 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1481 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1482 } else {
1483 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1484 }
1485
1486 rst_flags = AR_RTC_RC_MAC_WARM;
1487 if (type == ATH9K_RESET_COLD)
1488 rst_flags |= AR_RTC_RC_MAC_COLD;
1489 }
1490
1491 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1492 udelay(50);
1493
1494 REG_WRITE(ah, AR_RTC_RC, 0);
1495 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1496 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1497 "RTC stuck in MAC reset\n");
1498 return false;
1499 }
1500
1501 if (!AR_SREV_9100(ah))
1502 REG_WRITE(ah, AR_RC, 0);
1503
1504 ath9k_hw_init_pll(ah, NULL);
1505
1506 if (AR_SREV_9100(ah))
1507 udelay(50);
1508
1509 return true;
1510 }
1511
1512 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1513 {
1514 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1515 AR_RTC_FORCE_WAKE_ON_INT);
1516
1517 REG_WRITE(ah, AR_RTC_RESET, 0);
1518 REG_WRITE(ah, AR_RTC_RESET, 1);
1519
1520 if (!ath9k_hw_wait(ah,
1521 AR_RTC_STATUS,
1522 AR_RTC_STATUS_M,
1523 AR_RTC_STATUS_ON)) {
1524 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1525 return false;
1526 }
1527
1528 ath9k_hw_read_revisions(ah);
1529
1530 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1531 }
1532
1533 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1534 {
1535 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1536 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1537
1538 switch (type) {
1539 case ATH9K_RESET_POWER_ON:
1540 return ath9k_hw_set_reset_power_on(ah);
1541 break;
1542 case ATH9K_RESET_WARM:
1543 case ATH9K_RESET_COLD:
1544 return ath9k_hw_set_reset(ah, type);
1545 break;
1546 default:
1547 return false;
1548 }
1549 }
1550
1551 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1552 enum ath9k_ht_macmode macmode)
1553 {
1554 u32 phymode;
1555 u32 enableDacFifo = 0;
1556
1557 if (AR_SREV_9285_10_OR_LATER(ah))
1558 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1559 AR_PHY_FC_ENABLE_DAC_FIFO);
1560
1561 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1562 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1563
1564 if (IS_CHAN_HT40(chan)) {
1565 phymode |= AR_PHY_FC_DYN2040_EN;
1566
1567 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1568 (chan->chanmode == CHANNEL_G_HT40PLUS))
1569 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1570
1571 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1572 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1573 }
1574 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1575
1576 ath9k_hw_set11nmac2040(ah, macmode);
1577
1578 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1579 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1580 }
1581
1582 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1583 struct ath9k_channel *chan)
1584 {
1585 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1586 return false;
1587
1588 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1589 return false;
1590
1591 ah->chip_fullsleep = false;
1592 ath9k_hw_init_pll(ah, chan);
1593 ath9k_hw_set_rfmode(ah, chan);
1594
1595 return true;
1596 }
1597
1598 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1599 struct ath9k_channel *chan,
1600 enum ath9k_ht_macmode macmode)
1601 {
1602 struct ieee80211_channel *channel = chan->chan;
1603 u32 synthDelay, qnum;
1604
1605 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1606 if (ath9k_hw_numtxpending(ah, qnum)) {
1607 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1608 "Transmit frames pending on queue %d\n", qnum);
1609 return false;
1610 }
1611 }
1612
1613 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1614 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1615 AR_PHY_RFBUS_GRANT_EN)) {
1616 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1617 "Could not kill baseband RX\n");
1618 return false;
1619 }
1620
1621 ath9k_hw_set_regs(ah, chan, macmode);
1622
1623 if (AR_SREV_9280_10_OR_LATER(ah)) {
1624 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1625 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1626 "failed to set channel\n");
1627 return false;
1628 }
1629 } else {
1630 if (!(ath9k_hw_set_channel(ah, chan))) {
1631 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1632 "failed to set channel\n");
1633 return false;
1634 }
1635 }
1636
1637 if (ah->eep_ops->set_txpower(ah, chan,
1638 ath9k_regd_get_ctl(ah, chan),
1639 channel->max_antenna_gain * 2,
1640 channel->max_power * 2,
1641 min((u32) MAX_RATE_POWER,
1642 (u32) ah->regulatory.power_limit)) != 0) {
1643 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1644 "error init'ing transmit power\n");
1645 return false;
1646 }
1647
1648 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1649 if (IS_CHAN_B(chan))
1650 synthDelay = (4 * synthDelay) / 22;
1651 else
1652 synthDelay /= 10;
1653
1654 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1655
1656 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1657
1658 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1659 ath9k_hw_set_delta_slope(ah, chan);
1660
1661 if (AR_SREV_9280_10_OR_LATER(ah))
1662 ath9k_hw_9280_spur_mitigate(ah, chan);
1663 else
1664 ath9k_hw_spur_mitigate(ah, chan);
1665
1666 if (!chan->oneTimeCalsDone)
1667 chan->oneTimeCalsDone = true;
1668
1669 return true;
1670 }
1671
1672 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1673 {
1674 int bb_spur = AR_NO_SPUR;
1675 int freq;
1676 int bin, cur_bin;
1677 int bb_spur_off, spur_subchannel_sd;
1678 int spur_freq_sd;
1679 int spur_delta_phase;
1680 int denominator;
1681 int upper, lower, cur_vit_mask;
1682 int tmp, newVal;
1683 int i;
1684 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1685 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1686 };
1687 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1688 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1689 };
1690 int inc[4] = { 0, 100, 0, 0 };
1691 struct chan_centers centers;
1692
1693 int8_t mask_m[123];
1694 int8_t mask_p[123];
1695 int8_t mask_amt;
1696 int tmp_mask;
1697 int cur_bb_spur;
1698 bool is2GHz = IS_CHAN_2GHZ(chan);
1699
1700 memset(&mask_m, 0, sizeof(int8_t) * 123);
1701 memset(&mask_p, 0, sizeof(int8_t) * 123);
1702
1703 ath9k_hw_get_channel_centers(ah, chan, &centers);
1704 freq = centers.synth_center;
1705
1706 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1707 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1708 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1709
1710 if (is2GHz)
1711 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1712 else
1713 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1714
1715 if (AR_NO_SPUR == cur_bb_spur)
1716 break;
1717 cur_bb_spur = cur_bb_spur - freq;
1718
1719 if (IS_CHAN_HT40(chan)) {
1720 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1721 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1722 bb_spur = cur_bb_spur;
1723 break;
1724 }
1725 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1726 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1727 bb_spur = cur_bb_spur;
1728 break;
1729 }
1730 }
1731
1732 if (AR_NO_SPUR == bb_spur) {
1733 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1734 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1735 return;
1736 } else {
1737 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1738 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1739 }
1740
1741 bin = bb_spur * 320;
1742
1743 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1744
1745 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1746 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1747 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1748 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1749 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1750
1751 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1752 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1753 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1754 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1755 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1756 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1757
1758 if (IS_CHAN_HT40(chan)) {
1759 if (bb_spur < 0) {
1760 spur_subchannel_sd = 1;
1761 bb_spur_off = bb_spur + 10;
1762 } else {
1763 spur_subchannel_sd = 0;
1764 bb_spur_off = bb_spur - 10;
1765 }
1766 } else {
1767 spur_subchannel_sd = 0;
1768 bb_spur_off = bb_spur;
1769 }
1770
1771 if (IS_CHAN_HT40(chan))
1772 spur_delta_phase =
1773 ((bb_spur * 262144) /
1774 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1775 else
1776 spur_delta_phase =
1777 ((bb_spur * 524288) /
1778 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1779
1780 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1781 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1782
1783 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1784 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1785 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1786 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1787
1788 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1789 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1790
1791 cur_bin = -6000;
1792 upper = bin + 100;
1793 lower = bin - 100;
1794
1795 for (i = 0; i < 4; i++) {
1796 int pilot_mask = 0;
1797 int chan_mask = 0;
1798 int bp = 0;
1799 for (bp = 0; bp < 30; bp++) {
1800 if ((cur_bin > lower) && (cur_bin < upper)) {
1801 pilot_mask = pilot_mask | 0x1 << bp;
1802 chan_mask = chan_mask | 0x1 << bp;
1803 }
1804 cur_bin += 100;
1805 }
1806 cur_bin += inc[i];
1807 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1808 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1809 }
1810
1811 cur_vit_mask = 6100;
1812 upper = bin + 120;
1813 lower = bin - 120;
1814
1815 for (i = 0; i < 123; i++) {
1816 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1817
1818 /* workaround for gcc bug #37014 */
1819 volatile int tmp_v = abs(cur_vit_mask - bin);
1820
1821 if (tmp_v < 75)
1822 mask_amt = 1;
1823 else
1824 mask_amt = 0;
1825 if (cur_vit_mask < 0)
1826 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1827 else
1828 mask_p[cur_vit_mask / 100] = mask_amt;
1829 }
1830 cur_vit_mask -= 100;
1831 }
1832
1833 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1834 | (mask_m[48] << 26) | (mask_m[49] << 24)
1835 | (mask_m[50] << 22) | (mask_m[51] << 20)
1836 | (mask_m[52] << 18) | (mask_m[53] << 16)
1837 | (mask_m[54] << 14) | (mask_m[55] << 12)
1838 | (mask_m[56] << 10) | (mask_m[57] << 8)
1839 | (mask_m[58] << 6) | (mask_m[59] << 4)
1840 | (mask_m[60] << 2) | (mask_m[61] << 0);
1841 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1842 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1843
1844 tmp_mask = (mask_m[31] << 28)
1845 | (mask_m[32] << 26) | (mask_m[33] << 24)
1846 | (mask_m[34] << 22) | (mask_m[35] << 20)
1847 | (mask_m[36] << 18) | (mask_m[37] << 16)
1848 | (mask_m[48] << 14) | (mask_m[39] << 12)
1849 | (mask_m[40] << 10) | (mask_m[41] << 8)
1850 | (mask_m[42] << 6) | (mask_m[43] << 4)
1851 | (mask_m[44] << 2) | (mask_m[45] << 0);
1852 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1853 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1854
1855 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1856 | (mask_m[18] << 26) | (mask_m[18] << 24)
1857 | (mask_m[20] << 22) | (mask_m[20] << 20)
1858 | (mask_m[22] << 18) | (mask_m[22] << 16)
1859 | (mask_m[24] << 14) | (mask_m[24] << 12)
1860 | (mask_m[25] << 10) | (mask_m[26] << 8)
1861 | (mask_m[27] << 6) | (mask_m[28] << 4)
1862 | (mask_m[29] << 2) | (mask_m[30] << 0);
1863 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1864 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1865
1866 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1867 | (mask_m[2] << 26) | (mask_m[3] << 24)
1868 | (mask_m[4] << 22) | (mask_m[5] << 20)
1869 | (mask_m[6] << 18) | (mask_m[7] << 16)
1870 | (mask_m[8] << 14) | (mask_m[9] << 12)
1871 | (mask_m[10] << 10) | (mask_m[11] << 8)
1872 | (mask_m[12] << 6) | (mask_m[13] << 4)
1873 | (mask_m[14] << 2) | (mask_m[15] << 0);
1874 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1875 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1876
1877 tmp_mask = (mask_p[15] << 28)
1878 | (mask_p[14] << 26) | (mask_p[13] << 24)
1879 | (mask_p[12] << 22) | (mask_p[11] << 20)
1880 | (mask_p[10] << 18) | (mask_p[9] << 16)
1881 | (mask_p[8] << 14) | (mask_p[7] << 12)
1882 | (mask_p[6] << 10) | (mask_p[5] << 8)
1883 | (mask_p[4] << 6) | (mask_p[3] << 4)
1884 | (mask_p[2] << 2) | (mask_p[1] << 0);
1885 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1886 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1887
1888 tmp_mask = (mask_p[30] << 28)
1889 | (mask_p[29] << 26) | (mask_p[28] << 24)
1890 | (mask_p[27] << 22) | (mask_p[26] << 20)
1891 | (mask_p[25] << 18) | (mask_p[24] << 16)
1892 | (mask_p[23] << 14) | (mask_p[22] << 12)
1893 | (mask_p[21] << 10) | (mask_p[20] << 8)
1894 | (mask_p[19] << 6) | (mask_p[18] << 4)
1895 | (mask_p[17] << 2) | (mask_p[16] << 0);
1896 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1897 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1898
1899 tmp_mask = (mask_p[45] << 28)
1900 | (mask_p[44] << 26) | (mask_p[43] << 24)
1901 | (mask_p[42] << 22) | (mask_p[41] << 20)
1902 | (mask_p[40] << 18) | (mask_p[39] << 16)
1903 | (mask_p[38] << 14) | (mask_p[37] << 12)
1904 | (mask_p[36] << 10) | (mask_p[35] << 8)
1905 | (mask_p[34] << 6) | (mask_p[33] << 4)
1906 | (mask_p[32] << 2) | (mask_p[31] << 0);
1907 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1908 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1909
1910 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1911 | (mask_p[59] << 26) | (mask_p[58] << 24)
1912 | (mask_p[57] << 22) | (mask_p[56] << 20)
1913 | (mask_p[55] << 18) | (mask_p[54] << 16)
1914 | (mask_p[53] << 14) | (mask_p[52] << 12)
1915 | (mask_p[51] << 10) | (mask_p[50] << 8)
1916 | (mask_p[49] << 6) | (mask_p[48] << 4)
1917 | (mask_p[47] << 2) | (mask_p[46] << 0);
1918 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1919 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1920 }
1921
1922 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1923 {
1924 int bb_spur = AR_NO_SPUR;
1925 int bin, cur_bin;
1926 int spur_freq_sd;
1927 int spur_delta_phase;
1928 int denominator;
1929 int upper, lower, cur_vit_mask;
1930 int tmp, new;
1931 int i;
1932 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1933 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1934 };
1935 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1936 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1937 };
1938 int inc[4] = { 0, 100, 0, 0 };
1939
1940 int8_t mask_m[123];
1941 int8_t mask_p[123];
1942 int8_t mask_amt;
1943 int tmp_mask;
1944 int cur_bb_spur;
1945 bool is2GHz = IS_CHAN_2GHZ(chan);
1946
1947 memset(&mask_m, 0, sizeof(int8_t) * 123);
1948 memset(&mask_p, 0, sizeof(int8_t) * 123);
1949
1950 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1951 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1952 if (AR_NO_SPUR == cur_bb_spur)
1953 break;
1954 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1955 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1956 bb_spur = cur_bb_spur;
1957 break;
1958 }
1959 }
1960
1961 if (AR_NO_SPUR == bb_spur)
1962 return;
1963
1964 bin = bb_spur * 32;
1965
1966 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1967 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1968 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1969 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1970 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1971
1972 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
1973
1974 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1975 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1976 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1977 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1978 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1979 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
1980
1981 spur_delta_phase = ((bb_spur * 524288) / 100) &
1982 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1983
1984 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
1985 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
1986
1987 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1988 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1989 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1990 REG_WRITE(ah, AR_PHY_TIMING11, new);
1991
1992 cur_bin = -6000;
1993 upper = bin + 100;
1994 lower = bin - 100;
1995
1996 for (i = 0; i < 4; i++) {
1997 int pilot_mask = 0;
1998 int chan_mask = 0;
1999 int bp = 0;
2000 for (bp = 0; bp < 30; bp++) {
2001 if ((cur_bin > lower) && (cur_bin < upper)) {
2002 pilot_mask = pilot_mask | 0x1 << bp;
2003 chan_mask = chan_mask | 0x1 << bp;
2004 }
2005 cur_bin += 100;
2006 }
2007 cur_bin += inc[i];
2008 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2009 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2010 }
2011
2012 cur_vit_mask = 6100;
2013 upper = bin + 120;
2014 lower = bin - 120;
2015
2016 for (i = 0; i < 123; i++) {
2017 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2018
2019 /* workaround for gcc bug #37014 */
2020 volatile int tmp_v = abs(cur_vit_mask - bin);
2021
2022 if (tmp_v < 75)
2023 mask_amt = 1;
2024 else
2025 mask_amt = 0;
2026 if (cur_vit_mask < 0)
2027 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2028 else
2029 mask_p[cur_vit_mask / 100] = mask_amt;
2030 }
2031 cur_vit_mask -= 100;
2032 }
2033
2034 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2035 | (mask_m[48] << 26) | (mask_m[49] << 24)
2036 | (mask_m[50] << 22) | (mask_m[51] << 20)
2037 | (mask_m[52] << 18) | (mask_m[53] << 16)
2038 | (mask_m[54] << 14) | (mask_m[55] << 12)
2039 | (mask_m[56] << 10) | (mask_m[57] << 8)
2040 | (mask_m[58] << 6) | (mask_m[59] << 4)
2041 | (mask_m[60] << 2) | (mask_m[61] << 0);
2042 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2043 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2044
2045 tmp_mask = (mask_m[31] << 28)
2046 | (mask_m[32] << 26) | (mask_m[33] << 24)
2047 | (mask_m[34] << 22) | (mask_m[35] << 20)
2048 | (mask_m[36] << 18) | (mask_m[37] << 16)
2049 | (mask_m[48] << 14) | (mask_m[39] << 12)
2050 | (mask_m[40] << 10) | (mask_m[41] << 8)
2051 | (mask_m[42] << 6) | (mask_m[43] << 4)
2052 | (mask_m[44] << 2) | (mask_m[45] << 0);
2053 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2054 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2055
2056 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2057 | (mask_m[18] << 26) | (mask_m[18] << 24)
2058 | (mask_m[20] << 22) | (mask_m[20] << 20)
2059 | (mask_m[22] << 18) | (mask_m[22] << 16)
2060 | (mask_m[24] << 14) | (mask_m[24] << 12)
2061 | (mask_m[25] << 10) | (mask_m[26] << 8)
2062 | (mask_m[27] << 6) | (mask_m[28] << 4)
2063 | (mask_m[29] << 2) | (mask_m[30] << 0);
2064 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2065 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2066
2067 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2068 | (mask_m[2] << 26) | (mask_m[3] << 24)
2069 | (mask_m[4] << 22) | (mask_m[5] << 20)
2070 | (mask_m[6] << 18) | (mask_m[7] << 16)
2071 | (mask_m[8] << 14) | (mask_m[9] << 12)
2072 | (mask_m[10] << 10) | (mask_m[11] << 8)
2073 | (mask_m[12] << 6) | (mask_m[13] << 4)
2074 | (mask_m[14] << 2) | (mask_m[15] << 0);
2075 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2076 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2077
2078 tmp_mask = (mask_p[15] << 28)
2079 | (mask_p[14] << 26) | (mask_p[13] << 24)
2080 | (mask_p[12] << 22) | (mask_p[11] << 20)
2081 | (mask_p[10] << 18) | (mask_p[9] << 16)
2082 | (mask_p[8] << 14) | (mask_p[7] << 12)
2083 | (mask_p[6] << 10) | (mask_p[5] << 8)
2084 | (mask_p[4] << 6) | (mask_p[3] << 4)
2085 | (mask_p[2] << 2) | (mask_p[1] << 0);
2086 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2087 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2088
2089 tmp_mask = (mask_p[30] << 28)
2090 | (mask_p[29] << 26) | (mask_p[28] << 24)
2091 | (mask_p[27] << 22) | (mask_p[26] << 20)
2092 | (mask_p[25] << 18) | (mask_p[24] << 16)
2093 | (mask_p[23] << 14) | (mask_p[22] << 12)
2094 | (mask_p[21] << 10) | (mask_p[20] << 8)
2095 | (mask_p[19] << 6) | (mask_p[18] << 4)
2096 | (mask_p[17] << 2) | (mask_p[16] << 0);
2097 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2098 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2099
2100 tmp_mask = (mask_p[45] << 28)
2101 | (mask_p[44] << 26) | (mask_p[43] << 24)
2102 | (mask_p[42] << 22) | (mask_p[41] << 20)
2103 | (mask_p[40] << 18) | (mask_p[39] << 16)
2104 | (mask_p[38] << 14) | (mask_p[37] << 12)
2105 | (mask_p[36] << 10) | (mask_p[35] << 8)
2106 | (mask_p[34] << 6) | (mask_p[33] << 4)
2107 | (mask_p[32] << 2) | (mask_p[31] << 0);
2108 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2109 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2110
2111 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2112 | (mask_p[59] << 26) | (mask_p[58] << 24)
2113 | (mask_p[57] << 22) | (mask_p[56] << 20)
2114 | (mask_p[55] << 18) | (mask_p[54] << 16)
2115 | (mask_p[53] << 14) | (mask_p[52] << 12)
2116 | (mask_p[51] << 10) | (mask_p[50] << 8)
2117 | (mask_p[49] << 6) | (mask_p[48] << 4)
2118 | (mask_p[47] << 2) | (mask_p[46] << 0);
2119 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2120 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2121 }
2122
2123 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2124 bool bChannelChange)
2125 {
2126 u32 saveLedState;
2127 struct ath_softc *sc = ah->ah_sc;
2128 struct ath9k_channel *curchan = ah->curchan;
2129 u32 saveDefAntenna;
2130 u32 macStaId1;
2131 int i, rx_chainmask, r;
2132
2133 ah->extprotspacing = sc->ht_extprotspacing;
2134 ah->txchainmask = sc->tx_chainmask;
2135 ah->rxchainmask = sc->rx_chainmask;
2136
2137 if (AR_SREV_9285(ah)) {
2138 ah->txchainmask &= 0x1;
2139 ah->rxchainmask &= 0x1;
2140 } else if (AR_SREV_9280(ah)) {
2141 ah->txchainmask &= 0x3;
2142 ah->rxchainmask &= 0x3;
2143 }
2144
2145 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2146 return -EIO;
2147
2148 if (curchan)
2149 ath9k_hw_getnf(ah, curchan);
2150
2151 if (bChannelChange &&
2152 (ah->chip_fullsleep != true) &&
2153 (ah->curchan != NULL) &&
2154 (chan->channel != ah->curchan->channel) &&
2155 ((chan->channelFlags & CHANNEL_ALL) ==
2156 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2157 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2158 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2159
2160 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2161 ath9k_hw_loadnf(ah, ah->curchan);
2162 ath9k_hw_start_nfcal(ah);
2163 return 0;
2164 }
2165 }
2166
2167 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2168 if (saveDefAntenna == 0)
2169 saveDefAntenna = 1;
2170
2171 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2172
2173 saveLedState = REG_READ(ah, AR_CFG_LED) &
2174 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2175 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2176
2177 ath9k_hw_mark_phy_inactive(ah);
2178
2179 if (!ath9k_hw_chip_reset(ah, chan)) {
2180 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2181 return -EINVAL;
2182 }
2183
2184 if (AR_SREV_9280_10_OR_LATER(ah))
2185 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2186
2187 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2188 if (r)
2189 return r;
2190
2191 /* Setup MFP options for CCMP */
2192 if (AR_SREV_9280_20_OR_LATER(ah)) {
2193 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2194 * frames when constructing CCMP AAD. */
2195 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2196 0xc7ff);
2197 ah->sw_mgmt_crypto = false;
2198 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2199 /* Disable hardware crypto for management frames */
2200 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2201 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2202 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2203 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2204 ah->sw_mgmt_crypto = true;
2205 } else
2206 ah->sw_mgmt_crypto = true;
2207
2208 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2209 ath9k_hw_set_delta_slope(ah, chan);
2210
2211 if (AR_SREV_9280_10_OR_LATER(ah))
2212 ath9k_hw_9280_spur_mitigate(ah, chan);
2213 else
2214 ath9k_hw_spur_mitigate(ah, chan);
2215
2216 if (!ah->eep_ops->set_board_values(ah, chan)) {
2217 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2218 "error setting board options\n");
2219 return -EIO;
2220 }
2221
2222 ath9k_hw_decrease_chain_power(ah, chan);
2223
2224 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2225 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2226 | macStaId1
2227 | AR_STA_ID1_RTS_USE_DEF
2228 | (ah->config.
2229 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2230 | ah->sta_id1_defaults);
2231 ath9k_hw_set_operating_mode(ah, ah->opmode);
2232
2233 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2234 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2235
2236 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2237
2238 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2239 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2240 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2241
2242 REG_WRITE(ah, AR_ISR, ~0);
2243
2244 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2245
2246 if (AR_SREV_9280_10_OR_LATER(ah)) {
2247 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2248 return -EIO;
2249 } else {
2250 if (!(ath9k_hw_set_channel(ah, chan)))
2251 return -EIO;
2252 }
2253
2254 for (i = 0; i < AR_NUM_DCU; i++)
2255 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2256
2257 ah->intr_txqs = 0;
2258 for (i = 0; i < ah->caps.total_queues; i++)
2259 ath9k_hw_resettxqueue(ah, i);
2260
2261 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2262 ath9k_hw_init_qos(ah);
2263
2264 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2265 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2266 ath9k_enable_rfkill(ah);
2267 #endif
2268 ath9k_hw_init_user_settings(ah);
2269
2270 REG_WRITE(ah, AR_STA_ID1,
2271 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2272
2273 ath9k_hw_set_dma(ah);
2274
2275 REG_WRITE(ah, AR_OBS, 8);
2276
2277 if (ah->intr_mitigation) {
2278
2279 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2280 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2281 }
2282
2283 ath9k_hw_init_bb(ah, chan);
2284
2285 if (!ath9k_hw_init_cal(ah, chan))
2286 return -EIO;;
2287
2288 rx_chainmask = ah->rxchainmask;
2289 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2290 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2291 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2292 }
2293
2294 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2295
2296 if (AR_SREV_9100(ah)) {
2297 u32 mask;
2298 mask = REG_READ(ah, AR_CFG);
2299 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2300 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2301 "CFG Byte Swap Set 0x%x\n", mask);
2302 } else {
2303 mask =
2304 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2305 REG_WRITE(ah, AR_CFG, mask);
2306 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2307 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2308 }
2309 } else {
2310 #ifdef __BIG_ENDIAN
2311 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2312 #endif
2313 }
2314
2315 return 0;
2316 }
2317
2318 /************************/
2319 /* Key Cache Management */
2320 /************************/
2321
2322 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2323 {
2324 u32 keyType;
2325
2326 if (entry >= ah->caps.keycache_size) {
2327 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2328 "entry %u out of range\n", entry);
2329 return false;
2330 }
2331
2332 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2333
2334 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2335 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2336 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2337 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2338 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2339 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2340 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2341 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2342
2343 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2344 u16 micentry = entry + 64;
2345
2346 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2347 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2348 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2349 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2350
2351 }
2352
2353 if (ah->curchan == NULL)
2354 return true;
2355
2356 return true;
2357 }
2358
2359 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2360 {
2361 u32 macHi, macLo;
2362
2363 if (entry >= ah->caps.keycache_size) {
2364 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2365 "entry %u out of range\n", entry);
2366 return false;
2367 }
2368
2369 if (mac != NULL) {
2370 macHi = (mac[5] << 8) | mac[4];
2371 macLo = (mac[3] << 24) |
2372 (mac[2] << 16) |
2373 (mac[1] << 8) |
2374 mac[0];
2375 macLo >>= 1;
2376 macLo |= (macHi & 1) << 31;
2377 macHi >>= 1;
2378 } else {
2379 macLo = macHi = 0;
2380 }
2381 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2382 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2383
2384 return true;
2385 }
2386
2387 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2388 const struct ath9k_keyval *k,
2389 const u8 *mac, int xorKey)
2390 {
2391 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2392 u32 key0, key1, key2, key3, key4;
2393 u32 keyType;
2394 u32 xorMask = xorKey ?
2395 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2396 | ATH9K_KEY_XOR) : 0;
2397
2398 if (entry >= pCap->keycache_size) {
2399 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2400 "entry %u out of range\n", entry);
2401 return false;
2402 }
2403
2404 switch (k->kv_type) {
2405 case ATH9K_CIPHER_AES_OCB:
2406 keyType = AR_KEYTABLE_TYPE_AES;
2407 break;
2408 case ATH9K_CIPHER_AES_CCM:
2409 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2410 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2411 "AES-CCM not supported by mac rev 0x%x\n",
2412 ah->hw_version.macRev);
2413 return false;
2414 }
2415 keyType = AR_KEYTABLE_TYPE_CCM;
2416 break;
2417 case ATH9K_CIPHER_TKIP:
2418 keyType = AR_KEYTABLE_TYPE_TKIP;
2419 if (ATH9K_IS_MIC_ENABLED(ah)
2420 && entry + 64 >= pCap->keycache_size) {
2421 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2422 "entry %u inappropriate for TKIP\n", entry);
2423 return false;
2424 }
2425 break;
2426 case ATH9K_CIPHER_WEP:
2427 if (k->kv_len < LEN_WEP40) {
2428 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2429 "WEP key length %u too small\n", k->kv_len);
2430 return false;
2431 }
2432 if (k->kv_len <= LEN_WEP40)
2433 keyType = AR_KEYTABLE_TYPE_40;
2434 else if (k->kv_len <= LEN_WEP104)
2435 keyType = AR_KEYTABLE_TYPE_104;
2436 else
2437 keyType = AR_KEYTABLE_TYPE_128;
2438 break;
2439 case ATH9K_CIPHER_CLR:
2440 keyType = AR_KEYTABLE_TYPE_CLR;
2441 break;
2442 default:
2443 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2444 "cipher %u not supported\n", k->kv_type);
2445 return false;
2446 }
2447
2448 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2449 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2450 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2451 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2452 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2453 if (k->kv_len <= LEN_WEP104)
2454 key4 &= 0xff;
2455
2456 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2457 u16 micentry = entry + 64;
2458
2459 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2460 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2461 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2462 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2463 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2464 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2465 (void) ath9k_hw_keysetmac(ah, entry, mac);
2466
2467 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2468 u32 mic0, mic1, mic2, mic3, mic4;
2469
2470 mic0 = get_unaligned_le32(k->kv_mic + 0);
2471 mic2 = get_unaligned_le32(k->kv_mic + 4);
2472 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2473 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2474 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2475 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2476 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2477 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2478 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2479 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2480 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2481 AR_KEYTABLE_TYPE_CLR);
2482
2483 } else {
2484 u32 mic0, mic2;
2485
2486 mic0 = get_unaligned_le32(k->kv_mic + 0);
2487 mic2 = get_unaligned_le32(k->kv_mic + 4);
2488 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2489 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2490 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2491 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2492 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2493 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2494 AR_KEYTABLE_TYPE_CLR);
2495 }
2496 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2497 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2498 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2499 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2500 } else {
2501 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2502 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2503 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2504 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2505 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2506 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2507
2508 (void) ath9k_hw_keysetmac(ah, entry, mac);
2509 }
2510
2511 if (ah->curchan == NULL)
2512 return true;
2513
2514 return true;
2515 }
2516
2517 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2518 {
2519 if (entry < ah->caps.keycache_size) {
2520 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2521 if (val & AR_KEYTABLE_VALID)
2522 return true;
2523 }
2524 return false;
2525 }
2526
2527 /******************************/
2528 /* Power Management (Chipset) */
2529 /******************************/
2530
2531 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2532 {
2533 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2534 if (setChip) {
2535 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2536 AR_RTC_FORCE_WAKE_EN);
2537 if (!AR_SREV_9100(ah))
2538 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2539
2540 REG_CLR_BIT(ah, (AR_RTC_RESET),
2541 AR_RTC_RESET_EN);
2542 }
2543 }
2544
2545 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2546 {
2547 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2548 if (setChip) {
2549 struct ath9k_hw_capabilities *pCap = &ah->caps;
2550
2551 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2552 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2553 AR_RTC_FORCE_WAKE_ON_INT);
2554 } else {
2555 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2556 AR_RTC_FORCE_WAKE_EN);
2557 }
2558 }
2559 }
2560
2561 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2562 {
2563 u32 val;
2564 int i;
2565
2566 if (setChip) {
2567 if ((REG_READ(ah, AR_RTC_STATUS) &
2568 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2569 if (ath9k_hw_set_reset_reg(ah,
2570 ATH9K_RESET_POWER_ON) != true) {
2571 return false;
2572 }
2573 }
2574 if (AR_SREV_9100(ah))
2575 REG_SET_BIT(ah, AR_RTC_RESET,
2576 AR_RTC_RESET_EN);
2577
2578 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2579 AR_RTC_FORCE_WAKE_EN);
2580 udelay(50);
2581
2582 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2583 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2584 if (val == AR_RTC_STATUS_ON)
2585 break;
2586 udelay(50);
2587 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2588 AR_RTC_FORCE_WAKE_EN);
2589 }
2590 if (i == 0) {
2591 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2592 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2593 return false;
2594 }
2595 }
2596
2597 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2598
2599 return true;
2600 }
2601
2602 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2603 {
2604 int status = true, setChip = true;
2605 static const char *modes[] = {
2606 "AWAKE",
2607 "FULL-SLEEP",
2608 "NETWORK SLEEP",
2609 "UNDEFINED"
2610 };
2611
2612 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2613 modes[ah->power_mode], modes[mode],
2614 setChip ? "set chip " : "");
2615
2616 switch (mode) {
2617 case ATH9K_PM_AWAKE:
2618 status = ath9k_hw_set_power_awake(ah, setChip);
2619 break;
2620 case ATH9K_PM_FULL_SLEEP:
2621 ath9k_set_power_sleep(ah, setChip);
2622 ah->chip_fullsleep = true;
2623 break;
2624 case ATH9K_PM_NETWORK_SLEEP:
2625 ath9k_set_power_network_sleep(ah, setChip);
2626 break;
2627 default:
2628 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2629 "Unknown power mode %u\n", mode);
2630 return false;
2631 }
2632 ah->power_mode = mode;
2633
2634 return status;
2635 }
2636
2637 /*
2638 * Helper for ASPM support.
2639 *
2640 * Disable PLL when in L0s as well as receiver clock when in L1.
2641 * This power saving option must be enabled through the SerDes.
2642 *
2643 * Programming the SerDes must go through the same 288 bit serial shift
2644 * register as the other analog registers. Hence the 9 writes.
2645 */
2646 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2647 {
2648 u8 i;
2649
2650 if (ah->is_pciexpress != true)
2651 return;
2652
2653 /* Do not touch SerDes registers */
2654 if (ah->config.pcie_powersave_enable == 2)
2655 return;
2656
2657 /* Nothing to do on restore for 11N */
2658 if (restore)
2659 return;
2660
2661 if (AR_SREV_9280_20_OR_LATER(ah)) {
2662 /*
2663 * AR9280 2.0 or later chips use SerDes values from the
2664 * initvals.h initialized depending on chipset during
2665 * ath9k_hw_do_attach()
2666 */
2667 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2668 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2669 INI_RA(&ah->iniPcieSerdes, i, 1));
2670 }
2671 } else if (AR_SREV_9280(ah) &&
2672 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2673 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2674 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2675
2676 /* RX shut off when elecidle is asserted */
2677 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2678 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2679 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2680
2681 /* Shut off CLKREQ active in L1 */
2682 if (ah->config.pcie_clock_req)
2683 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2684 else
2685 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2686
2687 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2688 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2689 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2690
2691 /* Load the new settings */
2692 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2693
2694 } else {
2695 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2696 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2697
2698 /* RX shut off when elecidle is asserted */
2699 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2700 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2701 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2702
2703 /*
2704 * Ignore ah->ah_config.pcie_clock_req setting for
2705 * pre-AR9280 11n
2706 */
2707 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2708
2709 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2710 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2711 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2712
2713 /* Load the new settings */
2714 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2715 }
2716
2717 udelay(1000);
2718
2719 /* set bit 19 to allow forcing of pcie core into L1 state */
2720 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2721
2722 /* Several PCIe massages to ensure proper behaviour */
2723 if (ah->config.pcie_waen) {
2724 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2725 } else {
2726 if (AR_SREV_9285(ah))
2727 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2728 /*
2729 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2730 * otherwise card may disappear.
2731 */
2732 else if (AR_SREV_9280(ah))
2733 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2734 else
2735 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2736 }
2737 }
2738
2739 /**********************/
2740 /* Interrupt Handling */
2741 /**********************/
2742
2743 bool ath9k_hw_intrpend(struct ath_hw *ah)
2744 {
2745 u32 host_isr;
2746
2747 if (AR_SREV_9100(ah))
2748 return true;
2749
2750 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2751 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2752 return true;
2753
2754 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2755 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2756 && (host_isr != AR_INTR_SPURIOUS))
2757 return true;
2758
2759 return false;
2760 }
2761
2762 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2763 {
2764 u32 isr = 0;
2765 u32 mask2 = 0;
2766 struct ath9k_hw_capabilities *pCap = &ah->caps;
2767 u32 sync_cause = 0;
2768 bool fatal_int = false;
2769
2770 if (!AR_SREV_9100(ah)) {
2771 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2772 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2773 == AR_RTC_STATUS_ON) {
2774 isr = REG_READ(ah, AR_ISR);
2775 }
2776 }
2777
2778 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2779 AR_INTR_SYNC_DEFAULT;
2780
2781 *masked = 0;
2782
2783 if (!isr && !sync_cause)
2784 return false;
2785 } else {
2786 *masked = 0;
2787 isr = REG_READ(ah, AR_ISR);
2788 }
2789
2790 if (isr) {
2791 if (isr & AR_ISR_BCNMISC) {
2792 u32 isr2;
2793 isr2 = REG_READ(ah, AR_ISR_S2);
2794 if (isr2 & AR_ISR_S2_TIM)
2795 mask2 |= ATH9K_INT_TIM;
2796 if (isr2 & AR_ISR_S2_DTIM)
2797 mask2 |= ATH9K_INT_DTIM;
2798 if (isr2 & AR_ISR_S2_DTIMSYNC)
2799 mask2 |= ATH9K_INT_DTIMSYNC;
2800 if (isr2 & (AR_ISR_S2_CABEND))
2801 mask2 |= ATH9K_INT_CABEND;
2802 if (isr2 & AR_ISR_S2_GTT)
2803 mask2 |= ATH9K_INT_GTT;
2804 if (isr2 & AR_ISR_S2_CST)
2805 mask2 |= ATH9K_INT_CST;
2806 if (isr2 & AR_ISR_S2_TSFOOR)
2807 mask2 |= ATH9K_INT_TSFOOR;
2808 }
2809
2810 isr = REG_READ(ah, AR_ISR_RAC);
2811 if (isr == 0xffffffff) {
2812 *masked = 0;
2813 return false;
2814 }
2815
2816 *masked = isr & ATH9K_INT_COMMON;
2817
2818 if (ah->intr_mitigation) {
2819 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2820 *masked |= ATH9K_INT_RX;
2821 }
2822
2823 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2824 *masked |= ATH9K_INT_RX;
2825 if (isr &
2826 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2827 AR_ISR_TXEOL)) {
2828 u32 s0_s, s1_s;
2829
2830 *masked |= ATH9K_INT_TX;
2831
2832 s0_s = REG_READ(ah, AR_ISR_S0_S);
2833 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2834 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2835
2836 s1_s = REG_READ(ah, AR_ISR_S1_S);
2837 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2838 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2839 }
2840
2841 if (isr & AR_ISR_RXORN) {
2842 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2843 "receive FIFO overrun interrupt\n");
2844 }
2845
2846 if (!AR_SREV_9100(ah)) {
2847 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2848 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2849 if (isr5 & AR_ISR_S5_TIM_TIMER)
2850 *masked |= ATH9K_INT_TIM_TIMER;
2851 }
2852 }
2853
2854 *masked |= mask2;
2855 }
2856
2857 if (AR_SREV_9100(ah))
2858 return true;
2859
2860 if (sync_cause) {
2861 fatal_int =
2862 (sync_cause &
2863 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2864 ? true : false;
2865
2866 if (fatal_int) {
2867 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2868 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2869 "received PCI FATAL interrupt\n");
2870 }
2871 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2872 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2873 "received PCI PERR interrupt\n");
2874 }
2875 }
2876 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2877 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2878 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2879 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2880 REG_WRITE(ah, AR_RC, 0);
2881 *masked |= ATH9K_INT_FATAL;
2882 }
2883 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2884 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2885 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2886 }
2887
2888 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2889 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2890 }
2891
2892 return true;
2893 }
2894
2895 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
2896 {
2897 return ah->mask_reg;
2898 }
2899
2900 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2901 {
2902 u32 omask = ah->mask_reg;
2903 u32 mask, mask2;
2904 struct ath9k_hw_capabilities *pCap = &ah->caps;
2905
2906 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2907
2908 if (omask & ATH9K_INT_GLOBAL) {
2909 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2910 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2911 (void) REG_READ(ah, AR_IER);
2912 if (!AR_SREV_9100(ah)) {
2913 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2914 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2915
2916 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2917 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2918 }
2919 }
2920
2921 mask = ints & ATH9K_INT_COMMON;
2922 mask2 = 0;
2923
2924 if (ints & ATH9K_INT_TX) {
2925 if (ah->txok_interrupt_mask)
2926 mask |= AR_IMR_TXOK;
2927 if (ah->txdesc_interrupt_mask)
2928 mask |= AR_IMR_TXDESC;
2929 if (ah->txerr_interrupt_mask)
2930 mask |= AR_IMR_TXERR;
2931 if (ah->txeol_interrupt_mask)
2932 mask |= AR_IMR_TXEOL;
2933 }
2934 if (ints & ATH9K_INT_RX) {
2935 mask |= AR_IMR_RXERR;
2936 if (ah->intr_mitigation)
2937 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2938 else
2939 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2940 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2941 mask |= AR_IMR_GENTMR;
2942 }
2943
2944 if (ints & (ATH9K_INT_BMISC)) {
2945 mask |= AR_IMR_BCNMISC;
2946 if (ints & ATH9K_INT_TIM)
2947 mask2 |= AR_IMR_S2_TIM;
2948 if (ints & ATH9K_INT_DTIM)
2949 mask2 |= AR_IMR_S2_DTIM;
2950 if (ints & ATH9K_INT_DTIMSYNC)
2951 mask2 |= AR_IMR_S2_DTIMSYNC;
2952 if (ints & ATH9K_INT_CABEND)
2953 mask2 |= AR_IMR_S2_CABEND;
2954 if (ints & ATH9K_INT_TSFOOR)
2955 mask2 |= AR_IMR_S2_TSFOOR;
2956 }
2957
2958 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2959 mask |= AR_IMR_BCNMISC;
2960 if (ints & ATH9K_INT_GTT)
2961 mask2 |= AR_IMR_S2_GTT;
2962 if (ints & ATH9K_INT_CST)
2963 mask2 |= AR_IMR_S2_CST;
2964 }
2965
2966 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2967 REG_WRITE(ah, AR_IMR, mask);
2968 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2969 AR_IMR_S2_DTIM |
2970 AR_IMR_S2_DTIMSYNC |
2971 AR_IMR_S2_CABEND |
2972 AR_IMR_S2_CABTO |
2973 AR_IMR_S2_TSFOOR |
2974 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2975 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2976 ah->mask_reg = ints;
2977
2978 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2979 if (ints & ATH9K_INT_TIM_TIMER)
2980 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2981 else
2982 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2983 }
2984
2985 if (ints & ATH9K_INT_GLOBAL) {
2986 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
2987 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2988 if (!AR_SREV_9100(ah)) {
2989 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2990 AR_INTR_MAC_IRQ);
2991 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2992
2993
2994 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2995 AR_INTR_SYNC_DEFAULT);
2996 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2997 AR_INTR_SYNC_DEFAULT);
2998 }
2999 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3000 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3001 }
3002
3003 return omask;
3004 }
3005
3006 /*******************/
3007 /* Beacon Handling */
3008 /*******************/
3009
3010 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3011 {
3012 int flags = 0;
3013
3014 ah->beacon_interval = beacon_period;
3015
3016 switch (ah->opmode) {
3017 case NL80211_IFTYPE_STATION:
3018 case NL80211_IFTYPE_MONITOR:
3019 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3020 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3021 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3022 flags |= AR_TBTT_TIMER_EN;
3023 break;
3024 case NL80211_IFTYPE_ADHOC:
3025 REG_SET_BIT(ah, AR_TXCFG,
3026 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3027 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3028 TU_TO_USEC(next_beacon +
3029 (ah->atim_window ? ah->
3030 atim_window : 1)));
3031 flags |= AR_NDP_TIMER_EN;
3032 case NL80211_IFTYPE_AP:
3033 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3034 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3035 TU_TO_USEC(next_beacon -
3036 ah->config.
3037 dma_beacon_response_time));
3038 REG_WRITE(ah, AR_NEXT_SWBA,
3039 TU_TO_USEC(next_beacon -
3040 ah->config.
3041 sw_beacon_response_time));
3042 flags |=
3043 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3044 break;
3045 default:
3046 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3047 "%s: unsupported opmode: %d\n",
3048 __func__, ah->opmode);
3049 return;
3050 break;
3051 }
3052
3053 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3054 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3055 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3056 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3057
3058 beacon_period &= ~ATH9K_BEACON_ENA;
3059 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3060 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3061 ath9k_hw_reset_tsf(ah);
3062 }
3063
3064 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3065 }
3066
3067 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3068 const struct ath9k_beacon_state *bs)
3069 {
3070 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3071 struct ath9k_hw_capabilities *pCap = &ah->caps;
3072
3073 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3074
3075 REG_WRITE(ah, AR_BEACON_PERIOD,
3076 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3077 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3078 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3079
3080 REG_RMW_FIELD(ah, AR_RSSI_THR,
3081 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3082
3083 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3084
3085 if (bs->bs_sleepduration > beaconintval)
3086 beaconintval = bs->bs_sleepduration;
3087
3088 dtimperiod = bs->bs_dtimperiod;
3089 if (bs->bs_sleepduration > dtimperiod)
3090 dtimperiod = bs->bs_sleepduration;
3091
3092 if (beaconintval == dtimperiod)
3093 nextTbtt = bs->bs_nextdtim;
3094 else
3095 nextTbtt = bs->bs_nexttbtt;
3096
3097 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3098 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3099 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3100 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3101
3102 REG_WRITE(ah, AR_NEXT_DTIM,
3103 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3104 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3105
3106 REG_WRITE(ah, AR_SLEEP1,
3107 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3108 | AR_SLEEP1_ASSUME_DTIM);
3109
3110 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3111 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3112 else
3113 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3114
3115 REG_WRITE(ah, AR_SLEEP2,
3116 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3117
3118 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3119 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3120
3121 REG_SET_BIT(ah, AR_TIMER_MODE,
3122 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3123 AR_DTIM_TIMER_EN);
3124
3125 /* TSF Out of Range Threshold */
3126 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3127 }
3128
3129 /*******************/
3130 /* HW Capabilities */
3131 /*******************/
3132
3133 bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3134 {
3135 struct ath9k_hw_capabilities *pCap = &ah->caps;
3136 u16 capField = 0, eeval;
3137
3138 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3139 ah->regulatory.current_rd = eeval;
3140
3141 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3142 if (AR_SREV_9285_10_OR_LATER(ah))
3143 eeval |= AR9285_RDEXT_DEFAULT;
3144 ah->regulatory.current_rd_ext = eeval;
3145
3146 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3147
3148 if (ah->opmode != NL80211_IFTYPE_AP &&
3149 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3150 if (ah->regulatory.current_rd == 0x64 ||
3151 ah->regulatory.current_rd == 0x65)
3152 ah->regulatory.current_rd += 5;
3153 else if (ah->regulatory.current_rd == 0x41)
3154 ah->regulatory.current_rd = 0x43;
3155 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3156 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3157 }
3158
3159 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3160 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3161
3162 if (eeval & AR5416_OPFLAGS_11A) {
3163 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3164 if (ah->config.ht_enable) {
3165 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3166 set_bit(ATH9K_MODE_11NA_HT20,
3167 pCap->wireless_modes);
3168 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3169 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3170 pCap->wireless_modes);
3171 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3172 pCap->wireless_modes);
3173 }
3174 }
3175 }
3176
3177 if (eeval & AR5416_OPFLAGS_11G) {
3178 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3179 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3180 if (ah->config.ht_enable) {
3181 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3182 set_bit(ATH9K_MODE_11NG_HT20,
3183 pCap->wireless_modes);
3184 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3185 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3186 pCap->wireless_modes);
3187 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3188 pCap->wireless_modes);
3189 }
3190 }
3191 }
3192
3193 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3194 if ((ah->is_pciexpress)
3195 || (eeval & AR5416_OPFLAGS_11A)) {
3196 pCap->rx_chainmask =
3197 ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3198 } else {
3199 pCap->rx_chainmask =
3200 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3201 }
3202
3203 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3204 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3205
3206 pCap->low_2ghz_chan = 2312;
3207 pCap->high_2ghz_chan = 2732;
3208
3209 pCap->low_5ghz_chan = 4920;
3210 pCap->high_5ghz_chan = 6100;
3211
3212 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3213 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3214 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3215
3216 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3217 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3218 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3219
3220 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3221
3222 if (ah->config.ht_enable)
3223 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3224 else
3225 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3226
3227 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3228 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3229 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3230 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3231
3232 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3233 pCap->total_queues =
3234 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3235 else
3236 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3237
3238 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3239 pCap->keycache_size =
3240 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3241 else
3242 pCap->keycache_size = AR_KEYTABLE_SIZE;
3243
3244 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3245 pCap->num_mr_retries = 4;
3246 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3247
3248 if (AR_SREV_9285_10_OR_LATER(ah))
3249 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3250 else if (AR_SREV_9280_10_OR_LATER(ah))
3251 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3252 else
3253 pCap->num_gpio_pins = AR_NUM_GPIO;
3254
3255 if (AR_SREV_9280_10_OR_LATER(ah)) {
3256 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3257 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3258 } else {
3259 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3260 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3261 }
3262
3263 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3264 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3265 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3266 } else {
3267 pCap->rts_aggr_limit = (8 * 1024);
3268 }
3269
3270 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3271
3272 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3273 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3274 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3275 ah->rfkill_gpio =
3276 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3277 ah->rfkill_polarity =
3278 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3279
3280 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3281 }
3282 #endif
3283
3284 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3285 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3286 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3287 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3288 (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3289 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3290 else
3291 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3292
3293 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3294 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3295 else
3296 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3297
3298 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3299 pCap->reg_cap =
3300 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3301 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3302 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3303 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3304 } else {
3305 pCap->reg_cap =
3306 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3307 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3308 }
3309
3310 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3311
3312 pCap->num_antcfg_5ghz =
3313 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3314 pCap->num_antcfg_2ghz =
3315 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3316
3317 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3318 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3319 ah->btactive_gpio = 6;
3320 ah->wlanactive_gpio = 5;
3321 }
3322
3323 return true;
3324 }
3325
3326 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3327 u32 capability, u32 *result)
3328 {
3329 const struct ath9k_hw_capabilities *pCap = &ah->caps;
3330
3331 switch (type) {
3332 case ATH9K_CAP_CIPHER:
3333 switch (capability) {
3334 case ATH9K_CIPHER_AES_CCM:
3335 case ATH9K_CIPHER_AES_OCB:
3336 case ATH9K_CIPHER_TKIP:
3337 case ATH9K_CIPHER_WEP:
3338 case ATH9K_CIPHER_MIC:
3339 case ATH9K_CIPHER_CLR:
3340 return true;
3341 default:
3342 return false;
3343 }
3344 case ATH9K_CAP_TKIP_MIC:
3345 switch (capability) {
3346 case 0:
3347 return true;
3348 case 1:
3349 return (ah->sta_id1_defaults &
3350 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3351 false;
3352 }
3353 case ATH9K_CAP_TKIP_SPLIT:
3354 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3355 false : true;
3356 case ATH9K_CAP_WME_TKIPMIC:
3357 return 0;
3358 case ATH9K_CAP_PHYCOUNTERS:
3359 return ah->has_hw_phycounters ? 0 : -ENXIO;
3360 case ATH9K_CAP_DIVERSITY:
3361 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3362 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3363 true : false;
3364 case ATH9K_CAP_PHYDIAG:
3365 return true;
3366 case ATH9K_CAP_MCAST_KEYSRCH:
3367 switch (capability) {
3368 case 0:
3369 return true;
3370 case 1:
3371 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3372 return false;
3373 } else {
3374 return (ah->sta_id1_defaults &
3375 AR_STA_ID1_MCAST_KSRCH) ? true :
3376 false;
3377 }
3378 }
3379 return false;
3380 case ATH9K_CAP_TSF_ADJUST:
3381 return (ah->misc_mode & AR_PCU_TX_ADD_TSF) ?
3382 true : false;
3383 case ATH9K_CAP_RFSILENT:
3384 if (capability == 3)
3385 return false;
3386 case ATH9K_CAP_ANT_CFG_2GHZ:
3387 *result = pCap->num_antcfg_2ghz;
3388 return true;
3389 case ATH9K_CAP_ANT_CFG_5GHZ:
3390 *result = pCap->num_antcfg_5ghz;
3391 return true;
3392 case ATH9K_CAP_TXPOW:
3393 switch (capability) {
3394 case 0:
3395 return 0;
3396 case 1:
3397 *result = ah->regulatory.power_limit;
3398 return 0;
3399 case 2:
3400 *result = ah->regulatory.max_power_level;
3401 return 0;
3402 case 3:
3403 *result = ah->regulatory.tp_scale;
3404 return 0;
3405 }
3406 return false;
3407 default:
3408 return false;
3409 }
3410 }
3411
3412 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3413 u32 capability, u32 setting, int *status)
3414 {
3415 u32 v;
3416
3417 switch (type) {
3418 case ATH9K_CAP_TKIP_MIC:
3419 if (setting)
3420 ah->sta_id1_defaults |=
3421 AR_STA_ID1_CRPT_MIC_ENABLE;
3422 else
3423 ah->sta_id1_defaults &=
3424 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3425 return true;
3426 case ATH9K_CAP_DIVERSITY:
3427 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3428 if (setting)
3429 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3430 else
3431 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3432 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3433 return true;
3434 case ATH9K_CAP_MCAST_KEYSRCH:
3435 if (setting)
3436 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3437 else
3438 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3439 return true;
3440 case ATH9K_CAP_TSF_ADJUST:
3441 if (setting)
3442 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3443 else
3444 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3445 return true;
3446 default:
3447 return false;
3448 }
3449 }
3450
3451 /****************************/
3452 /* GPIO / RFKILL / Antennae */
3453 /****************************/
3454
3455 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3456 u32 gpio, u32 type)
3457 {
3458 int addr;
3459 u32 gpio_shift, tmp;
3460
3461 if (gpio > 11)
3462 addr = AR_GPIO_OUTPUT_MUX3;
3463 else if (gpio > 5)
3464 addr = AR_GPIO_OUTPUT_MUX2;
3465 else
3466 addr = AR_GPIO_OUTPUT_MUX1;
3467
3468 gpio_shift = (gpio % 6) * 5;
3469
3470 if (AR_SREV_9280_20_OR_LATER(ah)
3471 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3472 REG_RMW(ah, addr, (type << gpio_shift),
3473 (0x1f << gpio_shift));
3474 } else {
3475 tmp = REG_READ(ah, addr);
3476 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3477 tmp &= ~(0x1f << gpio_shift);
3478 tmp |= (type << gpio_shift);
3479 REG_WRITE(ah, addr, tmp);
3480 }
3481 }
3482
3483 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3484 {
3485 u32 gpio_shift;
3486
3487 ASSERT(gpio < ah->caps.num_gpio_pins);
3488
3489 gpio_shift = gpio << 1;
3490
3491 REG_RMW(ah,
3492 AR_GPIO_OE_OUT,
3493 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3494 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3495 }
3496
3497 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3498 {
3499 #define MS_REG_READ(x, y) \
3500 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3501
3502 if (gpio >= ah->caps.num_gpio_pins)
3503 return 0xffffffff;
3504
3505 if (AR_SREV_9285_10_OR_LATER(ah))
3506 return MS_REG_READ(AR9285, gpio) != 0;
3507 else if (AR_SREV_9280_10_OR_LATER(ah))
3508 return MS_REG_READ(AR928X, gpio) != 0;
3509 else
3510 return MS_REG_READ(AR, gpio) != 0;
3511 }
3512
3513 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3514 u32 ah_signal_type)
3515 {
3516 u32 gpio_shift;
3517
3518 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3519
3520 gpio_shift = 2 * gpio;
3521
3522 REG_RMW(ah,
3523 AR_GPIO_OE_OUT,
3524 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3525 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3526 }
3527
3528 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3529 {
3530 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3531 AR_GPIO_BIT(gpio));
3532 }
3533
3534 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3535 void ath9k_enable_rfkill(struct ath_hw *ah)
3536 {
3537 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3538 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3539
3540 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3541 AR_GPIO_INPUT_MUX2_RFSILENT);
3542
3543 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3544 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3545 }
3546 #endif
3547
3548 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3549 {
3550 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3551 }
3552
3553 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3554 {
3555 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3556 }
3557
3558 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3559 enum ath9k_ant_setting settings,
3560 struct ath9k_channel *chan,
3561 u8 *tx_chainmask,
3562 u8 *rx_chainmask,
3563 u8 *antenna_cfgd)
3564 {
3565 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3566
3567 if (AR_SREV_9280(ah)) {
3568 if (!tx_chainmask_cfg) {
3569
3570 tx_chainmask_cfg = *tx_chainmask;
3571 rx_chainmask_cfg = *rx_chainmask;
3572 }
3573
3574 switch (settings) {
3575 case ATH9K_ANT_FIXED_A:
3576 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3577 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3578 *antenna_cfgd = true;
3579 break;
3580 case ATH9K_ANT_FIXED_B:
3581 if (ah->caps.tx_chainmask >
3582 ATH9K_ANTENNA1_CHAINMASK) {
3583 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3584 }
3585 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3586 *antenna_cfgd = true;
3587 break;
3588 case ATH9K_ANT_VARIABLE:
3589 *tx_chainmask = tx_chainmask_cfg;
3590 *rx_chainmask = rx_chainmask_cfg;
3591 *antenna_cfgd = true;
3592 break;
3593 default:
3594 break;
3595 }
3596 } else {
3597 ah->diversity_control = settings;
3598 }
3599
3600 return true;
3601 }
3602
3603 /*********************/
3604 /* General Operation */
3605 /*********************/
3606
3607 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3608 {
3609 u32 bits = REG_READ(ah, AR_RX_FILTER);
3610 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3611
3612 if (phybits & AR_PHY_ERR_RADAR)
3613 bits |= ATH9K_RX_FILTER_PHYRADAR;
3614 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3615 bits |= ATH9K_RX_FILTER_PHYERR;
3616
3617 return bits;
3618 }
3619
3620 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3621 {
3622 u32 phybits;
3623
3624 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3625 phybits = 0;
3626 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3627 phybits |= AR_PHY_ERR_RADAR;
3628 if (bits & ATH9K_RX_FILTER_PHYERR)
3629 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3630 REG_WRITE(ah, AR_PHY_ERR, phybits);
3631
3632 if (phybits)
3633 REG_WRITE(ah, AR_RXCFG,
3634 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3635 else
3636 REG_WRITE(ah, AR_RXCFG,
3637 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3638 }
3639
3640 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3641 {
3642 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3643 }
3644
3645 bool ath9k_hw_disable(struct ath_hw *ah)
3646 {
3647 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3648 return false;
3649
3650 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3651 }
3652
3653 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3654 {
3655 struct ath9k_channel *chan = ah->curchan;
3656 struct ieee80211_channel *channel = chan->chan;
3657
3658 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3659
3660 if (ah->eep_ops->set_txpower(ah, chan,
3661 ath9k_regd_get_ctl(ah, chan),
3662 channel->max_antenna_gain * 2,
3663 channel->max_power * 2,
3664 min((u32) MAX_RATE_POWER,
3665 (u32) ah->regulatory.power_limit)) != 0)
3666 return false;
3667
3668 return true;
3669 }
3670
3671 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3672 {
3673 memcpy(ah->macaddr, mac, ETH_ALEN);
3674 }
3675
3676 void ath9k_hw_setopmode(struct ath_hw *ah)
3677 {
3678 ath9k_hw_set_operating_mode(ah, ah->opmode);
3679 }
3680
3681 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3682 {
3683 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3684 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3685 }
3686
3687 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3688 {
3689 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3690 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3691 }
3692
3693 void ath9k_hw_write_associd(struct ath_softc *sc)
3694 {
3695 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3696 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3697 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3698 }
3699
3700 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3701 {
3702 u64 tsf;
3703
3704 tsf = REG_READ(ah, AR_TSF_U32);
3705 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3706
3707 return tsf;
3708 }
3709
3710 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3711 {
3712 REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3713 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3714 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3715 }
3716
3717 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3718 {
3719 int count;
3720
3721 count = 0;
3722 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3723 count++;
3724 if (count > 10) {
3725 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3726 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3727 break;
3728 }
3729 udelay(10);
3730 }
3731 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3732 }
3733
3734 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3735 {
3736 if (setting)
3737 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3738 else
3739 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3740
3741 return true;
3742 }
3743
3744 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3745 {
3746 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3747 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3748 ah->slottime = (u32) -1;
3749 return false;
3750 } else {
3751 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3752 ah->slottime = us;
3753 return true;
3754 }
3755 }
3756
3757 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3758 {
3759 u32 macmode;
3760
3761 if (mode == ATH9K_HT_MACMODE_2040 &&
3762 !ah->config.cwm_ignore_extcca)
3763 macmode = AR_2040_JOINED_RX_CLEAR;
3764 else
3765 macmode = 0;
3766
3767 REG_WRITE(ah, AR_2040_MODE, macmode);
3768 }
3769
3770 /***************************/
3771 /* Bluetooth Coexistence */
3772 /***************************/
3773
3774 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3775 {
3776 /* connect bt_active to baseband */
3777 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3778 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3779 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3780
3781 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3782 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3783
3784 /* Set input mux for bt_active to gpio pin */
3785 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3786 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3787 ah->btactive_gpio);
3788
3789 /* Configure the desired gpio port for input */
3790 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3791
3792 /* Configure the desired GPIO port for TX_FRAME output */
3793 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3794 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3795 }
Linux kernel - Deliverables
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