2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
32 #define ATHEROS_VENDOR_ID 0x168c
33 #define AR5416_DEVID_PCI 0x0023
34 #define AR5416_DEVID_PCIE 0x0024
35 #define AR9160_DEVID_PCI 0x0027
36 #define AR9280_DEVID_PCI 0x0029
37 #define AR9280_DEVID_PCIE 0x002a
38 #define AR9285_DEVID_PCIE 0x002b
39 #define AR5416_AR9100_DEVID 0x000b
40 #define AR_SUBVENDOR_ID_NOG 0x0e11
41 #define AR_SUBVENDOR_ID_NEW_A 0x7065
42 #define AR5416_MAGIC 0x19641014
44 /* Register read/write primitives */
45 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sc->mem + _reg)
46 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sc->mem + _reg)
48 #define SM(_v, _f) (((_v) << _f##_S) & _f)
49 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
50 #define REG_RMW(_a, _r, _set, _clr) \
51 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
52 #define REG_RMW_FIELD(_a, _r, _f, _v) \
54 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
55 #define REG_SET_BIT(_a, _r, _f) \
56 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
57 #define REG_CLR_BIT(_a, _r, _f) \
58 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
60 #define DO_DELAY(x) do { \
61 if ((++(x) % 64) == 0) \
65 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
67 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
68 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
69 INI_RA((iniarray), r, (column))); \
74 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
75 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
76 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
77 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
78 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
79 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
81 #define AR_GPIOD_MASK 0x00001FFF
82 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
84 #define BASE_ACTIVATE_DELAY 100
85 #define RTC_PLL_SETTLE_DELAY 1000
86 #define COEF_SCALE_S 24
87 #define HT40_CHANNEL_CENTER_SHIFT 10
89 #define ATH9K_ANTENNA0_CHAINMASK 0x1
90 #define ATH9K_ANTENNA1_CHAINMASK 0x2
92 #define ATH9K_NUM_DMA_DEBUG_REGS 8
93 #define ATH9K_NUM_QUEUES 10
95 #define MAX_RATE_POWER 63
96 #define AH_TIMEOUT 100000
97 #define AH_TIME_QUANTUM 10
98 #define AR_KEYTABLE_SIZE 128
99 #define POWER_UP_TIME 200000
100 #define SPUR_RSSI_THRESH 40
102 #define CAB_TIMEOUT_VAL 10
103 #define BEACON_TIMEOUT_VAL 10
104 #define MIN_BEACON_TIMEOUT_VAL 1
107 #define INIT_CONFIG_STATUS 0x00000000
108 #define INIT_RSSI_THR 0x00000700
109 #define INIT_BCON_CNTRL_REG 0x00000000
111 #define TU_TO_USEC(_tu) ((_tu) << 10)
117 ATH9K_MODE_11NA_HT20
= 6,
118 ATH9K_MODE_11NG_HT20
= 7,
119 ATH9K_MODE_11NA_HT40PLUS
= 8,
120 ATH9K_MODE_11NA_HT40MINUS
= 9,
121 ATH9K_MODE_11NG_HT40PLUS
= 10,
122 ATH9K_MODE_11NG_HT40MINUS
= 11,
127 ATH9K_HW_CAP_CHAN_SPREAD
= BIT(0),
128 ATH9K_HW_CAP_MIC_AESCCM
= BIT(1),
129 ATH9K_HW_CAP_MIC_CKIP
= BIT(2),
130 ATH9K_HW_CAP_MIC_TKIP
= BIT(3),
131 ATH9K_HW_CAP_CIPHER_AESCCM
= BIT(4),
132 ATH9K_HW_CAP_CIPHER_CKIP
= BIT(5),
133 ATH9K_HW_CAP_CIPHER_TKIP
= BIT(6),
134 ATH9K_HW_CAP_VEOL
= BIT(7),
135 ATH9K_HW_CAP_BSSIDMASK
= BIT(8),
136 ATH9K_HW_CAP_MCAST_KEYSEARCH
= BIT(9),
137 ATH9K_HW_CAP_CHAN_HALFRATE
= BIT(10),
138 ATH9K_HW_CAP_CHAN_QUARTERRATE
= BIT(11),
139 ATH9K_HW_CAP_HT
= BIT(12),
140 ATH9K_HW_CAP_GTT
= BIT(13),
141 ATH9K_HW_CAP_FASTCC
= BIT(14),
142 ATH9K_HW_CAP_RFSILENT
= BIT(15),
143 ATH9K_HW_CAP_WOW
= BIT(16),
144 ATH9K_HW_CAP_CST
= BIT(17),
145 ATH9K_HW_CAP_ENHANCEDPM
= BIT(18),
146 ATH9K_HW_CAP_AUTOSLEEP
= BIT(19),
147 ATH9K_HW_CAP_4KB_SPLITTRANS
= BIT(20),
148 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT
= BIT(21),
149 ATH9K_HW_CAP_BT_COEX
= BIT(22)
152 enum ath9k_capability_type
{
153 ATH9K_CAP_CIPHER
= 0,
155 ATH9K_CAP_TKIP_SPLIT
,
156 ATH9K_CAP_PHYCOUNTERS
,
160 ATH9K_CAP_MCAST_KEYSRCH
,
161 ATH9K_CAP_TSF_ADJUST
,
162 ATH9K_CAP_WME_TKIPMIC
,
164 ATH9K_CAP_ANT_CFG_2GHZ
,
165 ATH9K_CAP_ANT_CFG_5GHZ
168 struct ath9k_hw_capabilities
{
169 u32 hw_caps
; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
170 DECLARE_BITMAP(wireless_modes
, ATH9K_MODE_MAX
); /* ATH9K_MODE_* */
173 u16 low_5ghz_chan
, high_5ghz_chan
;
174 u16 low_2ghz_chan
, high_2ghz_chan
;
179 u16 tx_triglevel_max
;
186 struct ath9k_ops_config
{
187 int dma_beacon_response_time
;
188 int sw_beacon_response_time
;
189 int additional_swba_backoff
;
191 int cwm_ignore_extcca
;
192 u8 pcie_powersave_enable
;
193 u8 pcie_l1skp_enable
;
196 int pcie_power_reset
;
205 u8 noise_immunity_level
;
206 u32 ofdm_weaksignal_det
;
207 u32 cck_weaksignal_thr
;
208 u8 spur_immunity_level
;
210 int8_t rssi_thr_high
;
212 u16 diversity_control
;
213 u16 antenna_switch_swap
;
214 int serialize_regmode
;
216 #define SPUR_DISABLE 0
217 #define SPUR_ENABLE_IOCTL 1
218 #define SPUR_ENABLE_EEPROM 2
219 #define AR_EEPROM_MODAL_SPURS 5
220 #define AR_SPUR_5413_1 1640
221 #define AR_SPUR_5413_2 1200
222 #define AR_NO_SPUR 0x8000
223 #define AR_BASE_FREQ_2GHZ 2300
224 #define AR_BASE_FREQ_5GHZ 4900
225 #define AR_SPUR_FEEQ_BOUND_HT40 19
226 #define AR_SPUR_FEEQ_BOUND_HT20 10
228 u16 spurchans
[AR_EEPROM_MODAL_SPURS
][2];
232 ATH9K_INT_RX
= 0x00000001,
233 ATH9K_INT_RXDESC
= 0x00000002,
234 ATH9K_INT_RXNOFRM
= 0x00000008,
235 ATH9K_INT_RXEOL
= 0x00000010,
236 ATH9K_INT_RXORN
= 0x00000020,
237 ATH9K_INT_TX
= 0x00000040,
238 ATH9K_INT_TXDESC
= 0x00000080,
239 ATH9K_INT_TIM_TIMER
= 0x00000100,
240 ATH9K_INT_TXURN
= 0x00000800,
241 ATH9K_INT_MIB
= 0x00001000,
242 ATH9K_INT_RXPHY
= 0x00004000,
243 ATH9K_INT_RXKCM
= 0x00008000,
244 ATH9K_INT_SWBA
= 0x00010000,
245 ATH9K_INT_BMISS
= 0x00040000,
246 ATH9K_INT_BNR
= 0x00100000,
247 ATH9K_INT_TIM
= 0x00200000,
248 ATH9K_INT_DTIM
= 0x00400000,
249 ATH9K_INT_DTIMSYNC
= 0x00800000,
250 ATH9K_INT_GPIO
= 0x01000000,
251 ATH9K_INT_CABEND
= 0x02000000,
252 ATH9K_INT_CST
= 0x10000000,
253 ATH9K_INT_GTT
= 0x20000000,
254 ATH9K_INT_FATAL
= 0x40000000,
255 ATH9K_INT_GLOBAL
= 0x80000000,
256 ATH9K_INT_BMISC
= ATH9K_INT_TIM
|
260 ATH9K_INT_COMMON
= ATH9K_INT_RXNOFRM
|
272 ATH9K_INT_NOCARD
= 0xffffffff
275 #define CHANNEL_CW_INT 0x00002
276 #define CHANNEL_CCK 0x00020
277 #define CHANNEL_OFDM 0x00040
278 #define CHANNEL_2GHZ 0x00080
279 #define CHANNEL_5GHZ 0x00100
280 #define CHANNEL_PASSIVE 0x00200
281 #define CHANNEL_DYN 0x00400
282 #define CHANNEL_HALF 0x04000
283 #define CHANNEL_QUARTER 0x08000
284 #define CHANNEL_HT20 0x10000
285 #define CHANNEL_HT40PLUS 0x20000
286 #define CHANNEL_HT40MINUS 0x40000
288 #define CHANNEL_INTERFERENCE 0x01
289 #define CHANNEL_DFS 0x02
290 #define CHANNEL_4MS_LIMIT 0x04
291 #define CHANNEL_DFS_CLEAR 0x08
292 #define CHANNEL_DISALLOW_ADHOC 0x10
293 #define CHANNEL_PER_11D_ADHOC 0x20
295 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
296 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
297 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
298 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
299 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
300 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
301 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
302 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
303 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
304 #define CHANNEL_ALL \
313 struct ath9k_channel
{
314 struct ieee80211_channel
*chan
;
319 bool oneTimeCalsDone
;
322 int16_t rawNoiseFloor
;
325 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
326 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
327 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
328 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
329 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
330 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
331 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
332 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
333 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
334 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
335 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
336 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
337 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
338 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
339 #define IS_CHAN_A_5MHZ_SPACED(_c) \
340 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
341 (((_c)->channel % 20) != 0) && \
342 (((_c)->channel % 10) != 0))
344 /* These macros check chanmode and not channelFlags */
345 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
346 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
347 ((_c)->chanmode == CHANNEL_G_HT20))
348 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
349 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
350 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
351 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
352 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
354 enum ath9k_power_mode
{
357 ATH9K_PM_NETWORK_SLEEP
,
361 enum ath9k_ant_setting
{
362 ATH9K_ANT_VARIABLE
= 0,
367 enum ath9k_tp_scale
{
368 ATH9K_TP_SCALE_MAX
= 0,
376 SER_REG_MODE_OFF
= 0,
378 SER_REG_MODE_AUTO
= 2,
381 struct ath9k_beacon_state
{
385 #define ATH9K_BEACON_PERIOD 0x0000ffff
386 #define ATH9K_BEACON_ENA 0x00800000
387 #define ATH9K_BEACON_RESET_TSF 0x01000000
390 u16 bs_cfpmaxduration
;
393 u16 bs_bmissthreshold
;
394 u32 bs_sleepduration
;
397 struct chan_centers
{
404 ATH9K_RESET_POWER_ON
,
409 struct ath9k_hw_version
{
421 struct ath_softc
*ah_sc
;
422 struct ath9k_hw_version hw_version
;
423 struct ath9k_ops_config config
;
424 struct ath9k_hw_capabilities caps
;
425 struct ath9k_regulatory regulatory
;
426 struct ath9k_channel channels
[38];
427 struct ath9k_channel
*curchan
;
430 struct ar5416_eeprom_def def
;
431 struct ar5416_eeprom_4k map4k
;
433 const struct eeprom_ops
*eep_ops
;
434 enum ath9k_eep_map eep_map
;
438 u8 macaddr
[ETH_ALEN
];
447 enum nl80211_iftype opmode
;
448 enum ath9k_power_mode power_mode
;
449 enum ath9k_power_mode restore_mode
;
451 struct ath9k_nfcal_hist nfCalHist
[NUM_NF_READINGS
];
452 struct ar5416Stats stats
;
453 struct ath9k_tx_queue_info txq
[ATH9K_NUM_TX_QUEUES
];
455 int16_t curchan_rad_index
;
457 u32 txok_interrupt_mask
;
458 u32 txerr_interrupt_mask
;
459 u32 txdesc_interrupt_mask
;
460 u32 txeol_interrupt_mask
;
461 u32 txurn_interrupt_mask
;
464 u16 antenna_switch_swap
;
465 enum ath9k_ant_setting diversity_control
;
468 enum hal_cal_types supp_cals
;
469 struct hal_cal_list iq_caldata
;
470 struct hal_cal_list adcgain_caldata
;
471 struct hal_cal_list adcdc_calinitdata
;
472 struct hal_cal_list adcdc_caldata
;
473 struct hal_cal_list
*cal_list
;
474 struct hal_cal_list
*cal_list_last
;
475 struct hal_cal_list
*cal_list_curr
;
476 #define totalPowerMeasI meas0.unsign
477 #define totalPowerMeasQ meas1.unsign
478 #define totalIqCorrMeas meas2.sign
479 #define totalAdcIOddPhase meas0.unsign
480 #define totalAdcIEvenPhase meas1.unsign
481 #define totalAdcQOddPhase meas2.unsign
482 #define totalAdcQEvenPhase meas3.unsign
483 #define totalAdcDcOffsetIOddPhase meas0.sign
484 #define totalAdcDcOffsetIEvenPhase meas1.sign
485 #define totalAdcDcOffsetQOddPhase meas2.sign
486 #define totalAdcDcOffsetQEvenPhase meas3.sign
488 u32 unsign
[AR5416_MAX_CHAINS
];
489 int32_t sign
[AR5416_MAX_CHAINS
];
492 u32 unsign
[AR5416_MAX_CHAINS
];
493 int32_t sign
[AR5416_MAX_CHAINS
];
496 u32 unsign
[AR5416_MAX_CHAINS
];
497 int32_t sign
[AR5416_MAX_CHAINS
];
500 u32 unsign
[AR5416_MAX_CHAINS
];
501 int32_t sign
[AR5416_MAX_CHAINS
];
505 u32 sta_id1_defaults
;
511 } enable_32kHz_clock
;
514 u32
*analogBank0Data
;
515 u32
*analogBank1Data
;
516 u32
*analogBank2Data
;
517 u32
*analogBank3Data
;
518 u32
*analogBank6Data
;
519 u32
*analogBank6TPCData
;
520 u32
*analogBank7Data
;
524 int16_t txpower_indexoffset
;
534 bool has_hw_phycounters
;
536 struct ar5416AniState
*curani
;
537 struct ar5416AniState ani
[255];
538 int totalSizeDesired
[5];
542 enum ath9k_ani_cmd ani_function
;
545 bool intr_mitigation
;
546 enum ath9k_ht_extprotspacing extprotspacing
;
550 struct ar5416IniArray iniModes
;
551 struct ar5416IniArray iniCommon
;
552 struct ar5416IniArray iniBank0
;
553 struct ar5416IniArray iniBB_RfGain
;
554 struct ar5416IniArray iniBank1
;
555 struct ar5416IniArray iniBank2
;
556 struct ar5416IniArray iniBank3
;
557 struct ar5416IniArray iniBank6
;
558 struct ar5416IniArray iniBank6TPC
;
559 struct ar5416IniArray iniBank7
;
560 struct ar5416IniArray iniAddac
;
561 struct ar5416IniArray iniPcieSerdes
;
562 struct ar5416IniArray iniModesAdditional
;
563 struct ar5416IniArray iniModesRxGain
;
564 struct ar5416IniArray iniModesTxGain
;
567 /* Attach, Detach, Reset */
568 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
);
569 void ath9k_hw_detach(struct ath_hw
*ah
);
570 struct ath_hw
*ath9k_hw_attach(u16 devid
, struct ath_softc
*sc
, int *error
);
571 void ath9k_hw_rfdetach(struct ath_hw
*ah
);
572 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
573 bool bChannelChange
);
574 bool ath9k_hw_fill_cap_info(struct ath_hw
*ah
);
575 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
576 u32 capability
, u32
*result
);
577 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
578 u32 capability
, u32 setting
, int *status
);
580 /* Key Cache Management */
581 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
);
582 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
);
583 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
584 const struct ath9k_keyval
*k
,
585 const u8
*mac
, int xorKey
);
586 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
);
588 /* GPIO / RFKILL / Antennae */
589 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
);
590 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
);
591 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
593 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
);
594 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
595 void ath9k_enable_rfkill(struct ath_hw
*ah
);
597 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
);
598 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
);
599 bool ath9k_hw_setantennaswitch(struct ath_hw
*ah
,
600 enum ath9k_ant_setting settings
,
601 struct ath9k_channel
*chan
,
602 u8
*tx_chainmask
, u8
*rx_chainmask
,
605 /* General Operation */
606 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
);
607 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
);
608 bool ath9k_get_channel_edges(struct ath_hw
*ah
, u16 flags
, u16
*low
, u16
*high
);
609 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
, struct ath_rate_table
*rates
,
610 u32 frameLen
, u16 rateix
, bool shortPreamble
);
611 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
612 struct ath9k_channel
*chan
,
613 struct chan_centers
*centers
);
614 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
);
615 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
);
616 bool ath9k_hw_phy_disable(struct ath_hw
*ah
);
617 bool ath9k_hw_disable(struct ath_hw
*ah
);
618 bool ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
);
619 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
);
620 void ath9k_hw_setopmode(struct ath_hw
*ah
);
621 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
);
622 void ath9k_hw_setbssidmask(struct ath_softc
*sc
);
623 void ath9k_hw_write_associd(struct ath_softc
*sc
);
624 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
);
625 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
);
626 void ath9k_hw_reset_tsf(struct ath_hw
*ah
);
627 bool ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
);
628 bool ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
);
629 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
, enum ath9k_ht_macmode mode
);
630 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
);
631 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
632 const struct ath9k_beacon_state
*bs
);
633 bool ath9k_hw_setpower(struct ath_hw
*ah
,
634 enum ath9k_power_mode mode
);
635 void ath9k_hw_configpcipowersave(struct ath_hw
*ah
, int restore
);
637 /* Interrupt Handling */
638 bool ath9k_hw_intrpend(struct ath_hw
*ah
);
639 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
);
640 enum ath9k_int
ath9k_hw_intrget(struct ath_hw
*ah
);
641 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
);
643 void ath9k_hw_btcoex_enable(struct ath_hw
*ah
);