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ath9k: Handle power modes in isr for power save.
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 #define ATH_PCI_VERSION "0.1"
21
22 static char *dev_info = "ath9k";
23
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
28
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
33 /* We use the hw_value as an index into our private channel structure */
34
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39 }
40
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46 }
47
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67 };
68
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102 };
103
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
106 {
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
118 else
119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
135 break;
136 default:
137 BUG_ON(1);
138 break;
139 }
140 }
141
142 static void ath_update_txpow(struct ath_softc *sc)
143 {
144 struct ath_hw *ah = sc->sc_ah;
145 u32 txpow;
146
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
152 }
153 }
154
155 static u8 parse_mpdudensity(u8 mpdudensity)
156 {
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188 }
189
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191 {
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
227 sband->n_bitrates++;
228
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
231 }
232 }
233
234 /*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238 */
239 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
240 {
241 struct ath_hw *ah = sc->sc_ah;
242 bool fastcc = true, stopped;
243 struct ieee80211_hw *hw = sc->hw;
244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
250 ath9k_ps_wakeup(sc);
251
252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
262 ath_drain_all_txq(sc, false);
263 stopped = ath_stoprecv(sc);
264
265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
268
269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
274 sc->sc_ah->curchan->channel,
275 channel->center_freq, sc->tx_chan_width);
276
277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %u\n",
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
287 }
288 spin_unlock_bh(&sc->sc_resetlock);
289
290 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
291 sc->sc_flags &= ~SC_OP_FULL_RESET;
292
293 if (ath_startrecv(sc) != 0) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to restart recv logic\n");
296 return -EIO;
297 }
298
299 ath_cache_conf_rate(sc, &hw->conf);
300 ath_update_txpow(sc);
301 ath9k_hw_set_interrupts(ah, sc->imask);
302 ath9k_ps_restore(sc);
303 return 0;
304 }
305
306 /*
307 * This routine performs the periodic noise floor calibration function
308 * that is used to adjust and optimize the chip performance. This
309 * takes environmental changes (location, temperature) into account.
310 * When the task is complete, it reschedules itself depending on the
311 * appropriate interval that was calculated.
312 */
313 static void ath_ani_calibrate(unsigned long data)
314 {
315 struct ath_softc *sc = (struct ath_softc *)data;
316 struct ath_hw *ah = sc->sc_ah;
317 bool longcal = false;
318 bool shortcal = false;
319 bool aniflag = false;
320 unsigned int timestamp = jiffies_to_msecs(jiffies);
321 u32 cal_interval, short_cal_interval;
322
323 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
324 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
325
326 /*
327 * don't calibrate when we're scanning.
328 * we are most likely not on our home channel.
329 */
330 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
331 goto set_timer;
332
333 /* Long calibration runs independently of short calibration. */
334 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
335 longcal = true;
336 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
337 sc->ani.longcal_timer = timestamp;
338 }
339
340 /* Short calibration applies only while caldone is false */
341 if (!sc->ani.caldone) {
342 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
343 shortcal = true;
344 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
345 sc->ani.shortcal_timer = timestamp;
346 sc->ani.resetcal_timer = timestamp;
347 }
348 } else {
349 if ((timestamp - sc->ani.resetcal_timer) >=
350 ATH_RESTART_CALINTERVAL) {
351 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
352 if (sc->ani.caldone)
353 sc->ani.resetcal_timer = timestamp;
354 }
355 }
356
357 /* Verify whether we must check ANI */
358 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
359 aniflag = true;
360 sc->ani.checkani_timer = timestamp;
361 }
362
363 /* Skip all processing if there's nothing to do. */
364 if (longcal || shortcal || aniflag) {
365 /* Call ANI routine if necessary */
366 if (aniflag)
367 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
368
369 /* Perform calibration if necessary */
370 if (longcal || shortcal) {
371 bool iscaldone = false;
372
373 if (ath9k_hw_calibrate(ah, ah->curchan,
374 sc->rx_chainmask, longcal,
375 &iscaldone)) {
376 if (longcal)
377 sc->ani.noise_floor =
378 ath9k_hw_getchan_noise(ah,
379 ah->curchan);
380
381 DPRINTF(sc, ATH_DBG_ANI,
382 "calibrate chan %u/%x nf: %d\n",
383 ah->curchan->channel,
384 ah->curchan->channelFlags,
385 sc->ani.noise_floor);
386 } else {
387 DPRINTF(sc, ATH_DBG_ANY,
388 "calibrate chan %u/%x failed\n",
389 ah->curchan->channel,
390 ah->curchan->channelFlags);
391 }
392 sc->ani.caldone = iscaldone;
393 }
394 }
395
396 set_timer:
397 /*
398 * Set timer interval based on previous results.
399 * The interval must be the shortest necessary to satisfy ANI,
400 * short calibration and long calibration.
401 */
402 cal_interval = ATH_LONG_CALINTERVAL;
403 if (sc->sc_ah->config.enable_ani)
404 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
405 if (!sc->ani.caldone)
406 cal_interval = min(cal_interval, (u32)short_cal_interval);
407
408 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
409 }
410
411 /*
412 * Update tx/rx chainmask. For legacy association,
413 * hard code chainmask to 1x1, for 11n association, use
414 * the chainmask configuration, for bt coexistence, use
415 * the chainmask configuration even in legacy mode.
416 */
417 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
418 {
419 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
420 if (is_ht ||
421 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
422 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
423 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
424 } else {
425 sc->tx_chainmask = 1;
426 sc->rx_chainmask = 1;
427 }
428
429 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
430 sc->tx_chainmask, sc->rx_chainmask);
431 }
432
433 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434 {
435 struct ath_node *an;
436
437 an = (struct ath_node *)sta->drv_priv;
438
439 if (sc->sc_flags & SC_OP_TXAGGR)
440 ath_tx_node_init(sc, an);
441
442 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443 sta->ht_cap.ampdu_factor);
444 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445 }
446
447 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448 {
449 struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451 if (sc->sc_flags & SC_OP_TXAGGR)
452 ath_tx_node_cleanup(sc, an);
453 }
454
455 static void ath9k_tasklet(unsigned long data)
456 {
457 struct ath_softc *sc = (struct ath_softc *)data;
458 u32 status = sc->intrstatus;
459
460 if (status & ATH9K_INT_FATAL) {
461 /* need a chip reset */
462 ath_reset(sc, false);
463 return;
464 } else {
465
466 if (status &
467 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
468 spin_lock_bh(&sc->rx.rxflushlock);
469 ath_rx_tasklet(sc, 0);
470 spin_unlock_bh(&sc->rx.rxflushlock);
471 }
472 /* XXX: optimize this */
473 if (status & ATH9K_INT_TX)
474 ath_tx_tasklet(sc);
475 }
476
477 /* re-enable hardware interrupt */
478 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
479 }
480
481 irqreturn_t ath_isr(int irq, void *dev)
482 {
483 struct ath_softc *sc = dev;
484 struct ath_hw *ah = sc->sc_ah;
485 enum ath9k_int status;
486 bool sched = false;
487
488 do {
489 if (sc->sc_flags & SC_OP_INVALID) {
490 /*
491 * The hardware is not ready/present, don't
492 * touch anything. Note this can happen early
493 * on if the IRQ is shared.
494 */
495 return IRQ_NONE;
496 }
497 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
498 return IRQ_NONE;
499 }
500
501 /*
502 * Figure out the reason(s) for the interrupt. Note
503 * that the hal returns a pseudo-ISR that may include
504 * bits we haven't explicitly enabled so we mask the
505 * value to insure we only process bits we requested.
506 */
507 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
508
509 status &= sc->imask; /* discard unasked-for bits */
510
511 /*
512 * If there are no status bits set, then this interrupt was not
513 * for me (should have been caught above).
514 */
515 if (!status)
516 return IRQ_NONE;
517
518 sc->intrstatus = status;
519 ath9k_ps_wakeup(sc);
520
521 if (status & ATH9K_INT_FATAL) {
522 /* need a chip reset */
523 sched = true;
524 } else if (status & ATH9K_INT_RXORN) {
525 /* need a chip reset */
526 sched = true;
527 } else {
528 if (status & ATH9K_INT_SWBA) {
529 /* schedule a tasklet for beacon handling */
530 tasklet_schedule(&sc->bcon_tasklet);
531 }
532 if (status & ATH9K_INT_RXEOL) {
533 /*
534 * NB: the hardware should re-read the link when
535 * RXE bit is written, but it doesn't work
536 * at least on older hardware revs.
537 */
538 sched = true;
539 }
540
541 if (status & ATH9K_INT_TXURN)
542 /* bump tx trigger level */
543 ath9k_hw_updatetxtriglevel(ah, true);
544 /* XXX: optimize this */
545 if (status & ATH9K_INT_RX)
546 sched = true;
547 if (status & ATH9K_INT_TX)
548 sched = true;
549 if (status & ATH9K_INT_BMISS)
550 sched = true;
551 /* carrier sense timeout */
552 if (status & ATH9K_INT_CST)
553 sched = true;
554 if (status & ATH9K_INT_MIB) {
555 /*
556 * Disable interrupts until we service the MIB
557 * interrupt; otherwise it will continue to
558 * fire.
559 */
560 ath9k_hw_set_interrupts(ah, 0);
561 /*
562 * Let the hal handle the event. We assume
563 * it will clear whatever condition caused
564 * the interrupt.
565 */
566 ath9k_hw_procmibevent(ah, &sc->nodestats);
567 ath9k_hw_set_interrupts(ah, sc->imask);
568 }
569 if (status & ATH9K_INT_TIM_TIMER) {
570 if (!(ah->caps.hw_caps &
571 ATH9K_HW_CAP_AUTOSLEEP)) {
572 /* Clear RxAbort bit so that we can
573 * receive frames */
574 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
575 ath9k_hw_setrxabort(ah, 0);
576 sched = true;
577 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
578 }
579 }
580 if (status & ATH9K_INT_TSFOOR) {
581 /* FIXME: Handle this interrupt for power save */
582 sched = true;
583 }
584 }
585 ath9k_ps_restore(sc);
586 } while (0);
587
588 ath_debug_stat_interrupt(sc, status);
589
590 if (sched) {
591 /* turn off every interrupt except SWBA */
592 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
593 tasklet_schedule(&sc->intr_tq);
594 }
595
596 return IRQ_HANDLED;
597 }
598
599 static u32 ath_get_extchanmode(struct ath_softc *sc,
600 struct ieee80211_channel *chan,
601 enum nl80211_channel_type channel_type)
602 {
603 u32 chanmode = 0;
604
605 switch (chan->band) {
606 case IEEE80211_BAND_2GHZ:
607 switch(channel_type) {
608 case NL80211_CHAN_NO_HT:
609 case NL80211_CHAN_HT20:
610 chanmode = CHANNEL_G_HT20;
611 break;
612 case NL80211_CHAN_HT40PLUS:
613 chanmode = CHANNEL_G_HT40PLUS;
614 break;
615 case NL80211_CHAN_HT40MINUS:
616 chanmode = CHANNEL_G_HT40MINUS;
617 break;
618 }
619 break;
620 case IEEE80211_BAND_5GHZ:
621 switch(channel_type) {
622 case NL80211_CHAN_NO_HT:
623 case NL80211_CHAN_HT20:
624 chanmode = CHANNEL_A_HT20;
625 break;
626 case NL80211_CHAN_HT40PLUS:
627 chanmode = CHANNEL_A_HT40PLUS;
628 break;
629 case NL80211_CHAN_HT40MINUS:
630 chanmode = CHANNEL_A_HT40MINUS;
631 break;
632 }
633 break;
634 default:
635 break;
636 }
637
638 return chanmode;
639 }
640
641 static int ath_keyset(struct ath_softc *sc, u16 keyix,
642 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
643 {
644 bool status;
645
646 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
647 keyix, hk, mac);
648
649 return status != false;
650 }
651
652 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
653 struct ath9k_keyval *hk, const u8 *addr,
654 bool authenticator)
655 {
656 const u8 *key_rxmic;
657 const u8 *key_txmic;
658
659 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
660 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
661
662 if (addr == NULL) {
663 /* Group key installation */
664 if (authenticator) {
665 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
666 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
667 } else {
668 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
669 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
670 }
671 return ath_keyset(sc, keyix, hk, addr);
672 }
673 if (!sc->splitmic) {
674 /*
675 * data key goes at first index,
676 * the hal handles the MIC keys at index+64.
677 */
678 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
679 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
680 return ath_keyset(sc, keyix, hk, addr);
681 }
682 /*
683 * TX key goes at first index, RX key at +32.
684 * The hal handles the MIC keys at index+64.
685 */
686 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
687 if (!ath_keyset(sc, keyix, hk, NULL)) {
688 /* Txmic entry failed. No need to proceed further */
689 DPRINTF(sc, ATH_DBG_KEYCACHE,
690 "Setting TX MIC Key Failed\n");
691 return 0;
692 }
693
694 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
695 /* XXX delete tx key on failure? */
696 return ath_keyset(sc, keyix + 32, hk, addr);
697 }
698
699 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
700 {
701 int i;
702
703 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
704 if (test_bit(i, sc->keymap) ||
705 test_bit(i + 64, sc->keymap))
706 continue; /* At least one part of TKIP key allocated */
707 if (sc->splitmic &&
708 (test_bit(i + 32, sc->keymap) ||
709 test_bit(i + 64 + 32, sc->keymap)))
710 continue; /* At least one part of TKIP key allocated */
711
712 /* Found a free slot for a TKIP key */
713 return i;
714 }
715 return -1;
716 }
717
718 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
719 {
720 int i;
721
722 /* First, try to find slots that would not be available for TKIP. */
723 if (sc->splitmic) {
724 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
725 if (!test_bit(i, sc->keymap) &&
726 (test_bit(i + 32, sc->keymap) ||
727 test_bit(i + 64, sc->keymap) ||
728 test_bit(i + 64 + 32, sc->keymap)))
729 return i;
730 if (!test_bit(i + 32, sc->keymap) &&
731 (test_bit(i, sc->keymap) ||
732 test_bit(i + 64, sc->keymap) ||
733 test_bit(i + 64 + 32, sc->keymap)))
734 return i + 32;
735 if (!test_bit(i + 64, sc->keymap) &&
736 (test_bit(i , sc->keymap) ||
737 test_bit(i + 32, sc->keymap) ||
738 test_bit(i + 64 + 32, sc->keymap)))
739 return i + 64;
740 if (!test_bit(i + 64 + 32, sc->keymap) &&
741 (test_bit(i, sc->keymap) ||
742 test_bit(i + 32, sc->keymap) ||
743 test_bit(i + 64, sc->keymap)))
744 return i + 64 + 32;
745 }
746 } else {
747 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
748 if (!test_bit(i, sc->keymap) &&
749 test_bit(i + 64, sc->keymap))
750 return i;
751 if (test_bit(i, sc->keymap) &&
752 !test_bit(i + 64, sc->keymap))
753 return i + 64;
754 }
755 }
756
757 /* No partially used TKIP slots, pick any available slot */
758 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
759 /* Do not allow slots that could be needed for TKIP group keys
760 * to be used. This limitation could be removed if we know that
761 * TKIP will not be used. */
762 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
763 continue;
764 if (sc->splitmic) {
765 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
766 continue;
767 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
768 continue;
769 }
770
771 if (!test_bit(i, sc->keymap))
772 return i; /* Found a free slot for a key */
773 }
774
775 /* No free slot found */
776 return -1;
777 }
778
779 static int ath_key_config(struct ath_softc *sc,
780 struct ieee80211_vif *vif,
781 struct ieee80211_sta *sta,
782 struct ieee80211_key_conf *key)
783 {
784 struct ath9k_keyval hk;
785 const u8 *mac = NULL;
786 int ret = 0;
787 int idx;
788
789 memset(&hk, 0, sizeof(hk));
790
791 switch (key->alg) {
792 case ALG_WEP:
793 hk.kv_type = ATH9K_CIPHER_WEP;
794 break;
795 case ALG_TKIP:
796 hk.kv_type = ATH9K_CIPHER_TKIP;
797 break;
798 case ALG_CCMP:
799 hk.kv_type = ATH9K_CIPHER_AES_CCM;
800 break;
801 default:
802 return -EOPNOTSUPP;
803 }
804
805 hk.kv_len = key->keylen;
806 memcpy(hk.kv_val, key->key, key->keylen);
807
808 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
809 /* For now, use the default keys for broadcast keys. This may
810 * need to change with virtual interfaces. */
811 idx = key->keyidx;
812 } else if (key->keyidx) {
813 struct ieee80211_vif *vif;
814
815 if (WARN_ON(!sta))
816 return -EOPNOTSUPP;
817 mac = sta->addr;
818
819 vif = sc->vifs[0];
820 if (vif->type != NL80211_IFTYPE_AP) {
821 /* Only keyidx 0 should be used with unicast key, but
822 * allow this for client mode for now. */
823 idx = key->keyidx;
824 } else
825 return -EIO;
826 } else {
827 if (WARN_ON(!sta))
828 return -EOPNOTSUPP;
829 mac = sta->addr;
830
831 if (key->alg == ALG_TKIP)
832 idx = ath_reserve_key_cache_slot_tkip(sc);
833 else
834 idx = ath_reserve_key_cache_slot(sc);
835 if (idx < 0)
836 return -ENOSPC; /* no free key cache entries */
837 }
838
839 if (key->alg == ALG_TKIP)
840 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
841 vif->type == NL80211_IFTYPE_AP);
842 else
843 ret = ath_keyset(sc, idx, &hk, mac);
844
845 if (!ret)
846 return -EIO;
847
848 set_bit(idx, sc->keymap);
849 if (key->alg == ALG_TKIP) {
850 set_bit(idx + 64, sc->keymap);
851 if (sc->splitmic) {
852 set_bit(idx + 32, sc->keymap);
853 set_bit(idx + 64 + 32, sc->keymap);
854 }
855 }
856
857 return idx;
858 }
859
860 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
861 {
862 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
863 if (key->hw_key_idx < IEEE80211_WEP_NKID)
864 return;
865
866 clear_bit(key->hw_key_idx, sc->keymap);
867 if (key->alg != ALG_TKIP)
868 return;
869
870 clear_bit(key->hw_key_idx + 64, sc->keymap);
871 if (sc->splitmic) {
872 clear_bit(key->hw_key_idx + 32, sc->keymap);
873 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
874 }
875 }
876
877 static void setup_ht_cap(struct ath_softc *sc,
878 struct ieee80211_sta_ht_cap *ht_info)
879 {
880 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
881 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
882
883 ht_info->ht_supported = true;
884 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
885 IEEE80211_HT_CAP_SM_PS |
886 IEEE80211_HT_CAP_SGI_40 |
887 IEEE80211_HT_CAP_DSSSCCK40;
888
889 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
890 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
891
892 /* set up supported mcs set */
893 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
894
895 switch(sc->rx_chainmask) {
896 case 1:
897 ht_info->mcs.rx_mask[0] = 0xff;
898 break;
899 case 3:
900 case 5:
901 case 7:
902 default:
903 ht_info->mcs.rx_mask[0] = 0xff;
904 ht_info->mcs.rx_mask[1] = 0xff;
905 break;
906 }
907
908 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
909 }
910
911 static void ath9k_bss_assoc_info(struct ath_softc *sc,
912 struct ieee80211_vif *vif,
913 struct ieee80211_bss_conf *bss_conf)
914 {
915 struct ath_vif *avp = (void *)vif->drv_priv;
916
917 if (bss_conf->assoc) {
918 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
919 bss_conf->aid, sc->curbssid);
920
921 /* New association, store aid */
922 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
923 sc->curaid = bss_conf->aid;
924 ath9k_hw_write_associd(sc);
925 }
926
927 /* Configure the beacon */
928 ath_beacon_config(sc, 0);
929 sc->sc_flags |= SC_OP_BEACONS;
930
931 /* Reset rssi stats */
932 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
933 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
934 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
935 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
936
937 /* Start ANI */
938 mod_timer(&sc->ani.timer,
939 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
940 } else {
941 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
942 sc->curaid = 0;
943 }
944 }
945
946 /********************************/
947 /* LED functions */
948 /********************************/
949
950 static void ath_led_blink_work(struct work_struct *work)
951 {
952 struct ath_softc *sc = container_of(work, struct ath_softc,
953 ath_led_blink_work.work);
954
955 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
956 return;
957 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
958 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
959
960 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
961 (sc->sc_flags & SC_OP_LED_ON) ?
962 msecs_to_jiffies(sc->led_off_duration) :
963 msecs_to_jiffies(sc->led_on_duration));
964
965 sc->led_on_duration =
966 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
967 sc->led_off_duration =
968 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
969 sc->led_on_cnt = sc->led_off_cnt = 0;
970 if (sc->sc_flags & SC_OP_LED_ON)
971 sc->sc_flags &= ~SC_OP_LED_ON;
972 else
973 sc->sc_flags |= SC_OP_LED_ON;
974 }
975
976 static void ath_led_brightness(struct led_classdev *led_cdev,
977 enum led_brightness brightness)
978 {
979 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
980 struct ath_softc *sc = led->sc;
981
982 switch (brightness) {
983 case LED_OFF:
984 if (led->led_type == ATH_LED_ASSOC ||
985 led->led_type == ATH_LED_RADIO) {
986 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
987 (led->led_type == ATH_LED_RADIO));
988 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
989 if (led->led_type == ATH_LED_RADIO)
990 sc->sc_flags &= ~SC_OP_LED_ON;
991 } else {
992 sc->led_off_cnt++;
993 }
994 break;
995 case LED_FULL:
996 if (led->led_type == ATH_LED_ASSOC) {
997 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
998 queue_delayed_work(sc->hw->workqueue,
999 &sc->ath_led_blink_work, 0);
1000 } else if (led->led_type == ATH_LED_RADIO) {
1001 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1002 sc->sc_flags |= SC_OP_LED_ON;
1003 } else {
1004 sc->led_on_cnt++;
1005 }
1006 break;
1007 default:
1008 break;
1009 }
1010 }
1011
1012 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1013 char *trigger)
1014 {
1015 int ret;
1016
1017 led->sc = sc;
1018 led->led_cdev.name = led->name;
1019 led->led_cdev.default_trigger = trigger;
1020 led->led_cdev.brightness_set = ath_led_brightness;
1021
1022 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1023 if (ret)
1024 DPRINTF(sc, ATH_DBG_FATAL,
1025 "Failed to register led:%s", led->name);
1026 else
1027 led->registered = 1;
1028 return ret;
1029 }
1030
1031 static void ath_unregister_led(struct ath_led *led)
1032 {
1033 if (led->registered) {
1034 led_classdev_unregister(&led->led_cdev);
1035 led->registered = 0;
1036 }
1037 }
1038
1039 static void ath_deinit_leds(struct ath_softc *sc)
1040 {
1041 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1042 ath_unregister_led(&sc->assoc_led);
1043 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1044 ath_unregister_led(&sc->tx_led);
1045 ath_unregister_led(&sc->rx_led);
1046 ath_unregister_led(&sc->radio_led);
1047 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1048 }
1049
1050 static void ath_init_leds(struct ath_softc *sc)
1051 {
1052 char *trigger;
1053 int ret;
1054
1055 /* Configure gpio 1 for output */
1056 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1057 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1058 /* LED off, active low */
1059 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1060
1061 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1062
1063 trigger = ieee80211_get_radio_led_name(sc->hw);
1064 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1065 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1066 ret = ath_register_led(sc, &sc->radio_led, trigger);
1067 sc->radio_led.led_type = ATH_LED_RADIO;
1068 if (ret)
1069 goto fail;
1070
1071 trigger = ieee80211_get_assoc_led_name(sc->hw);
1072 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1073 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1074 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1075 sc->assoc_led.led_type = ATH_LED_ASSOC;
1076 if (ret)
1077 goto fail;
1078
1079 trigger = ieee80211_get_tx_led_name(sc->hw);
1080 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1081 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1082 ret = ath_register_led(sc, &sc->tx_led, trigger);
1083 sc->tx_led.led_type = ATH_LED_TX;
1084 if (ret)
1085 goto fail;
1086
1087 trigger = ieee80211_get_rx_led_name(sc->hw);
1088 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1089 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1090 ret = ath_register_led(sc, &sc->rx_led, trigger);
1091 sc->rx_led.led_type = ATH_LED_RX;
1092 if (ret)
1093 goto fail;
1094
1095 return;
1096
1097 fail:
1098 ath_deinit_leds(sc);
1099 }
1100
1101 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1102
1103 /*******************/
1104 /* Rfkill */
1105 /*******************/
1106
1107 static void ath_radio_enable(struct ath_softc *sc)
1108 {
1109 struct ath_hw *ah = sc->sc_ah;
1110 struct ieee80211_channel *channel = sc->hw->conf.channel;
1111 int r;
1112
1113 ath9k_ps_wakeup(sc);
1114 spin_lock_bh(&sc->sc_resetlock);
1115
1116 r = ath9k_hw_reset(ah, ah->curchan, false);
1117
1118 if (r) {
1119 DPRINTF(sc, ATH_DBG_FATAL,
1120 "Unable to reset channel %u (%uMhz) ",
1121 "reset status %u\n",
1122 channel->center_freq, r);
1123 }
1124 spin_unlock_bh(&sc->sc_resetlock);
1125
1126 ath_update_txpow(sc);
1127 if (ath_startrecv(sc) != 0) {
1128 DPRINTF(sc, ATH_DBG_FATAL,
1129 "Unable to restart recv logic\n");
1130 return;
1131 }
1132
1133 if (sc->sc_flags & SC_OP_BEACONS)
1134 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1135
1136 /* Re-Enable interrupts */
1137 ath9k_hw_set_interrupts(ah, sc->imask);
1138
1139 /* Enable LED */
1140 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1141 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1142 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1143
1144 ieee80211_wake_queues(sc->hw);
1145 ath9k_ps_restore(sc);
1146 }
1147
1148 static void ath_radio_disable(struct ath_softc *sc)
1149 {
1150 struct ath_hw *ah = sc->sc_ah;
1151 struct ieee80211_channel *channel = sc->hw->conf.channel;
1152 int r;
1153
1154 ath9k_ps_wakeup(sc);
1155 ieee80211_stop_queues(sc->hw);
1156
1157 /* Disable LED */
1158 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1159 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1160
1161 /* Disable interrupts */
1162 ath9k_hw_set_interrupts(ah, 0);
1163
1164 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1165 ath_stoprecv(sc); /* turn off frame recv */
1166 ath_flushrecv(sc); /* flush recv queue */
1167
1168 spin_lock_bh(&sc->sc_resetlock);
1169 r = ath9k_hw_reset(ah, ah->curchan, false);
1170 if (r) {
1171 DPRINTF(sc, ATH_DBG_FATAL,
1172 "Unable to reset channel %u (%uMhz) "
1173 "reset status %u\n",
1174 channel->center_freq, r);
1175 }
1176 spin_unlock_bh(&sc->sc_resetlock);
1177
1178 ath9k_hw_phy_disable(ah);
1179 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1180 ath9k_ps_restore(sc);
1181 }
1182
1183 static bool ath_is_rfkill_set(struct ath_softc *sc)
1184 {
1185 struct ath_hw *ah = sc->sc_ah;
1186
1187 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1188 ah->rfkill_polarity;
1189 }
1190
1191 /* h/w rfkill poll function */
1192 static void ath_rfkill_poll(struct work_struct *work)
1193 {
1194 struct ath_softc *sc = container_of(work, struct ath_softc,
1195 rf_kill.rfkill_poll.work);
1196 bool radio_on;
1197
1198 if (sc->sc_flags & SC_OP_INVALID)
1199 return;
1200
1201 radio_on = !ath_is_rfkill_set(sc);
1202
1203 /*
1204 * enable/disable radio only when there is a
1205 * state change in RF switch
1206 */
1207 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1208 enum rfkill_state state;
1209
1210 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1211 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1212 : RFKILL_STATE_HARD_BLOCKED;
1213 } else if (radio_on) {
1214 ath_radio_enable(sc);
1215 state = RFKILL_STATE_UNBLOCKED;
1216 } else {
1217 ath_radio_disable(sc);
1218 state = RFKILL_STATE_HARD_BLOCKED;
1219 }
1220
1221 if (state == RFKILL_STATE_HARD_BLOCKED)
1222 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1223 else
1224 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1225
1226 rfkill_force_state(sc->rf_kill.rfkill, state);
1227 }
1228
1229 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1230 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1231 }
1232
1233 /* s/w rfkill handler */
1234 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1235 {
1236 struct ath_softc *sc = data;
1237
1238 switch (state) {
1239 case RFKILL_STATE_SOFT_BLOCKED:
1240 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1241 SC_OP_RFKILL_SW_BLOCKED)))
1242 ath_radio_disable(sc);
1243 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1244 return 0;
1245 case RFKILL_STATE_UNBLOCKED:
1246 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1247 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1248 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1249 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1250 "radio as it is disabled by h/w\n");
1251 return -EPERM;
1252 }
1253 ath_radio_enable(sc);
1254 }
1255 return 0;
1256 default:
1257 return -EINVAL;
1258 }
1259 }
1260
1261 /* Init s/w rfkill */
1262 static int ath_init_sw_rfkill(struct ath_softc *sc)
1263 {
1264 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1265 RFKILL_TYPE_WLAN);
1266 if (!sc->rf_kill.rfkill) {
1267 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1268 return -ENOMEM;
1269 }
1270
1271 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1272 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1273 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1274 sc->rf_kill.rfkill->data = sc;
1275 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1276 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1277 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1278
1279 return 0;
1280 }
1281
1282 /* Deinitialize rfkill */
1283 static void ath_deinit_rfkill(struct ath_softc *sc)
1284 {
1285 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1286 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1287
1288 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1289 rfkill_unregister(sc->rf_kill.rfkill);
1290 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1291 sc->rf_kill.rfkill = NULL;
1292 }
1293 }
1294
1295 static int ath_start_rfkill_poll(struct ath_softc *sc)
1296 {
1297 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1298 queue_delayed_work(sc->hw->workqueue,
1299 &sc->rf_kill.rfkill_poll, 0);
1300
1301 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1302 if (rfkill_register(sc->rf_kill.rfkill)) {
1303 DPRINTF(sc, ATH_DBG_FATAL,
1304 "Unable to register rfkill\n");
1305 rfkill_free(sc->rf_kill.rfkill);
1306
1307 /* Deinitialize the device */
1308 ath_cleanup(sc);
1309 return -EIO;
1310 } else {
1311 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1312 }
1313 }
1314
1315 return 0;
1316 }
1317 #endif /* CONFIG_RFKILL */
1318
1319 void ath_cleanup(struct ath_softc *sc)
1320 {
1321 ath_detach(sc);
1322 free_irq(sc->irq, sc);
1323 ath_bus_cleanup(sc);
1324 ieee80211_free_hw(sc->hw);
1325 }
1326
1327 void ath_detach(struct ath_softc *sc)
1328 {
1329 struct ieee80211_hw *hw = sc->hw;
1330 int i = 0;
1331
1332 ath9k_ps_wakeup(sc);
1333
1334 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1335
1336 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1337 ath_deinit_rfkill(sc);
1338 #endif
1339 ath_deinit_leds(sc);
1340
1341 ieee80211_unregister_hw(hw);
1342 ath_rx_cleanup(sc);
1343 ath_tx_cleanup(sc);
1344
1345 tasklet_kill(&sc->intr_tq);
1346 tasklet_kill(&sc->bcon_tasklet);
1347
1348 if (!(sc->sc_flags & SC_OP_INVALID))
1349 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1350
1351 /* cleanup tx queues */
1352 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1353 if (ATH_TXQ_SETUP(sc, i))
1354 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1355
1356 ath9k_hw_detach(sc->sc_ah);
1357 ath9k_exit_debug(sc);
1358 ath9k_ps_restore(sc);
1359 }
1360
1361 static int ath_init(u16 devid, struct ath_softc *sc)
1362 {
1363 struct ath_hw *ah = NULL;
1364 int status;
1365 int error = 0, i;
1366 int csz = 0;
1367
1368 /* XXX: hardware will not be ready until ath_open() being called */
1369 sc->sc_flags |= SC_OP_INVALID;
1370
1371 if (ath9k_init_debug(sc) < 0)
1372 printk(KERN_ERR "Unable to create debugfs files\n");
1373
1374 spin_lock_init(&sc->sc_resetlock);
1375 mutex_init(&sc->mutex);
1376 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1377 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1378 (unsigned long)sc);
1379
1380 /*
1381 * Cache line size is used to size and align various
1382 * structures used to communicate with the hardware.
1383 */
1384 ath_read_cachesize(sc, &csz);
1385 /* XXX assert csz is non-zero */
1386 sc->cachelsz = csz << 2; /* convert to bytes */
1387
1388 ah = ath9k_hw_attach(devid, sc, &status);
1389 if (ah == NULL) {
1390 DPRINTF(sc, ATH_DBG_FATAL,
1391 "Unable to attach hardware; HAL status %d\n", status);
1392 error = -ENXIO;
1393 goto bad;
1394 }
1395 sc->sc_ah = ah;
1396
1397 /* Get the hardware key cache size. */
1398 sc->keymax = ah->caps.keycache_size;
1399 if (sc->keymax > ATH_KEYMAX) {
1400 DPRINTF(sc, ATH_DBG_KEYCACHE,
1401 "Warning, using only %u entries in %u key cache\n",
1402 ATH_KEYMAX, sc->keymax);
1403 sc->keymax = ATH_KEYMAX;
1404 }
1405
1406 /*
1407 * Reset the key cache since some parts do not
1408 * reset the contents on initial power up.
1409 */
1410 for (i = 0; i < sc->keymax; i++)
1411 ath9k_hw_keyreset(ah, (u16) i);
1412
1413 if (ath9k_regd_init(sc->sc_ah))
1414 goto bad;
1415
1416 /* default to MONITOR mode */
1417 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1418
1419 /* Setup rate tables */
1420
1421 ath_rate_attach(sc);
1422 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1423 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1424
1425 /*
1426 * Allocate hardware transmit queues: one queue for
1427 * beacon frames and one data queue for each QoS
1428 * priority. Note that the hal handles reseting
1429 * these queues at the needed time.
1430 */
1431 sc->beacon.beaconq = ath_beaconq_setup(ah);
1432 if (sc->beacon.beaconq == -1) {
1433 DPRINTF(sc, ATH_DBG_FATAL,
1434 "Unable to setup a beacon xmit queue\n");
1435 error = -EIO;
1436 goto bad2;
1437 }
1438 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1439 if (sc->beacon.cabq == NULL) {
1440 DPRINTF(sc, ATH_DBG_FATAL,
1441 "Unable to setup CAB xmit queue\n");
1442 error = -EIO;
1443 goto bad2;
1444 }
1445
1446 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1447 ath_cabq_update(sc);
1448
1449 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1450 sc->tx.hwq_map[i] = -1;
1451
1452 /* Setup data queues */
1453 /* NB: ensure BK queue is the lowest priority h/w queue */
1454 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1455 DPRINTF(sc, ATH_DBG_FATAL,
1456 "Unable to setup xmit queue for BK traffic\n");
1457 error = -EIO;
1458 goto bad2;
1459 }
1460
1461 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1462 DPRINTF(sc, ATH_DBG_FATAL,
1463 "Unable to setup xmit queue for BE traffic\n");
1464 error = -EIO;
1465 goto bad2;
1466 }
1467 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1468 DPRINTF(sc, ATH_DBG_FATAL,
1469 "Unable to setup xmit queue for VI traffic\n");
1470 error = -EIO;
1471 goto bad2;
1472 }
1473 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1474 DPRINTF(sc, ATH_DBG_FATAL,
1475 "Unable to setup xmit queue for VO traffic\n");
1476 error = -EIO;
1477 goto bad2;
1478 }
1479
1480 /* Initializes the noise floor to a reasonable default value.
1481 * Later on this will be updated during ANI processing. */
1482
1483 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1484 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1485
1486 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1487 ATH9K_CIPHER_TKIP, NULL)) {
1488 /*
1489 * Whether we should enable h/w TKIP MIC.
1490 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1491 * report WMM capable, so it's always safe to turn on
1492 * TKIP MIC in this case.
1493 */
1494 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1495 0, 1, NULL);
1496 }
1497
1498 /*
1499 * Check whether the separate key cache entries
1500 * are required to handle both tx+rx MIC keys.
1501 * With split mic keys the number of stations is limited
1502 * to 27 otherwise 59.
1503 */
1504 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1505 ATH9K_CIPHER_TKIP, NULL)
1506 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1507 ATH9K_CIPHER_MIC, NULL)
1508 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1509 0, NULL))
1510 sc->splitmic = 1;
1511
1512 /* turn on mcast key search if possible */
1513 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1514 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1515 1, NULL);
1516
1517 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1518
1519 /* 11n Capabilities */
1520 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1521 sc->sc_flags |= SC_OP_TXAGGR;
1522 sc->sc_flags |= SC_OP_RXAGGR;
1523 }
1524
1525 sc->tx_chainmask = ah->caps.tx_chainmask;
1526 sc->rx_chainmask = ah->caps.rx_chainmask;
1527
1528 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1529 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1530
1531 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1532 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1533 ATH_SET_VIF_BSSID_MASK(sc->bssidmask);
1534 ath9k_hw_setbssidmask(sc);
1535 }
1536
1537 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1538
1539 /* initialize beacon slots */
1540 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1541 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1542
1543 /* save MISC configurations */
1544 sc->config.swBeaconProcess = 1;
1545
1546 /* setup channels and rates */
1547
1548 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1549 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1550 sc->rates[IEEE80211_BAND_2GHZ];
1551 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1552 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1553 ARRAY_SIZE(ath9k_2ghz_chantable);
1554
1555 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1556 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1557 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1558 sc->rates[IEEE80211_BAND_5GHZ];
1559 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1560 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1561 ARRAY_SIZE(ath9k_5ghz_chantable);
1562 }
1563
1564 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1565 ath9k_hw_btcoex_enable(sc->sc_ah);
1566
1567 return 0;
1568 bad2:
1569 /* cleanup tx queues */
1570 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1571 if (ATH_TXQ_SETUP(sc, i))
1572 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1573 bad:
1574 if (ah)
1575 ath9k_hw_detach(ah);
1576 ath9k_exit_debug(sc);
1577
1578 return error;
1579 }
1580
1581 int ath_attach(u16 devid, struct ath_softc *sc)
1582 {
1583 struct ieee80211_hw *hw = sc->hw;
1584 const struct ieee80211_regdomain *regd;
1585 int error = 0, i;
1586
1587 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1588
1589 error = ath_init(devid, sc);
1590 if (error != 0)
1591 return error;
1592
1593 /* get mac address from hardware and set in mac80211 */
1594
1595 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1596
1597 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1598 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1599 IEEE80211_HW_SIGNAL_DBM |
1600 IEEE80211_HW_AMPDU_AGGREGATION |
1601 IEEE80211_HW_SUPPORTS_PS |
1602 IEEE80211_HW_PS_NULLFUNC_STACK;
1603
1604 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1605 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1606
1607 hw->wiphy->interface_modes =
1608 BIT(NL80211_IFTYPE_AP) |
1609 BIT(NL80211_IFTYPE_STATION) |
1610 BIT(NL80211_IFTYPE_ADHOC);
1611
1612 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1613 hw->wiphy->strict_regulatory = true;
1614
1615 hw->queues = 4;
1616 hw->max_rates = 4;
1617 hw->channel_change_time = 5000;
1618 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1619 hw->sta_data_size = sizeof(struct ath_node);
1620 hw->vif_data_size = sizeof(struct ath_vif);
1621
1622 hw->rate_control_algorithm = "ath9k_rate_control";
1623
1624 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1625 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1626 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1627 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1628 }
1629
1630 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1631 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1632 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1633 &sc->sbands[IEEE80211_BAND_5GHZ];
1634
1635 /* initialize tx/rx engine */
1636 error = ath_tx_init(sc, ATH_TXBUF);
1637 if (error != 0)
1638 goto error_attach;
1639
1640 error = ath_rx_init(sc, ATH_RXBUF);
1641 if (error != 0)
1642 goto error_attach;
1643
1644 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1645 /* Initialze h/w Rfkill */
1646 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1647 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1648
1649 /* Initialize s/w rfkill */
1650 error = ath_init_sw_rfkill(sc);
1651 if (error)
1652 goto error_attach;
1653 #endif
1654
1655 if (ath9k_is_world_regd(sc->sc_ah)) {
1656 /* Anything applied here (prior to wiphy registration) gets
1657 * saved on the wiphy orig_* parameters */
1658 regd = ath9k_world_regdomain(sc->sc_ah);
1659 hw->wiphy->custom_regulatory = true;
1660 hw->wiphy->strict_regulatory = false;
1661 } else {
1662 /* This gets applied in the case of the absense of CRDA,
1663 * it's our own custom world regulatory domain, similar to
1664 * cfg80211's but we enable passive scanning */
1665 regd = ath9k_default_world_regdomain();
1666 }
1667 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1668 ath9k_reg_apply_radar_flags(hw->wiphy);
1669 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1670
1671 error = ieee80211_register_hw(hw);
1672
1673 if (!ath9k_is_world_regd(sc->sc_ah)) {
1674 error = regulatory_hint(hw->wiphy,
1675 sc->sc_ah->regulatory.alpha2);
1676 if (error)
1677 goto error_attach;
1678 }
1679
1680 /* Initialize LED control */
1681 ath_init_leds(sc);
1682
1683
1684 return 0;
1685
1686 error_attach:
1687 /* cleanup tx queues */
1688 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1689 if (ATH_TXQ_SETUP(sc, i))
1690 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1691
1692 ath9k_hw_detach(sc->sc_ah);
1693 ath9k_exit_debug(sc);
1694
1695 return error;
1696 }
1697
1698 int ath_reset(struct ath_softc *sc, bool retry_tx)
1699 {
1700 struct ath_hw *ah = sc->sc_ah;
1701 struct ieee80211_hw *hw = sc->hw;
1702 int r;
1703
1704 ath9k_hw_set_interrupts(ah, 0);
1705 ath_drain_all_txq(sc, retry_tx);
1706 ath_stoprecv(sc);
1707 ath_flushrecv(sc);
1708
1709 spin_lock_bh(&sc->sc_resetlock);
1710 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1711 if (r)
1712 DPRINTF(sc, ATH_DBG_FATAL,
1713 "Unable to reset hardware; reset status %u\n", r);
1714 spin_unlock_bh(&sc->sc_resetlock);
1715
1716 if (ath_startrecv(sc) != 0)
1717 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1718
1719 /*
1720 * We may be doing a reset in response to a request
1721 * that changes the channel so update any state that
1722 * might change as a result.
1723 */
1724 ath_cache_conf_rate(sc, &hw->conf);
1725
1726 ath_update_txpow(sc);
1727
1728 if (sc->sc_flags & SC_OP_BEACONS)
1729 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1730
1731 ath9k_hw_set_interrupts(ah, sc->imask);
1732
1733 if (retry_tx) {
1734 int i;
1735 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1736 if (ATH_TXQ_SETUP(sc, i)) {
1737 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1738 ath_txq_schedule(sc, &sc->tx.txq[i]);
1739 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1740 }
1741 }
1742 }
1743
1744 return r;
1745 }
1746
1747 /*
1748 * This function will allocate both the DMA descriptor structure, and the
1749 * buffers it contains. These are used to contain the descriptors used
1750 * by the system.
1751 */
1752 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1753 struct list_head *head, const char *name,
1754 int nbuf, int ndesc)
1755 {
1756 #define DS2PHYS(_dd, _ds) \
1757 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1758 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1759 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1760
1761 struct ath_desc *ds;
1762 struct ath_buf *bf;
1763 int i, bsize, error;
1764
1765 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1766 name, nbuf, ndesc);
1767
1768 /* ath_desc must be a multiple of DWORDs */
1769 if ((sizeof(struct ath_desc) % 4) != 0) {
1770 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1771 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1772 error = -ENOMEM;
1773 goto fail;
1774 }
1775
1776 dd->dd_name = name;
1777 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1778
1779 /*
1780 * Need additional DMA memory because we can't use
1781 * descriptors that cross the 4K page boundary. Assume
1782 * one skipped descriptor per 4K page.
1783 */
1784 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1785 u32 ndesc_skipped =
1786 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1787 u32 dma_len;
1788
1789 while (ndesc_skipped) {
1790 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1791 dd->dd_desc_len += dma_len;
1792
1793 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1794 };
1795 }
1796
1797 /* allocate descriptors */
1798 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1799 &dd->dd_desc_paddr, GFP_ATOMIC);
1800 if (dd->dd_desc == NULL) {
1801 error = -ENOMEM;
1802 goto fail;
1803 }
1804 ds = dd->dd_desc;
1805 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1806 dd->dd_name, ds, (u32) dd->dd_desc_len,
1807 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1808
1809 /* allocate buffers */
1810 bsize = sizeof(struct ath_buf) * nbuf;
1811 bf = kmalloc(bsize, GFP_KERNEL);
1812 if (bf == NULL) {
1813 error = -ENOMEM;
1814 goto fail2;
1815 }
1816 memset(bf, 0, bsize);
1817 dd->dd_bufptr = bf;
1818
1819 INIT_LIST_HEAD(head);
1820 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1821 bf->bf_desc = ds;
1822 bf->bf_daddr = DS2PHYS(dd, ds);
1823
1824 if (!(sc->sc_ah->caps.hw_caps &
1825 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1826 /*
1827 * Skip descriptor addresses which can cause 4KB
1828 * boundary crossing (addr + length) with a 32 dword
1829 * descriptor fetch.
1830 */
1831 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1832 ASSERT((caddr_t) bf->bf_desc <
1833 ((caddr_t) dd->dd_desc +
1834 dd->dd_desc_len));
1835
1836 ds += ndesc;
1837 bf->bf_desc = ds;
1838 bf->bf_daddr = DS2PHYS(dd, ds);
1839 }
1840 }
1841 list_add_tail(&bf->list, head);
1842 }
1843 return 0;
1844 fail2:
1845 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1846 dd->dd_desc_paddr);
1847 fail:
1848 memset(dd, 0, sizeof(*dd));
1849 return error;
1850 #undef ATH_DESC_4KB_BOUND_CHECK
1851 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1852 #undef DS2PHYS
1853 }
1854
1855 void ath_descdma_cleanup(struct ath_softc *sc,
1856 struct ath_descdma *dd,
1857 struct list_head *head)
1858 {
1859 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1860 dd->dd_desc_paddr);
1861
1862 INIT_LIST_HEAD(head);
1863 kfree(dd->dd_bufptr);
1864 memset(dd, 0, sizeof(*dd));
1865 }
1866
1867 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1868 {
1869 int qnum;
1870
1871 switch (queue) {
1872 case 0:
1873 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1874 break;
1875 case 1:
1876 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1877 break;
1878 case 2:
1879 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1880 break;
1881 case 3:
1882 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1883 break;
1884 default:
1885 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1886 break;
1887 }
1888
1889 return qnum;
1890 }
1891
1892 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1893 {
1894 int qnum;
1895
1896 switch (queue) {
1897 case ATH9K_WME_AC_VO:
1898 qnum = 0;
1899 break;
1900 case ATH9K_WME_AC_VI:
1901 qnum = 1;
1902 break;
1903 case ATH9K_WME_AC_BE:
1904 qnum = 2;
1905 break;
1906 case ATH9K_WME_AC_BK:
1907 qnum = 3;
1908 break;
1909 default:
1910 qnum = -1;
1911 break;
1912 }
1913
1914 return qnum;
1915 }
1916
1917 /* XXX: Remove me once we don't depend on ath9k_channel for all
1918 * this redundant data */
1919 static void ath9k_update_ichannel(struct ath_softc *sc,
1920 struct ath9k_channel *ichan)
1921 {
1922 struct ieee80211_hw *hw = sc->hw;
1923 struct ieee80211_channel *chan = hw->conf.channel;
1924 struct ieee80211_conf *conf = &hw->conf;
1925
1926 ichan->channel = chan->center_freq;
1927 ichan->chan = chan;
1928
1929 if (chan->band == IEEE80211_BAND_2GHZ) {
1930 ichan->chanmode = CHANNEL_G;
1931 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1932 } else {
1933 ichan->chanmode = CHANNEL_A;
1934 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1935 }
1936
1937 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1938
1939 if (conf_is_ht(conf)) {
1940 if (conf_is_ht40(conf))
1941 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1942
1943 ichan->chanmode = ath_get_extchanmode(sc, chan,
1944 conf->channel_type);
1945 }
1946 }
1947
1948 /**********************/
1949 /* mac80211 callbacks */
1950 /**********************/
1951
1952 static int ath9k_start(struct ieee80211_hw *hw)
1953 {
1954 struct ath_softc *sc = hw->priv;
1955 struct ieee80211_channel *curchan = hw->conf.channel;
1956 struct ath9k_channel *init_channel;
1957 int r, pos;
1958
1959 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1960 "initial channel: %d MHz\n", curchan->center_freq);
1961
1962 mutex_lock(&sc->mutex);
1963
1964 /* setup initial channel */
1965
1966 pos = curchan->hw_value;
1967
1968 init_channel = &sc->sc_ah->channels[pos];
1969 ath9k_update_ichannel(sc, init_channel);
1970
1971 /* Reset SERDES registers */
1972 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1973
1974 /*
1975 * The basic interface to setting the hardware in a good
1976 * state is ``reset''. On return the hardware is known to
1977 * be powered up and with interrupts disabled. This must
1978 * be followed by initialization of the appropriate bits
1979 * and then setup of the interrupt mask.
1980 */
1981 spin_lock_bh(&sc->sc_resetlock);
1982 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1983 if (r) {
1984 DPRINTF(sc, ATH_DBG_FATAL,
1985 "Unable to reset hardware; reset status %u "
1986 "(freq %u MHz)\n", r,
1987 curchan->center_freq);
1988 spin_unlock_bh(&sc->sc_resetlock);
1989 goto mutex_unlock;
1990 }
1991 spin_unlock_bh(&sc->sc_resetlock);
1992
1993 /*
1994 * This is needed only to setup initial state
1995 * but it's best done after a reset.
1996 */
1997 ath_update_txpow(sc);
1998
1999 /*
2000 * Setup the hardware after reset:
2001 * The receive engine is set going.
2002 * Frame transmit is handled entirely
2003 * in the frame output path; there's nothing to do
2004 * here except setup the interrupt mask.
2005 */
2006 if (ath_startrecv(sc) != 0) {
2007 DPRINTF(sc, ATH_DBG_FATAL,
2008 "Unable to start recv logic\n");
2009 r = -EIO;
2010 goto mutex_unlock;
2011 }
2012
2013 /* Setup our intr mask. */
2014 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2015 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2016 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2017
2018 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2019 sc->imask |= ATH9K_INT_GTT;
2020
2021 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2022 sc->imask |= ATH9K_INT_CST;
2023
2024 ath_cache_conf_rate(sc, &hw->conf);
2025
2026 sc->sc_flags &= ~SC_OP_INVALID;
2027
2028 /* Disable BMISS interrupt when we're not associated */
2029 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2030 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2031
2032 ieee80211_wake_queues(sc->hw);
2033
2034 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2035 r = ath_start_rfkill_poll(sc);
2036 #endif
2037
2038 mutex_unlock:
2039 mutex_unlock(&sc->mutex);
2040
2041 return r;
2042 }
2043
2044 static int ath9k_tx(struct ieee80211_hw *hw,
2045 struct sk_buff *skb)
2046 {
2047 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2048 struct ath_softc *sc = hw->priv;
2049 struct ath_tx_control txctl;
2050 int hdrlen, padsize;
2051
2052 memset(&txctl, 0, sizeof(struct ath_tx_control));
2053
2054 /*
2055 * As a temporary workaround, assign seq# here; this will likely need
2056 * to be cleaned up to work better with Beacon transmission and virtual
2057 * BSSes.
2058 */
2059 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2060 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2061 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2062 sc->tx.seq_no += 0x10;
2063 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2064 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2065 }
2066
2067 /* Add the padding after the header if this is not already done */
2068 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2069 if (hdrlen & 3) {
2070 padsize = hdrlen % 4;
2071 if (skb_headroom(skb) < padsize)
2072 return -1;
2073 skb_push(skb, padsize);
2074 memmove(skb->data, skb->data + padsize, hdrlen);
2075 }
2076
2077 /* Check if a tx queue is available */
2078
2079 txctl.txq = ath_test_get_txq(sc, skb);
2080 if (!txctl.txq)
2081 goto exit;
2082
2083 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2084
2085 if (ath_tx_start(sc, skb, &txctl) != 0) {
2086 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2087 goto exit;
2088 }
2089
2090 return 0;
2091 exit:
2092 dev_kfree_skb_any(skb);
2093 return 0;
2094 }
2095
2096 static void ath9k_stop(struct ieee80211_hw *hw)
2097 {
2098 struct ath_softc *sc = hw->priv;
2099
2100 if (sc->sc_flags & SC_OP_INVALID) {
2101 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2102 return;
2103 }
2104
2105 mutex_lock(&sc->mutex);
2106
2107 ieee80211_stop_queues(sc->hw);
2108
2109 /* make sure h/w will not generate any interrupt
2110 * before setting the invalid flag. */
2111 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2112
2113 if (!(sc->sc_flags & SC_OP_INVALID)) {
2114 ath_drain_all_txq(sc, false);
2115 ath_stoprecv(sc);
2116 ath9k_hw_phy_disable(sc->sc_ah);
2117 } else
2118 sc->rx.rxlink = NULL;
2119
2120 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2121 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2122 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2123 #endif
2124 /* disable HAL and put h/w to sleep */
2125 ath9k_hw_disable(sc->sc_ah);
2126 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2127
2128 sc->sc_flags |= SC_OP_INVALID;
2129
2130 mutex_unlock(&sc->mutex);
2131
2132 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2133 }
2134
2135 static int ath9k_add_interface(struct ieee80211_hw *hw,
2136 struct ieee80211_if_init_conf *conf)
2137 {
2138 struct ath_softc *sc = hw->priv;
2139 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2140 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2141
2142 /* Support only vif for now */
2143
2144 if (sc->nvifs)
2145 return -ENOBUFS;
2146
2147 mutex_lock(&sc->mutex);
2148
2149 switch (conf->type) {
2150 case NL80211_IFTYPE_STATION:
2151 ic_opmode = NL80211_IFTYPE_STATION;
2152 break;
2153 case NL80211_IFTYPE_ADHOC:
2154 ic_opmode = NL80211_IFTYPE_ADHOC;
2155 break;
2156 case NL80211_IFTYPE_AP:
2157 ic_opmode = NL80211_IFTYPE_AP;
2158 break;
2159 default:
2160 DPRINTF(sc, ATH_DBG_FATAL,
2161 "Interface type %d not yet supported\n", conf->type);
2162 mutex_unlock(&sc->mutex);
2163 return -EOPNOTSUPP;
2164 }
2165
2166 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2167
2168 /* Set the VIF opmode */
2169 avp->av_opmode = ic_opmode;
2170 avp->av_bslot = -1;
2171
2172 if (ic_opmode == NL80211_IFTYPE_AP)
2173 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2174
2175 sc->vifs[0] = conf->vif;
2176 sc->nvifs++;
2177
2178 /* Set the device opmode */
2179 sc->sc_ah->opmode = ic_opmode;
2180
2181 /*
2182 * Enable MIB interrupts when there are hardware phy counters.
2183 * Note we only do this (at the moment) for station mode.
2184 */
2185 if ((conf->type == NL80211_IFTYPE_STATION) ||
2186 (conf->type == NL80211_IFTYPE_ADHOC)) {
2187 if (ath9k_hw_phycounters(sc->sc_ah))
2188 sc->imask |= ATH9K_INT_MIB;
2189 sc->imask |= ATH9K_INT_TSFOOR;
2190 }
2191
2192 /*
2193 * Some hardware processes the TIM IE and fires an
2194 * interrupt when the TIM bit is set. For hardware
2195 * that does, if not overridden by configuration,
2196 * enable the TIM interrupt when operating as station.
2197 */
2198 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2199 (conf->type == NL80211_IFTYPE_STATION) &&
2200 !sc->config.swBeaconProcess)
2201 sc->imask |= ATH9K_INT_TIM;
2202
2203 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2204
2205 if (conf->type == NL80211_IFTYPE_AP) {
2206 /* TODO: is this a suitable place to start ANI for AP mode? */
2207 /* Start ANI */
2208 mod_timer(&sc->ani.timer,
2209 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2210 }
2211
2212 mutex_unlock(&sc->mutex);
2213
2214 return 0;
2215 }
2216
2217 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2218 struct ieee80211_if_init_conf *conf)
2219 {
2220 struct ath_softc *sc = hw->priv;
2221 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2222
2223 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2224
2225 mutex_lock(&sc->mutex);
2226
2227 /* Stop ANI */
2228 del_timer_sync(&sc->ani.timer);
2229
2230 /* Reclaim beacon resources */
2231 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2232 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
2233 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2234 ath_beacon_return(sc, avp);
2235 }
2236
2237 sc->sc_flags &= ~SC_OP_BEACONS;
2238
2239 sc->vifs[0] = NULL;
2240 sc->nvifs--;
2241
2242 mutex_unlock(&sc->mutex);
2243 }
2244
2245 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2246 {
2247 struct ath_softc *sc = hw->priv;
2248 struct ieee80211_conf *conf = &hw->conf;
2249
2250 mutex_lock(&sc->mutex);
2251
2252 if (changed & IEEE80211_CONF_CHANGE_PS) {
2253 if (conf->flags & IEEE80211_CONF_PS) {
2254 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2255 sc->imask |= ATH9K_INT_TIM_TIMER;
2256 ath9k_hw_set_interrupts(sc->sc_ah,
2257 sc->imask);
2258 }
2259 ath9k_hw_setrxabort(sc->sc_ah, 1);
2260 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2261 } else {
2262 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2263 ath9k_hw_setrxabort(sc->sc_ah, 0);
2264 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2265 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2266 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2267 ath9k_hw_set_interrupts(sc->sc_ah,
2268 sc->imask);
2269 }
2270 }
2271 }
2272
2273 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2274 struct ieee80211_channel *curchan = hw->conf.channel;
2275 int pos = curchan->hw_value;
2276
2277 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2278 curchan->center_freq);
2279
2280 /* XXX: remove me eventualy */
2281 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
2282
2283 ath_update_chainmask(sc, conf_is_ht(conf));
2284
2285 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
2286 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2287 mutex_unlock(&sc->mutex);
2288 return -EINVAL;
2289 }
2290 }
2291
2292 if (changed & IEEE80211_CONF_CHANGE_POWER)
2293 sc->config.txpowlimit = 2 * conf->power_level;
2294
2295 mutex_unlock(&sc->mutex);
2296
2297 return 0;
2298 }
2299
2300 static int ath9k_config_interface(struct ieee80211_hw *hw,
2301 struct ieee80211_vif *vif,
2302 struct ieee80211_if_conf *conf)
2303 {
2304 struct ath_softc *sc = hw->priv;
2305 struct ath_hw *ah = sc->sc_ah;
2306 struct ath_vif *avp = (void *)vif->drv_priv;
2307 u32 rfilt = 0;
2308 int error, i;
2309
2310 /* TODO: Need to decide which hw opmode to use for multi-interface
2311 * cases */
2312 if (vif->type == NL80211_IFTYPE_AP &&
2313 ah->opmode != NL80211_IFTYPE_AP) {
2314 ah->opmode = NL80211_IFTYPE_STATION;
2315 ath9k_hw_setopmode(ah);
2316 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2317 sc->curaid = 0;
2318 ath9k_hw_write_associd(sc);
2319 /* Request full reset to get hw opmode changed properly */
2320 sc->sc_flags |= SC_OP_FULL_RESET;
2321 }
2322
2323 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2324 !is_zero_ether_addr(conf->bssid)) {
2325 switch (vif->type) {
2326 case NL80211_IFTYPE_STATION:
2327 case NL80211_IFTYPE_ADHOC:
2328 /* Set BSSID */
2329 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2330 sc->curaid = 0;
2331 ath9k_hw_write_associd(sc);
2332
2333 /* Set aggregation protection mode parameters */
2334 sc->config.ath_aggr_prot = 0;
2335
2336 DPRINTF(sc, ATH_DBG_CONFIG,
2337 "RX filter 0x%x bssid %pM aid 0x%x\n",
2338 rfilt, sc->curbssid, sc->curaid);
2339
2340 /* need to reconfigure the beacon */
2341 sc->sc_flags &= ~SC_OP_BEACONS ;
2342
2343 break;
2344 default:
2345 break;
2346 }
2347 }
2348
2349 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2350 (vif->type == NL80211_IFTYPE_AP)) {
2351 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2352 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2353 conf->enable_beacon)) {
2354 /*
2355 * Allocate and setup the beacon frame.
2356 *
2357 * Stop any previous beacon DMA. This may be
2358 * necessary, for example, when an ibss merge
2359 * causes reconfiguration; we may be called
2360 * with beacon transmission active.
2361 */
2362 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2363
2364 error = ath_beacon_alloc(sc, 0);
2365 if (error != 0)
2366 return error;
2367
2368 ath_beacon_sync(sc, 0);
2369 }
2370 }
2371
2372 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2373 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2374 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2375 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2376 ath9k_hw_keysetmac(sc->sc_ah,
2377 (u16)i,
2378 sc->curbssid);
2379 }
2380
2381 /* Only legacy IBSS for now */
2382 if (vif->type == NL80211_IFTYPE_ADHOC)
2383 ath_update_chainmask(sc, 0);
2384
2385 return 0;
2386 }
2387
2388 #define SUPPORTED_FILTERS \
2389 (FIF_PROMISC_IN_BSS | \
2390 FIF_ALLMULTI | \
2391 FIF_CONTROL | \
2392 FIF_OTHER_BSS | \
2393 FIF_BCN_PRBRESP_PROMISC | \
2394 FIF_FCSFAIL)
2395
2396 /* FIXME: sc->sc_full_reset ? */
2397 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2398 unsigned int changed_flags,
2399 unsigned int *total_flags,
2400 int mc_count,
2401 struct dev_mc_list *mclist)
2402 {
2403 struct ath_softc *sc = hw->priv;
2404 u32 rfilt;
2405
2406 changed_flags &= SUPPORTED_FILTERS;
2407 *total_flags &= SUPPORTED_FILTERS;
2408
2409 sc->rx.rxfilter = *total_flags;
2410 rfilt = ath_calcrxfilter(sc);
2411 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2412
2413 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2414 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2415 memcpy(sc->curbssid, ath_bcast_mac, ETH_ALEN);
2416 sc->curaid = 0;
2417 ath9k_hw_write_associd(sc);
2418 }
2419 }
2420
2421 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2422 }
2423
2424 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2425 struct ieee80211_vif *vif,
2426 enum sta_notify_cmd cmd,
2427 struct ieee80211_sta *sta)
2428 {
2429 struct ath_softc *sc = hw->priv;
2430
2431 switch (cmd) {
2432 case STA_NOTIFY_ADD:
2433 ath_node_attach(sc, sta);
2434 break;
2435 case STA_NOTIFY_REMOVE:
2436 ath_node_detach(sc, sta);
2437 break;
2438 default:
2439 break;
2440 }
2441 }
2442
2443 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2444 const struct ieee80211_tx_queue_params *params)
2445 {
2446 struct ath_softc *sc = hw->priv;
2447 struct ath9k_tx_queue_info qi;
2448 int ret = 0, qnum;
2449
2450 if (queue >= WME_NUM_AC)
2451 return 0;
2452
2453 mutex_lock(&sc->mutex);
2454
2455 qi.tqi_aifs = params->aifs;
2456 qi.tqi_cwmin = params->cw_min;
2457 qi.tqi_cwmax = params->cw_max;
2458 qi.tqi_burstTime = params->txop;
2459 qnum = ath_get_hal_qnum(queue, sc);
2460
2461 DPRINTF(sc, ATH_DBG_CONFIG,
2462 "Configure tx [queue/halq] [%d/%d], "
2463 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2464 queue, qnum, params->aifs, params->cw_min,
2465 params->cw_max, params->txop);
2466
2467 ret = ath_txq_update(sc, qnum, &qi);
2468 if (ret)
2469 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2470
2471 mutex_unlock(&sc->mutex);
2472
2473 return ret;
2474 }
2475
2476 static int ath9k_set_key(struct ieee80211_hw *hw,
2477 enum set_key_cmd cmd,
2478 struct ieee80211_vif *vif,
2479 struct ieee80211_sta *sta,
2480 struct ieee80211_key_conf *key)
2481 {
2482 struct ath_softc *sc = hw->priv;
2483 int ret = 0;
2484
2485 if (modparam_nohwcrypt)
2486 return -ENOSPC;
2487
2488 mutex_lock(&sc->mutex);
2489 ath9k_ps_wakeup(sc);
2490 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2491
2492 switch (cmd) {
2493 case SET_KEY:
2494 ret = ath_key_config(sc, vif, sta, key);
2495 if (ret >= 0) {
2496 key->hw_key_idx = ret;
2497 /* push IV and Michael MIC generation to stack */
2498 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2499 if (key->alg == ALG_TKIP)
2500 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2501 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2502 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2503 ret = 0;
2504 }
2505 break;
2506 case DISABLE_KEY:
2507 ath_key_delete(sc, key);
2508 break;
2509 default:
2510 ret = -EINVAL;
2511 }
2512
2513 ath9k_ps_restore(sc);
2514 mutex_unlock(&sc->mutex);
2515
2516 return ret;
2517 }
2518
2519 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2520 struct ieee80211_vif *vif,
2521 struct ieee80211_bss_conf *bss_conf,
2522 u32 changed)
2523 {
2524 struct ath_softc *sc = hw->priv;
2525
2526 mutex_lock(&sc->mutex);
2527
2528 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2529 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2530 bss_conf->use_short_preamble);
2531 if (bss_conf->use_short_preamble)
2532 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2533 else
2534 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2535 }
2536
2537 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2538 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2539 bss_conf->use_cts_prot);
2540 if (bss_conf->use_cts_prot &&
2541 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2542 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2543 else
2544 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2545 }
2546
2547 if (changed & BSS_CHANGED_ASSOC) {
2548 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2549 bss_conf->assoc);
2550 ath9k_bss_assoc_info(sc, vif, bss_conf);
2551 }
2552
2553 mutex_unlock(&sc->mutex);
2554 }
2555
2556 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2557 {
2558 u64 tsf;
2559 struct ath_softc *sc = hw->priv;
2560
2561 mutex_lock(&sc->mutex);
2562 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2563 mutex_unlock(&sc->mutex);
2564
2565 return tsf;
2566 }
2567
2568 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2569 {
2570 struct ath_softc *sc = hw->priv;
2571
2572 mutex_lock(&sc->mutex);
2573 ath9k_hw_settsf64(sc->sc_ah, tsf);
2574 mutex_unlock(&sc->mutex);
2575 }
2576
2577 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2578 {
2579 struct ath_softc *sc = hw->priv;
2580
2581 mutex_lock(&sc->mutex);
2582 ath9k_hw_reset_tsf(sc->sc_ah);
2583 mutex_unlock(&sc->mutex);
2584 }
2585
2586 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2587 enum ieee80211_ampdu_mlme_action action,
2588 struct ieee80211_sta *sta,
2589 u16 tid, u16 *ssn)
2590 {
2591 struct ath_softc *sc = hw->priv;
2592 int ret = 0;
2593
2594 switch (action) {
2595 case IEEE80211_AMPDU_RX_START:
2596 if (!(sc->sc_flags & SC_OP_RXAGGR))
2597 ret = -ENOTSUPP;
2598 break;
2599 case IEEE80211_AMPDU_RX_STOP:
2600 break;
2601 case IEEE80211_AMPDU_TX_START:
2602 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2603 if (ret < 0)
2604 DPRINTF(sc, ATH_DBG_FATAL,
2605 "Unable to start TX aggregation\n");
2606 else
2607 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2608 break;
2609 case IEEE80211_AMPDU_TX_STOP:
2610 ret = ath_tx_aggr_stop(sc, sta, tid);
2611 if (ret < 0)
2612 DPRINTF(sc, ATH_DBG_FATAL,
2613 "Unable to stop TX aggregation\n");
2614
2615 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2616 break;
2617 case IEEE80211_AMPDU_TX_RESUME:
2618 ath_tx_aggr_resume(sc, sta, tid);
2619 break;
2620 default:
2621 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2622 }
2623
2624 return ret;
2625 }
2626
2627 struct ieee80211_ops ath9k_ops = {
2628 .tx = ath9k_tx,
2629 .start = ath9k_start,
2630 .stop = ath9k_stop,
2631 .add_interface = ath9k_add_interface,
2632 .remove_interface = ath9k_remove_interface,
2633 .config = ath9k_config,
2634 .config_interface = ath9k_config_interface,
2635 .configure_filter = ath9k_configure_filter,
2636 .sta_notify = ath9k_sta_notify,
2637 .conf_tx = ath9k_conf_tx,
2638 .bss_info_changed = ath9k_bss_info_changed,
2639 .set_key = ath9k_set_key,
2640 .get_tsf = ath9k_get_tsf,
2641 .set_tsf = ath9k_set_tsf,
2642 .reset_tsf = ath9k_reset_tsf,
2643 .ampdu_action = ath9k_ampdu_action,
2644 };
2645
2646 static struct {
2647 u32 version;
2648 const char * name;
2649 } ath_mac_bb_names[] = {
2650 { AR_SREV_VERSION_5416_PCI, "5416" },
2651 { AR_SREV_VERSION_5416_PCIE, "5418" },
2652 { AR_SREV_VERSION_9100, "9100" },
2653 { AR_SREV_VERSION_9160, "9160" },
2654 { AR_SREV_VERSION_9280, "9280" },
2655 { AR_SREV_VERSION_9285, "9285" }
2656 };
2657
2658 static struct {
2659 u16 version;
2660 const char * name;
2661 } ath_rf_names[] = {
2662 { 0, "5133" },
2663 { AR_RAD5133_SREV_MAJOR, "5133" },
2664 { AR_RAD5122_SREV_MAJOR, "5122" },
2665 { AR_RAD2133_SREV_MAJOR, "2133" },
2666 { AR_RAD2122_SREV_MAJOR, "2122" }
2667 };
2668
2669 /*
2670 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2671 */
2672 const char *
2673 ath_mac_bb_name(u32 mac_bb_version)
2674 {
2675 int i;
2676
2677 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2678 if (ath_mac_bb_names[i].version == mac_bb_version) {
2679 return ath_mac_bb_names[i].name;
2680 }
2681 }
2682
2683 return "????";
2684 }
2685
2686 /*
2687 * Return the RF name. "????" is returned if the RF is unknown.
2688 */
2689 const char *
2690 ath_rf_name(u16 rf_version)
2691 {
2692 int i;
2693
2694 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2695 if (ath_rf_names[i].version == rf_version) {
2696 return ath_rf_names[i].name;
2697 }
2698 }
2699
2700 return "????";
2701 }
2702
2703 static int __init ath9k_init(void)
2704 {
2705 int error;
2706
2707 /* Register rate control algorithm */
2708 error = ath_rate_control_register();
2709 if (error != 0) {
2710 printk(KERN_ERR
2711 "ath9k: Unable to register rate control "
2712 "algorithm: %d\n",
2713 error);
2714 goto err_out;
2715 }
2716
2717 error = ath_pci_init();
2718 if (error < 0) {
2719 printk(KERN_ERR
2720 "ath9k: No PCI devices found, driver not installed.\n");
2721 error = -ENODEV;
2722 goto err_rate_unregister;
2723 }
2724
2725 error = ath_ahb_init();
2726 if (error < 0) {
2727 error = -ENODEV;
2728 goto err_pci_exit;
2729 }
2730
2731 return 0;
2732
2733 err_pci_exit:
2734 ath_pci_exit();
2735
2736 err_rate_unregister:
2737 ath_rate_control_unregister();
2738 err_out:
2739 return error;
2740 }
2741 module_init(ath9k_init);
2742
2743 static void __exit ath9k_exit(void)
2744 {
2745 ath_ahb_exit();
2746 ath_pci_exit();
2747 ath_rate_control_unregister();
2748 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2749 }
2750 module_exit(ath9k_exit);
Linux kernel - Deliverables
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