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ath9k: simplify regulatory code
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "core.h"
19 #include "reg.h"
20 #include "hw.h"
21
22 #define ATH_PCI_VERSION "0.1"
23
24 static char *dev_info = "ath9k";
25
26 MODULE_AUTHOR("Atheros Communications");
27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29 MODULE_LICENSE("Dual BSD/GPL");
30
31 /* We use the hw_value as an index into our private channel structure */
32
33 #define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
36 .max_power = 30, \
37 }
38
39 #define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
43 .max_power = 30, \
44 }
45
46 /* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65 };
66
67 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100 };
101
102 static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
104 {
105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
116 else
117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
133 break;
134 default:
135 BUG_ON(1);
136 break;
137 }
138 }
139
140 static void ath_update_txpow(struct ath_softc *sc)
141 {
142 struct ath_hal *ah = sc->sc_ah;
143 u32 txpow;
144
145 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
149 sc->sc_curtxpow = txpow;
150 }
151 }
152
153 static u8 parse_mpdudensity(u8 mpdudensity)
154 {
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186 }
187
188 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189 {
190 struct ath_rate_table *rate_table = NULL;
191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
220 sband->n_bitrates++;
221 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
222 rate[i].bitrate / 10, rate[i].hw_value);
223 }
224 }
225
226 /*
227 * Set/change channels. If the channel is really being changed, it's done
228 * by reseting the chip. To accomplish this we must first cleanup any pending
229 * DMA, then restart stuff.
230 */
231 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
232 {
233 struct ath_hal *ah = sc->sc_ah;
234 bool fastcc = true, stopped;
235 struct ieee80211_hw *hw = sc->hw;
236 struct ieee80211_channel *channel = hw->conf.channel;
237 int r;
238
239 if (sc->sc_flags & SC_OP_INVALID)
240 return -EIO;
241
242 ath9k_ps_wakeup(sc);
243
244 /*
245 * This is only performed if the channel settings have
246 * actually changed.
247 *
248 * To switch channels clear any pending DMA operations;
249 * wait long enough for the RX fifo to drain, reset the
250 * hardware at the new frequency, and then re-enable
251 * the relevant bits of the h/w.
252 */
253 ath9k_hw_set_interrupts(ah, 0);
254 ath_drain_all_txq(sc, false);
255 stopped = ath_stoprecv(sc);
256
257 /* XXX: do not flush receive queue here. We don't want
258 * to flush data frames already in queue because of
259 * changing channel. */
260
261 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
262 fastcc = false;
263
264 DPRINTF(sc, ATH_DBG_CONFIG,
265 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
266 sc->sc_ah->ah_curchan->channel,
267 channel->center_freq, sc->tx_chan_width);
268
269 spin_lock_bh(&sc->sc_resetlock);
270
271 r = ath9k_hw_reset(ah, hchan, fastcc);
272 if (r) {
273 DPRINTF(sc, ATH_DBG_FATAL,
274 "Unable to reset channel (%u Mhz) "
275 "reset status %u\n",
276 channel->center_freq, r);
277 spin_unlock_bh(&sc->sc_resetlock);
278 return r;
279 }
280 spin_unlock_bh(&sc->sc_resetlock);
281
282 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
283 sc->sc_flags &= ~SC_OP_FULL_RESET;
284
285 if (ath_startrecv(sc) != 0) {
286 DPRINTF(sc, ATH_DBG_FATAL,
287 "Unable to restart recv logic\n");
288 return -EIO;
289 }
290
291 ath_cache_conf_rate(sc, &hw->conf);
292 ath_update_txpow(sc);
293 ath9k_hw_set_interrupts(ah, sc->sc_imask);
294 ath9k_ps_restore(sc);
295 return 0;
296 }
297
298 /*
299 * This routine performs the periodic noise floor calibration function
300 * that is used to adjust and optimize the chip performance. This
301 * takes environmental changes (location, temperature) into account.
302 * When the task is complete, it reschedules itself depending on the
303 * appropriate interval that was calculated.
304 */
305 static void ath_ani_calibrate(unsigned long data)
306 {
307 struct ath_softc *sc;
308 struct ath_hal *ah;
309 bool longcal = false;
310 bool shortcal = false;
311 bool aniflag = false;
312 unsigned int timestamp = jiffies_to_msecs(jiffies);
313 u32 cal_interval;
314
315 sc = (struct ath_softc *)data;
316 ah = sc->sc_ah;
317
318 /*
319 * don't calibrate when we're scanning.
320 * we are most likely not on our home channel.
321 */
322 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
323 return;
324
325 /* Long calibration runs independently of short calibration. */
326 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
327 longcal = true;
328 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
329 sc->sc_ani.sc_longcal_timer = timestamp;
330 }
331
332 /* Short calibration applies only while sc_caldone is false */
333 if (!sc->sc_ani.sc_caldone) {
334 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
335 ATH_SHORT_CALINTERVAL) {
336 shortcal = true;
337 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
338 sc->sc_ani.sc_shortcal_timer = timestamp;
339 sc->sc_ani.sc_resetcal_timer = timestamp;
340 }
341 } else {
342 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
343 ATH_RESTART_CALINTERVAL) {
344 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
345 if (sc->sc_ani.sc_caldone)
346 sc->sc_ani.sc_resetcal_timer = timestamp;
347 }
348 }
349
350 /* Verify whether we must check ANI */
351 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
352 ATH_ANI_POLLINTERVAL) {
353 aniflag = true;
354 sc->sc_ani.sc_checkani_timer = timestamp;
355 }
356
357 /* Skip all processing if there's nothing to do. */
358 if (longcal || shortcal || aniflag) {
359 /* Call ANI routine if necessary */
360 if (aniflag)
361 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
362 ah->ah_curchan);
363
364 /* Perform calibration if necessary */
365 if (longcal || shortcal) {
366 bool iscaldone = false;
367
368 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
369 sc->sc_rx_chainmask, longcal,
370 &iscaldone)) {
371 if (longcal)
372 sc->sc_ani.sc_noise_floor =
373 ath9k_hw_getchan_noise(ah,
374 ah->ah_curchan);
375
376 DPRINTF(sc, ATH_DBG_ANI,
377 "calibrate chan %u/%x nf: %d\n",
378 ah->ah_curchan->channel,
379 ah->ah_curchan->channelFlags,
380 sc->sc_ani.sc_noise_floor);
381 } else {
382 DPRINTF(sc, ATH_DBG_ANY,
383 "calibrate chan %u/%x failed\n",
384 ah->ah_curchan->channel,
385 ah->ah_curchan->channelFlags);
386 }
387 sc->sc_ani.sc_caldone = iscaldone;
388 }
389 }
390
391 /*
392 * Set timer interval based on previous results.
393 * The interval must be the shortest necessary to satisfy ANI,
394 * short calibration and long calibration.
395 */
396 cal_interval = ATH_LONG_CALINTERVAL;
397 if (sc->sc_ah->ah_config.enable_ani)
398 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
399 if (!sc->sc_ani.sc_caldone)
400 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
401
402 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
403 }
404
405 /*
406 * Update tx/rx chainmask. For legacy association,
407 * hard code chainmask to 1x1, for 11n association, use
408 * the chainmask configuration, for bt coexistence, use
409 * the chainmask configuration even in legacy mode.
410 */
411 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
412 {
413 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
414 if (is_ht ||
415 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
416 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
417 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
418 } else {
419 sc->sc_tx_chainmask = 1;
420 sc->sc_rx_chainmask = 1;
421 }
422
423 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
424 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
425 }
426
427 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
428 {
429 struct ath_node *an;
430
431 an = (struct ath_node *)sta->drv_priv;
432
433 if (sc->sc_flags & SC_OP_TXAGGR)
434 ath_tx_node_init(sc, an);
435
436 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
437 sta->ht_cap.ampdu_factor);
438 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
439 }
440
441 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
442 {
443 struct ath_node *an = (struct ath_node *)sta->drv_priv;
444
445 if (sc->sc_flags & SC_OP_TXAGGR)
446 ath_tx_node_cleanup(sc, an);
447 }
448
449 static void ath9k_tasklet(unsigned long data)
450 {
451 struct ath_softc *sc = (struct ath_softc *)data;
452 u32 status = sc->sc_intrstatus;
453
454 if (status & ATH9K_INT_FATAL) {
455 /* need a chip reset */
456 ath_reset(sc, false);
457 return;
458 } else {
459
460 if (status &
461 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
462 spin_lock_bh(&sc->rx.rxflushlock);
463 ath_rx_tasklet(sc, 0);
464 spin_unlock_bh(&sc->rx.rxflushlock);
465 }
466 /* XXX: optimize this */
467 if (status & ATH9K_INT_TX)
468 ath_tx_tasklet(sc);
469 }
470
471 /* re-enable hardware interrupt */
472 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
473 }
474
475 irqreturn_t ath_isr(int irq, void *dev)
476 {
477 struct ath_softc *sc = dev;
478 struct ath_hal *ah = sc->sc_ah;
479 enum ath9k_int status;
480 bool sched = false;
481
482 do {
483 if (sc->sc_flags & SC_OP_INVALID) {
484 /*
485 * The hardware is not ready/present, don't
486 * touch anything. Note this can happen early
487 * on if the IRQ is shared.
488 */
489 return IRQ_NONE;
490 }
491 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
492 return IRQ_NONE;
493 }
494
495 /*
496 * Figure out the reason(s) for the interrupt. Note
497 * that the hal returns a pseudo-ISR that may include
498 * bits we haven't explicitly enabled so we mask the
499 * value to insure we only process bits we requested.
500 */
501 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
502
503 status &= sc->sc_imask; /* discard unasked-for bits */
504
505 /*
506 * If there are no status bits set, then this interrupt was not
507 * for me (should have been caught above).
508 */
509 if (!status)
510 return IRQ_NONE;
511
512 sc->sc_intrstatus = status;
513
514 if (status & ATH9K_INT_FATAL) {
515 /* need a chip reset */
516 sched = true;
517 } else if (status & ATH9K_INT_RXORN) {
518 /* need a chip reset */
519 sched = true;
520 } else {
521 if (status & ATH9K_INT_SWBA) {
522 /* schedule a tasklet for beacon handling */
523 tasklet_schedule(&sc->bcon_tasklet);
524 }
525 if (status & ATH9K_INT_RXEOL) {
526 /*
527 * NB: the hardware should re-read the link when
528 * RXE bit is written, but it doesn't work
529 * at least on older hardware revs.
530 */
531 sched = true;
532 }
533
534 if (status & ATH9K_INT_TXURN)
535 /* bump tx trigger level */
536 ath9k_hw_updatetxtriglevel(ah, true);
537 /* XXX: optimize this */
538 if (status & ATH9K_INT_RX)
539 sched = true;
540 if (status & ATH9K_INT_TX)
541 sched = true;
542 if (status & ATH9K_INT_BMISS)
543 sched = true;
544 /* carrier sense timeout */
545 if (status & ATH9K_INT_CST)
546 sched = true;
547 if (status & ATH9K_INT_MIB) {
548 /*
549 * Disable interrupts until we service the MIB
550 * interrupt; otherwise it will continue to
551 * fire.
552 */
553 ath9k_hw_set_interrupts(ah, 0);
554 /*
555 * Let the hal handle the event. We assume
556 * it will clear whatever condition caused
557 * the interrupt.
558 */
559 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
560 ath9k_hw_set_interrupts(ah, sc->sc_imask);
561 }
562 if (status & ATH9K_INT_TIM_TIMER) {
563 if (!(ah->ah_caps.hw_caps &
564 ATH9K_HW_CAP_AUTOSLEEP)) {
565 /* Clear RxAbort bit so that we can
566 * receive frames */
567 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
568 ath9k_hw_setrxabort(ah, 0);
569 sched = true;
570 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
571 }
572 }
573 }
574 } while (0);
575
576 ath_debug_stat_interrupt(sc, status);
577
578 if (sched) {
579 /* turn off every interrupt except SWBA */
580 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
581 tasklet_schedule(&sc->intr_tq);
582 }
583
584 return IRQ_HANDLED;
585 }
586
587 static u32 ath_get_extchanmode(struct ath_softc *sc,
588 struct ieee80211_channel *chan,
589 enum nl80211_channel_type channel_type)
590 {
591 u32 chanmode = 0;
592
593 switch (chan->band) {
594 case IEEE80211_BAND_2GHZ:
595 switch(channel_type) {
596 case NL80211_CHAN_NO_HT:
597 case NL80211_CHAN_HT20:
598 chanmode = CHANNEL_G_HT20;
599 break;
600 case NL80211_CHAN_HT40PLUS:
601 chanmode = CHANNEL_G_HT40PLUS;
602 break;
603 case NL80211_CHAN_HT40MINUS:
604 chanmode = CHANNEL_G_HT40MINUS;
605 break;
606 }
607 break;
608 case IEEE80211_BAND_5GHZ:
609 switch(channel_type) {
610 case NL80211_CHAN_NO_HT:
611 case NL80211_CHAN_HT20:
612 chanmode = CHANNEL_A_HT20;
613 break;
614 case NL80211_CHAN_HT40PLUS:
615 chanmode = CHANNEL_A_HT40PLUS;
616 break;
617 case NL80211_CHAN_HT40MINUS:
618 chanmode = CHANNEL_A_HT40MINUS;
619 break;
620 }
621 break;
622 default:
623 break;
624 }
625
626 return chanmode;
627 }
628
629 static int ath_keyset(struct ath_softc *sc, u16 keyix,
630 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
631 {
632 bool status;
633
634 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
635 keyix, hk, mac, false);
636
637 return status != false;
638 }
639
640 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
641 struct ath9k_keyval *hk,
642 const u8 *addr)
643 {
644 const u8 *key_rxmic;
645 const u8 *key_txmic;
646
647 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
648 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
649
650 if (addr == NULL) {
651 /* Group key installation */
652 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
653 return ath_keyset(sc, keyix, hk, addr);
654 }
655 if (!sc->sc_splitmic) {
656 /*
657 * data key goes at first index,
658 * the hal handles the MIC keys at index+64.
659 */
660 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
661 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
662 return ath_keyset(sc, keyix, hk, addr);
663 }
664 /*
665 * TX key goes at first index, RX key at +32.
666 * The hal handles the MIC keys at index+64.
667 */
668 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
669 if (!ath_keyset(sc, keyix, hk, NULL)) {
670 /* Txmic entry failed. No need to proceed further */
671 DPRINTF(sc, ATH_DBG_KEYCACHE,
672 "Setting TX MIC Key Failed\n");
673 return 0;
674 }
675
676 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
677 /* XXX delete tx key on failure? */
678 return ath_keyset(sc, keyix + 32, hk, addr);
679 }
680
681 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
682 {
683 int i;
684
685 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
686 if (test_bit(i, sc->sc_keymap) ||
687 test_bit(i + 64, sc->sc_keymap))
688 continue; /* At least one part of TKIP key allocated */
689 if (sc->sc_splitmic &&
690 (test_bit(i + 32, sc->sc_keymap) ||
691 test_bit(i + 64 + 32, sc->sc_keymap)))
692 continue; /* At least one part of TKIP key allocated */
693
694 /* Found a free slot for a TKIP key */
695 return i;
696 }
697 return -1;
698 }
699
700 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
701 {
702 int i;
703
704 /* First, try to find slots that would not be available for TKIP. */
705 if (sc->sc_splitmic) {
706 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
707 if (!test_bit(i, sc->sc_keymap) &&
708 (test_bit(i + 32, sc->sc_keymap) ||
709 test_bit(i + 64, sc->sc_keymap) ||
710 test_bit(i + 64 + 32, sc->sc_keymap)))
711 return i;
712 if (!test_bit(i + 32, sc->sc_keymap) &&
713 (test_bit(i, sc->sc_keymap) ||
714 test_bit(i + 64, sc->sc_keymap) ||
715 test_bit(i + 64 + 32, sc->sc_keymap)))
716 return i + 32;
717 if (!test_bit(i + 64, sc->sc_keymap) &&
718 (test_bit(i , sc->sc_keymap) ||
719 test_bit(i + 32, sc->sc_keymap) ||
720 test_bit(i + 64 + 32, sc->sc_keymap)))
721 return i + 64;
722 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
723 (test_bit(i, sc->sc_keymap) ||
724 test_bit(i + 32, sc->sc_keymap) ||
725 test_bit(i + 64, sc->sc_keymap)))
726 return i + 64 + 32;
727 }
728 } else {
729 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
730 if (!test_bit(i, sc->sc_keymap) &&
731 test_bit(i + 64, sc->sc_keymap))
732 return i;
733 if (test_bit(i, sc->sc_keymap) &&
734 !test_bit(i + 64, sc->sc_keymap))
735 return i + 64;
736 }
737 }
738
739 /* No partially used TKIP slots, pick any available slot */
740 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
741 /* Do not allow slots that could be needed for TKIP group keys
742 * to be used. This limitation could be removed if we know that
743 * TKIP will not be used. */
744 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
745 continue;
746 if (sc->sc_splitmic) {
747 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
748 continue;
749 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
750 continue;
751 }
752
753 if (!test_bit(i, sc->sc_keymap))
754 return i; /* Found a free slot for a key */
755 }
756
757 /* No free slot found */
758 return -1;
759 }
760
761 static int ath_key_config(struct ath_softc *sc,
762 struct ieee80211_sta *sta,
763 struct ieee80211_key_conf *key)
764 {
765 struct ath9k_keyval hk;
766 const u8 *mac = NULL;
767 int ret = 0;
768 int idx;
769
770 memset(&hk, 0, sizeof(hk));
771
772 switch (key->alg) {
773 case ALG_WEP:
774 hk.kv_type = ATH9K_CIPHER_WEP;
775 break;
776 case ALG_TKIP:
777 hk.kv_type = ATH9K_CIPHER_TKIP;
778 break;
779 case ALG_CCMP:
780 hk.kv_type = ATH9K_CIPHER_AES_CCM;
781 break;
782 default:
783 return -EOPNOTSUPP;
784 }
785
786 hk.kv_len = key->keylen;
787 memcpy(hk.kv_val, key->key, key->keylen);
788
789 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
790 /* For now, use the default keys for broadcast keys. This may
791 * need to change with virtual interfaces. */
792 idx = key->keyidx;
793 } else if (key->keyidx) {
794 struct ieee80211_vif *vif;
795
796 if (WARN_ON(!sta))
797 return -EOPNOTSUPP;
798 mac = sta->addr;
799
800 vif = sc->sc_vaps[0];
801 if (vif->type != NL80211_IFTYPE_AP) {
802 /* Only keyidx 0 should be used with unicast key, but
803 * allow this for client mode for now. */
804 idx = key->keyidx;
805 } else
806 return -EIO;
807 } else {
808 if (WARN_ON(!sta))
809 return -EOPNOTSUPP;
810 mac = sta->addr;
811
812 if (key->alg == ALG_TKIP)
813 idx = ath_reserve_key_cache_slot_tkip(sc);
814 else
815 idx = ath_reserve_key_cache_slot(sc);
816 if (idx < 0)
817 return -ENOSPC; /* no free key cache entries */
818 }
819
820 if (key->alg == ALG_TKIP)
821 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
822 else
823 ret = ath_keyset(sc, idx, &hk, mac);
824
825 if (!ret)
826 return -EIO;
827
828 set_bit(idx, sc->sc_keymap);
829 if (key->alg == ALG_TKIP) {
830 set_bit(idx + 64, sc->sc_keymap);
831 if (sc->sc_splitmic) {
832 set_bit(idx + 32, sc->sc_keymap);
833 set_bit(idx + 64 + 32, sc->sc_keymap);
834 }
835 }
836
837 return idx;
838 }
839
840 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
841 {
842 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
843 if (key->hw_key_idx < IEEE80211_WEP_NKID)
844 return;
845
846 clear_bit(key->hw_key_idx, sc->sc_keymap);
847 if (key->alg != ALG_TKIP)
848 return;
849
850 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
851 if (sc->sc_splitmic) {
852 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
853 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
854 }
855 }
856
857 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
858 {
859 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
860 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
861
862 ht_info->ht_supported = true;
863 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
864 IEEE80211_HT_CAP_SM_PS |
865 IEEE80211_HT_CAP_SGI_40 |
866 IEEE80211_HT_CAP_DSSSCCK40;
867
868 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
869 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
870 /* set up supported mcs set */
871 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
872 ht_info->mcs.rx_mask[0] = 0xff;
873 ht_info->mcs.rx_mask[1] = 0xff;
874 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
875 }
876
877 static void ath9k_bss_assoc_info(struct ath_softc *sc,
878 struct ieee80211_vif *vif,
879 struct ieee80211_bss_conf *bss_conf)
880 {
881 struct ath_vap *avp = (void *)vif->drv_priv;
882
883 if (bss_conf->assoc) {
884 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
885 bss_conf->aid, sc->sc_curbssid);
886
887 /* New association, store aid */
888 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
889 sc->sc_curaid = bss_conf->aid;
890 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
891 sc->sc_curaid);
892 }
893
894 /* Configure the beacon */
895 ath_beacon_config(sc, 0);
896 sc->sc_flags |= SC_OP_BEACONS;
897
898 /* Reset rssi stats */
899 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
900 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
901 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
902 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
903
904 /* Start ANI */
905 mod_timer(&sc->sc_ani.timer,
906 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
907
908 } else {
909 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
910 sc->sc_curaid = 0;
911 }
912 }
913
914 /********************************/
915 /* LED functions */
916 /********************************/
917
918 static void ath_led_brightness(struct led_classdev *led_cdev,
919 enum led_brightness brightness)
920 {
921 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
922 struct ath_softc *sc = led->sc;
923
924 switch (brightness) {
925 case LED_OFF:
926 if (led->led_type == ATH_LED_ASSOC ||
927 led->led_type == ATH_LED_RADIO)
928 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
929 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
930 (led->led_type == ATH_LED_RADIO) ? 1 :
931 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
932 break;
933 case LED_FULL:
934 if (led->led_type == ATH_LED_ASSOC)
935 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
936 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
937 break;
938 default:
939 break;
940 }
941 }
942
943 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
944 char *trigger)
945 {
946 int ret;
947
948 led->sc = sc;
949 led->led_cdev.name = led->name;
950 led->led_cdev.default_trigger = trigger;
951 led->led_cdev.brightness_set = ath_led_brightness;
952
953 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
954 if (ret)
955 DPRINTF(sc, ATH_DBG_FATAL,
956 "Failed to register led:%s", led->name);
957 else
958 led->registered = 1;
959 return ret;
960 }
961
962 static void ath_unregister_led(struct ath_led *led)
963 {
964 if (led->registered) {
965 led_classdev_unregister(&led->led_cdev);
966 led->registered = 0;
967 }
968 }
969
970 static void ath_deinit_leds(struct ath_softc *sc)
971 {
972 ath_unregister_led(&sc->assoc_led);
973 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
974 ath_unregister_led(&sc->tx_led);
975 ath_unregister_led(&sc->rx_led);
976 ath_unregister_led(&sc->radio_led);
977 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
978 }
979
980 static void ath_init_leds(struct ath_softc *sc)
981 {
982 char *trigger;
983 int ret;
984
985 /* Configure gpio 1 for output */
986 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
987 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
988 /* LED off, active low */
989 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
990
991 trigger = ieee80211_get_radio_led_name(sc->hw);
992 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
993 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
994 ret = ath_register_led(sc, &sc->radio_led, trigger);
995 sc->radio_led.led_type = ATH_LED_RADIO;
996 if (ret)
997 goto fail;
998
999 trigger = ieee80211_get_assoc_led_name(sc->hw);
1000 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1001 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1002 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1003 sc->assoc_led.led_type = ATH_LED_ASSOC;
1004 if (ret)
1005 goto fail;
1006
1007 trigger = ieee80211_get_tx_led_name(sc->hw);
1008 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1009 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1010 ret = ath_register_led(sc, &sc->tx_led, trigger);
1011 sc->tx_led.led_type = ATH_LED_TX;
1012 if (ret)
1013 goto fail;
1014
1015 trigger = ieee80211_get_rx_led_name(sc->hw);
1016 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1017 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1018 ret = ath_register_led(sc, &sc->rx_led, trigger);
1019 sc->rx_led.led_type = ATH_LED_RX;
1020 if (ret)
1021 goto fail;
1022
1023 return;
1024
1025 fail:
1026 ath_deinit_leds(sc);
1027 }
1028
1029 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1030
1031 /*******************/
1032 /* Rfkill */
1033 /*******************/
1034
1035 static void ath_radio_enable(struct ath_softc *sc)
1036 {
1037 struct ath_hal *ah = sc->sc_ah;
1038 struct ieee80211_channel *channel = sc->hw->conf.channel;
1039 int r;
1040
1041 ath9k_ps_wakeup(sc);
1042 spin_lock_bh(&sc->sc_resetlock);
1043
1044 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1045
1046 if (r) {
1047 DPRINTF(sc, ATH_DBG_FATAL,
1048 "Unable to reset channel %u (%uMhz) ",
1049 "reset status %u\n",
1050 channel->center_freq, r);
1051 }
1052 spin_unlock_bh(&sc->sc_resetlock);
1053
1054 ath_update_txpow(sc);
1055 if (ath_startrecv(sc) != 0) {
1056 DPRINTF(sc, ATH_DBG_FATAL,
1057 "Unable to restart recv logic\n");
1058 return;
1059 }
1060
1061 if (sc->sc_flags & SC_OP_BEACONS)
1062 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1063
1064 /* Re-Enable interrupts */
1065 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1066
1067 /* Enable LED */
1068 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1069 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1070 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1071
1072 ieee80211_wake_queues(sc->hw);
1073 ath9k_ps_restore(sc);
1074 }
1075
1076 static void ath_radio_disable(struct ath_softc *sc)
1077 {
1078 struct ath_hal *ah = sc->sc_ah;
1079 struct ieee80211_channel *channel = sc->hw->conf.channel;
1080 int r;
1081
1082 ath9k_ps_wakeup(sc);
1083 ieee80211_stop_queues(sc->hw);
1084
1085 /* Disable LED */
1086 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1087 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1088
1089 /* Disable interrupts */
1090 ath9k_hw_set_interrupts(ah, 0);
1091
1092 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1093 ath_stoprecv(sc); /* turn off frame recv */
1094 ath_flushrecv(sc); /* flush recv queue */
1095
1096 spin_lock_bh(&sc->sc_resetlock);
1097 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1098 if (r) {
1099 DPRINTF(sc, ATH_DBG_FATAL,
1100 "Unable to reset channel %u (%uMhz) "
1101 "reset status %u\n",
1102 channel->center_freq, r);
1103 }
1104 spin_unlock_bh(&sc->sc_resetlock);
1105
1106 ath9k_hw_phy_disable(ah);
1107 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1108 ath9k_ps_restore(sc);
1109 }
1110
1111 static bool ath_is_rfkill_set(struct ath_softc *sc)
1112 {
1113 struct ath_hal *ah = sc->sc_ah;
1114
1115 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1116 ah->ah_rfkill_polarity;
1117 }
1118
1119 /* h/w rfkill poll function */
1120 static void ath_rfkill_poll(struct work_struct *work)
1121 {
1122 struct ath_softc *sc = container_of(work, struct ath_softc,
1123 rf_kill.rfkill_poll.work);
1124 bool radio_on;
1125
1126 if (sc->sc_flags & SC_OP_INVALID)
1127 return;
1128
1129 radio_on = !ath_is_rfkill_set(sc);
1130
1131 /*
1132 * enable/disable radio only when there is a
1133 * state change in RF switch
1134 */
1135 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1136 enum rfkill_state state;
1137
1138 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1139 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1140 : RFKILL_STATE_HARD_BLOCKED;
1141 } else if (radio_on) {
1142 ath_radio_enable(sc);
1143 state = RFKILL_STATE_UNBLOCKED;
1144 } else {
1145 ath_radio_disable(sc);
1146 state = RFKILL_STATE_HARD_BLOCKED;
1147 }
1148
1149 if (state == RFKILL_STATE_HARD_BLOCKED)
1150 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1151 else
1152 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1153
1154 rfkill_force_state(sc->rf_kill.rfkill, state);
1155 }
1156
1157 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1158 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1159 }
1160
1161 /* s/w rfkill handler */
1162 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1163 {
1164 struct ath_softc *sc = data;
1165
1166 switch (state) {
1167 case RFKILL_STATE_SOFT_BLOCKED:
1168 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1169 SC_OP_RFKILL_SW_BLOCKED)))
1170 ath_radio_disable(sc);
1171 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1172 return 0;
1173 case RFKILL_STATE_UNBLOCKED:
1174 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1175 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1176 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1177 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1178 "radio as it is disabled by h/w\n");
1179 return -EPERM;
1180 }
1181 ath_radio_enable(sc);
1182 }
1183 return 0;
1184 default:
1185 return -EINVAL;
1186 }
1187 }
1188
1189 /* Init s/w rfkill */
1190 static int ath_init_sw_rfkill(struct ath_softc *sc)
1191 {
1192 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1193 RFKILL_TYPE_WLAN);
1194 if (!sc->rf_kill.rfkill) {
1195 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1196 return -ENOMEM;
1197 }
1198
1199 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1200 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1201 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1202 sc->rf_kill.rfkill->data = sc;
1203 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1204 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1205 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1206
1207 return 0;
1208 }
1209
1210 /* Deinitialize rfkill */
1211 static void ath_deinit_rfkill(struct ath_softc *sc)
1212 {
1213 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1214 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1215
1216 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1217 rfkill_unregister(sc->rf_kill.rfkill);
1218 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1219 sc->rf_kill.rfkill = NULL;
1220 }
1221 }
1222
1223 static int ath_start_rfkill_poll(struct ath_softc *sc)
1224 {
1225 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1226 queue_delayed_work(sc->hw->workqueue,
1227 &sc->rf_kill.rfkill_poll, 0);
1228
1229 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1230 if (rfkill_register(sc->rf_kill.rfkill)) {
1231 DPRINTF(sc, ATH_DBG_FATAL,
1232 "Unable to register rfkill\n");
1233 rfkill_free(sc->rf_kill.rfkill);
1234
1235 /* Deinitialize the device */
1236 ath_cleanup(sc);
1237 return -EIO;
1238 } else {
1239 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1240 }
1241 }
1242
1243 return 0;
1244 }
1245 #endif /* CONFIG_RFKILL */
1246
1247 void ath_cleanup(struct ath_softc *sc)
1248 {
1249 ath_detach(sc);
1250 free_irq(sc->irq, sc);
1251 ath_bus_cleanup(sc);
1252 ieee80211_free_hw(sc->hw);
1253 }
1254
1255 void ath_detach(struct ath_softc *sc)
1256 {
1257 struct ieee80211_hw *hw = sc->hw;
1258 int i = 0;
1259
1260 ath9k_ps_wakeup(sc);
1261
1262 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1263
1264 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1265 ath_deinit_rfkill(sc);
1266 #endif
1267 ath_deinit_leds(sc);
1268
1269 ieee80211_unregister_hw(hw);
1270 ath_rx_cleanup(sc);
1271 ath_tx_cleanup(sc);
1272
1273 tasklet_kill(&sc->intr_tq);
1274 tasklet_kill(&sc->bcon_tasklet);
1275
1276 if (!(sc->sc_flags & SC_OP_INVALID))
1277 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1278
1279 /* cleanup tx queues */
1280 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1281 if (ATH_TXQ_SETUP(sc, i))
1282 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1283
1284 ath9k_hw_detach(sc->sc_ah);
1285 ath9k_exit_debug(sc);
1286 ath9k_ps_restore(sc);
1287 }
1288
1289 static int ath_init(u16 devid, struct ath_softc *sc)
1290 {
1291 struct ath_hal *ah = NULL;
1292 int status;
1293 int error = 0, i;
1294 int csz = 0;
1295
1296 /* XXX: hardware will not be ready until ath_open() being called */
1297 sc->sc_flags |= SC_OP_INVALID;
1298
1299 if (ath9k_init_debug(sc) < 0)
1300 printk(KERN_ERR "Unable to create debugfs files\n");
1301
1302 spin_lock_init(&sc->sc_resetlock);
1303 mutex_init(&sc->mutex);
1304 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1305 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1306 (unsigned long)sc);
1307
1308 /*
1309 * Cache line size is used to size and align various
1310 * structures used to communicate with the hardware.
1311 */
1312 ath_read_cachesize(sc, &csz);
1313 /* XXX assert csz is non-zero */
1314 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1315
1316 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1317 if (ah == NULL) {
1318 DPRINTF(sc, ATH_DBG_FATAL,
1319 "Unable to attach hardware; HAL status %d\n", status);
1320 error = -ENXIO;
1321 goto bad;
1322 }
1323 sc->sc_ah = ah;
1324
1325 /* Get the hardware key cache size. */
1326 sc->sc_keymax = ah->ah_caps.keycache_size;
1327 if (sc->sc_keymax > ATH_KEYMAX) {
1328 DPRINTF(sc, ATH_DBG_KEYCACHE,
1329 "Warning, using only %u entries in %u key cache\n",
1330 ATH_KEYMAX, sc->sc_keymax);
1331 sc->sc_keymax = ATH_KEYMAX;
1332 }
1333
1334 /*
1335 * Reset the key cache since some parts do not
1336 * reset the contents on initial power up.
1337 */
1338 for (i = 0; i < sc->sc_keymax; i++)
1339 ath9k_hw_keyreset(ah, (u16) i);
1340
1341 if (ath9k_regd_init(sc->sc_ah))
1342 goto bad;
1343
1344 /* default to MONITOR mode */
1345 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1346
1347 /* Setup rate tables */
1348
1349 ath_rate_attach(sc);
1350 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1351 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1352
1353 /*
1354 * Allocate hardware transmit queues: one queue for
1355 * beacon frames and one data queue for each QoS
1356 * priority. Note that the hal handles reseting
1357 * these queues at the needed time.
1358 */
1359 sc->beacon.beaconq = ath_beaconq_setup(ah);
1360 if (sc->beacon.beaconq == -1) {
1361 DPRINTF(sc, ATH_DBG_FATAL,
1362 "Unable to setup a beacon xmit queue\n");
1363 error = -EIO;
1364 goto bad2;
1365 }
1366 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1367 if (sc->beacon.cabq == NULL) {
1368 DPRINTF(sc, ATH_DBG_FATAL,
1369 "Unable to setup CAB xmit queue\n");
1370 error = -EIO;
1371 goto bad2;
1372 }
1373
1374 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1375 ath_cabq_update(sc);
1376
1377 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1378 sc->tx.hwq_map[i] = -1;
1379
1380 /* Setup data queues */
1381 /* NB: ensure BK queue is the lowest priority h/w queue */
1382 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1383 DPRINTF(sc, ATH_DBG_FATAL,
1384 "Unable to setup xmit queue for BK traffic\n");
1385 error = -EIO;
1386 goto bad2;
1387 }
1388
1389 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1390 DPRINTF(sc, ATH_DBG_FATAL,
1391 "Unable to setup xmit queue for BE traffic\n");
1392 error = -EIO;
1393 goto bad2;
1394 }
1395 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1396 DPRINTF(sc, ATH_DBG_FATAL,
1397 "Unable to setup xmit queue for VI traffic\n");
1398 error = -EIO;
1399 goto bad2;
1400 }
1401 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1402 DPRINTF(sc, ATH_DBG_FATAL,
1403 "Unable to setup xmit queue for VO traffic\n");
1404 error = -EIO;
1405 goto bad2;
1406 }
1407
1408 /* Initializes the noise floor to a reasonable default value.
1409 * Later on this will be updated during ANI processing. */
1410
1411 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1412 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1413
1414 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1415 ATH9K_CIPHER_TKIP, NULL)) {
1416 /*
1417 * Whether we should enable h/w TKIP MIC.
1418 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1419 * report WMM capable, so it's always safe to turn on
1420 * TKIP MIC in this case.
1421 */
1422 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1423 0, 1, NULL);
1424 }
1425
1426 /*
1427 * Check whether the separate key cache entries
1428 * are required to handle both tx+rx MIC keys.
1429 * With split mic keys the number of stations is limited
1430 * to 27 otherwise 59.
1431 */
1432 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1433 ATH9K_CIPHER_TKIP, NULL)
1434 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1435 ATH9K_CIPHER_MIC, NULL)
1436 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1437 0, NULL))
1438 sc->sc_splitmic = 1;
1439
1440 /* turn on mcast key search if possible */
1441 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1442 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1443 1, NULL);
1444
1445 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1446 sc->sc_config.txpowlimit_override = 0;
1447
1448 /* 11n Capabilities */
1449 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1450 sc->sc_flags |= SC_OP_TXAGGR;
1451 sc->sc_flags |= SC_OP_RXAGGR;
1452 }
1453
1454 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1455 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1456
1457 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1458 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1459
1460 ath9k_hw_getmac(ah, sc->sc_myaddr);
1461 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1462 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1463 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1464 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1465 }
1466
1467 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1468
1469 /* initialize beacon slots */
1470 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1471 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1472
1473 /* save MISC configurations */
1474 sc->sc_config.swBeaconProcess = 1;
1475
1476 /* setup channels and rates */
1477
1478 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1479 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1480 sc->rates[IEEE80211_BAND_2GHZ];
1481 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1482 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1483 ARRAY_SIZE(ath9k_2ghz_chantable);
1484
1485 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1486 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1487 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1488 sc->rates[IEEE80211_BAND_5GHZ];
1489 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1490 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1491 ARRAY_SIZE(ath9k_5ghz_chantable);
1492 }
1493
1494 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1495 ath9k_hw_btcoex_enable(sc->sc_ah);
1496
1497 return 0;
1498 bad2:
1499 /* cleanup tx queues */
1500 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1501 if (ATH_TXQ_SETUP(sc, i))
1502 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1503 bad:
1504 if (ah)
1505 ath9k_hw_detach(ah);
1506
1507 return error;
1508 }
1509
1510 int ath_attach(u16 devid, struct ath_softc *sc)
1511 {
1512 struct ieee80211_hw *hw = sc->hw;
1513 int error = 0;
1514
1515 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1516
1517 error = ath_init(devid, sc);
1518 if (error != 0)
1519 return error;
1520
1521 /* get mac address from hardware and set in mac80211 */
1522
1523 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1524
1525 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1526 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1527 IEEE80211_HW_SIGNAL_DBM |
1528 IEEE80211_HW_AMPDU_AGGREGATION |
1529 IEEE80211_HW_SUPPORTS_PS |
1530 IEEE80211_HW_PS_NULLFUNC_STACK;
1531
1532 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1533 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1534
1535 hw->wiphy->interface_modes =
1536 BIT(NL80211_IFTYPE_AP) |
1537 BIT(NL80211_IFTYPE_STATION) |
1538 BIT(NL80211_IFTYPE_ADHOC);
1539
1540 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1541 hw->wiphy->strict_regulatory = true;
1542
1543 hw->queues = 4;
1544 hw->max_rates = 4;
1545 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1546 hw->sta_data_size = sizeof(struct ath_node);
1547 hw->vif_data_size = sizeof(struct ath_vap);
1548
1549 hw->rate_control_algorithm = "ath9k_rate_control";
1550
1551 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1552 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1553 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1554 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1555 }
1556
1557 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1558 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1559 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1560 &sc->sbands[IEEE80211_BAND_5GHZ];
1561
1562 /* initialize tx/rx engine */
1563 error = ath_tx_init(sc, ATH_TXBUF);
1564 if (error != 0)
1565 goto detach;
1566
1567 error = ath_rx_init(sc, ATH_RXBUF);
1568 if (error != 0)
1569 goto detach;
1570
1571 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1572 /* Initialze h/w Rfkill */
1573 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1574 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1575
1576 /* Initialize s/w rfkill */
1577 if (ath_init_sw_rfkill(sc))
1578 goto detach;
1579 #endif
1580
1581 if (ath9k_is_world_regd(sc->sc_ah)) {
1582 /* Anything applied here (prior to wiphy registratoin) gets
1583 * saved on the wiphy orig_* parameters */
1584 const struct ieee80211_regdomain *regd =
1585 ath9k_world_regdomain(sc->sc_ah);
1586 hw->wiphy->custom_regulatory = true;
1587 hw->wiphy->strict_regulatory = false;
1588 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1589 ath9k_reg_apply_radar_flags(hw->wiphy);
1590 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1591 } else {
1592 /* This gets applied in the case of the absense of CRDA,
1593 * its our own custom world regulatory domain, similar to
1594 * cfg80211's but we enable passive scanning */
1595 const struct ieee80211_regdomain *regd =
1596 ath9k_default_world_regdomain();
1597 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1598 ath9k_reg_apply_radar_flags(hw->wiphy);
1599 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1600 }
1601
1602 error = ieee80211_register_hw(hw);
1603
1604 if (!ath9k_is_world_regd(sc->sc_ah))
1605 regulatory_hint(hw->wiphy, sc->sc_ah->alpha2);
1606
1607 /* Initialize LED control */
1608 ath_init_leds(sc);
1609
1610
1611 return 0;
1612 detach:
1613 ath_detach(sc);
1614 return error;
1615 }
1616
1617 int ath_reset(struct ath_softc *sc, bool retry_tx)
1618 {
1619 struct ath_hal *ah = sc->sc_ah;
1620 struct ieee80211_hw *hw = sc->hw;
1621 int r;
1622
1623 ath9k_hw_set_interrupts(ah, 0);
1624 ath_drain_all_txq(sc, retry_tx);
1625 ath_stoprecv(sc);
1626 ath_flushrecv(sc);
1627
1628 spin_lock_bh(&sc->sc_resetlock);
1629 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1630 if (r)
1631 DPRINTF(sc, ATH_DBG_FATAL,
1632 "Unable to reset hardware; reset status %u\n", r);
1633 spin_unlock_bh(&sc->sc_resetlock);
1634
1635 if (ath_startrecv(sc) != 0)
1636 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1637
1638 /*
1639 * We may be doing a reset in response to a request
1640 * that changes the channel so update any state that
1641 * might change as a result.
1642 */
1643 ath_cache_conf_rate(sc, &hw->conf);
1644
1645 ath_update_txpow(sc);
1646
1647 if (sc->sc_flags & SC_OP_BEACONS)
1648 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1649
1650 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1651
1652 if (retry_tx) {
1653 int i;
1654 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1655 if (ATH_TXQ_SETUP(sc, i)) {
1656 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1657 ath_txq_schedule(sc, &sc->tx.txq[i]);
1658 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1659 }
1660 }
1661 }
1662
1663 return r;
1664 }
1665
1666 /*
1667 * This function will allocate both the DMA descriptor structure, and the
1668 * buffers it contains. These are used to contain the descriptors used
1669 * by the system.
1670 */
1671 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1672 struct list_head *head, const char *name,
1673 int nbuf, int ndesc)
1674 {
1675 #define DS2PHYS(_dd, _ds) \
1676 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1677 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1678 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1679
1680 struct ath_desc *ds;
1681 struct ath_buf *bf;
1682 int i, bsize, error;
1683
1684 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1685 name, nbuf, ndesc);
1686
1687 /* ath_desc must be a multiple of DWORDs */
1688 if ((sizeof(struct ath_desc) % 4) != 0) {
1689 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1690 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1691 error = -ENOMEM;
1692 goto fail;
1693 }
1694
1695 dd->dd_name = name;
1696 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1697
1698 /*
1699 * Need additional DMA memory because we can't use
1700 * descriptors that cross the 4K page boundary. Assume
1701 * one skipped descriptor per 4K page.
1702 */
1703 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1704 u32 ndesc_skipped =
1705 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1706 u32 dma_len;
1707
1708 while (ndesc_skipped) {
1709 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1710 dd->dd_desc_len += dma_len;
1711
1712 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1713 };
1714 }
1715
1716 /* allocate descriptors */
1717 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1718 &dd->dd_desc_paddr, GFP_ATOMIC);
1719 if (dd->dd_desc == NULL) {
1720 error = -ENOMEM;
1721 goto fail;
1722 }
1723 ds = dd->dd_desc;
1724 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1725 dd->dd_name, ds, (u32) dd->dd_desc_len,
1726 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1727
1728 /* allocate buffers */
1729 bsize = sizeof(struct ath_buf) * nbuf;
1730 bf = kmalloc(bsize, GFP_KERNEL);
1731 if (bf == NULL) {
1732 error = -ENOMEM;
1733 goto fail2;
1734 }
1735 memset(bf, 0, bsize);
1736 dd->dd_bufptr = bf;
1737
1738 INIT_LIST_HEAD(head);
1739 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1740 bf->bf_desc = ds;
1741 bf->bf_daddr = DS2PHYS(dd, ds);
1742
1743 if (!(sc->sc_ah->ah_caps.hw_caps &
1744 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1745 /*
1746 * Skip descriptor addresses which can cause 4KB
1747 * boundary crossing (addr + length) with a 32 dword
1748 * descriptor fetch.
1749 */
1750 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1751 ASSERT((caddr_t) bf->bf_desc <
1752 ((caddr_t) dd->dd_desc +
1753 dd->dd_desc_len));
1754
1755 ds += ndesc;
1756 bf->bf_desc = ds;
1757 bf->bf_daddr = DS2PHYS(dd, ds);
1758 }
1759 }
1760 list_add_tail(&bf->list, head);
1761 }
1762 return 0;
1763 fail2:
1764 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1765 dd->dd_desc_paddr);
1766 fail:
1767 memset(dd, 0, sizeof(*dd));
1768 return error;
1769 #undef ATH_DESC_4KB_BOUND_CHECK
1770 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1771 #undef DS2PHYS
1772 }
1773
1774 void ath_descdma_cleanup(struct ath_softc *sc,
1775 struct ath_descdma *dd,
1776 struct list_head *head)
1777 {
1778 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1779 dd->dd_desc_paddr);
1780
1781 INIT_LIST_HEAD(head);
1782 kfree(dd->dd_bufptr);
1783 memset(dd, 0, sizeof(*dd));
1784 }
1785
1786 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1787 {
1788 int qnum;
1789
1790 switch (queue) {
1791 case 0:
1792 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1793 break;
1794 case 1:
1795 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1796 break;
1797 case 2:
1798 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1799 break;
1800 case 3:
1801 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1802 break;
1803 default:
1804 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1805 break;
1806 }
1807
1808 return qnum;
1809 }
1810
1811 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1812 {
1813 int qnum;
1814
1815 switch (queue) {
1816 case ATH9K_WME_AC_VO:
1817 qnum = 0;
1818 break;
1819 case ATH9K_WME_AC_VI:
1820 qnum = 1;
1821 break;
1822 case ATH9K_WME_AC_BE:
1823 qnum = 2;
1824 break;
1825 case ATH9K_WME_AC_BK:
1826 qnum = 3;
1827 break;
1828 default:
1829 qnum = -1;
1830 break;
1831 }
1832
1833 return qnum;
1834 }
1835
1836 /* XXX: Remove me once we don't depend on ath9k_channel for all
1837 * this redundant data */
1838 static void ath9k_update_ichannel(struct ath_softc *sc,
1839 struct ath9k_channel *ichan)
1840 {
1841 struct ieee80211_hw *hw = sc->hw;
1842 struct ieee80211_channel *chan = hw->conf.channel;
1843 struct ieee80211_conf *conf = &hw->conf;
1844
1845 ichan->channel = chan->center_freq;
1846 ichan->chan = chan;
1847
1848 if (chan->band == IEEE80211_BAND_2GHZ) {
1849 ichan->chanmode = CHANNEL_G;
1850 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1851 } else {
1852 ichan->chanmode = CHANNEL_A;
1853 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1854 }
1855
1856 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1857
1858 if (conf_is_ht(conf)) {
1859 if (conf_is_ht40(conf))
1860 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1861
1862 ichan->chanmode = ath_get_extchanmode(sc, chan,
1863 conf->channel_type);
1864 }
1865 }
1866
1867 /**********************/
1868 /* mac80211 callbacks */
1869 /**********************/
1870
1871 static int ath9k_start(struct ieee80211_hw *hw)
1872 {
1873 struct ath_softc *sc = hw->priv;
1874 struct ieee80211_channel *curchan = hw->conf.channel;
1875 struct ath9k_channel *init_channel;
1876 int r, pos;
1877
1878 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1879 "initial channel: %d MHz\n", curchan->center_freq);
1880
1881 /* setup initial channel */
1882
1883 pos = curchan->hw_value;
1884
1885 init_channel = &sc->sc_ah->ah_channels[pos];
1886 ath9k_update_ichannel(sc, init_channel);
1887
1888 /* Reset SERDES registers */
1889 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1890
1891 /*
1892 * The basic interface to setting the hardware in a good
1893 * state is ``reset''. On return the hardware is known to
1894 * be powered up and with interrupts disabled. This must
1895 * be followed by initialization of the appropriate bits
1896 * and then setup of the interrupt mask.
1897 */
1898 spin_lock_bh(&sc->sc_resetlock);
1899 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1900 if (r) {
1901 DPRINTF(sc, ATH_DBG_FATAL,
1902 "Unable to reset hardware; reset status %u "
1903 "(freq %u MHz)\n", r,
1904 curchan->center_freq);
1905 spin_unlock_bh(&sc->sc_resetlock);
1906 return r;
1907 }
1908 spin_unlock_bh(&sc->sc_resetlock);
1909
1910 /*
1911 * This is needed only to setup initial state
1912 * but it's best done after a reset.
1913 */
1914 ath_update_txpow(sc);
1915
1916 /*
1917 * Setup the hardware after reset:
1918 * The receive engine is set going.
1919 * Frame transmit is handled entirely
1920 * in the frame output path; there's nothing to do
1921 * here except setup the interrupt mask.
1922 */
1923 if (ath_startrecv(sc) != 0) {
1924 DPRINTF(sc, ATH_DBG_FATAL,
1925 "Unable to start recv logic\n");
1926 return -EIO;
1927 }
1928
1929 /* Setup our intr mask. */
1930 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1931 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1932 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1933
1934 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1935 sc->sc_imask |= ATH9K_INT_GTT;
1936
1937 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1938 sc->sc_imask |= ATH9K_INT_CST;
1939
1940 /*
1941 * Enable MIB interrupts when there are hardware phy counters.
1942 * Note we only do this (at the moment) for station mode.
1943 */
1944 if (ath9k_hw_phycounters(sc->sc_ah) &&
1945 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1946 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1947 sc->sc_imask |= ATH9K_INT_MIB;
1948 /*
1949 * Some hardware processes the TIM IE and fires an
1950 * interrupt when the TIM bit is set. For hardware
1951 * that does, if not overridden by configuration,
1952 * enable the TIM interrupt when operating as station.
1953 */
1954 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1955 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1956 !sc->sc_config.swBeaconProcess)
1957 sc->sc_imask |= ATH9K_INT_TIM;
1958
1959 ath_cache_conf_rate(sc, &hw->conf);
1960
1961 sc->sc_flags &= ~SC_OP_INVALID;
1962
1963 /* Disable BMISS interrupt when we're not associated */
1964 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1965 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1966
1967 ieee80211_wake_queues(sc->hw);
1968
1969 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1970 r = ath_start_rfkill_poll(sc);
1971 #endif
1972 return r;
1973 }
1974
1975 static int ath9k_tx(struct ieee80211_hw *hw,
1976 struct sk_buff *skb)
1977 {
1978 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1979 struct ath_softc *sc = hw->priv;
1980 struct ath_tx_control txctl;
1981 int hdrlen, padsize;
1982
1983 memset(&txctl, 0, sizeof(struct ath_tx_control));
1984
1985 /*
1986 * As a temporary workaround, assign seq# here; this will likely need
1987 * to be cleaned up to work better with Beacon transmission and virtual
1988 * BSSes.
1989 */
1990 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1991 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1992 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1993 sc->tx.seq_no += 0x10;
1994 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1995 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1996 }
1997
1998 /* Add the padding after the header if this is not already done */
1999 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2000 if (hdrlen & 3) {
2001 padsize = hdrlen % 4;
2002 if (skb_headroom(skb) < padsize)
2003 return -1;
2004 skb_push(skb, padsize);
2005 memmove(skb->data, skb->data + padsize, hdrlen);
2006 }
2007
2008 /* Check if a tx queue is available */
2009
2010 txctl.txq = ath_test_get_txq(sc, skb);
2011 if (!txctl.txq)
2012 goto exit;
2013
2014 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2015
2016 if (ath_tx_start(sc, skb, &txctl) != 0) {
2017 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2018 goto exit;
2019 }
2020
2021 return 0;
2022 exit:
2023 dev_kfree_skb_any(skb);
2024 return 0;
2025 }
2026
2027 static void ath9k_stop(struct ieee80211_hw *hw)
2028 {
2029 struct ath_softc *sc = hw->priv;
2030
2031 if (sc->sc_flags & SC_OP_INVALID) {
2032 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2033 return;
2034 }
2035
2036 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2037
2038 ieee80211_stop_queues(sc->hw);
2039
2040 /* make sure h/w will not generate any interrupt
2041 * before setting the invalid flag. */
2042 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2043
2044 if (!(sc->sc_flags & SC_OP_INVALID)) {
2045 ath_drain_all_txq(sc, false);
2046 ath_stoprecv(sc);
2047 ath9k_hw_phy_disable(sc->sc_ah);
2048 } else
2049 sc->rx.rxlink = NULL;
2050
2051 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2052 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2053 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2054 #endif
2055 /* disable HAL and put h/w to sleep */
2056 ath9k_hw_disable(sc->sc_ah);
2057 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2058
2059 sc->sc_flags |= SC_OP_INVALID;
2060
2061 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2062 }
2063
2064 static int ath9k_add_interface(struct ieee80211_hw *hw,
2065 struct ieee80211_if_init_conf *conf)
2066 {
2067 struct ath_softc *sc = hw->priv;
2068 struct ath_vap *avp = (void *)conf->vif->drv_priv;
2069 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2070
2071 /* Support only vap for now */
2072
2073 if (sc->sc_nvaps)
2074 return -ENOBUFS;
2075
2076 switch (conf->type) {
2077 case NL80211_IFTYPE_STATION:
2078 ic_opmode = NL80211_IFTYPE_STATION;
2079 break;
2080 case NL80211_IFTYPE_ADHOC:
2081 ic_opmode = NL80211_IFTYPE_ADHOC;
2082 break;
2083 case NL80211_IFTYPE_AP:
2084 ic_opmode = NL80211_IFTYPE_AP;
2085 break;
2086 default:
2087 DPRINTF(sc, ATH_DBG_FATAL,
2088 "Interface type %d not yet supported\n", conf->type);
2089 return -EOPNOTSUPP;
2090 }
2091
2092 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2093
2094 /* Set the VAP opmode */
2095 avp->av_opmode = ic_opmode;
2096 avp->av_bslot = -1;
2097
2098 if (ic_opmode == NL80211_IFTYPE_AP)
2099 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2100
2101 sc->sc_vaps[0] = conf->vif;
2102 sc->sc_nvaps++;
2103
2104 /* Set the device opmode */
2105 sc->sc_ah->ah_opmode = ic_opmode;
2106
2107 if (conf->type == NL80211_IFTYPE_AP) {
2108 /* TODO: is this a suitable place to start ANI for AP mode? */
2109 /* Start ANI */
2110 mod_timer(&sc->sc_ani.timer,
2111 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2112 }
2113
2114 return 0;
2115 }
2116
2117 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2118 struct ieee80211_if_init_conf *conf)
2119 {
2120 struct ath_softc *sc = hw->priv;
2121 struct ath_vap *avp = (void *)conf->vif->drv_priv;
2122
2123 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2124
2125 /* Stop ANI */
2126 del_timer_sync(&sc->sc_ani.timer);
2127
2128 /* Reclaim beacon resources */
2129 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2130 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2131 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2132 ath_beacon_return(sc, avp);
2133 }
2134
2135 sc->sc_flags &= ~SC_OP_BEACONS;
2136
2137 sc->sc_vaps[0] = NULL;
2138 sc->sc_nvaps--;
2139 }
2140
2141 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2142 {
2143 struct ath_softc *sc = hw->priv;
2144 struct ieee80211_conf *conf = &hw->conf;
2145
2146 mutex_lock(&sc->mutex);
2147 if (changed & IEEE80211_CONF_CHANGE_PS) {
2148 if (conf->flags & IEEE80211_CONF_PS) {
2149 if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) {
2150 sc->sc_imask |= ATH9K_INT_TIM_TIMER;
2151 ath9k_hw_set_interrupts(sc->sc_ah,
2152 sc->sc_imask);
2153 }
2154 ath9k_hw_setrxabort(sc->sc_ah, 1);
2155 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2156 } else {
2157 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2158 ath9k_hw_setrxabort(sc->sc_ah, 0);
2159 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2160 if (sc->sc_imask & ATH9K_INT_TIM_TIMER) {
2161 sc->sc_imask &= ~ATH9K_INT_TIM_TIMER;
2162 ath9k_hw_set_interrupts(sc->sc_ah,
2163 sc->sc_imask);
2164 }
2165 }
2166 }
2167
2168 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2169 struct ieee80211_channel *curchan = hw->conf.channel;
2170 int pos = curchan->hw_value;
2171
2172 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2173 curchan->center_freq);
2174
2175 /* XXX: remove me eventualy */
2176 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]);
2177
2178 ath_update_chainmask(sc, conf_is_ht(conf));
2179
2180 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2181 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2182 mutex_unlock(&sc->mutex);
2183 return -EINVAL;
2184 }
2185 }
2186
2187 if (changed & IEEE80211_CONF_CHANGE_POWER)
2188 sc->sc_config.txpowlimit = 2 * conf->power_level;
2189
2190 mutex_unlock(&sc->mutex);
2191 return 0;
2192 }
2193
2194 static int ath9k_config_interface(struct ieee80211_hw *hw,
2195 struct ieee80211_vif *vif,
2196 struct ieee80211_if_conf *conf)
2197 {
2198 struct ath_softc *sc = hw->priv;
2199 struct ath_hal *ah = sc->sc_ah;
2200 struct ath_vap *avp = (void *)vif->drv_priv;
2201 u32 rfilt = 0;
2202 int error, i;
2203
2204 /* TODO: Need to decide which hw opmode to use for multi-interface
2205 * cases */
2206 if (vif->type == NL80211_IFTYPE_AP &&
2207 ah->ah_opmode != NL80211_IFTYPE_AP) {
2208 ah->ah_opmode = NL80211_IFTYPE_STATION;
2209 ath9k_hw_setopmode(ah);
2210 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2211 /* Request full reset to get hw opmode changed properly */
2212 sc->sc_flags |= SC_OP_FULL_RESET;
2213 }
2214
2215 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2216 !is_zero_ether_addr(conf->bssid)) {
2217 switch (vif->type) {
2218 case NL80211_IFTYPE_STATION:
2219 case NL80211_IFTYPE_ADHOC:
2220 /* Set BSSID */
2221 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2222 sc->sc_curaid = 0;
2223 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2224 sc->sc_curaid);
2225
2226 /* Set aggregation protection mode parameters */
2227 sc->sc_config.ath_aggr_prot = 0;
2228
2229 DPRINTF(sc, ATH_DBG_CONFIG,
2230 "RX filter 0x%x bssid %pM aid 0x%x\n",
2231 rfilt, sc->sc_curbssid, sc->sc_curaid);
2232
2233 /* need to reconfigure the beacon */
2234 sc->sc_flags &= ~SC_OP_BEACONS ;
2235
2236 break;
2237 default:
2238 break;
2239 }
2240 }
2241
2242 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2243 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2244 (vif->type == NL80211_IFTYPE_AP))) {
2245 /*
2246 * Allocate and setup the beacon frame.
2247 *
2248 * Stop any previous beacon DMA. This may be
2249 * necessary, for example, when an ibss merge
2250 * causes reconfiguration; we may be called
2251 * with beacon transmission active.
2252 */
2253 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2254
2255 error = ath_beacon_alloc(sc, 0);
2256 if (error != 0)
2257 return error;
2258
2259 ath_beacon_sync(sc, 0);
2260 }
2261
2262 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2263 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2264 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2265 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2266 ath9k_hw_keysetmac(sc->sc_ah,
2267 (u16)i,
2268 sc->sc_curbssid);
2269 }
2270
2271 /* Only legacy IBSS for now */
2272 if (vif->type == NL80211_IFTYPE_ADHOC)
2273 ath_update_chainmask(sc, 0);
2274
2275 return 0;
2276 }
2277
2278 #define SUPPORTED_FILTERS \
2279 (FIF_PROMISC_IN_BSS | \
2280 FIF_ALLMULTI | \
2281 FIF_CONTROL | \
2282 FIF_OTHER_BSS | \
2283 FIF_BCN_PRBRESP_PROMISC | \
2284 FIF_FCSFAIL)
2285
2286 /* FIXME: sc->sc_full_reset ? */
2287 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2288 unsigned int changed_flags,
2289 unsigned int *total_flags,
2290 int mc_count,
2291 struct dev_mc_list *mclist)
2292 {
2293 struct ath_softc *sc = hw->priv;
2294 u32 rfilt;
2295
2296 changed_flags &= SUPPORTED_FILTERS;
2297 *total_flags &= SUPPORTED_FILTERS;
2298
2299 sc->rx.rxfilter = *total_flags;
2300 rfilt = ath_calcrxfilter(sc);
2301 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2302
2303 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2304 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2305 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2306 }
2307
2308 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2309 }
2310
2311 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2312 struct ieee80211_vif *vif,
2313 enum sta_notify_cmd cmd,
2314 struct ieee80211_sta *sta)
2315 {
2316 struct ath_softc *sc = hw->priv;
2317
2318 switch (cmd) {
2319 case STA_NOTIFY_ADD:
2320 ath_node_attach(sc, sta);
2321 break;
2322 case STA_NOTIFY_REMOVE:
2323 ath_node_detach(sc, sta);
2324 break;
2325 default:
2326 break;
2327 }
2328 }
2329
2330 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2331 u16 queue,
2332 const struct ieee80211_tx_queue_params *params)
2333 {
2334 struct ath_softc *sc = hw->priv;
2335 struct ath9k_tx_queue_info qi;
2336 int ret = 0, qnum;
2337
2338 if (queue >= WME_NUM_AC)
2339 return 0;
2340
2341 qi.tqi_aifs = params->aifs;
2342 qi.tqi_cwmin = params->cw_min;
2343 qi.tqi_cwmax = params->cw_max;
2344 qi.tqi_burstTime = params->txop;
2345 qnum = ath_get_hal_qnum(queue, sc);
2346
2347 DPRINTF(sc, ATH_DBG_CONFIG,
2348 "Configure tx [queue/halq] [%d/%d], "
2349 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2350 queue, qnum, params->aifs, params->cw_min,
2351 params->cw_max, params->txop);
2352
2353 ret = ath_txq_update(sc, qnum, &qi);
2354 if (ret)
2355 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2356
2357 return ret;
2358 }
2359
2360 static int ath9k_set_key(struct ieee80211_hw *hw,
2361 enum set_key_cmd cmd,
2362 struct ieee80211_vif *vif,
2363 struct ieee80211_sta *sta,
2364 struct ieee80211_key_conf *key)
2365 {
2366 struct ath_softc *sc = hw->priv;
2367 int ret = 0;
2368
2369 ath9k_ps_wakeup(sc);
2370 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2371
2372 switch (cmd) {
2373 case SET_KEY:
2374 ret = ath_key_config(sc, sta, key);
2375 if (ret >= 0) {
2376 key->hw_key_idx = ret;
2377 /* push IV and Michael MIC generation to stack */
2378 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2379 if (key->alg == ALG_TKIP)
2380 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2381 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2382 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2383 ret = 0;
2384 }
2385 break;
2386 case DISABLE_KEY:
2387 ath_key_delete(sc, key);
2388 break;
2389 default:
2390 ret = -EINVAL;
2391 }
2392
2393 ath9k_ps_restore(sc);
2394 return ret;
2395 }
2396
2397 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2398 struct ieee80211_vif *vif,
2399 struct ieee80211_bss_conf *bss_conf,
2400 u32 changed)
2401 {
2402 struct ath_softc *sc = hw->priv;
2403
2404 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2405 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2406 bss_conf->use_short_preamble);
2407 if (bss_conf->use_short_preamble)
2408 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2409 else
2410 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2411 }
2412
2413 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2414 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2415 bss_conf->use_cts_prot);
2416 if (bss_conf->use_cts_prot &&
2417 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2418 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2419 else
2420 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2421 }
2422
2423 if (changed & BSS_CHANGED_ASSOC) {
2424 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2425 bss_conf->assoc);
2426 ath9k_bss_assoc_info(sc, vif, bss_conf);
2427 }
2428 }
2429
2430 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2431 {
2432 u64 tsf;
2433 struct ath_softc *sc = hw->priv;
2434 struct ath_hal *ah = sc->sc_ah;
2435
2436 tsf = ath9k_hw_gettsf64(ah);
2437
2438 return tsf;
2439 }
2440
2441 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2442 {
2443 struct ath_softc *sc = hw->priv;
2444 struct ath_hal *ah = sc->sc_ah;
2445
2446 ath9k_hw_reset_tsf(ah);
2447 }
2448
2449 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2450 enum ieee80211_ampdu_mlme_action action,
2451 struct ieee80211_sta *sta,
2452 u16 tid, u16 *ssn)
2453 {
2454 struct ath_softc *sc = hw->priv;
2455 int ret = 0;
2456
2457 switch (action) {
2458 case IEEE80211_AMPDU_RX_START:
2459 if (!(sc->sc_flags & SC_OP_RXAGGR))
2460 ret = -ENOTSUPP;
2461 break;
2462 case IEEE80211_AMPDU_RX_STOP:
2463 break;
2464 case IEEE80211_AMPDU_TX_START:
2465 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2466 if (ret < 0)
2467 DPRINTF(sc, ATH_DBG_FATAL,
2468 "Unable to start TX aggregation\n");
2469 else
2470 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2471 break;
2472 case IEEE80211_AMPDU_TX_STOP:
2473 ret = ath_tx_aggr_stop(sc, sta, tid);
2474 if (ret < 0)
2475 DPRINTF(sc, ATH_DBG_FATAL,
2476 "Unable to stop TX aggregation\n");
2477
2478 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2479 break;
2480 case IEEE80211_AMPDU_TX_RESUME:
2481 ath_tx_aggr_resume(sc, sta, tid);
2482 break;
2483 default:
2484 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2485 }
2486
2487 return ret;
2488 }
2489
2490 struct ieee80211_ops ath9k_ops = {
2491 .tx = ath9k_tx,
2492 .start = ath9k_start,
2493 .stop = ath9k_stop,
2494 .add_interface = ath9k_add_interface,
2495 .remove_interface = ath9k_remove_interface,
2496 .config = ath9k_config,
2497 .config_interface = ath9k_config_interface,
2498 .configure_filter = ath9k_configure_filter,
2499 .sta_notify = ath9k_sta_notify,
2500 .conf_tx = ath9k_conf_tx,
2501 .bss_info_changed = ath9k_bss_info_changed,
2502 .set_key = ath9k_set_key,
2503 .get_tsf = ath9k_get_tsf,
2504 .reset_tsf = ath9k_reset_tsf,
2505 .ampdu_action = ath9k_ampdu_action,
2506 };
2507
2508 static struct {
2509 u32 version;
2510 const char * name;
2511 } ath_mac_bb_names[] = {
2512 { AR_SREV_VERSION_5416_PCI, "5416" },
2513 { AR_SREV_VERSION_5416_PCIE, "5418" },
2514 { AR_SREV_VERSION_9100, "9100" },
2515 { AR_SREV_VERSION_9160, "9160" },
2516 { AR_SREV_VERSION_9280, "9280" },
2517 { AR_SREV_VERSION_9285, "9285" }
2518 };
2519
2520 static struct {
2521 u16 version;
2522 const char * name;
2523 } ath_rf_names[] = {
2524 { 0, "5133" },
2525 { AR_RAD5133_SREV_MAJOR, "5133" },
2526 { AR_RAD5122_SREV_MAJOR, "5122" },
2527 { AR_RAD2133_SREV_MAJOR, "2133" },
2528 { AR_RAD2122_SREV_MAJOR, "2122" }
2529 };
2530
2531 /*
2532 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2533 */
2534 const char *
2535 ath_mac_bb_name(u32 mac_bb_version)
2536 {
2537 int i;
2538
2539 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2540 if (ath_mac_bb_names[i].version == mac_bb_version) {
2541 return ath_mac_bb_names[i].name;
2542 }
2543 }
2544
2545 return "????";
2546 }
2547
2548 /*
2549 * Return the RF name. "????" is returned if the RF is unknown.
2550 */
2551 const char *
2552 ath_rf_name(u16 rf_version)
2553 {
2554 int i;
2555
2556 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2557 if (ath_rf_names[i].version == rf_version) {
2558 return ath_rf_names[i].name;
2559 }
2560 }
2561
2562 return "????";
2563 }
2564
2565 static int __init ath9k_init(void)
2566 {
2567 int error;
2568
2569 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2570
2571 /* Register rate control algorithm */
2572 error = ath_rate_control_register();
2573 if (error != 0) {
2574 printk(KERN_ERR
2575 "Unable to register rate control algorithm: %d\n",
2576 error);
2577 goto err_out;
2578 }
2579
2580 error = ath_pci_init();
2581 if (error < 0) {
2582 printk(KERN_ERR
2583 "ath_pci: No devices found, driver not installed.\n");
2584 error = -ENODEV;
2585 goto err_rate_unregister;
2586 }
2587
2588 error = ath_ahb_init();
2589 if (error < 0) {
2590 error = -ENODEV;
2591 goto err_pci_exit;
2592 }
2593
2594 return 0;
2595
2596 err_pci_exit:
2597 ath_pci_exit();
2598
2599 err_rate_unregister:
2600 ath_rate_control_unregister();
2601 err_out:
2602 return error;
2603 }
2604 module_init(ath9k_init);
2605
2606 static void __exit ath9k_exit(void)
2607 {
2608 ath_ahb_exit();
2609 ath_pci_exit();
2610 ath_rate_control_unregister();
2611 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2612 }
2613 module_exit(ath9k_exit);
Linux kernel - Deliverables
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