2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * Setup and link descriptors.
22 * 11N: we can no longer afford to self link the last descriptor.
23 * MAC acknowledges BA status as long as it copies frames to host
24 * buffer (or rx fifo). This can incorrectly acknowledge packets
25 * to a sender if last desc is self-linked.
27 static void ath_rx_buf_link(struct ath_softc
*sc
, struct ath_buf
*bf
)
29 struct ath_hal
*ah
= sc
->sc_ah
;
36 ds
->ds_link
= 0; /* link to null */
37 ds
->ds_data
= bf
->bf_buf_addr
;
39 /* virtual addr of the beginning of the buffer. */
42 ds
->ds_vdata
= skb
->data
;
44 /* setup rx descriptors. The rx.bufsize here tells the harware
45 * how much data it can DMA to us and that we are prepared
47 ath9k_hw_setuprxdesc(ah
, ds
,
51 if (sc
->rx
.rxlink
== NULL
)
52 ath9k_hw_putrxbuf(ah
, bf
->bf_daddr
);
54 *sc
->rx
.rxlink
= bf
->bf_daddr
;
56 sc
->rx
.rxlink
= &ds
->ds_link
;
60 static void ath_setdefantenna(struct ath_softc
*sc
, u32 antenna
)
62 /* XXX block beacon interrupts */
63 ath9k_hw_setantenna(sc
->sc_ah
, antenna
);
64 sc
->rx
.defant
= antenna
;
65 sc
->rx
.rxotherant
= 0;
69 * Extend 15-bit time stamp from rx descriptor to
70 * a full 64-bit TSF using the current h/w TSF.
72 static u64
ath_extend_tsf(struct ath_softc
*sc
, u32 rstamp
)
76 tsf
= ath9k_hw_gettsf64(sc
->sc_ah
);
77 if ((tsf
& 0x7fff) < rstamp
)
79 return (tsf
& ~0x7fff) | rstamp
;
82 static struct sk_buff
*ath_rxbuf_alloc(struct ath_softc
*sc
, u32 len
)
88 * Cache-line-align. This is important (for the
89 * 5210 at least) as not doing so causes bogus data
93 /* Note: the kernel can allocate a value greater than
94 * what we ask it to give us. We really only need 4 KB as that
95 * is this hardware supports and in fact we need at least 3849
96 * as that is the MAX AMSDU size this hardware supports.
97 * Unfortunately this means we may get 8 KB here from the
98 * kernel... and that is actually what is observed on some
100 skb
= dev_alloc_skb(len
+ sc
->sc_cachelsz
- 1);
102 off
= ((unsigned long) skb
->data
) % sc
->sc_cachelsz
;
104 skb_reserve(skb
, sc
->sc_cachelsz
- off
);
106 DPRINTF(sc
, ATH_DBG_FATAL
,
107 "skbuff alloc of size %u failed\n", len
);
115 * For Decrypt or Demic errors, we only mark packet status here and always push
116 * up the frame up to let mac80211 handle the actual error case, be it no
117 * decryption key or real decryption error. This let us keep statistics there.
119 static int ath_rx_prepare(struct sk_buff
*skb
, struct ath_desc
*ds
,
120 struct ieee80211_rx_status
*rx_status
, bool *decrypt_error
,
121 struct ath_softc
*sc
)
123 struct ieee80211_hdr
*hdr
;
127 hdr
= (struct ieee80211_hdr
*)skb
->data
;
128 fc
= hdr
->frame_control
;
129 memset(rx_status
, 0, sizeof(struct ieee80211_rx_status
));
131 if (ds
->ds_rxstat
.rs_more
) {
133 * Frame spans multiple descriptors; this cannot happen yet
134 * as we don't support jumbograms. If not in monitor mode,
135 * discard the frame. Enable this if you want to see
136 * error frames in Monitor mode.
138 if (sc
->sc_ah
->ah_opmode
!= NL80211_IFTYPE_MONITOR
)
140 } else if (ds
->ds_rxstat
.rs_status
!= 0) {
141 if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_CRC
)
142 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
143 if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_PHY
)
146 if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_DECRYPT
) {
147 *decrypt_error
= true;
148 } else if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_MIC
) {
149 if (ieee80211_is_ctl(fc
))
151 * Sometimes, we get invalid
152 * MIC failures on valid control frames.
153 * Remove these mic errors.
155 ds
->ds_rxstat
.rs_status
&= ~ATH9K_RXERR_MIC
;
157 rx_status
->flag
|= RX_FLAG_MMIC_ERROR
;
160 * Reject error frames with the exception of
161 * decryption and MIC failures. For monitor mode,
162 * we also ignore the CRC error.
164 if (sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_MONITOR
) {
165 if (ds
->ds_rxstat
.rs_status
&
166 ~(ATH9K_RXERR_DECRYPT
| ATH9K_RXERR_MIC
|
170 if (ds
->ds_rxstat
.rs_status
&
171 ~(ATH9K_RXERR_DECRYPT
| ATH9K_RXERR_MIC
)) {
177 ratecode
= ds
->ds_rxstat
.rs_rate
;
179 if (ratecode
& 0x80) {
181 rx_status
->flag
|= RX_FLAG_HT
;
182 if (ds
->ds_rxstat
.rs_flags
& ATH9K_RX_2040
)
183 rx_status
->flag
|= RX_FLAG_40MHZ
;
184 if (ds
->ds_rxstat
.rs_flags
& ATH9K_RX_GI
)
185 rx_status
->flag
|= RX_FLAG_SHORT_GI
;
186 rx_status
->rate_idx
= ratecode
& 0x7f;
188 int i
= 0, cur_band
, n_rates
;
189 struct ieee80211_hw
*hw
= sc
->hw
;
191 cur_band
= hw
->conf
.channel
->band
;
192 n_rates
= sc
->sbands
[cur_band
].n_bitrates
;
194 for (i
= 0; i
< n_rates
; i
++) {
195 if (sc
->sbands
[cur_band
].bitrates
[i
].hw_value
==
197 rx_status
->rate_idx
= i
;
201 if (sc
->sbands
[cur_band
].bitrates
[i
].hw_value_short
==
203 rx_status
->rate_idx
= i
;
204 rx_status
->flag
|= RX_FLAG_SHORTPRE
;
210 rx_status
->mactime
= ath_extend_tsf(sc
, ds
->ds_rxstat
.rs_tstamp
);
211 rx_status
->band
= sc
->hw
->conf
.channel
->band
;
212 rx_status
->freq
= sc
->hw
->conf
.channel
->center_freq
;
213 rx_status
->noise
= sc
->sc_ani
.sc_noise_floor
;
214 rx_status
->signal
= rx_status
->noise
+ ds
->ds_rxstat
.rs_rssi
;
215 rx_status
->antenna
= ds
->ds_rxstat
.rs_antenna
;
217 /* at 45 you will be able to use MCS 15 reliably. A more elaborate
218 * scheme can be used here but it requires tables of SNR/throughput for
219 * each possible mode used. */
220 rx_status
->qual
= ds
->ds_rxstat
.rs_rssi
* 100 / 45;
222 /* rssi can be more than 45 though, anything above that
223 * should be considered at 100% */
224 if (rx_status
->qual
> 100)
225 rx_status
->qual
= 100;
227 rx_status
->flag
|= RX_FLAG_TSFT
;
234 static void ath_opmode_init(struct ath_softc
*sc
)
236 struct ath_hal
*ah
= sc
->sc_ah
;
239 /* configure rx filter */
240 rfilt
= ath_calcrxfilter(sc
);
241 ath9k_hw_setrxfilter(ah
, rfilt
);
243 /* configure bssid mask */
244 if (ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
245 ath9k_hw_setbssidmask(ah
, sc
->sc_bssidmask
);
247 /* configure operational mode */
248 ath9k_hw_setopmode(ah
);
250 /* Handle any link-level address change. */
251 ath9k_hw_setmac(ah
, sc
->sc_myaddr
);
253 /* calculate and install multicast filter */
254 mfilt
[0] = mfilt
[1] = ~0;
255 ath9k_hw_setmcastfilter(ah
, mfilt
[0], mfilt
[1]);
258 int ath_rx_init(struct ath_softc
*sc
, int nbufs
)
265 spin_lock_init(&sc
->rx
.rxflushlock
);
266 sc
->sc_flags
&= ~SC_OP_RXFLUSH
;
267 spin_lock_init(&sc
->rx
.rxbuflock
);
269 sc
->rx
.bufsize
= roundup(IEEE80211_MAX_MPDU_LEN
,
273 DPRINTF(sc
, ATH_DBG_CONFIG
, "cachelsz %u rxbufsize %u\n",
274 sc
->sc_cachelsz
, sc
->rx
.bufsize
);
276 /* Initialize rx descriptors */
278 error
= ath_descdma_setup(sc
, &sc
->rx
.rxdma
, &sc
->rx
.rxbuf
,
281 DPRINTF(sc
, ATH_DBG_FATAL
,
282 "failed to allocate rx descriptors: %d\n", error
);
286 list_for_each_entry(bf
, &sc
->rx
.rxbuf
, list
) {
287 skb
= ath_rxbuf_alloc(sc
, sc
->rx
.bufsize
);
294 bf
->bf_buf_addr
= pci_map_single(sc
->pdev
, skb
->data
,
297 if (unlikely(pci_dma_mapping_error(sc
->pdev
,
299 dev_kfree_skb_any(skb
);
301 DPRINTF(sc
, ATH_DBG_CONFIG
,
302 "pci_dma_mapping_error() on RX init\n");
306 bf
->bf_dmacontext
= bf
->bf_buf_addr
;
308 sc
->rx
.rxlink
= NULL
;
318 void ath_rx_cleanup(struct ath_softc
*sc
)
323 list_for_each_entry(bf
, &sc
->rx
.rxbuf
, list
) {
329 if (sc
->rx
.rxdma
.dd_desc_len
!= 0)
330 ath_descdma_cleanup(sc
, &sc
->rx
.rxdma
, &sc
->rx
.rxbuf
);
334 * Calculate the receive filter according to the
335 * operating mode and state:
337 * o always accept unicast, broadcast, and multicast traffic
338 * o maintain current state of phy error reception (the hal
339 * may enable phy error frames for noise immunity work)
340 * o probe request frames are accepted only when operating in
341 * hostap, adhoc, or monitor modes
342 * o enable promiscuous mode according to the interface state
344 * - when operating in adhoc mode so the 802.11 layer creates
345 * node table entries for peers,
346 * - when operating in station mode for collecting rssi data when
347 * the station is otherwise quiet, or
348 * - when operating as a repeater so we see repeater-sta beacons
352 u32
ath_calcrxfilter(struct ath_softc
*sc
)
354 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
358 rfilt
= (ath9k_hw_getrxfilter(sc
->sc_ah
) & RX_FILTER_PRESERVE
)
359 | ATH9K_RX_FILTER_UCAST
| ATH9K_RX_FILTER_BCAST
360 | ATH9K_RX_FILTER_MCAST
;
362 /* If not a STA, enable processing of Probe Requests */
363 if (sc
->sc_ah
->ah_opmode
!= NL80211_IFTYPE_STATION
)
364 rfilt
|= ATH9K_RX_FILTER_PROBEREQ
;
366 /* Can't set HOSTAP into promiscous mode */
367 if (((sc
->sc_ah
->ah_opmode
!= NL80211_IFTYPE_AP
) &&
368 (sc
->rx
.rxfilter
& FIF_PROMISC_IN_BSS
)) ||
369 (sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_MONITOR
)) {
370 rfilt
|= ATH9K_RX_FILTER_PROM
;
371 /* ??? To prevent from sending ACK */
372 rfilt
&= ~ATH9K_RX_FILTER_UCAST
;
375 if (sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_STATION
||
376 sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_ADHOC
)
377 rfilt
|= ATH9K_RX_FILTER_BEACON
;
379 /* If in HOSTAP mode, want to enable reception of PSPOLL frames
381 if (sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_AP
)
382 rfilt
|= (ATH9K_RX_FILTER_BEACON
| ATH9K_RX_FILTER_PSPOLL
);
386 #undef RX_FILTER_PRESERVE
389 int ath_startrecv(struct ath_softc
*sc
)
391 struct ath_hal
*ah
= sc
->sc_ah
;
392 struct ath_buf
*bf
, *tbf
;
394 spin_lock_bh(&sc
->rx
.rxbuflock
);
395 if (list_empty(&sc
->rx
.rxbuf
))
398 sc
->rx
.rxlink
= NULL
;
399 list_for_each_entry_safe(bf
, tbf
, &sc
->rx
.rxbuf
, list
) {
400 ath_rx_buf_link(sc
, bf
);
403 /* We could have deleted elements so the list may be empty now */
404 if (list_empty(&sc
->rx
.rxbuf
))
407 bf
= list_first_entry(&sc
->rx
.rxbuf
, struct ath_buf
, list
);
408 ath9k_hw_putrxbuf(ah
, bf
->bf_daddr
);
412 spin_unlock_bh(&sc
->rx
.rxbuflock
);
414 ath9k_hw_startpcureceive(ah
);
419 bool ath_stoprecv(struct ath_softc
*sc
)
421 struct ath_hal
*ah
= sc
->sc_ah
;
424 ath9k_hw_stoppcurecv(ah
);
425 ath9k_hw_setrxfilter(ah
, 0);
426 stopped
= ath9k_hw_stopdmarecv(ah
);
427 mdelay(3); /* 3ms is long enough for 1 frame */
428 sc
->rx
.rxlink
= NULL
;
433 void ath_flushrecv(struct ath_softc
*sc
)
435 spin_lock_bh(&sc
->rx
.rxflushlock
);
436 sc
->sc_flags
|= SC_OP_RXFLUSH
;
437 ath_rx_tasklet(sc
, 1);
438 sc
->sc_flags
&= ~SC_OP_RXFLUSH
;
439 spin_unlock_bh(&sc
->rx
.rxflushlock
);
442 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
)
444 #define PA2DESC(_sc, _pa) \
445 ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \
446 ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr)))
450 struct sk_buff
*skb
= NULL
, *requeue_skb
;
451 struct ieee80211_rx_status rx_status
;
452 struct ath_hal
*ah
= sc
->sc_ah
;
453 struct ieee80211_hdr
*hdr
;
454 int hdrlen
, padsize
, retval
;
455 bool decrypt_error
= false;
458 spin_lock_bh(&sc
->rx
.rxbuflock
);
461 /* If handling rx interrupt and flush is in progress => exit */
462 if ((sc
->sc_flags
& SC_OP_RXFLUSH
) && (flush
== 0))
465 if (list_empty(&sc
->rx
.rxbuf
)) {
466 sc
->rx
.rxlink
= NULL
;
470 bf
= list_first_entry(&sc
->rx
.rxbuf
, struct ath_buf
, list
);
474 * Must provide the virtual address of the current
475 * descriptor, the physical address, and the virtual
476 * address of the next descriptor in the h/w chain.
477 * This allows the HAL to look ahead to see if the
478 * hardware is done with a descriptor by checking the
479 * done bit in the following descriptor and the address
480 * of the current descriptor the DMA engine is working
481 * on. All this is necessary because of our use of
482 * a self-linked list to avoid rx overruns.
484 retval
= ath9k_hw_rxprocdesc(ah
, ds
,
486 PA2DESC(sc
, ds
->ds_link
),
488 if (retval
== -EINPROGRESS
) {
490 struct ath_desc
*tds
;
492 if (list_is_last(&bf
->list
, &sc
->rx
.rxbuf
)) {
493 sc
->rx
.rxlink
= NULL
;
497 tbf
= list_entry(bf
->list
.next
, struct ath_buf
, list
);
500 * On some hardware the descriptor status words could
501 * get corrupted, including the done bit. Because of
502 * this, check if the next descriptor's done bit is
505 * If the next descriptor's done bit is set, the current
506 * descriptor has been corrupted. Force s/w to discard
507 * this descriptor and continue...
511 retval
= ath9k_hw_rxprocdesc(ah
, tds
, tbf
->bf_daddr
,
512 PA2DESC(sc
, tds
->ds_link
), 0);
513 if (retval
== -EINPROGRESS
) {
523 * Synchronize the DMA transfer with CPU before
524 * 1. accessing the frame
525 * 2. requeueing the same buffer to h/w
527 pci_dma_sync_single_for_cpu(sc
->pdev
, bf
->bf_buf_addr
,
532 * If we're asked to flush receive queue, directly
533 * chain it back at the queue without processing it.
538 if (!ds
->ds_rxstat
.rs_datalen
)
541 /* The status portion of the descriptor could get corrupted. */
542 if (sc
->rx
.bufsize
< ds
->ds_rxstat
.rs_datalen
)
545 if (!ath_rx_prepare(skb
, ds
, &rx_status
, &decrypt_error
, sc
))
548 /* Ensure we always have an skb to requeue once we are done
549 * processing the current buffer's skb */
550 requeue_skb
= ath_rxbuf_alloc(sc
, sc
->rx
.bufsize
);
552 /* If there is no memory we ignore the current RX'd frame,
553 * tell hardware it can give us a new frame using the old
554 * skb and put it at the tail of the sc->rx.rxbuf list for
559 /* Unmap the frame */
560 pci_unmap_single(sc
->pdev
, bf
->bf_buf_addr
,
564 skb_put(skb
, ds
->ds_rxstat
.rs_datalen
);
565 skb
->protocol
= cpu_to_be16(ETH_P_CONTROL
);
567 /* see if any padding is done by the hw and remove it */
568 hdr
= (struct ieee80211_hdr
*)skb
->data
;
569 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
571 /* The MAC header is padded to have 32-bit boundary if the
572 * packet payload is non-zero. The general calculation for
573 * padsize would take into account odd header lengths:
574 * padsize = (4 - hdrlen % 4) % 4; However, since only
575 * even-length headers are used, padding can only be 0 or 2
576 * bytes and we can optimize this a bit. In addition, we must
577 * not try to remove padding from short control frames that do
578 * not have payload. */
579 padsize
= hdrlen
& 3;
580 if (padsize
&& hdrlen
>= 24) {
581 memmove(skb
->data
+ padsize
, skb
->data
, hdrlen
);
582 skb_pull(skb
, padsize
);
585 keyix
= ds
->ds_rxstat
.rs_keyix
;
587 if (!(keyix
== ATH9K_RXKEYIX_INVALID
) && !decrypt_error
) {
588 rx_status
.flag
|= RX_FLAG_DECRYPTED
;
589 } else if ((le16_to_cpu(hdr
->frame_control
) & IEEE80211_FCTL_PROTECTED
)
590 && !decrypt_error
&& skb
->len
>= hdrlen
+ 4) {
591 keyix
= skb
->data
[hdrlen
+ 3] >> 6;
593 if (test_bit(keyix
, sc
->sc_keymap
))
594 rx_status
.flag
|= RX_FLAG_DECRYPTED
;
597 /* Send the frame to mac80211 */
598 __ieee80211_rx(sc
->hw
, skb
, &rx_status
);
600 /* We will now give hardware our shiny new allocated skb */
601 bf
->bf_mpdu
= requeue_skb
;
602 bf
->bf_buf_addr
= pci_map_single(sc
->pdev
, requeue_skb
->data
,
605 if (unlikely(pci_dma_mapping_error(sc
->pdev
,
607 dev_kfree_skb_any(requeue_skb
);
609 DPRINTF(sc
, ATH_DBG_CONFIG
,
610 "pci_dma_mapping_error() on RX\n");
613 bf
->bf_dmacontext
= bf
->bf_buf_addr
;
616 * change the default rx antenna if rx diversity chooses the
617 * other antenna 3 times in a row.
619 if (sc
->rx
.defant
!= ds
->ds_rxstat
.rs_antenna
) {
620 if (++sc
->rx
.rxotherant
>= 3)
621 ath_setdefantenna(sc
, ds
->ds_rxstat
.rs_antenna
);
623 sc
->rx
.rxotherant
= 0;
626 list_move_tail(&bf
->list
, &sc
->rx
.rxbuf
);
627 ath_rx_buf_link(sc
, bf
);
630 spin_unlock_bh(&sc
->rx
.rxbuflock
);