2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol
[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
58 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
59 struct ath_atx_tid
*tid
,
60 struct list_head
*bf_head
);
61 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
62 struct list_head
*bf_q
,
63 int txok
, int sendbar
);
64 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
65 struct list_head
*head
);
66 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
);
68 /*********************/
69 /* Aggregation logic */
70 /*********************/
72 static int ath_aggr_query(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
74 struct ath_atx_tid
*tid
;
75 tid
= ATH_AN_2_TID(an
, tidno
);
77 if (tid
->state
& AGGR_ADDBA_COMPLETE
||
78 tid
->state
& AGGR_ADDBA_PROGRESS
)
84 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
86 struct ath_atx_ac
*ac
= tid
->ac
;
95 list_add_tail(&tid
->list
, &ac
->tid_q
);
101 list_add_tail(&ac
->list
, &txq
->axq_acq
);
104 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
106 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
108 spin_lock_bh(&txq
->axq_lock
);
110 spin_unlock_bh(&txq
->axq_lock
);
113 static void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
115 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
117 ASSERT(tid
->paused
> 0);
118 spin_lock_bh(&txq
->axq_lock
);
125 if (list_empty(&tid
->buf_q
))
128 ath_tx_queue_tid(txq
, tid
);
129 ath_txq_schedule(sc
, txq
);
131 spin_unlock_bh(&txq
->axq_lock
);
134 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
136 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
138 struct list_head bf_head
;
139 INIT_LIST_HEAD(&bf_head
);
141 ASSERT(tid
->paused
> 0);
142 spin_lock_bh(&txq
->axq_lock
);
146 if (tid
->paused
> 0) {
147 spin_unlock_bh(&txq
->axq_lock
);
151 while (!list_empty(&tid
->buf_q
)) {
152 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
153 ASSERT(!bf_isretried(bf
));
154 list_move_tail(&bf
->list
, &bf_head
);
155 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
158 spin_unlock_bh(&txq
->axq_lock
);
161 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
166 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
167 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
169 tid
->tx_buf
[cindex
] = NULL
;
171 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
172 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
173 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
177 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
182 if (bf_isretried(bf
))
185 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
186 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
188 ASSERT(tid
->tx_buf
[cindex
] == NULL
);
189 tid
->tx_buf
[cindex
] = bf
;
191 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
192 (ATH_TID_MAX_BUFS
- 1))) {
193 tid
->baw_tail
= cindex
;
194 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
199 * TODO: For frame(s) that are in the retry state, we will reuse the
200 * sequence number(s) without setting the retry bit. The
201 * alternative is to give up on these and BAR the receiver's window
204 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
205 struct ath_atx_tid
*tid
)
209 struct list_head bf_head
;
210 INIT_LIST_HEAD(&bf_head
);
213 if (list_empty(&tid
->buf_q
))
216 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
217 list_move_tail(&bf
->list
, &bf_head
);
219 if (bf_isretried(bf
))
220 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
222 spin_unlock(&txq
->axq_lock
);
223 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
224 spin_lock(&txq
->axq_lock
);
227 tid
->seq_next
= tid
->seq_start
;
228 tid
->baw_tail
= tid
->baw_head
;
231 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_buf
*bf
)
234 struct ieee80211_hdr
*hdr
;
236 bf
->bf_state
.bf_type
|= BUF_RETRY
;
240 hdr
= (struct ieee80211_hdr
*)skb
->data
;
241 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
244 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
248 spin_lock_bh(&sc
->tx
.txbuflock
);
249 ASSERT(!list_empty((&sc
->tx
.txbuf
)));
250 tbf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
251 list_del(&tbf
->list
);
252 spin_unlock_bh(&sc
->tx
.txbuflock
);
254 ATH_TXBUF_RESET(tbf
);
256 tbf
->bf_mpdu
= bf
->bf_mpdu
;
257 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
258 *(tbf
->bf_desc
) = *(bf
->bf_desc
);
259 tbf
->bf_state
= bf
->bf_state
;
260 tbf
->bf_dmacontext
= bf
->bf_dmacontext
;
265 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
266 struct ath_buf
*bf
, struct list_head
*bf_q
,
269 struct ath_node
*an
= NULL
;
271 struct ieee80211_sta
*sta
;
272 struct ieee80211_hdr
*hdr
;
273 struct ath_atx_tid
*tid
= NULL
;
274 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
275 struct ath_desc
*ds
= bf_last
->bf_desc
;
276 struct list_head bf_head
, bf_pending
;
278 u32 ba
[WME_BA_BMP_SIZE
>> 5];
279 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0;
281 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
282 hdr
= (struct ieee80211_hdr
*)skb
->data
;
286 sta
= ieee80211_find_sta(sc
->hw
, hdr
->addr1
);
292 an
= (struct ath_node
*)sta
->drv_priv
;
293 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
295 isaggr
= bf_isaggr(bf
);
296 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
298 if (isaggr
&& txok
) {
299 if (ATH_DS_TX_BA(ds
)) {
300 seq_st
= ATH_DS_BA_SEQ(ds
);
301 memcpy(ba
, ATH_DS_BA_BITMAP(ds
),
302 WME_BA_BMP_SIZE
>> 3);
305 * AR5416 can become deaf/mute when BA
306 * issue happens. Chip needs to be reset.
307 * But AP code may have sychronization issues
308 * when perform internal reset in this routine.
309 * Only enable reset in STA mode for now.
311 if (sc
->sc_ah
->ah_opmode
== NL80211_IFTYPE_STATION
)
316 INIT_LIST_HEAD(&bf_pending
);
317 INIT_LIST_HEAD(&bf_head
);
320 txfail
= txpending
= 0;
321 bf_next
= bf
->bf_next
;
323 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
324 /* transmit completion, subframe is
325 * acked by block ack */
326 } else if (!isaggr
&& txok
) {
327 /* transmit completion */
329 if (!(tid
->state
& AGGR_CLEANUP
) &&
330 ds
->ds_txstat
.ts_flags
!= ATH9K_TX_SW_ABORTED
) {
331 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
332 ath_tx_set_retry(sc
, bf
);
335 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
341 * cleanup in progress, just fail
342 * the un-acked sub-frames
348 if (bf_next
== NULL
) {
349 INIT_LIST_HEAD(&bf_head
);
351 ASSERT(!list_empty(bf_q
));
352 list_move_tail(&bf
->list
, &bf_head
);
357 * complete the acked-ones/xretried ones; update
360 spin_lock_bh(&txq
->axq_lock
);
361 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
362 spin_unlock_bh(&txq
->axq_lock
);
364 ath_tx_complete_buf(sc
, bf
, &bf_head
, !txfail
, sendbar
);
366 /* retry the un-acked ones */
367 if (bf
->bf_next
== NULL
&&
368 bf_last
->bf_status
& ATH_BUFSTATUS_STALE
) {
371 tbf
= ath_clone_txbuf(sc
, bf_last
);
372 ath9k_hw_cleartxdesc(sc
->sc_ah
, tbf
->bf_desc
);
373 list_add_tail(&tbf
->list
, &bf_head
);
376 * Clear descriptor status words for
379 ath9k_hw_cleartxdesc(sc
->sc_ah
, bf
->bf_desc
);
383 * Put this buffer to the temporary pending
384 * queue to retain ordering
386 list_splice_tail_init(&bf_head
, &bf_pending
);
392 if (tid
->state
& AGGR_CLEANUP
) {
393 if (tid
->baw_head
== tid
->baw_tail
) {
394 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
395 tid
->addba_exchangeattempts
= 0;
396 tid
->state
&= ~AGGR_CLEANUP
;
398 /* send buffered frames as singles */
399 ath_tx_flush_tid(sc
, tid
);
405 /* prepend un-acked frames to the beginning of the pending frame queue */
406 if (!list_empty(&bf_pending
)) {
407 spin_lock_bh(&txq
->axq_lock
);
408 list_splice(&bf_pending
, &tid
->buf_q
);
409 ath_tx_queue_tid(txq
, tid
);
410 spin_unlock_bh(&txq
->axq_lock
);
416 ath_reset(sc
, false);
419 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
420 struct ath_atx_tid
*tid
)
422 struct ath_rate_table
*rate_table
= sc
->cur_rate_table
;
424 struct ieee80211_tx_info
*tx_info
;
425 struct ieee80211_tx_rate
*rates
;
426 struct ath_tx_info_priv
*tx_info_priv
;
427 u32 max_4ms_framelen
, frmlen
;
428 u16 aggr_limit
, legacy
= 0, maxampdu
;
431 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
432 tx_info
= IEEE80211_SKB_CB(skb
);
433 rates
= tx_info
->control
.rates
;
434 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->rate_driver_data
[0];
437 * Find the lowest frame length among the rate series that will have a
438 * 4ms transmit duration.
439 * TODO - TXOP limit needs to be considered.
441 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
443 for (i
= 0; i
< 4; i
++) {
444 if (rates
[i
].count
) {
445 if (!WLAN_RC_PHY_HT(rate_table
->info
[rates
[i
].idx
].phy
)) {
450 frmlen
= rate_table
->info
[rates
[i
].idx
].max_4ms_framelen
;
451 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
456 * limit aggregate size by the minimum rate if rate selected is
457 * not a probe rate, if rate selected is a probe rate then
458 * avoid aggregation of this packet.
460 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
463 aggr_limit
= min(max_4ms_framelen
, (u32
)ATH_AMPDU_LIMIT_DEFAULT
);
466 * h/w can accept aggregates upto 16 bit lengths (65535).
467 * The IE, however can hold upto 65536, which shows up here
468 * as zero. Ignore 65536 since we are constrained by hw.
470 maxampdu
= tid
->an
->maxampdu
;
472 aggr_limit
= min(aggr_limit
, maxampdu
);
478 * Returns the number of delimiters to be added to
479 * meet the minimum required mpdudensity.
480 * caller should make sure that the rate is HT rate .
482 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
483 struct ath_buf
*bf
, u16 frmlen
)
485 struct ath_rate_table
*rt
= sc
->cur_rate_table
;
486 struct sk_buff
*skb
= bf
->bf_mpdu
;
487 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
488 u32 nsymbits
, nsymbols
, mpdudensity
;
491 int width
, half_gi
, ndelim
, mindelim
;
493 /* Select standard number of delimiters based on frame length alone */
494 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
497 * If encryption enabled, hardware requires some more padding between
499 * TODO - this could be improved to be dependent on the rate.
500 * The hardware can keep up at lower rates, but not higher rates
502 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
503 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
506 * Convert desired mpdu density from microeconds to bytes based
507 * on highest rate in rate series (i.e. first rate) to determine
508 * required minimum length for subframe. Take into account
509 * whether high rate is 20 or 40Mhz and half or full GI.
511 mpdudensity
= tid
->an
->mpdudensity
;
514 * If there is no mpdu density restriction, no further calculation
517 if (mpdudensity
== 0)
520 rix
= tx_info
->control
.rates
[0].idx
;
521 flags
= tx_info
->control
.rates
[0].flags
;
522 rc
= rt
->info
[rix
].ratecode
;
523 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
524 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
527 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity
);
529 nsymbols
= NUM_SYMBOLS_PER_USEC(mpdudensity
);
534 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
535 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
537 if (frmlen
< minlen
) {
538 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
539 ndelim
= max(mindelim
, ndelim
);
545 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
546 struct ath_atx_tid
*tid
,
547 struct list_head
*bf_q
)
549 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
550 struct ath_buf
*bf
, *bf_first
, *bf_prev
= NULL
;
551 int rl
= 0, nframes
= 0, ndelim
, prev_al
= 0;
552 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
553 al_delta
, h_baw
= tid
->baw_size
/ 2;
554 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
556 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
559 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
561 /* do not step over block-ack window */
562 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
563 status
= ATH_AGGR_BAW_CLOSED
;
568 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
572 /* do not exceed aggregation limit */
573 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
576 (aggr_limit
< (al
+ bpad
+ al_delta
+ prev_al
))) {
577 status
= ATH_AGGR_LIMITED
;
581 /* do not exceed subframe limit */
582 if (nframes
>= min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
583 status
= ATH_AGGR_LIMITED
;
588 /* add padding for previous frame to aggregation length */
589 al
+= bpad
+ al_delta
;
592 * Get the delimiters needed to meet the MPDU
593 * density for this node.
595 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, bf
->bf_frmlen
);
596 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
599 bf
->bf_desc
->ds_link
= 0;
601 /* link buffers of this frame to the aggregate */
602 ath_tx_addto_baw(sc
, tid
, bf
);
603 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
, bf
->bf_desc
, ndelim
);
604 list_move_tail(&bf
->list
, bf_q
);
606 bf_prev
->bf_next
= bf
;
607 bf_prev
->bf_desc
->ds_link
= bf
->bf_daddr
;
610 } while (!list_empty(&tid
->buf_q
));
612 bf_first
->bf_al
= al
;
613 bf_first
->bf_nframes
= nframes
;
619 static void ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
620 struct ath_atx_tid
*tid
)
623 enum ATH_AGGR_STATUS status
;
624 struct list_head bf_q
;
627 if (list_empty(&tid
->buf_q
))
630 INIT_LIST_HEAD(&bf_q
);
632 status
= ath_tx_form_aggr(sc
, tid
, &bf_q
);
635 * no frames picked up to be aggregated;
636 * block-ack window is not open.
638 if (list_empty(&bf_q
))
641 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
642 bf
->bf_lastbf
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
644 /* if only one frame, send as non-aggregate */
645 if (bf
->bf_nframes
== 1) {
646 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
647 ath9k_hw_clr11n_aggr(sc
->sc_ah
, bf
->bf_desc
);
648 ath_buf_set_rate(sc
, bf
);
649 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
653 /* setup first desc of aggregate */
654 bf
->bf_state
.bf_type
|= BUF_AGGR
;
655 ath_buf_set_rate(sc
, bf
);
656 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
658 /* anchor last desc of aggregate */
659 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, bf
->bf_lastbf
->bf_desc
);
661 txq
->axq_aggr_depth
++;
662 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
664 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
665 status
!= ATH_AGGR_BAW_CLOSED
);
668 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
671 struct ath_atx_tid
*txtid
;
674 an
= (struct ath_node
*)sta
->drv_priv
;
676 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
677 txtid
= ATH_AN_2_TID(an
, tid
);
678 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
679 ath_tx_pause_tid(sc
, txtid
);
680 *ssn
= txtid
->seq_start
;
686 int ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
688 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
689 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
690 struct ath_txq
*txq
= &sc
->tx
.txq
[txtid
->ac
->qnum
];
692 struct list_head bf_head
;
693 INIT_LIST_HEAD(&bf_head
);
695 if (txtid
->state
& AGGR_CLEANUP
)
698 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
699 txtid
->addba_exchangeattempts
= 0;
703 ath_tx_pause_tid(sc
, txtid
);
705 /* drop all software retried frames and mark this TID */
706 spin_lock_bh(&txq
->axq_lock
);
707 while (!list_empty(&txtid
->buf_q
)) {
708 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
709 if (!bf_isretried(bf
)) {
711 * NB: it's based on the assumption that
712 * software retried frame will always stay
713 * at the head of software queue.
717 list_move_tail(&bf
->list
, &bf_head
);
718 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
719 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
721 spin_unlock_bh(&txq
->axq_lock
);
723 if (txtid
->baw_head
!= txtid
->baw_tail
) {
724 txtid
->state
|= AGGR_CLEANUP
;
726 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
727 txtid
->addba_exchangeattempts
= 0;
728 ath_tx_flush_tid(sc
, txtid
);
734 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
736 struct ath_atx_tid
*txtid
;
739 an
= (struct ath_node
*)sta
->drv_priv
;
741 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
742 txtid
= ATH_AN_2_TID(an
, tid
);
744 IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
745 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
746 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
747 ath_tx_resume_tid(sc
, txtid
);
751 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
753 struct ath_atx_tid
*txtid
;
755 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
758 txtid
= ATH_AN_2_TID(an
, tidno
);
760 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
761 if (!(txtid
->state
& AGGR_ADDBA_PROGRESS
) &&
762 (txtid
->addba_exchangeattempts
< ADDBA_EXCHANGE_ATTEMPTS
)) {
763 txtid
->addba_exchangeattempts
++;
771 /********************/
772 /* Queue Management */
773 /********************/
775 static u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
)
777 return sc
->tx
.txq
[qnum
].axq_depth
;
780 static void ath_get_beaconconfig(struct ath_softc
*sc
, int if_id
,
781 struct ath_beacon_config
*conf
)
783 struct ieee80211_hw
*hw
= sc
->hw
;
785 /* fill in beacon config data */
787 conf
->beacon_interval
= hw
->conf
.beacon_int
;
788 conf
->listen_interval
= 100;
789 conf
->dtim_count
= 1;
790 conf
->bmiss_timeout
= ATH_DEFAULT_BMISS_LIMIT
* conf
->listen_interval
;
793 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
796 struct ath_atx_ac
*ac
, *ac_tmp
;
797 struct ath_atx_tid
*tid
, *tid_tmp
;
799 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
802 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
803 list_del(&tid
->list
);
805 ath_tid_drain(sc
, txq
, tid
);
810 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
812 struct ath_hal
*ah
= sc
->sc_ah
;
813 struct ath9k_tx_queue_info qi
;
816 memset(&qi
, 0, sizeof(qi
));
817 qi
.tqi_subtype
= subtype
;
818 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
819 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
820 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
821 qi
.tqi_physCompBuf
= 0;
824 * Enable interrupts only for EOL and DESC conditions.
825 * We mark tx descriptors to receive a DESC interrupt
826 * when a tx queue gets deep; otherwise waiting for the
827 * EOL to reap descriptors. Note that this is done to
828 * reduce interrupt load and this only defers reaping
829 * descriptors, never transmitting frames. Aside from
830 * reducing interrupts this also permits more concurrency.
831 * The only potential downside is if the tx queue backs
832 * up in which case the top half of the kernel may backup
833 * due to a lack of tx descriptors.
835 * The UAPSD queue is an exception, since we take a desc-
836 * based intr on the EOSP frames.
838 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
839 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
841 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
842 TXQ_FLAG_TXDESCINT_ENABLE
;
843 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
846 * NB: don't print a message, this happens
847 * normally on parts with too few tx queues
851 if (qnum
>= ARRAY_SIZE(sc
->tx
.txq
)) {
852 DPRINTF(sc
, ATH_DBG_FATAL
,
853 "qnum %u out of range, max %u!\n",
854 qnum
, (unsigned int)ARRAY_SIZE(sc
->tx
.txq
));
855 ath9k_hw_releasetxqueue(ah
, qnum
);
858 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
859 struct ath_txq
*txq
= &sc
->tx
.txq
[qnum
];
861 txq
->axq_qnum
= qnum
;
862 txq
->axq_link
= NULL
;
863 INIT_LIST_HEAD(&txq
->axq_q
);
864 INIT_LIST_HEAD(&txq
->axq_acq
);
865 spin_lock_init(&txq
->axq_lock
);
867 txq
->axq_aggr_depth
= 0;
868 txq
->axq_totalqueued
= 0;
869 txq
->axq_linkbuf
= NULL
;
870 sc
->tx
.txqsetup
|= 1<<qnum
;
872 return &sc
->tx
.txq
[qnum
];
875 static int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
880 case ATH9K_TX_QUEUE_DATA
:
881 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
882 DPRINTF(sc
, ATH_DBG_FATAL
,
883 "HAL AC %u out of range, max %zu!\n",
884 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
887 qnum
= sc
->tx
.hwq_map
[haltype
];
889 case ATH9K_TX_QUEUE_BEACON
:
890 qnum
= sc
->beacon
.beaconq
;
892 case ATH9K_TX_QUEUE_CAB
:
893 qnum
= sc
->beacon
.cabq
->axq_qnum
;
901 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
)
903 struct ath_txq
*txq
= NULL
;
906 qnum
= ath_get_hal_qnum(skb_get_queue_mapping(skb
), sc
);
907 txq
= &sc
->tx
.txq
[qnum
];
909 spin_lock_bh(&txq
->axq_lock
);
911 if (txq
->axq_depth
>= (ATH_TXBUF
- 20)) {
912 DPRINTF(sc
, ATH_DBG_FATAL
,
913 "TX queue: %d is full, depth: %d\n",
914 qnum
, txq
->axq_depth
);
915 ieee80211_stop_queue(sc
->hw
, skb_get_queue_mapping(skb
));
917 spin_unlock_bh(&txq
->axq_lock
);
921 spin_unlock_bh(&txq
->axq_lock
);
926 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
927 struct ath9k_tx_queue_info
*qinfo
)
929 struct ath_hal
*ah
= sc
->sc_ah
;
931 struct ath9k_tx_queue_info qi
;
933 if (qnum
== sc
->beacon
.beaconq
) {
935 * XXX: for beacon queue, we just save the parameter.
936 * It will be picked up by ath_beaconq_config when
939 sc
->beacon
.beacon_qi
= *qinfo
;
943 ASSERT(sc
->tx
.txq
[qnum
].axq_qnum
== qnum
);
945 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
946 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
947 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
948 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
949 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
950 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
952 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
953 DPRINTF(sc
, ATH_DBG_FATAL
,
954 "Unable to update hardware queue %u!\n", qnum
);
957 ath9k_hw_resettxqueue(ah
, qnum
);
963 int ath_cabq_update(struct ath_softc
*sc
)
965 struct ath9k_tx_queue_info qi
;
966 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
967 struct ath_beacon_config conf
;
969 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
971 * Ensure the readytime % is within the bounds.
973 if (sc
->sc_config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
974 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
975 else if (sc
->sc_config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
976 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
978 ath_get_beaconconfig(sc
, ATH_IF_ID_ANY
, &conf
);
980 (conf
.beacon_interval
* sc
->sc_config
.cabqReadytime
) / 100;
981 ath_txq_update(sc
, qnum
, &qi
);
987 * Drain a given TX queue (could be Beacon or Data)
989 * This assumes output has been stopped and
990 * we do not need to block ath_tx_tasklet.
992 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
, bool retry_tx
)
994 struct ath_buf
*bf
, *lastbf
;
995 struct list_head bf_head
;
997 INIT_LIST_HEAD(&bf_head
);
1000 spin_lock_bh(&txq
->axq_lock
);
1002 if (list_empty(&txq
->axq_q
)) {
1003 txq
->axq_link
= NULL
;
1004 txq
->axq_linkbuf
= NULL
;
1005 spin_unlock_bh(&txq
->axq_lock
);
1009 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
1011 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
1012 list_del(&bf
->list
);
1013 spin_unlock_bh(&txq
->axq_lock
);
1015 spin_lock_bh(&sc
->tx
.txbuflock
);
1016 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
1017 spin_unlock_bh(&sc
->tx
.txbuflock
);
1021 lastbf
= bf
->bf_lastbf
;
1023 lastbf
->bf_desc
->ds_txstat
.ts_flags
=
1024 ATH9K_TX_SW_ABORTED
;
1026 /* remove ath_buf's of the same mpdu from txq */
1027 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
1030 spin_unlock_bh(&txq
->axq_lock
);
1033 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, 0);
1035 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
1038 /* flush any pending frames if aggregation is enabled */
1039 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
1041 spin_lock_bh(&txq
->axq_lock
);
1042 ath_txq_drain_pending_buffers(sc
, txq
);
1043 spin_unlock_bh(&txq
->axq_lock
);
1048 void ath_drain_all_txq(struct ath_softc
*sc
, bool retry_tx
)
1050 struct ath_hal
*ah
= sc
->sc_ah
;
1051 struct ath_txq
*txq
;
1054 if (sc
->sc_flags
& SC_OP_INVALID
)
1057 /* Stop beacon queue */
1058 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
1060 /* Stop data queues */
1061 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1062 if (ATH_TXQ_SETUP(sc
, i
)) {
1063 txq
= &sc
->tx
.txq
[i
];
1064 ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1065 npend
+= ath9k_hw_numtxpending(ah
, txq
->axq_qnum
);
1072 DPRINTF(sc
, ATH_DBG_XMIT
, "Unable to stop TxDMA. Reset HAL!\n");
1074 spin_lock_bh(&sc
->sc_resetlock
);
1075 r
= ath9k_hw_reset(ah
, sc
->sc_ah
->ah_curchan
, true);
1077 DPRINTF(sc
, ATH_DBG_FATAL
,
1078 "Unable to reset hardware; reset status %u\n",
1080 spin_unlock_bh(&sc
->sc_resetlock
);
1083 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1084 if (ATH_TXQ_SETUP(sc
, i
))
1085 ath_draintxq(sc
, &sc
->tx
.txq
[i
], retry_tx
);
1089 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1091 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1092 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1095 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1097 struct ath_atx_ac
*ac
;
1098 struct ath_atx_tid
*tid
;
1100 if (list_empty(&txq
->axq_acq
))
1103 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
1104 list_del(&ac
->list
);
1108 if (list_empty(&ac
->tid_q
))
1111 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
1112 list_del(&tid
->list
);
1118 if ((txq
->axq_depth
% 2) == 0)
1119 ath_tx_sched_aggr(sc
, txq
, tid
);
1122 * add tid to round-robin queue if more frames
1123 * are pending for the tid
1125 if (!list_empty(&tid
->buf_q
))
1126 ath_tx_queue_tid(txq
, tid
);
1129 } while (!list_empty(&ac
->tid_q
));
1131 if (!list_empty(&ac
->tid_q
)) {
1134 list_add_tail(&ac
->list
, &txq
->axq_acq
);
1139 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
1141 struct ath_txq
*txq
;
1143 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
1144 DPRINTF(sc
, ATH_DBG_FATAL
,
1145 "HAL AC %u out of range, max %zu!\n",
1146 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
1149 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
1151 sc
->tx
.hwq_map
[haltype
] = txq
->axq_qnum
;
1162 * Insert a chain of ath_buf (descriptors) on a txq and
1163 * assume the descriptors are already chained together by caller.
1165 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1166 struct list_head
*head
)
1168 struct ath_hal
*ah
= sc
->sc_ah
;
1172 * Insert the frame on the outbound list and
1173 * pass it on to the hardware.
1176 if (list_empty(head
))
1179 bf
= list_first_entry(head
, struct ath_buf
, list
);
1181 list_splice_tail_init(head
, &txq
->axq_q
);
1183 txq
->axq_totalqueued
++;
1184 txq
->axq_linkbuf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
1186 DPRINTF(sc
, ATH_DBG_QUEUE
,
1187 "qnum: %d, txq depth: %d\n", txq
->axq_qnum
, txq
->axq_depth
);
1189 if (txq
->axq_link
== NULL
) {
1190 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1191 DPRINTF(sc
, ATH_DBG_XMIT
,
1192 "TXDP[%u] = %llx (%p)\n",
1193 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
1195 *txq
->axq_link
= bf
->bf_daddr
;
1196 DPRINTF(sc
, ATH_DBG_XMIT
, "link[%u] (%p)=%llx (%p)\n",
1197 txq
->axq_qnum
, txq
->axq_link
,
1198 ito64(bf
->bf_daddr
), bf
->bf_desc
);
1200 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
1201 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
1204 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
1206 struct ath_buf
*bf
= NULL
;
1208 spin_lock_bh(&sc
->tx
.txbuflock
);
1210 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
1211 spin_unlock_bh(&sc
->tx
.txbuflock
);
1215 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
1216 list_del(&bf
->list
);
1218 spin_unlock_bh(&sc
->tx
.txbuflock
);
1223 static void ath_tx_send_ampdu(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
1224 struct list_head
*bf_head
,
1225 struct ath_tx_control
*txctl
)
1229 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1230 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1233 * Do not queue to h/w when any of the following conditions is true:
1234 * - there are pending frames in software queue
1235 * - the TID is currently paused for ADDBA/BAR request
1236 * - seqno is not within block-ack window
1237 * - h/w queue depth exceeds low water mark
1239 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1240 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1241 txctl
->txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1243 * Add this frame to software queue for scheduling later
1246 list_move_tail(&bf
->list
, &tid
->buf_q
);
1247 ath_tx_queue_tid(txctl
->txq
, tid
);
1251 /* Add sub-frame to BAW */
1252 ath_tx_addto_baw(sc
, tid
, bf
);
1254 /* Queue to h/w without aggregation */
1257 ath_buf_set_rate(sc
, bf
);
1258 ath_tx_txqaddbuf(sc
, txctl
->txq
, bf_head
);
1261 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1262 struct ath_atx_tid
*tid
,
1263 struct list_head
*bf_head
)
1267 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1268 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
;
1270 /* update starting sequence number for subsequent ADDBA request */
1271 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
1275 ath_buf_set_rate(sc
, bf
);
1276 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
1279 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1281 struct ieee80211_hdr
*hdr
;
1282 enum ath9k_pkt_type htype
;
1285 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1286 fc
= hdr
->frame_control
;
1288 if (ieee80211_is_beacon(fc
))
1289 htype
= ATH9K_PKT_TYPE_BEACON
;
1290 else if (ieee80211_is_probe_resp(fc
))
1291 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
1292 else if (ieee80211_is_atim(fc
))
1293 htype
= ATH9K_PKT_TYPE_ATIM
;
1294 else if (ieee80211_is_pspoll(fc
))
1295 htype
= ATH9K_PKT_TYPE_PSPOLL
;
1297 htype
= ATH9K_PKT_TYPE_NORMAL
;
1302 static bool is_pae(struct sk_buff
*skb
)
1304 struct ieee80211_hdr
*hdr
;
1307 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1308 fc
= hdr
->frame_control
;
1310 if (ieee80211_is_data(fc
)) {
1311 if (ieee80211_is_nullfunc(fc
) ||
1312 /* Port Access Entity (IEEE 802.1X) */
1313 (skb
->protocol
== cpu_to_be16(ETH_P_PAE
))) {
1321 static int get_hw_crypto_keytype(struct sk_buff
*skb
)
1323 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1325 if (tx_info
->control
.hw_key
) {
1326 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
1327 return ATH9K_KEY_TYPE_WEP
;
1328 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
1329 return ATH9K_KEY_TYPE_TKIP
;
1330 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
1331 return ATH9K_KEY_TYPE_AES
;
1334 return ATH9K_KEY_TYPE_CLEAR
;
1337 static void assign_aggr_tid_seqno(struct sk_buff
*skb
,
1340 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1341 struct ieee80211_hdr
*hdr
;
1342 struct ath_node
*an
;
1343 struct ath_atx_tid
*tid
;
1347 if (!tx_info
->control
.sta
)
1350 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1351 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1352 fc
= hdr
->frame_control
;
1354 if (ieee80211_is_data_qos(fc
)) {
1355 qc
= ieee80211_get_qos_ctl(hdr
);
1356 bf
->bf_tidno
= qc
[0] & 0xf;
1360 * For HT capable stations, we save tidno for later use.
1361 * We also override seqno set by upper layer with the one
1362 * in tx aggregation state.
1364 * If fragmentation is on, the sequence number is
1365 * not overridden, since it has been
1366 * incremented by the fragmentation routine.
1368 * FIXME: check if the fragmentation threshold exceeds
1371 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1372 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<<
1373 IEEE80211_SEQ_SEQ_SHIFT
);
1374 bf
->bf_seqno
= tid
->seq_next
;
1375 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
1378 static int setup_tx_flags(struct ath_softc
*sc
, struct sk_buff
*skb
,
1379 struct ath_txq
*txq
)
1381 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1384 flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
1385 flags
|= ATH9K_TXDESC_INTREQ
;
1387 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1388 flags
|= ATH9K_TXDESC_NOACK
;
1395 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1396 * width - 0 for 20 MHz, 1 for 40 MHz
1397 * half_gi - to use 4us v/s 3.6 us for symbol time
1399 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, struct ath_buf
*bf
,
1400 int width
, int half_gi
, bool shortPreamble
)
1402 struct ath_rate_table
*rate_table
= sc
->cur_rate_table
;
1403 u32 nbits
, nsymbits
, duration
, nsymbols
;
1405 int streams
, pktlen
;
1407 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
1408 rc
= rate_table
->info
[rix
].ratecode
;
1410 /* for legacy rates, use old function to compute packet duration */
1411 if (!IS_HT_RATE(rc
))
1412 return ath9k_hw_computetxtime(sc
->sc_ah
, rate_table
, pktlen
,
1413 rix
, shortPreamble
);
1415 /* find number of symbols: PLCP + data */
1416 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
1417 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
1418 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
1421 duration
= SYMBOL_TIME(nsymbols
);
1423 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
1425 /* addup duration for legacy/ht training and signal fields */
1426 streams
= HT_RC_2_STREAMS(rc
);
1427 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1432 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
1434 struct ath_rate_table
*rt
= sc
->cur_rate_table
;
1435 struct ath9k_11n_rate_series series
[4];
1436 struct sk_buff
*skb
;
1437 struct ieee80211_tx_info
*tx_info
;
1438 struct ieee80211_tx_rate
*rates
;
1439 struct ieee80211_hdr
*hdr
;
1441 u8 rix
= 0, ctsrate
= 0;
1444 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
1446 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1447 tx_info
= IEEE80211_SKB_CB(skb
);
1448 rates
= tx_info
->control
.rates
;
1449 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1450 is_pspoll
= ieee80211_is_pspoll(hdr
->frame_control
);
1453 * We check if Short Preamble is needed for the CTS rate by
1454 * checking the BSS's global flag.
1455 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1457 if (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
)
1458 ctsrate
= rt
->info
[tx_info
->control
.rts_cts_rate_idx
].ratecode
|
1459 rt
->info
[tx_info
->control
.rts_cts_rate_idx
].short_preamble
;
1461 ctsrate
= rt
->info
[tx_info
->control
.rts_cts_rate_idx
].ratecode
;
1464 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1465 * Check the first rate in the series to decide whether RTS/CTS
1466 * or CTS-to-self has to be used.
1468 if (rates
[0].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
)
1469 flags
= ATH9K_TXDESC_CTSENA
;
1470 else if (rates
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
1471 flags
= ATH9K_TXDESC_RTSENA
;
1473 /* FIXME: Handle aggregation protection */
1474 if (sc
->sc_config
.ath_aggr_prot
&&
1475 (!bf_isaggr(bf
) || (bf_isaggr(bf
) && bf
->bf_al
< 8192))) {
1476 flags
= ATH9K_TXDESC_RTSENA
;
1479 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1480 if (bf_isaggr(bf
) && (bf
->bf_al
> sc
->sc_ah
->ah_caps
.rts_aggr_limit
))
1481 flags
&= ~(ATH9K_TXDESC_RTSENA
);
1483 for (i
= 0; i
< 4; i
++) {
1484 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
1488 series
[i
].Tries
= rates
[i
].count
;
1489 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
1491 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
1492 series
[i
].Rate
= rt
->info
[rix
].ratecode
|
1493 rt
->info
[rix
].short_preamble
;
1495 series
[i
].Rate
= rt
->info
[rix
].ratecode
;
1497 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
1498 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1499 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
1500 series
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
1501 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
1502 series
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
1504 series
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, bf
,
1505 (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) != 0,
1506 (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
),
1507 (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
));
1510 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1511 ath9k_hw_set11n_ratescenario(sc
->sc_ah
, bf
->bf_desc
,
1512 bf
->bf_lastbf
->bf_desc
,
1513 !is_pspoll
, ctsrate
,
1514 0, series
, 4, flags
);
1516 if (sc
->sc_config
.ath_aggr_prot
&& flags
)
1517 ath9k_hw_set11n_burstduration(sc
->sc_ah
, bf
->bf_desc
, 8192);
1520 static int ath_tx_setup_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
,
1521 struct sk_buff
*skb
,
1522 struct ath_tx_control
*txctl
)
1524 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1525 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1526 struct ath_tx_info_priv
*tx_info_priv
;
1530 tx_info_priv
= kzalloc(sizeof(*tx_info_priv
), GFP_ATOMIC
);
1531 if (unlikely(!tx_info_priv
))
1533 tx_info
->rate_driver_data
[0] = tx_info_priv
;
1534 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1535 fc
= hdr
->frame_control
;
1537 ATH_TXBUF_RESET(bf
);
1539 bf
->bf_frmlen
= skb
->len
+ FCS_LEN
- (hdrlen
& 3);
1541 if ((conf_is_ht(&sc
->hw
->conf
) && !is_pae(skb
) &&
1542 (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)))
1543 bf
->bf_state
.bf_type
|= BUF_HT
;
1545 bf
->bf_flags
= setup_tx_flags(sc
, skb
, txctl
->txq
);
1547 bf
->bf_keytype
= get_hw_crypto_keytype(skb
);
1548 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
) {
1549 bf
->bf_frmlen
+= tx_info
->control
.hw_key
->icv_len
;
1550 bf
->bf_keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
1552 bf
->bf_keyix
= ATH9K_TXKEYIX_INVALID
;
1555 if (ieee80211_is_data_qos(fc
) && (sc
->sc_flags
& SC_OP_TXAGGR
))
1556 assign_aggr_tid_seqno(skb
, bf
);
1560 bf
->bf_dmacontext
= dma_map_single(sc
->dev
, skb
->data
,
1561 skb
->len
, DMA_TO_DEVICE
);
1562 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_dmacontext
))) {
1564 DPRINTF(sc
, ATH_DBG_CONFIG
,
1565 "dma_mapping_error() on TX\n");
1569 bf
->bf_buf_addr
= bf
->bf_dmacontext
;
1573 /* FIXME: tx power */
1574 static void ath_tx_start_dma(struct ath_softc
*sc
, struct ath_buf
*bf
,
1575 struct ath_tx_control
*txctl
)
1577 struct sk_buff
*skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1578 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1579 struct ath_node
*an
= NULL
;
1580 struct list_head bf_head
;
1581 struct ath_desc
*ds
;
1582 struct ath_atx_tid
*tid
;
1583 struct ath_hal
*ah
= sc
->sc_ah
;
1586 frm_type
= get_hw_packet_type(skb
);
1588 INIT_LIST_HEAD(&bf_head
);
1589 list_add_tail(&bf
->list
, &bf_head
);
1593 ds
->ds_data
= bf
->bf_buf_addr
;
1595 ath9k_hw_set11n_txdesc(ah
, ds
, bf
->bf_frmlen
, frm_type
, MAX_RATE_POWER
,
1596 bf
->bf_keyix
, bf
->bf_keytype
, bf
->bf_flags
);
1598 ath9k_hw_filltxdesc(ah
, ds
,
1599 skb
->len
, /* segment length */
1600 true, /* first segment */
1601 true, /* last segment */
1602 ds
); /* first descriptor */
1604 spin_lock_bh(&txctl
->txq
->axq_lock
);
1606 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
) &&
1607 tx_info
->control
.sta
) {
1608 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1609 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1611 if (ath_aggr_query(sc
, an
, bf
->bf_tidno
)) {
1613 * Try aggregation if it's a unicast data frame
1614 * and the destination is HT capable.
1616 ath_tx_send_ampdu(sc
, tid
, &bf_head
, txctl
);
1619 * Send this frame as regular when ADDBA
1620 * exchange is neither complete nor pending.
1622 ath_tx_send_normal(sc
, txctl
->txq
,
1629 ath_buf_set_rate(sc
, bf
);
1630 ath_tx_txqaddbuf(sc
, txctl
->txq
, &bf_head
);
1633 spin_unlock_bh(&txctl
->txq
->axq_lock
);
1636 /* Upon failure caller should free skb */
1637 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
,
1638 struct ath_tx_control
*txctl
)
1643 bf
= ath_tx_get_buffer(sc
);
1645 DPRINTF(sc
, ATH_DBG_XMIT
, "TX buffers are full\n");
1649 r
= ath_tx_setup_buffer(sc
, bf
, skb
, txctl
);
1651 struct ath_txq
*txq
= txctl
->txq
;
1653 DPRINTF(sc
, ATH_DBG_FATAL
, "TX mem alloc failure\n");
1655 /* upon ath_tx_processq() this TX queue will be resumed, we
1656 * guarantee this will happen by knowing beforehand that
1657 * we will at least have to run TX completionon one buffer
1659 spin_lock_bh(&txq
->axq_lock
);
1660 if (ath_txq_depth(sc
, txq
->axq_qnum
) > 1) {
1661 ieee80211_stop_queue(sc
->hw
,
1662 skb_get_queue_mapping(skb
));
1665 spin_unlock_bh(&txq
->axq_lock
);
1667 spin_lock_bh(&sc
->tx
.txbuflock
);
1668 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
1669 spin_unlock_bh(&sc
->tx
.txbuflock
);
1674 ath_tx_start_dma(sc
, bf
, txctl
);
1679 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
)
1681 int hdrlen
, padsize
;
1682 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1683 struct ath_tx_control txctl
;
1685 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
1688 * As a temporary workaround, assign seq# here; this will likely need
1689 * to be cleaned up to work better with Beacon transmission and virtual
1692 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
1693 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
1694 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
1695 sc
->tx
.seq_no
+= 0x10;
1696 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
1697 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
1700 /* Add the padding after the header if this is not already done */
1701 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1703 padsize
= hdrlen
% 4;
1704 if (skb_headroom(skb
) < padsize
) {
1705 DPRINTF(sc
, ATH_DBG_XMIT
, "TX CABQ padding failed\n");
1706 dev_kfree_skb_any(skb
);
1709 skb_push(skb
, padsize
);
1710 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
1713 txctl
.txq
= sc
->beacon
.cabq
;
1715 DPRINTF(sc
, ATH_DBG_XMIT
, "transmitting CABQ packet, skb: %p\n", skb
);
1717 if (ath_tx_start(sc
, skb
, &txctl
) != 0) {
1718 DPRINTF(sc
, ATH_DBG_XMIT
, "CABQ TX failed\n");
1724 dev_kfree_skb_any(skb
);
1731 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
1732 struct ath_xmit_status
*tx_status
)
1734 struct ieee80211_hw
*hw
= sc
->hw
;
1735 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1736 struct ath_tx_info_priv
*tx_info_priv
= ATH_TX_INFO_PRIV(tx_info
);
1737 int hdrlen
, padsize
;
1739 DPRINTF(sc
, ATH_DBG_XMIT
, "TX complete: skb: %p\n", skb
);
1741 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
||
1742 tx_info
->flags
& IEEE80211_TX_STAT_TX_FILTERED
) {
1743 kfree(tx_info_priv
);
1744 tx_info
->rate_driver_data
[0] = NULL
;
1747 if (tx_status
->flags
& ATH_TX_BAR
) {
1748 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
1749 tx_status
->flags
&= ~ATH_TX_BAR
;
1752 if (!(tx_status
->flags
& (ATH_TX_ERROR
| ATH_TX_XRETRY
))) {
1753 /* Frame was ACKed */
1754 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
1757 tx_info
->status
.rates
[0].count
= tx_status
->retries
+ 1;
1759 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1760 padsize
= hdrlen
& 3;
1761 if (padsize
&& hdrlen
>= 24) {
1763 * Remove MAC header padding before giving the frame back to
1766 memmove(skb
->data
+ padsize
, skb
->data
, hdrlen
);
1767 skb_pull(skb
, padsize
);
1770 ieee80211_tx_status(hw
, skb
);
1773 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
1774 struct list_head
*bf_q
,
1775 int txok
, int sendbar
)
1777 struct sk_buff
*skb
= bf
->bf_mpdu
;
1778 struct ath_xmit_status tx_status
;
1779 unsigned long flags
;
1782 * Set retry information.
1783 * NB: Don't use the information in the descriptor, because the frame
1784 * could be software retried.
1786 tx_status
.retries
= bf
->bf_retries
;
1787 tx_status
.flags
= 0;
1790 tx_status
.flags
= ATH_TX_BAR
;
1793 tx_status
.flags
|= ATH_TX_ERROR
;
1795 if (bf_isxretried(bf
))
1796 tx_status
.flags
|= ATH_TX_XRETRY
;
1799 dma_unmap_single(sc
->dev
, bf
->bf_dmacontext
, skb
->len
, DMA_TO_DEVICE
);
1800 ath_tx_complete(sc
, skb
, &tx_status
);
1803 * Return the list of ath_buf of this mpdu to free queue
1805 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
1806 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
1807 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
1810 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
1813 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
1814 struct ath_desc
*ds
= bf_last
->bf_desc
;
1816 u32 ba
[WME_BA_BMP_SIZE
>> 5];
1821 if (ds
->ds_txstat
.ts_flags
== ATH9K_TX_SW_ABORTED
)
1824 isaggr
= bf_isaggr(bf
);
1826 seq_st
= ATH_DS_BA_SEQ(ds
);
1827 memcpy(ba
, ATH_DS_BA_BITMAP(ds
), WME_BA_BMP_SIZE
>> 3);
1831 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
1832 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
1841 static void ath_tx_rc_status(struct ath_buf
*bf
, struct ath_desc
*ds
, int nbad
)
1843 struct sk_buff
*skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1844 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1845 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1846 struct ath_tx_info_priv
*tx_info_priv
= ATH_TX_INFO_PRIV(tx_info
);
1848 tx_info_priv
->update_rc
= false;
1849 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
)
1850 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1852 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
) == 0 &&
1853 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
1854 if (ieee80211_is_data(hdr
->frame_control
)) {
1855 memcpy(&tx_info_priv
->tx
, &ds
->ds_txstat
,
1856 sizeof(tx_info_priv
->tx
));
1857 tx_info_priv
->n_frames
= bf
->bf_nframes
;
1858 tx_info_priv
->n_bad_frames
= nbad
;
1859 tx_info_priv
->update_rc
= true;
1864 static void ath_wake_mac80211_queue(struct ath_softc
*sc
, struct ath_txq
*txq
)
1868 spin_lock_bh(&txq
->axq_lock
);
1870 ath_txq_depth(sc
, txq
->axq_qnum
) <= (ATH_TXBUF
- 20)) {
1871 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
1873 ieee80211_wake_queue(sc
->hw
, qnum
);
1877 spin_unlock_bh(&txq
->axq_lock
);
1880 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1882 struct ath_hal
*ah
= sc
->sc_ah
;
1883 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
1884 struct list_head bf_head
;
1885 struct ath_desc
*ds
;
1889 DPRINTF(sc
, ATH_DBG_QUEUE
, "tx queue %d (%x), link %p\n",
1890 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
1894 spin_lock_bh(&txq
->axq_lock
);
1895 if (list_empty(&txq
->axq_q
)) {
1896 txq
->axq_link
= NULL
;
1897 txq
->axq_linkbuf
= NULL
;
1898 spin_unlock_bh(&txq
->axq_lock
);
1901 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
1904 * There is a race condition that a BH gets scheduled
1905 * after sw writes TxE and before hw re-load the last
1906 * descriptor to get the newly chained one.
1907 * Software must keep the last DONE descriptor as a
1908 * holding descriptor - software does so by marking
1909 * it with the STALE flag.
1912 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
1914 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
1915 txq
->axq_link
= NULL
;
1916 txq
->axq_linkbuf
= NULL
;
1917 spin_unlock_bh(&txq
->axq_lock
);
1920 * The holding descriptor is the last
1921 * descriptor in queue. It's safe to remove
1922 * the last holding descriptor in BH context.
1924 spin_lock_bh(&sc
->tx
.txbuflock
);
1925 list_move_tail(&bf_held
->list
, &sc
->tx
.txbuf
);
1926 spin_unlock_bh(&sc
->tx
.txbuflock
);
1930 bf
= list_entry(bf_held
->list
.next
,
1931 struct ath_buf
, list
);
1935 lastbf
= bf
->bf_lastbf
;
1936 ds
= lastbf
->bf_desc
;
1938 status
= ath9k_hw_txprocdesc(ah
, ds
);
1939 if (status
== -EINPROGRESS
) {
1940 spin_unlock_bh(&txq
->axq_lock
);
1943 if (bf
->bf_desc
== txq
->axq_lastdsWithCTS
)
1944 txq
->axq_lastdsWithCTS
= NULL
;
1945 if (ds
== txq
->axq_gatingds
)
1946 txq
->axq_gatingds
= NULL
;
1949 * Remove ath_buf's of the same transmit unit from txq,
1950 * however leave the last descriptor back as the holding
1951 * descriptor for hw.
1953 lastbf
->bf_status
|= ATH_BUFSTATUS_STALE
;
1954 INIT_LIST_HEAD(&bf_head
);
1955 if (!list_is_singular(&lastbf
->list
))
1956 list_cut_position(&bf_head
,
1957 &txq
->axq_q
, lastbf
->list
.prev
);
1961 txq
->axq_aggr_depth
--;
1963 txok
= (ds
->ds_txstat
.ts_status
== 0);
1964 spin_unlock_bh(&txq
->axq_lock
);
1967 spin_lock_bh(&sc
->tx
.txbuflock
);
1968 list_move_tail(&bf_held
->list
, &sc
->tx
.txbuf
);
1969 spin_unlock_bh(&sc
->tx
.txbuflock
);
1972 if (!bf_isampdu(bf
)) {
1974 * This frame is sent out as a single frame.
1975 * Use hardware retry status for this frame.
1977 bf
->bf_retries
= ds
->ds_txstat
.ts_longretry
;
1978 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
)
1979 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
1982 nbad
= ath_tx_num_badfrms(sc
, bf
, txok
);
1985 ath_tx_rc_status(bf
, ds
, nbad
);
1988 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, txok
);
1990 ath_tx_complete_buf(sc
, bf
, &bf_head
, txok
, 0);
1992 ath_wake_mac80211_queue(sc
, txq
);
1994 spin_lock_bh(&txq
->axq_lock
);
1995 if (sc
->sc_flags
& SC_OP_TXAGGR
)
1996 ath_txq_schedule(sc
, txq
);
1997 spin_unlock_bh(&txq
->axq_lock
);
2002 void ath_tx_tasklet(struct ath_softc
*sc
)
2005 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2007 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2009 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2010 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2011 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2019 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2024 spin_lock_init(&sc
->tx
.txbuflock
);
2026 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2029 DPRINTF(sc
, ATH_DBG_FATAL
,
2030 "Failed to allocate tx descriptors: %d\n",
2035 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2036 "beacon", ATH_BCBUF
, 1);
2038 DPRINTF(sc
, ATH_DBG_FATAL
,
2039 "Failed to allocate beacon descriptors: %d\n",
2052 int ath_tx_cleanup(struct ath_softc
*sc
)
2054 if (sc
->beacon
.bdma
.dd_desc_len
!= 0)
2055 ath_descdma_cleanup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
);
2057 if (sc
->tx
.txdma
.dd_desc_len
!= 0)
2058 ath_descdma_cleanup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
);
2063 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2065 struct ath_atx_tid
*tid
;
2066 struct ath_atx_ac
*ac
;
2069 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2070 tidno
< WME_NUM_TID
;
2074 tid
->seq_start
= tid
->seq_next
= 0;
2075 tid
->baw_size
= WME_MAX_BA
;
2076 tid
->baw_head
= tid
->baw_tail
= 0;
2078 tid
->paused
= false;
2079 tid
->state
&= ~AGGR_CLEANUP
;
2080 INIT_LIST_HEAD(&tid
->buf_q
);
2081 acno
= TID_TO_WME_AC(tidno
);
2082 tid
->ac
= &an
->ac
[acno
];
2083 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2084 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2085 tid
->addba_exchangeattempts
= 0;
2088 for (acno
= 0, ac
= &an
->ac
[acno
];
2089 acno
< WME_NUM_AC
; acno
++, ac
++) {
2091 INIT_LIST_HEAD(&ac
->tid_q
);
2095 ac
->qnum
= ath_tx_get_qnum(sc
,
2096 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2099 ac
->qnum
= ath_tx_get_qnum(sc
,
2100 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2103 ac
->qnum
= ath_tx_get_qnum(sc
,
2104 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2107 ac
->qnum
= ath_tx_get_qnum(sc
,
2108 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2114 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2117 struct ath_atx_ac
*ac
, *ac_tmp
;
2118 struct ath_atx_tid
*tid
, *tid_tmp
;
2119 struct ath_txq
*txq
;
2121 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2122 if (ATH_TXQ_SETUP(sc
, i
)) {
2123 txq
= &sc
->tx
.txq
[i
];
2125 spin_lock(&txq
->axq_lock
);
2127 list_for_each_entry_safe(ac
,
2128 ac_tmp
, &txq
->axq_acq
, list
) {
2129 tid
= list_first_entry(&ac
->tid_q
,
2130 struct ath_atx_tid
, list
);
2131 if (tid
&& tid
->an
!= an
)
2133 list_del(&ac
->list
);
2136 list_for_each_entry_safe(tid
,
2137 tid_tmp
, &ac
->tid_q
, list
) {
2138 list_del(&tid
->list
);
2140 ath_tid_drain(sc
, txq
, tid
);
2141 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2142 tid
->addba_exchangeattempts
= 0;
2143 tid
->state
&= ~AGGR_CLEANUP
;
2147 spin_unlock(&txq
->axq_lock
);