2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol
[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
59 * Insert a chain of ath_buf (descriptors) on a txq and
60 * assume the descriptors are already chained together by caller.
61 * NB: must be called with txq lock held
64 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
65 struct list_head
*head
)
67 struct ath_hal
*ah
= sc
->sc_ah
;
71 * Insert the frame on the outbound list and
72 * pass it on to the hardware.
78 bf
= list_first_entry(head
, struct ath_buf
, list
);
80 list_splice_tail_init(head
, &txq
->axq_q
);
82 txq
->axq_totalqueued
++;
83 txq
->axq_linkbuf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
85 DPRINTF(sc
, ATH_DBG_QUEUE
,
86 "qnum: %d, txq depth: %d\n", txq
->axq_qnum
, txq
->axq_depth
);
88 if (txq
->axq_link
== NULL
) {
89 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
90 DPRINTF(sc
, ATH_DBG_XMIT
,
91 "TXDP[%u] = %llx (%p)\n",
92 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
94 *txq
->axq_link
= bf
->bf_daddr
;
95 DPRINTF(sc
, ATH_DBG_XMIT
, "link[%u] (%p)=%llx (%p)\n",
96 txq
->axq_qnum
, txq
->axq_link
,
97 ito64(bf
->bf_daddr
), bf
->bf_desc
);
99 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
100 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
103 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
104 struct ath_xmit_status
*tx_status
)
106 struct ieee80211_hw
*hw
= sc
->hw
;
107 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
108 struct ath_tx_info_priv
*tx_info_priv
= ATH_TX_INFO_PRIV(tx_info
);
111 DPRINTF(sc
, ATH_DBG_XMIT
, "TX complete: skb: %p\n", skb
);
113 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
||
114 tx_info
->flags
& IEEE80211_TX_STAT_TX_FILTERED
) {
116 tx_info
->rate_driver_data
[0] = NULL
;
119 if (tx_status
->flags
& ATH_TX_BAR
) {
120 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
121 tx_status
->flags
&= ~ATH_TX_BAR
;
124 if (!(tx_status
->flags
& (ATH_TX_ERROR
| ATH_TX_XRETRY
))) {
125 /* Frame was ACKed */
126 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
129 tx_info
->status
.rates
[0].count
= tx_status
->retries
;
130 if (tx_info
->status
.rates
[0].flags
& IEEE80211_TX_RC_MCS
) {
131 /* Change idx from internal table index to MCS index */
132 int idx
= tx_info
->status
.rates
[0].idx
;
133 struct ath_rate_table
*rate_table
= sc
->cur_rate_table
;
134 if (idx
>= 0 && idx
< rate_table
->rate_cnt
)
135 tx_info
->status
.rates
[0].idx
=
136 rate_table
->info
[idx
].ratecode
& 0x7f;
139 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
140 padsize
= hdrlen
& 3;
141 if (padsize
&& hdrlen
>= 24) {
143 * Remove MAC header padding before giving the frame back to
146 memmove(skb
->data
+ padsize
, skb
->data
, hdrlen
);
147 skb_pull(skb
, padsize
);
150 ieee80211_tx_status(hw
, skb
);
153 /* Check if it's okay to send out aggregates */
155 static int ath_aggr_query(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
157 struct ath_atx_tid
*tid
;
158 tid
= ATH_AN_2_TID(an
, tidno
);
160 if (tid
->state
& AGGR_ADDBA_COMPLETE
||
161 tid
->state
& AGGR_ADDBA_PROGRESS
)
167 static void ath_get_beaconconfig(struct ath_softc
*sc
, int if_id
,
168 struct ath_beacon_config
*conf
)
170 struct ieee80211_hw
*hw
= sc
->hw
;
172 /* fill in beacon config data */
174 conf
->beacon_interval
= hw
->conf
.beacon_int
;
175 conf
->listen_interval
= 100;
176 conf
->dtim_count
= 1;
177 conf
->bmiss_timeout
= ATH_DEFAULT_BMISS_LIMIT
* conf
->listen_interval
;
180 /* Calculate Atheros packet type from IEEE80211 packet header */
182 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
184 struct ieee80211_hdr
*hdr
;
185 enum ath9k_pkt_type htype
;
188 hdr
= (struct ieee80211_hdr
*)skb
->data
;
189 fc
= hdr
->frame_control
;
191 if (ieee80211_is_beacon(fc
))
192 htype
= ATH9K_PKT_TYPE_BEACON
;
193 else if (ieee80211_is_probe_resp(fc
))
194 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
195 else if (ieee80211_is_atim(fc
))
196 htype
= ATH9K_PKT_TYPE_ATIM
;
197 else if (ieee80211_is_pspoll(fc
))
198 htype
= ATH9K_PKT_TYPE_PSPOLL
;
200 htype
= ATH9K_PKT_TYPE_NORMAL
;
205 static bool is_pae(struct sk_buff
*skb
)
207 struct ieee80211_hdr
*hdr
;
210 hdr
= (struct ieee80211_hdr
*)skb
->data
;
211 fc
= hdr
->frame_control
;
213 if (ieee80211_is_data(fc
)) {
214 if (ieee80211_is_nullfunc(fc
) ||
215 /* Port Access Entity (IEEE 802.1X) */
216 (skb
->protocol
== cpu_to_be16(ETH_P_PAE
))) {
224 static int get_hw_crypto_keytype(struct sk_buff
*skb
)
226 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
228 if (tx_info
->control
.hw_key
) {
229 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
230 return ATH9K_KEY_TYPE_WEP
;
231 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
232 return ATH9K_KEY_TYPE_TKIP
;
233 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
234 return ATH9K_KEY_TYPE_AES
;
237 return ATH9K_KEY_TYPE_CLEAR
;
240 /* Called only when tx aggregation is enabled and HT is supported */
242 static void assign_aggr_tid_seqno(struct sk_buff
*skb
,
245 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
246 struct ieee80211_hdr
*hdr
;
248 struct ath_atx_tid
*tid
;
252 if (!tx_info
->control
.sta
)
255 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
256 hdr
= (struct ieee80211_hdr
*)skb
->data
;
257 fc
= hdr
->frame_control
;
261 if (ieee80211_is_data_qos(fc
)) {
262 qc
= ieee80211_get_qos_ctl(hdr
);
263 bf
->bf_tidno
= qc
[0] & 0xf;
268 if (ieee80211_is_data(fc
) && !is_pae(skb
)) {
269 /* For HT capable stations, we save tidno for later use.
270 * We also override seqno set by upper layer with the one
271 * in tx aggregation state.
273 * If fragmentation is on, the sequence number is
274 * not overridden, since it has been
275 * incremented by the fragmentation routine.
277 * FIXME: check if the fragmentation threshold exceeds
280 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
281 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<<
282 IEEE80211_SEQ_SEQ_SHIFT
);
283 bf
->bf_seqno
= tid
->seq_next
;
284 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
288 static int setup_tx_flags(struct ath_softc
*sc
, struct sk_buff
*skb
,
291 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
294 flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
295 flags
|= ATH9K_TXDESC_INTREQ
;
297 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
298 flags
|= ATH9K_TXDESC_NOACK
;
299 if (tx_info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
300 flags
|= ATH9K_TXDESC_RTSENA
;
305 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
307 struct ath_buf
*bf
= NULL
;
309 spin_lock_bh(&sc
->tx
.txbuflock
);
311 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
312 spin_unlock_bh(&sc
->tx
.txbuflock
);
316 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
319 spin_unlock_bh(&sc
->tx
.txbuflock
);
324 /* To complete a chain of buffers associated a frame */
326 static void ath_tx_complete_buf(struct ath_softc
*sc
,
328 struct list_head
*bf_q
,
329 int txok
, int sendbar
)
331 struct sk_buff
*skb
= bf
->bf_mpdu
;
332 struct ath_xmit_status tx_status
;
336 * Set retry information.
337 * NB: Don't use the information in the descriptor, because the frame
338 * could be software retried.
340 tx_status
.retries
= bf
->bf_retries
;
344 tx_status
.flags
= ATH_TX_BAR
;
347 tx_status
.flags
|= ATH_TX_ERROR
;
349 if (bf_isxretried(bf
))
350 tx_status
.flags
|= ATH_TX_XRETRY
;
353 /* Unmap this frame */
354 pci_unmap_single(sc
->pdev
,
358 /* complete this frame */
359 ath_tx_complete(sc
, skb
, &tx_status
);
362 * Return the list of ath_buf of this mpdu to free queue
364 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
365 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
366 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
370 * queue up a dest/ac pair for tx scheduling
371 * NB: must be called with txq lock held
374 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
376 struct ath_atx_ac
*ac
= tid
->ac
;
379 * if tid is paused, hold off
385 * add tid to ac atmost once
391 list_add_tail(&tid
->list
, &ac
->tid_q
);
394 * add node ac to txq atmost once
400 list_add_tail(&ac
->list
, &txq
->axq_acq
);
405 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
407 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
409 spin_lock_bh(&txq
->axq_lock
);
413 spin_unlock_bh(&txq
->axq_lock
);
416 /* resume a tid and schedule aggregate */
418 void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
420 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
422 ASSERT(tid
->paused
> 0);
423 spin_lock_bh(&txq
->axq_lock
);
430 if (list_empty(&tid
->buf_q
))
434 * Add this TID to scheduler and try to send out aggregates
436 ath_tx_queue_tid(txq
, tid
);
437 ath_txq_schedule(sc
, txq
);
439 spin_unlock_bh(&txq
->axq_lock
);
442 /* Compute the number of bad frames */
444 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
447 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
448 struct ath_desc
*ds
= bf_last
->bf_desc
;
450 u32 ba
[WME_BA_BMP_SIZE
>> 5];
455 if (ds
->ds_txstat
.ts_flags
== ATH9K_TX_SW_ABORTED
)
458 isaggr
= bf_isaggr(bf
);
460 seq_st
= ATH_DS_BA_SEQ(ds
);
461 memcpy(ba
, ATH_DS_BA_BITMAP(ds
), WME_BA_BMP_SIZE
>> 3);
465 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
466 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
475 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_buf
*bf
)
478 struct ieee80211_hdr
*hdr
;
480 bf
->bf_state
.bf_type
|= BUF_RETRY
;
484 hdr
= (struct ieee80211_hdr
*)skb
->data
;
485 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
488 /* Update block ack window */
490 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
495 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
496 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
498 tid
->tx_buf
[cindex
] = NULL
;
500 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
501 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
502 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
507 * ath_pkt_dur - compute packet duration (NB: not NAV)
510 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
511 * width - 0 for 20 MHz, 1 for 40 MHz
512 * half_gi - to use 4us v/s 3.6 us for symbol time
514 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, struct ath_buf
*bf
,
515 int width
, int half_gi
, bool shortPreamble
)
517 struct ath_rate_table
*rate_table
= sc
->cur_rate_table
;
518 u32 nbits
, nsymbits
, duration
, nsymbols
;
522 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
523 rc
= rate_table
->info
[rix
].ratecode
;
525 /* for legacy rates, use old function to compute packet duration */
527 return ath9k_hw_computetxtime(sc
->sc_ah
, rate_table
, pktlen
,
530 /* find number of symbols: PLCP + data */
531 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
532 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
533 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
536 duration
= SYMBOL_TIME(nsymbols
);
538 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
540 /* addup duration for legacy/ht training and signal fields */
541 streams
= HT_RC_2_STREAMS(rc
);
542 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
547 /* Rate module function to set rate related fields in tx descriptor */
549 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
551 struct ath_hal
*ah
= sc
->sc_ah
;
552 struct ath_rate_table
*rt
;
553 struct ath_desc
*ds
= bf
->bf_desc
;
554 struct ath_desc
*lastds
= bf
->bf_lastbf
->bf_desc
;
555 struct ath9k_11n_rate_series series
[4];
557 struct ieee80211_tx_info
*tx_info
;
558 struct ieee80211_tx_rate
*rates
;
559 struct ieee80211_hdr
*hdr
;
560 int i
, flags
, rtsctsena
= 0;
562 u8 rix
= 0, cix
, ctsrate
= 0;
565 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
567 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
568 hdr
= (struct ieee80211_hdr
*)skb
->data
;
569 fc
= hdr
->frame_control
;
570 tx_info
= IEEE80211_SKB_CB(skb
);
571 rates
= tx_info
->control
.rates
;
573 if (ieee80211_has_morefrags(fc
) ||
574 (le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
)) {
575 rates
[1].count
= rates
[2].count
= rates
[3].count
= 0;
576 rates
[1].idx
= rates
[2].idx
= rates
[3].idx
= 0;
577 rates
[0].count
= ATH_TXMAXTRY
;
580 /* get the cix for the lowest valid rix */
581 rt
= sc
->cur_rate_table
;
582 for (i
= 3; i
>= 0; i
--) {
583 if (rates
[i
].count
&& (rates
[i
].idx
>= 0)) {
589 flags
= (bf
->bf_flags
& (ATH9K_TXDESC_RTSENA
| ATH9K_TXDESC_CTSENA
));
590 cix
= rt
->info
[rix
].ctrl_rate
;
593 * If 802.11g protection is enabled, determine whether to use RTS/CTS or
594 * just CTS. Note that this is only done for OFDM/HT unicast frames.
596 if (sc
->sc_protmode
!= PROT_M_NONE
&& !(bf
->bf_flags
& ATH9K_TXDESC_NOACK
)
597 && (rt
->info
[rix
].phy
== WLAN_RC_PHY_OFDM
||
598 WLAN_RC_PHY_HT(rt
->info
[rix
].phy
))) {
599 if (sc
->sc_protmode
== PROT_M_RTSCTS
)
600 flags
= ATH9K_TXDESC_RTSENA
;
601 else if (sc
->sc_protmode
== PROT_M_CTSONLY
)
602 flags
= ATH9K_TXDESC_CTSENA
;
604 cix
= rt
->info
[sc
->sc_protrix
].ctrl_rate
;
608 /* For 11n, the default behavior is to enable RTS for hw retried frames.
609 * We enable the global flag here and let rate series flags determine
610 * which rates will actually use RTS.
612 if ((ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) && bf_isdata(bf
)) {
613 /* 802.11g protection not needed, use our default behavior */
615 flags
= ATH9K_TXDESC_RTSENA
;
618 /* Set protection if aggregate protection on */
619 if (sc
->sc_config
.ath_aggr_prot
&&
620 (!bf_isaggr(bf
) || (bf_isaggr(bf
) && bf
->bf_al
< 8192))) {
621 flags
= ATH9K_TXDESC_RTSENA
;
622 cix
= rt
->info
[sc
->sc_protrix
].ctrl_rate
;
626 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
627 if (bf_isaggr(bf
) && (bf
->bf_al
> ah
->ah_caps
.rts_aggr_limit
))
628 flags
&= ~(ATH9K_TXDESC_RTSENA
);
631 * CTS transmit rate is derived from the transmit rate by looking in the
632 * h/w rate table. We must also factor in whether or not a short
633 * preamble is to be used. NB: cix is set above where RTS/CTS is enabled
635 ctsrate
= rt
->info
[cix
].ratecode
|
636 (bf_isshpreamble(bf
) ? rt
->info
[cix
].short_preamble
: 0);
638 for (i
= 0; i
< 4; i
++) {
639 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
644 series
[i
].Rate
= rt
->info
[rix
].ratecode
|
645 (bf_isshpreamble(bf
) ? rt
->info
[rix
].short_preamble
: 0);
647 series
[i
].Tries
= rates
[i
].count
;
649 series
[i
].RateFlags
= (
650 (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) ?
651 ATH9K_RATESERIES_RTS_CTS
: 0) |
652 ((rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ?
653 ATH9K_RATESERIES_2040
: 0) |
654 ((rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
) ?
655 ATH9K_RATESERIES_HALFGI
: 0);
657 series
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, bf
,
658 (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) != 0,
659 (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
),
660 bf_isshpreamble(bf
));
662 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
665 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
668 /* set dur_update_en for l-sig computation except for PS-Poll frames */
669 ath9k_hw_set11n_ratescenario(ah
, ds
, lastds
, !bf_ispspoll(bf
),
670 ctsrate
, ctsduration
,
673 if (sc
->sc_config
.ath_aggr_prot
&& flags
)
674 ath9k_hw_set11n_burstduration(ah
, ds
, 8192);
678 * Function to send a normal HT (non-AMPDU) frame
679 * NB: must be called with txq lock held
681 static int ath_tx_send_normal(struct ath_softc
*sc
,
683 struct ath_atx_tid
*tid
,
684 struct list_head
*bf_head
)
688 BUG_ON(list_empty(bf_head
));
690 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
691 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
; /* regular HT frame */
693 /* update starting sequence number for subsequent ADDBA request */
694 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
696 /* Queue to h/w without aggregation */
698 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
699 ath_buf_set_rate(sc
, bf
);
700 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
705 /* flush tid's software queue and send frames as non-ampdu's */
707 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
709 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
711 struct list_head bf_head
;
712 INIT_LIST_HEAD(&bf_head
);
714 ASSERT(tid
->paused
> 0);
715 spin_lock_bh(&txq
->axq_lock
);
719 if (tid
->paused
> 0) {
720 spin_unlock_bh(&txq
->axq_lock
);
724 while (!list_empty(&tid
->buf_q
)) {
725 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
726 ASSERT(!bf_isretried(bf
));
727 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
728 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
731 spin_unlock_bh(&txq
->axq_lock
);
734 /* Completion routine of an aggregate */
736 static void ath_tx_complete_aggr_rifs(struct ath_softc
*sc
,
739 struct list_head
*bf_q
,
742 struct ath_node
*an
= NULL
;
744 struct ieee80211_tx_info
*tx_info
;
745 struct ath_atx_tid
*tid
= NULL
;
746 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
747 struct ath_desc
*ds
= bf_last
->bf_desc
;
748 struct ath_buf
*bf_next
, *bf_lastq
= NULL
;
749 struct list_head bf_head
, bf_pending
;
751 u32 ba
[WME_BA_BMP_SIZE
>> 5];
752 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0;
754 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
755 tx_info
= IEEE80211_SKB_CB(skb
);
757 if (tx_info
->control
.sta
) {
758 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
759 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
762 isaggr
= bf_isaggr(bf
);
765 if (ATH_DS_TX_BA(ds
)) {
767 * extract starting sequence and
770 seq_st
= ATH_DS_BA_SEQ(ds
);
772 ATH_DS_BA_BITMAP(ds
),
773 WME_BA_BMP_SIZE
>> 3);
775 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
778 * AR5416 can become deaf/mute when BA
779 * issue happens. Chip needs to be reset.
780 * But AP code may have sychronization issues
781 * when perform internal reset in this routine.
782 * Only enable reset in STA mode for now.
784 if (sc
->sc_ah
->ah_opmode
==
785 NL80211_IFTYPE_STATION
)
789 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
793 INIT_LIST_HEAD(&bf_pending
);
794 INIT_LIST_HEAD(&bf_head
);
797 txfail
= txpending
= 0;
798 bf_next
= bf
->bf_next
;
800 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
801 /* transmit completion, subframe is
802 * acked by block ack */
803 } else if (!isaggr
&& txok
) {
804 /* transmit completion */
807 if (!(tid
->state
& AGGR_CLEANUP
) &&
808 ds
->ds_txstat
.ts_flags
!= ATH9K_TX_SW_ABORTED
) {
809 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
810 ath_tx_set_retry(sc
, bf
);
813 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
819 * cleanup in progress, just fail
820 * the un-acked sub-frames
826 * Remove ath_buf's of this sub-frame from aggregate queue.
828 if (bf_next
== NULL
) { /* last subframe in the aggregate */
829 ASSERT(bf
->bf_lastfrm
== bf_last
);
832 * The last descriptor of the last sub frame could be
833 * a holding descriptor for h/w. If that's the case,
834 * bf->bf_lastfrm won't be in the bf_q.
835 * Make sure we handle bf_q properly here.
838 if (!list_empty(bf_q
)) {
839 bf_lastq
= list_entry(bf_q
->prev
,
840 struct ath_buf
, list
);
841 list_cut_position(&bf_head
,
842 bf_q
, &bf_lastq
->list
);
845 * XXX: if the last subframe only has one
846 * descriptor which is also being used as
847 * a holding descriptor. Then the ath_buf
848 * is not in the bf_q at all.
850 INIT_LIST_HEAD(&bf_head
);
853 ASSERT(!list_empty(bf_q
));
854 list_cut_position(&bf_head
,
855 bf_q
, &bf
->bf_lastfrm
->list
);
860 * complete the acked-ones/xretried ones; update
863 spin_lock_bh(&txq
->axq_lock
);
864 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
865 spin_unlock_bh(&txq
->axq_lock
);
867 /* complete this sub-frame */
868 ath_tx_complete_buf(sc
, bf
, &bf_head
, !txfail
, sendbar
);
871 * retry the un-acked ones
874 * XXX: if the last descriptor is holding descriptor,
875 * in order to requeue the frame to software queue, we
876 * need to allocate a new descriptor and
877 * copy the content of holding descriptor to it.
879 if (bf
->bf_next
== NULL
&&
880 bf_last
->bf_status
& ATH_BUFSTATUS_STALE
) {
883 /* allocate new descriptor */
884 spin_lock_bh(&sc
->tx
.txbuflock
);
885 ASSERT(!list_empty((&sc
->tx
.txbuf
)));
886 tbf
= list_first_entry(&sc
->tx
.txbuf
,
887 struct ath_buf
, list
);
888 list_del(&tbf
->list
);
889 spin_unlock_bh(&sc
->tx
.txbuflock
);
891 ATH_TXBUF_RESET(tbf
);
893 /* copy descriptor content */
894 tbf
->bf_mpdu
= bf_last
->bf_mpdu
;
895 tbf
->bf_buf_addr
= bf_last
->bf_buf_addr
;
896 *(tbf
->bf_desc
) = *(bf_last
->bf_desc
);
898 /* link it to the frame */
900 bf_lastq
->bf_desc
->ds_link
=
902 bf
->bf_lastfrm
= tbf
;
903 ath9k_hw_cleartxdesc(sc
->sc_ah
,
904 bf
->bf_lastfrm
->bf_desc
);
906 tbf
->bf_state
= bf_last
->bf_state
;
907 tbf
->bf_lastfrm
= tbf
;
908 ath9k_hw_cleartxdesc(sc
->sc_ah
,
909 tbf
->bf_lastfrm
->bf_desc
);
911 /* copy the DMA context */
913 bf_last
->bf_dmacontext
;
915 list_add_tail(&tbf
->list
, &bf_head
);
918 * Clear descriptor status words for
921 ath9k_hw_cleartxdesc(sc
->sc_ah
,
922 bf
->bf_lastfrm
->bf_desc
);
926 * Put this buffer to the temporary pending
927 * queue to retain ordering
929 list_splice_tail_init(&bf_head
, &bf_pending
);
935 if (tid
->state
& AGGR_CLEANUP
) {
936 /* check to see if we're done with cleaning the h/w queue */
937 spin_lock_bh(&txq
->axq_lock
);
939 if (tid
->baw_head
== tid
->baw_tail
) {
940 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
941 tid
->addba_exchangeattempts
= 0;
942 spin_unlock_bh(&txq
->axq_lock
);
944 tid
->state
&= ~AGGR_CLEANUP
;
946 /* send buffered frames as singles */
947 ath_tx_flush_tid(sc
, tid
);
949 spin_unlock_bh(&txq
->axq_lock
);
955 * prepend un-acked frames to the beginning of the pending frame queue
957 if (!list_empty(&bf_pending
)) {
958 spin_lock_bh(&txq
->axq_lock
);
959 /* Note: we _prepend_, we _do_not_ at to
960 * the end of the queue ! */
961 list_splice(&bf_pending
, &tid
->buf_q
);
962 ath_tx_queue_tid(txq
, tid
);
963 spin_unlock_bh(&txq
->axq_lock
);
967 ath_reset(sc
, false);
972 static void ath_tx_rc_status(struct ath_buf
*bf
, struct ath_desc
*ds
, int nbad
)
974 struct sk_buff
*skb
= (struct sk_buff
*)bf
->bf_mpdu
;
975 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
976 struct ath_tx_info_priv
*tx_info_priv
= ATH_TX_INFO_PRIV(tx_info
);
978 tx_info_priv
->update_rc
= false;
979 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
)
980 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
982 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
) == 0 &&
983 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
985 memcpy(&tx_info_priv
->tx
, &ds
->ds_txstat
,
986 sizeof(tx_info_priv
->tx
));
987 tx_info_priv
->n_frames
= bf
->bf_nframes
;
988 tx_info_priv
->n_bad_frames
= nbad
;
989 tx_info_priv
->update_rc
= true;
994 /* Process completed xmit descriptors from the specified queue */
996 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
998 struct ath_hal
*ah
= sc
->sc_ah
;
999 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
1000 struct list_head bf_head
;
1001 struct ath_desc
*ds
;
1005 DPRINTF(sc
, ATH_DBG_QUEUE
, "tx queue %d (%x), link %p\n",
1006 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
1010 spin_lock_bh(&txq
->axq_lock
);
1011 if (list_empty(&txq
->axq_q
)) {
1012 txq
->axq_link
= NULL
;
1013 txq
->axq_linkbuf
= NULL
;
1014 spin_unlock_bh(&txq
->axq_lock
);
1017 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
1020 * There is a race condition that a BH gets scheduled
1021 * after sw writes TxE and before hw re-load the last
1022 * descriptor to get the newly chained one.
1023 * Software must keep the last DONE descriptor as a
1024 * holding descriptor - software does so by marking
1025 * it with the STALE flag.
1028 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
1030 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
1032 * The holding descriptor is the last
1033 * descriptor in queue. It's safe to remove
1034 * the last holding descriptor in BH context.
1036 spin_unlock_bh(&txq
->axq_lock
);
1039 /* Lets work with the next buffer now */
1040 bf
= list_entry(bf_held
->list
.next
,
1041 struct ath_buf
, list
);
1045 lastbf
= bf
->bf_lastbf
;
1046 ds
= lastbf
->bf_desc
; /* NB: last decriptor */
1048 status
= ath9k_hw_txprocdesc(ah
, ds
);
1049 if (status
== -EINPROGRESS
) {
1050 spin_unlock_bh(&txq
->axq_lock
);
1053 if (bf
->bf_desc
== txq
->axq_lastdsWithCTS
)
1054 txq
->axq_lastdsWithCTS
= NULL
;
1055 if (ds
== txq
->axq_gatingds
)
1056 txq
->axq_gatingds
= NULL
;
1059 * Remove ath_buf's of the same transmit unit from txq,
1060 * however leave the last descriptor back as the holding
1061 * descriptor for hw.
1063 lastbf
->bf_status
|= ATH_BUFSTATUS_STALE
;
1064 INIT_LIST_HEAD(&bf_head
);
1066 if (!list_is_singular(&lastbf
->list
))
1067 list_cut_position(&bf_head
,
1068 &txq
->axq_q
, lastbf
->list
.prev
);
1073 txq
->axq_aggr_depth
--;
1075 txok
= (ds
->ds_txstat
.ts_status
== 0);
1077 spin_unlock_bh(&txq
->axq_lock
);
1080 list_del(&bf_held
->list
);
1081 spin_lock_bh(&sc
->tx
.txbuflock
);
1082 list_add_tail(&bf_held
->list
, &sc
->tx
.txbuf
);
1083 spin_unlock_bh(&sc
->tx
.txbuflock
);
1086 if (!bf_isampdu(bf
)) {
1088 * This frame is sent out as a single frame.
1089 * Use hardware retry status for this frame.
1091 bf
->bf_retries
= ds
->ds_txstat
.ts_longretry
;
1092 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
)
1093 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
1096 nbad
= ath_tx_num_badfrms(sc
, bf
, txok
);
1099 ath_tx_rc_status(bf
, ds
, nbad
);
1102 * Complete this transmit unit
1105 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, txok
);
1107 ath_tx_complete_buf(sc
, bf
, &bf_head
, txok
, 0);
1109 /* Wake up mac80211 queue */
1111 spin_lock_bh(&txq
->axq_lock
);
1112 if (txq
->stopped
&& ath_txq_depth(sc
, txq
->axq_qnum
) <=
1115 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
1117 ieee80211_wake_queue(sc
->hw
, qnum
);
1124 * schedule any pending packets if aggregation is enabled
1126 if (sc
->sc_flags
& SC_OP_TXAGGR
)
1127 ath_txq_schedule(sc
, txq
);
1128 spin_unlock_bh(&txq
->axq_lock
);
1132 static void ath_tx_stopdma(struct ath_softc
*sc
, struct ath_txq
*txq
)
1134 struct ath_hal
*ah
= sc
->sc_ah
;
1136 (void) ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1137 DPRINTF(sc
, ATH_DBG_XMIT
, "tx queue [%u] %x, link %p\n",
1138 txq
->axq_qnum
, ath9k_hw_gettxbuf(ah
, txq
->axq_qnum
),
1142 /* Drain only the data queues */
1144 static void ath_drain_txdataq(struct ath_softc
*sc
, bool retry_tx
)
1146 struct ath_hal
*ah
= sc
->sc_ah
;
1147 int i
, status
, npend
= 0;
1149 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
1150 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1151 if (ATH_TXQ_SETUP(sc
, i
)) {
1152 ath_tx_stopdma(sc
, &sc
->tx
.txq
[i
]);
1153 /* The TxDMA may not really be stopped.
1154 * Double check the hal tx pending count */
1155 npend
+= ath9k_hw_numtxpending(ah
,
1156 sc
->tx
.txq
[i
].axq_qnum
);
1162 /* TxDMA not stopped, reset the hal */
1163 DPRINTF(sc
, ATH_DBG_XMIT
, "Unable to stop TxDMA. Reset HAL!\n");
1165 spin_lock_bh(&sc
->sc_resetlock
);
1166 if (!ath9k_hw_reset(ah
,
1167 sc
->sc_ah
->ah_curchan
,
1169 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
1170 sc
->sc_ht_extprotspacing
, true, &status
)) {
1172 DPRINTF(sc
, ATH_DBG_FATAL
,
1173 "Unable to reset hardware; hal status %u\n",
1176 spin_unlock_bh(&sc
->sc_resetlock
);
1179 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1180 if (ATH_TXQ_SETUP(sc
, i
))
1181 ath_tx_draintxq(sc
, &sc
->tx
.txq
[i
], retry_tx
);
1185 /* Add a sub-frame to block ack window */
1187 static void ath_tx_addto_baw(struct ath_softc
*sc
,
1188 struct ath_atx_tid
*tid
,
1193 if (bf_isretried(bf
))
1196 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
1197 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
1199 ASSERT(tid
->tx_buf
[cindex
] == NULL
);
1200 tid
->tx_buf
[cindex
] = bf
;
1202 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
1203 (ATH_TID_MAX_BUFS
- 1))) {
1204 tid
->baw_tail
= cindex
;
1205 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
1210 * Function to send an A-MPDU
1211 * NB: must be called with txq lock held
1213 static int ath_tx_send_ampdu(struct ath_softc
*sc
,
1214 struct ath_atx_tid
*tid
,
1215 struct list_head
*bf_head
,
1216 struct ath_tx_control
*txctl
)
1220 BUG_ON(list_empty(bf_head
));
1222 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1223 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1226 * Do not queue to h/w when any of the following conditions is true:
1227 * - there are pending frames in software queue
1228 * - the TID is currently paused for ADDBA/BAR request
1229 * - seqno is not within block-ack window
1230 * - h/w queue depth exceeds low water mark
1232 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1233 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1234 txctl
->txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1236 * Add this frame to software queue for scheduling later
1239 list_splice_tail_init(bf_head
, &tid
->buf_q
);
1240 ath_tx_queue_tid(txctl
->txq
, tid
);
1244 /* Add sub-frame to BAW */
1245 ath_tx_addto_baw(sc
, tid
, bf
);
1247 /* Queue to h/w without aggregation */
1249 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
1250 ath_buf_set_rate(sc
, bf
);
1251 ath_tx_txqaddbuf(sc
, txctl
->txq
, bf_head
);
1258 * returns aggr limit based on lowest of the rates
1260 static u32
ath_lookup_rate(struct ath_softc
*sc
,
1262 struct ath_atx_tid
*tid
)
1264 struct ath_rate_table
*rate_table
= sc
->cur_rate_table
;
1265 struct sk_buff
*skb
;
1266 struct ieee80211_tx_info
*tx_info
;
1267 struct ieee80211_tx_rate
*rates
;
1268 struct ath_tx_info_priv
*tx_info_priv
;
1269 u32 max_4ms_framelen
, frame_length
;
1270 u16 aggr_limit
, legacy
= 0, maxampdu
;
1273 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1274 tx_info
= IEEE80211_SKB_CB(skb
);
1275 rates
= tx_info
->control
.rates
;
1277 (struct ath_tx_info_priv
*)tx_info
->rate_driver_data
[0];
1280 * Find the lowest frame length among the rate series that will have a
1281 * 4ms transmit duration.
1282 * TODO - TXOP limit needs to be considered.
1284 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
1286 for (i
= 0; i
< 4; i
++) {
1287 if (rates
[i
].count
) {
1288 if (!WLAN_RC_PHY_HT(rate_table
->info
[rates
[i
].idx
].phy
)) {
1294 rate_table
->info
[rates
[i
].idx
].max_4ms_framelen
;
1295 max_4ms_framelen
= min(max_4ms_framelen
, frame_length
);
1300 * limit aggregate size by the minimum rate if rate selected is
1301 * not a probe rate, if rate selected is a probe rate then
1302 * avoid aggregation of this packet.
1304 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
1307 aggr_limit
= min(max_4ms_framelen
,
1308 (u32
)ATH_AMPDU_LIMIT_DEFAULT
);
1311 * h/w can accept aggregates upto 16 bit lengths (65535).
1312 * The IE, however can hold upto 65536, which shows up here
1313 * as zero. Ignore 65536 since we are constrained by hw.
1315 maxampdu
= tid
->an
->maxampdu
;
1317 aggr_limit
= min(aggr_limit
, maxampdu
);
1323 * returns the number of delimiters to be added to
1324 * meet the minimum required mpdudensity.
1325 * caller should make sure that the rate is HT rate .
1327 static int ath_compute_num_delims(struct ath_softc
*sc
,
1328 struct ath_atx_tid
*tid
,
1332 struct ath_rate_table
*rt
= sc
->cur_rate_table
;
1333 struct sk_buff
*skb
= bf
->bf_mpdu
;
1334 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1335 u32 nsymbits
, nsymbols
, mpdudensity
;
1338 int width
, half_gi
, ndelim
, mindelim
;
1340 /* Select standard number of delimiters based on frame length alone */
1341 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
1344 * If encryption enabled, hardware requires some more padding between
1346 * TODO - this could be improved to be dependent on the rate.
1347 * The hardware can keep up at lower rates, but not higher rates
1349 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
1350 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
1353 * Convert desired mpdu density from microeconds to bytes based
1354 * on highest rate in rate series (i.e. first rate) to determine
1355 * required minimum length for subframe. Take into account
1356 * whether high rate is 20 or 40Mhz and half or full GI.
1358 mpdudensity
= tid
->an
->mpdudensity
;
1361 * If there is no mpdu density restriction, no further calculation
1364 if (mpdudensity
== 0)
1367 rix
= tx_info
->control
.rates
[0].idx
;
1368 flags
= tx_info
->control
.rates
[0].flags
;
1369 rc
= rt
->info
[rix
].ratecode
;
1370 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
1371 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
1374 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity
);
1376 nsymbols
= NUM_SYMBOLS_PER_USEC(mpdudensity
);
1381 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
1382 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
1384 /* Is frame shorter than required minimum length? */
1385 if (frmlen
< minlen
) {
1386 /* Get the minimum number of delimiters required. */
1387 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
1388 ndelim
= max(mindelim
, ndelim
);
1395 * For aggregation from software buffer queue.
1396 * NB: must be called with txq lock held
1398 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
1399 struct ath_atx_tid
*tid
,
1400 struct list_head
*bf_q
,
1401 struct ath_buf
**bf_last
,
1402 struct aggr_rifs_param
*param
,
1405 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1406 struct ath_buf
*bf
, *tbf
, *bf_first
, *bf_prev
= NULL
;
1407 struct list_head bf_head
;
1408 int rl
= 0, nframes
= 0, ndelim
;
1409 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
1410 al_delta
, h_baw
= tid
->baw_size
/ 2;
1411 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
1413 INIT_LIST_HEAD(&bf_head
);
1415 BUG_ON(list_empty(&tid
->buf_q
));
1417 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1420 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1423 * do not step over block-ack window
1425 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
1426 status
= ATH_AGGR_BAW_CLOSED
;
1431 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
1436 * do not exceed aggregation limit
1438 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
1440 if (nframes
&& (aggr_limit
<
1441 (al
+ bpad
+ al_delta
+ prev_al
))) {
1442 status
= ATH_AGGR_LIMITED
;
1447 * do not exceed subframe limit
1449 if ((nframes
+ *prev_frames
) >=
1450 min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
1451 status
= ATH_AGGR_LIMITED
;
1456 * add padding for previous frame to aggregation length
1458 al
+= bpad
+ al_delta
;
1461 * Get the delimiters needed to meet the MPDU
1462 * density for this node.
1464 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, bf
->bf_frmlen
);
1466 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
1469 bf
->bf_lastfrm
->bf_desc
->ds_link
= 0;
1472 * this packet is part of an aggregate
1473 * - remove all descriptors belonging to this frame from
1475 * - add it to block ack window
1476 * - set up descriptors for aggregation
1478 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1479 ath_tx_addto_baw(sc
, tid
, bf
);
1481 list_for_each_entry(tbf
, &bf_head
, list
) {
1482 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
,
1483 tbf
->bf_desc
, ndelim
);
1487 * link buffers of this frame to the aggregate
1489 list_splice_tail_init(&bf_head
, bf_q
);
1493 bf_prev
->bf_next
= bf
;
1494 bf_prev
->bf_lastfrm
->bf_desc
->ds_link
= bf
->bf_daddr
;
1500 * terminate aggregation on a small packet boundary
1502 if (bf
->bf_frmlen
< ATH_AGGR_MINPLEN
) {
1503 status
= ATH_AGGR_SHORTPKT
;
1507 } while (!list_empty(&tid
->buf_q
));
1509 bf_first
->bf_al
= al
;
1510 bf_first
->bf_nframes
= nframes
;
1517 * process pending frames possibly doing a-mpdu aggregation
1518 * NB: must be called with txq lock held
1520 static void ath_tx_sched_aggr(struct ath_softc
*sc
,
1521 struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
1523 struct ath_buf
*bf
, *tbf
, *bf_last
, *bf_lastaggr
= NULL
;
1524 enum ATH_AGGR_STATUS status
;
1525 struct list_head bf_q
;
1526 struct aggr_rifs_param param
= {0, 0, 0, 0, NULL
};
1527 int prev_frames
= 0;
1530 if (list_empty(&tid
->buf_q
))
1533 INIT_LIST_HEAD(&bf_q
);
1535 status
= ath_tx_form_aggr(sc
, tid
, &bf_q
, &bf_lastaggr
, ¶m
,
1539 * no frames picked up to be aggregated; block-ack
1540 * window is not open
1542 if (list_empty(&bf_q
))
1545 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1546 bf_last
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1547 bf
->bf_lastbf
= bf_last
;
1550 * if only one frame, send as non-aggregate
1552 if (bf
->bf_nframes
== 1) {
1553 ASSERT(bf
->bf_lastfrm
== bf_last
);
1555 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1557 * clear aggr bits for every descriptor
1558 * XXX TODO: is there a way to optimize it?
1560 list_for_each_entry(tbf
, &bf_q
, list
) {
1561 ath9k_hw_clr11n_aggr(sc
->sc_ah
, tbf
->bf_desc
);
1564 ath_buf_set_rate(sc
, bf
);
1565 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1570 * setup first desc with rate and aggr info
1572 bf
->bf_state
.bf_type
|= BUF_AGGR
;
1573 ath_buf_set_rate(sc
, bf
);
1574 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
1577 * anchor last frame of aggregate correctly
1579 ASSERT(bf_lastaggr
);
1580 ASSERT(bf_lastaggr
->bf_lastfrm
== bf_last
);
1582 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1584 /* XXX: We don't enter into this loop, consider removing this */
1585 while (!list_empty(&bf_q
) && !list_is_last(&tbf
->list
, &bf_q
)) {
1586 tbf
= list_entry(tbf
->list
.next
, struct ath_buf
, list
);
1587 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1590 txq
->axq_aggr_depth
++;
1593 * Normal aggregate, queue to hardware
1595 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1597 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
1598 status
!= ATH_AGGR_BAW_CLOSED
);
1601 /* Called with txq lock held */
1603 static void ath_tid_drain(struct ath_softc
*sc
,
1604 struct ath_txq
*txq
,
1605 struct ath_atx_tid
*tid
)
1609 struct list_head bf_head
;
1610 INIT_LIST_HEAD(&bf_head
);
1613 if (list_empty(&tid
->buf_q
))
1615 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1617 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1619 /* update baw for software retried frame */
1620 if (bf_isretried(bf
))
1621 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1624 * do not indicate packets while holding txq spinlock.
1625 * unlock is intentional here
1627 spin_unlock(&txq
->axq_lock
);
1629 /* complete this sub-frame */
1630 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
1632 spin_lock(&txq
->axq_lock
);
1636 * TODO: For frame(s) that are in the retry state, we will reuse the
1637 * sequence number(s) without setting the retry bit. The
1638 * alternative is to give up on these and BAR the receiver's window
1641 tid
->seq_next
= tid
->seq_start
;
1642 tid
->baw_tail
= tid
->baw_head
;
1646 * Drain all pending buffers
1647 * NB: must be called with txq lock held
1649 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
1650 struct ath_txq
*txq
)
1652 struct ath_atx_ac
*ac
, *ac_tmp
;
1653 struct ath_atx_tid
*tid
, *tid_tmp
;
1655 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1656 list_del(&ac
->list
);
1658 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
1659 list_del(&tid
->list
);
1661 ath_tid_drain(sc
, txq
, tid
);
1666 static int ath_tx_setup_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
,
1667 struct sk_buff
*skb
,
1668 struct ath_tx_control
*txctl
)
1670 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1671 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1672 struct ath_tx_info_priv
*tx_info_priv
;
1676 tx_info_priv
= kzalloc(sizeof(*tx_info_priv
), GFP_ATOMIC
);
1677 if (unlikely(!tx_info_priv
))
1679 tx_info
->rate_driver_data
[0] = tx_info_priv
;
1680 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1681 fc
= hdr
->frame_control
;
1683 ATH_TXBUF_RESET(bf
);
1687 bf
->bf_frmlen
= skb
->len
+ FCS_LEN
- (hdrlen
& 3);
1689 ieee80211_is_data(fc
) ?
1690 (bf
->bf_state
.bf_type
|= BUF_DATA
) :
1691 (bf
->bf_state
.bf_type
&= ~BUF_DATA
);
1692 ieee80211_is_back_req(fc
) ?
1693 (bf
->bf_state
.bf_type
|= BUF_BAR
) :
1694 (bf
->bf_state
.bf_type
&= ~BUF_BAR
);
1695 ieee80211_is_pspoll(fc
) ?
1696 (bf
->bf_state
.bf_type
|= BUF_PSPOLL
) :
1697 (bf
->bf_state
.bf_type
&= ~BUF_PSPOLL
);
1698 (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
) ?
1699 (bf
->bf_state
.bf_type
|= BUF_SHORT_PREAMBLE
) :
1700 (bf
->bf_state
.bf_type
&= ~BUF_SHORT_PREAMBLE
);
1701 (sc
->hw
->conf
.ht
.enabled
&& !is_pae(skb
) &&
1702 (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) ?
1703 (bf
->bf_state
.bf_type
|= BUF_HT
) :
1704 (bf
->bf_state
.bf_type
&= ~BUF_HT
);
1706 bf
->bf_flags
= setup_tx_flags(sc
, skb
, txctl
->txq
);
1710 bf
->bf_keytype
= get_hw_crypto_keytype(skb
);
1712 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
) {
1713 bf
->bf_frmlen
+= tx_info
->control
.hw_key
->icv_len
;
1714 bf
->bf_keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
1716 bf
->bf_keyix
= ATH9K_TXKEYIX_INVALID
;
1719 /* Assign seqno, tidno */
1721 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
))
1722 assign_aggr_tid_seqno(skb
, bf
);
1728 bf
->bf_dmacontext
= pci_map_single(sc
->pdev
, skb
->data
,
1729 skb
->len
, PCI_DMA_TODEVICE
);
1730 if (unlikely(pci_dma_mapping_error(sc
->pdev
, bf
->bf_dmacontext
))) {
1732 DPRINTF(sc
, ATH_DBG_CONFIG
,
1733 "pci_dma_mapping_error() on TX\n");
1737 bf
->bf_buf_addr
= bf
->bf_dmacontext
;
1741 /* FIXME: tx power */
1742 static void ath_tx_start_dma(struct ath_softc
*sc
, struct ath_buf
*bf
,
1743 struct ath_tx_control
*txctl
)
1745 struct sk_buff
*skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1746 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1747 struct ath_node
*an
= NULL
;
1748 struct list_head bf_head
;
1749 struct ath_desc
*ds
;
1750 struct ath_atx_tid
*tid
;
1751 struct ath_hal
*ah
= sc
->sc_ah
;
1754 frm_type
= get_hw_packet_type(skb
);
1756 INIT_LIST_HEAD(&bf_head
);
1757 list_add_tail(&bf
->list
, &bf_head
);
1759 /* setup descriptor */
1763 ds
->ds_data
= bf
->bf_buf_addr
;
1765 /* Formulate first tx descriptor with tx controls */
1767 ath9k_hw_set11n_txdesc(ah
, ds
, bf
->bf_frmlen
, frm_type
, MAX_RATE_POWER
,
1768 bf
->bf_keyix
, bf
->bf_keytype
, bf
->bf_flags
);
1770 ath9k_hw_filltxdesc(ah
, ds
,
1771 skb
->len
, /* segment length */
1772 true, /* first segment */
1773 true, /* last segment */
1774 ds
); /* first descriptor */
1776 bf
->bf_lastfrm
= bf
;
1778 spin_lock_bh(&txctl
->txq
->axq_lock
);
1780 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
) &&
1781 tx_info
->control
.sta
) {
1782 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1783 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1785 if (ath_aggr_query(sc
, an
, bf
->bf_tidno
)) {
1787 * Try aggregation if it's a unicast data frame
1788 * and the destination is HT capable.
1790 ath_tx_send_ampdu(sc
, tid
, &bf_head
, txctl
);
1793 * Send this frame as regular when ADDBA
1794 * exchange is neither complete nor pending.
1796 ath_tx_send_normal(sc
, txctl
->txq
,
1803 ath_buf_set_rate(sc
, bf
);
1804 ath_tx_txqaddbuf(sc
, txctl
->txq
, &bf_head
);
1807 spin_unlock_bh(&txctl
->txq
->axq_lock
);
1810 /* Upon failure caller should free skb */
1811 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
,
1812 struct ath_tx_control
*txctl
)
1817 /* Check if a tx buffer is available */
1819 bf
= ath_tx_get_buffer(sc
);
1821 DPRINTF(sc
, ATH_DBG_XMIT
, "TX buffers are full\n");
1825 r
= ath_tx_setup_buffer(sc
, bf
, skb
, txctl
);
1827 struct ath_txq
*txq
= txctl
->txq
;
1829 DPRINTF(sc
, ATH_DBG_FATAL
, "TX mem alloc failure\n");
1831 /* upon ath_tx_processq() this TX queue will be resumed, we
1832 * guarantee this will happen by knowing beforehand that
1833 * we will at least have to run TX completionon one buffer
1835 spin_lock_bh(&txq
->axq_lock
);
1836 if (ath_txq_depth(sc
, txq
->axq_qnum
) > 1) {
1837 ieee80211_stop_queue(sc
->hw
,
1838 skb_get_queue_mapping(skb
));
1841 spin_unlock_bh(&txq
->axq_lock
);
1843 spin_lock_bh(&sc
->tx
.txbuflock
);
1844 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
1845 spin_unlock_bh(&sc
->tx
.txbuflock
);
1850 ath_tx_start_dma(sc
, bf
, txctl
);
1855 /* Initialize TX queue and h/w */
1857 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
1862 spin_lock_init(&sc
->tx
.txbuflock
);
1864 /* Setup tx descriptors */
1865 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
1868 DPRINTF(sc
, ATH_DBG_FATAL
,
1869 "Failed to allocate tx descriptors: %d\n",
1874 /* XXX allocate beacon state together with vap */
1875 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
1876 "beacon", ATH_BCBUF
, 1);
1878 DPRINTF(sc
, ATH_DBG_FATAL
,
1879 "Failed to allocate beacon descriptors: %d\n",
1892 /* Reclaim all tx queue resources */
1894 int ath_tx_cleanup(struct ath_softc
*sc
)
1896 /* cleanup beacon descriptors */
1897 if (sc
->beacon
.bdma
.dd_desc_len
!= 0)
1898 ath_descdma_cleanup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
);
1900 /* cleanup tx descriptors */
1901 if (sc
->tx
.txdma
.dd_desc_len
!= 0)
1902 ath_descdma_cleanup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
);
1907 /* Setup a h/w transmit queue */
1909 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1911 struct ath_hal
*ah
= sc
->sc_ah
;
1912 struct ath9k_tx_queue_info qi
;
1915 memset(&qi
, 0, sizeof(qi
));
1916 qi
.tqi_subtype
= subtype
;
1917 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1918 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1919 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1920 qi
.tqi_physCompBuf
= 0;
1923 * Enable interrupts only for EOL and DESC conditions.
1924 * We mark tx descriptors to receive a DESC interrupt
1925 * when a tx queue gets deep; otherwise waiting for the
1926 * EOL to reap descriptors. Note that this is done to
1927 * reduce interrupt load and this only defers reaping
1928 * descriptors, never transmitting frames. Aside from
1929 * reducing interrupts this also permits more concurrency.
1930 * The only potential downside is if the tx queue backs
1931 * up in which case the top half of the kernel may backup
1932 * due to a lack of tx descriptors.
1934 * The UAPSD queue is an exception, since we take a desc-
1935 * based intr on the EOSP frames.
1937 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1938 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1940 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1941 TXQ_FLAG_TXDESCINT_ENABLE
;
1942 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1945 * NB: don't print a message, this happens
1946 * normally on parts with too few tx queues
1950 if (qnum
>= ARRAY_SIZE(sc
->tx
.txq
)) {
1951 DPRINTF(sc
, ATH_DBG_FATAL
,
1952 "qnum %u out of range, max %u!\n",
1953 qnum
, (unsigned int)ARRAY_SIZE(sc
->tx
.txq
));
1954 ath9k_hw_releasetxqueue(ah
, qnum
);
1957 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
1958 struct ath_txq
*txq
= &sc
->tx
.txq
[qnum
];
1960 txq
->axq_qnum
= qnum
;
1961 txq
->axq_link
= NULL
;
1962 INIT_LIST_HEAD(&txq
->axq_q
);
1963 INIT_LIST_HEAD(&txq
->axq_acq
);
1964 spin_lock_init(&txq
->axq_lock
);
1966 txq
->axq_aggr_depth
= 0;
1967 txq
->axq_totalqueued
= 0;
1968 txq
->axq_linkbuf
= NULL
;
1969 sc
->tx
.txqsetup
|= 1<<qnum
;
1971 return &sc
->tx
.txq
[qnum
];
1974 /* Reclaim resources for a setup queue */
1976 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1978 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1979 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1983 * Setup a hardware data transmit queue for the specified
1984 * access control. The hal may not support all requested
1985 * queues in which case it will return a reference to a
1986 * previously setup queue. We record the mapping from ac's
1987 * to h/w queues for use by ath_tx_start and also track
1988 * the set of h/w queues being used to optimize work in the
1989 * transmit interrupt handler and related routines.
1992 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
1994 struct ath_txq
*txq
;
1996 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
1997 DPRINTF(sc
, ATH_DBG_FATAL
,
1998 "HAL AC %u out of range, max %zu!\n",
1999 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
2002 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
2004 sc
->tx
.hwq_map
[haltype
] = txq
->axq_qnum
;
2010 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
2015 case ATH9K_TX_QUEUE_DATA
:
2016 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
2017 DPRINTF(sc
, ATH_DBG_FATAL
,
2018 "HAL AC %u out of range, max %zu!\n",
2019 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
2022 qnum
= sc
->tx
.hwq_map
[haltype
];
2024 case ATH9K_TX_QUEUE_BEACON
:
2025 qnum
= sc
->beacon
.beaconq
;
2027 case ATH9K_TX_QUEUE_CAB
:
2028 qnum
= sc
->beacon
.cabq
->axq_qnum
;
2036 /* Get a transmit queue, if available */
2038 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2040 struct ath_txq
*txq
= NULL
;
2043 qnum
= ath_get_hal_qnum(skb_get_queue_mapping(skb
), sc
);
2044 txq
= &sc
->tx
.txq
[qnum
];
2046 spin_lock_bh(&txq
->axq_lock
);
2048 /* Try to avoid running out of descriptors */
2049 if (txq
->axq_depth
>= (ATH_TXBUF
- 20)) {
2050 DPRINTF(sc
, ATH_DBG_FATAL
,
2051 "TX queue: %d is full, depth: %d\n",
2052 qnum
, txq
->axq_depth
);
2053 ieee80211_stop_queue(sc
->hw
, skb_get_queue_mapping(skb
));
2055 spin_unlock_bh(&txq
->axq_lock
);
2059 spin_unlock_bh(&txq
->axq_lock
);
2064 /* Update parameters for a transmit queue */
2066 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
2067 struct ath9k_tx_queue_info
*qinfo
)
2069 struct ath_hal
*ah
= sc
->sc_ah
;
2071 struct ath9k_tx_queue_info qi
;
2073 if (qnum
== sc
->beacon
.beaconq
) {
2075 * XXX: for beacon queue, we just save the parameter.
2076 * It will be picked up by ath_beaconq_config when
2079 sc
->beacon
.beacon_qi
= *qinfo
;
2083 ASSERT(sc
->tx
.txq
[qnum
].axq_qnum
== qnum
);
2085 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
2086 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
2087 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
2088 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
2089 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
2090 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
2092 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
2093 DPRINTF(sc
, ATH_DBG_FATAL
,
2094 "Unable to update hardware queue %u!\n", qnum
);
2097 ath9k_hw_resettxqueue(ah
, qnum
); /* push to h/w */
2103 int ath_cabq_update(struct ath_softc
*sc
)
2105 struct ath9k_tx_queue_info qi
;
2106 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
2107 struct ath_beacon_config conf
;
2109 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
2111 * Ensure the readytime % is within the bounds.
2113 if (sc
->sc_config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
2114 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
2115 else if (sc
->sc_config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
2116 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
2118 ath_get_beaconconfig(sc
, ATH_IF_ID_ANY
, &conf
);
2120 (conf
.beacon_interval
* sc
->sc_config
.cabqReadytime
) / 100;
2121 ath_txq_update(sc
, qnum
, &qi
);
2126 /* Deferred processing of transmit interrupt */
2128 void ath_tx_tasklet(struct ath_softc
*sc
)
2131 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2133 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2136 * Process each active queue.
2138 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2139 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2140 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2144 void ath_tx_draintxq(struct ath_softc
*sc
,
2145 struct ath_txq
*txq
, bool retry_tx
)
2147 struct ath_buf
*bf
, *lastbf
;
2148 struct list_head bf_head
;
2150 INIT_LIST_HEAD(&bf_head
);
2153 * NB: this assumes output has been stopped and
2154 * we do not need to block ath_tx_tasklet
2157 spin_lock_bh(&txq
->axq_lock
);
2159 if (list_empty(&txq
->axq_q
)) {
2160 txq
->axq_link
= NULL
;
2161 txq
->axq_linkbuf
= NULL
;
2162 spin_unlock_bh(&txq
->axq_lock
);
2166 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2168 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
2169 list_del(&bf
->list
);
2170 spin_unlock_bh(&txq
->axq_lock
);
2172 spin_lock_bh(&sc
->tx
.txbuflock
);
2173 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
2174 spin_unlock_bh(&sc
->tx
.txbuflock
);
2178 lastbf
= bf
->bf_lastbf
;
2180 lastbf
->bf_desc
->ds_txstat
.ts_flags
=
2181 ATH9K_TX_SW_ABORTED
;
2183 /* remove ath_buf's of the same mpdu from txq */
2184 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
2187 spin_unlock_bh(&txq
->axq_lock
);
2190 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, 0);
2192 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2195 /* flush any pending frames if aggregation is enabled */
2196 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2198 spin_lock_bh(&txq
->axq_lock
);
2199 ath_txq_drain_pending_buffers(sc
, txq
);
2200 spin_unlock_bh(&txq
->axq_lock
);
2205 /* Drain the transmit queues and reclaim resources */
2207 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
)
2209 /* stop beacon queue. The beacon will be freed when
2210 * we go to INIT state */
2211 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2212 (void) ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2213 DPRINTF(sc
, ATH_DBG_XMIT
, "beacon queue %x\n",
2214 ath9k_hw_gettxbuf(sc
->sc_ah
, sc
->beacon
.beaconq
));
2217 ath_drain_txdataq(sc
, retry_tx
);
2220 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
)
2222 return sc
->tx
.txq
[qnum
].axq_depth
;
2225 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
)
2227 return sc
->tx
.txq
[qnum
].axq_aggr_depth
;
2230 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
2232 struct ath_atx_tid
*txtid
;
2234 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
2237 txtid
= ATH_AN_2_TID(an
, tidno
);
2239 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
2240 if (!(txtid
->state
& AGGR_ADDBA_PROGRESS
) &&
2241 (txtid
->addba_exchangeattempts
< ADDBA_EXCHANGE_ATTEMPTS
)) {
2242 txtid
->addba_exchangeattempts
++;
2250 /* Start TX aggregation */
2252 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
2255 struct ath_atx_tid
*txtid
;
2256 struct ath_node
*an
;
2258 an
= (struct ath_node
*)sta
->drv_priv
;
2260 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2261 txtid
= ATH_AN_2_TID(an
, tid
);
2262 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
2263 ath_tx_pause_tid(sc
, txtid
);
2269 /* Stop tx aggregation */
2271 int ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
2273 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
2275 ath_tx_aggr_teardown(sc
, an
, tid
);
2279 /* Resume tx aggregation */
2281 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
2283 struct ath_atx_tid
*txtid
;
2284 struct ath_node
*an
;
2286 an
= (struct ath_node
*)sta
->drv_priv
;
2288 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2289 txtid
= ATH_AN_2_TID(an
, tid
);
2291 IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
2292 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
2293 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2294 ath_tx_resume_tid(sc
, txtid
);
2299 * Performs transmit side cleanup when TID changes from aggregated to
2301 * - Pause the TID and mark cleanup in progress
2302 * - Discard all retry frames from the s/w queue.
2305 void ath_tx_aggr_teardown(struct ath_softc
*sc
, struct ath_node
*an
, u8 tid
)
2307 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
2308 struct ath_txq
*txq
= &sc
->tx
.txq
[txtid
->ac
->qnum
];
2310 struct list_head bf_head
;
2311 INIT_LIST_HEAD(&bf_head
);
2313 if (txtid
->state
& AGGR_CLEANUP
) /* cleanup is in progress */
2316 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
2317 txtid
->addba_exchangeattempts
= 0;
2321 /* TID must be paused first */
2322 ath_tx_pause_tid(sc
, txtid
);
2324 /* drop all software retried frames and mark this TID */
2325 spin_lock_bh(&txq
->axq_lock
);
2326 while (!list_empty(&txtid
->buf_q
)) {
2327 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
2328 if (!bf_isretried(bf
)) {
2330 * NB: it's based on the assumption that
2331 * software retried frame will always stay
2332 * at the head of software queue.
2336 list_cut_position(&bf_head
,
2337 &txtid
->buf_q
, &bf
->bf_lastfrm
->list
);
2338 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
2340 /* complete this sub-frame */
2341 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2344 if (txtid
->baw_head
!= txtid
->baw_tail
) {
2345 spin_unlock_bh(&txq
->axq_lock
);
2346 txtid
->state
|= AGGR_CLEANUP
;
2348 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2349 txtid
->addba_exchangeattempts
= 0;
2350 spin_unlock_bh(&txq
->axq_lock
);
2351 ath_tx_flush_tid(sc
, txtid
);
2356 * Tx scheduling logic
2357 * NB: must be called with txq lock held
2360 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
2362 struct ath_atx_ac
*ac
;
2363 struct ath_atx_tid
*tid
;
2365 /* nothing to schedule */
2366 if (list_empty(&txq
->axq_acq
))
2369 * get the first node/ac pair on the queue
2371 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
2372 list_del(&ac
->list
);
2376 * process a single tid per destination
2379 /* nothing to schedule */
2380 if (list_empty(&ac
->tid_q
))
2383 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
2384 list_del(&tid
->list
);
2387 if (tid
->paused
) /* check next tid to keep h/w busy */
2390 if ((txq
->axq_depth
% 2) == 0)
2391 ath_tx_sched_aggr(sc
, txq
, tid
);
2394 * add tid to round-robin queue if more frames
2395 * are pending for the tid
2397 if (!list_empty(&tid
->buf_q
))
2398 ath_tx_queue_tid(txq
, tid
);
2400 /* only schedule one TID at a time */
2402 } while (!list_empty(&ac
->tid_q
));
2405 * schedule AC if more TIDs need processing
2407 if (!list_empty(&ac
->tid_q
)) {
2409 * add dest ac to txq if not already added
2413 list_add_tail(&ac
->list
, &txq
->axq_acq
);
2418 /* Initialize per-node transmit state */
2420 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2422 struct ath_atx_tid
*tid
;
2423 struct ath_atx_ac
*ac
;
2427 * Init per tid tx state
2429 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2430 tidno
< WME_NUM_TID
;
2434 tid
->seq_start
= tid
->seq_next
= 0;
2435 tid
->baw_size
= WME_MAX_BA
;
2436 tid
->baw_head
= tid
->baw_tail
= 0;
2438 tid
->paused
= false;
2439 tid
->state
&= ~AGGR_CLEANUP
;
2440 INIT_LIST_HEAD(&tid
->buf_q
);
2442 acno
= TID_TO_WME_AC(tidno
);
2443 tid
->ac
= &an
->ac
[acno
];
2446 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2447 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2448 tid
->addba_exchangeattempts
= 0;
2452 * Init per ac tx state
2454 for (acno
= 0, ac
= &an
->ac
[acno
];
2455 acno
< WME_NUM_AC
; acno
++, ac
++) {
2457 INIT_LIST_HEAD(&ac
->tid_q
);
2461 ac
->qnum
= ath_tx_get_qnum(sc
,
2462 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2465 ac
->qnum
= ath_tx_get_qnum(sc
,
2466 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2469 ac
->qnum
= ath_tx_get_qnum(sc
,
2470 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2473 ac
->qnum
= ath_tx_get_qnum(sc
,
2474 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2480 /* Cleanupthe pending buffers for the node. */
2482 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2485 struct ath_atx_ac
*ac
, *ac_tmp
;
2486 struct ath_atx_tid
*tid
, *tid_tmp
;
2487 struct ath_txq
*txq
;
2488 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2489 if (ATH_TXQ_SETUP(sc
, i
)) {
2490 txq
= &sc
->tx
.txq
[i
];
2492 spin_lock(&txq
->axq_lock
);
2494 list_for_each_entry_safe(ac
,
2495 ac_tmp
, &txq
->axq_acq
, list
) {
2496 tid
= list_first_entry(&ac
->tid_q
,
2497 struct ath_atx_tid
, list
);
2498 if (tid
&& tid
->an
!= an
)
2500 list_del(&ac
->list
);
2503 list_for_each_entry_safe(tid
,
2504 tid_tmp
, &ac
->tid_q
, list
) {
2505 list_del(&tid
->list
);
2507 ath_tid_drain(sc
, txq
, tid
);
2508 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2509 tid
->addba_exchangeattempts
= 0;
2510 tid
->state
&= ~AGGR_CLEANUP
;
2514 spin_unlock(&txq
->axq_lock
);
2519 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2521 int hdrlen
, padsize
;
2522 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2523 struct ath_tx_control txctl
;
2525 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2528 * As a temporary workaround, assign seq# here; this will likely need
2529 * to be cleaned up to work better with Beacon transmission and virtual
2532 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2533 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2534 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2535 sc
->tx
.seq_no
+= 0x10;
2536 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2537 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
2540 /* Add the padding after the header if this is not already done */
2541 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2543 padsize
= hdrlen
% 4;
2544 if (skb_headroom(skb
) < padsize
) {
2545 DPRINTF(sc
, ATH_DBG_XMIT
, "TX CABQ padding failed\n");
2546 dev_kfree_skb_any(skb
);
2549 skb_push(skb
, padsize
);
2550 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
2553 txctl
.txq
= sc
->beacon
.cabq
;
2555 DPRINTF(sc
, ATH_DBG_XMIT
, "transmitting CABQ packet, skb: %p\n", skb
);
2557 if (ath_tx_start(sc
, skb
, &txctl
) != 0) {
2558 DPRINTF(sc
, ATH_DBG_XMIT
, "CABQ TX failed\n");
2564 dev_kfree_skb_any(skb
);