projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / wireless / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "core.h"
18
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34 #define OFDM_SIFS_TIME 16
35
36 static u32 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54 };
55
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
57
58 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct list_head *bf_q,
63 int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
67
68 /*********************/
69 /* Aggregation logic */
70 /*********************/
71
72 static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno)
73 {
74 struct ath_atx_tid *tid;
75 tid = ATH_AN_2_TID(an, tidno);
76
77 if (tid->state & AGGR_ADDBA_COMPLETE ||
78 tid->state & AGGR_ADDBA_PROGRESS)
79 return 1;
80 else
81 return 0;
82 }
83
84 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
85 {
86 struct ath_atx_ac *ac = tid->ac;
87
88 if (tid->paused)
89 return;
90
91 if (tid->sched)
92 return;
93
94 tid->sched = true;
95 list_add_tail(&tid->list, &ac->tid_q);
96
97 if (ac->sched)
98 return;
99
100 ac->sched = true;
101 list_add_tail(&ac->list, &txq->axq_acq);
102 }
103
104 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
105 {
106 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
107
108 spin_lock_bh(&txq->axq_lock);
109 tid->paused++;
110 spin_unlock_bh(&txq->axq_lock);
111 }
112
113 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
114 {
115 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
116
117 ASSERT(tid->paused > 0);
118 spin_lock_bh(&txq->axq_lock);
119
120 tid->paused--;
121
122 if (tid->paused > 0)
123 goto unlock;
124
125 if (list_empty(&tid->buf_q))
126 goto unlock;
127
128 ath_tx_queue_tid(txq, tid);
129 ath_txq_schedule(sc, txq);
130 unlock:
131 spin_unlock_bh(&txq->axq_lock);
132 }
133
134 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
135 {
136 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
137 struct ath_buf *bf;
138 struct list_head bf_head;
139 INIT_LIST_HEAD(&bf_head);
140
141 ASSERT(tid->paused > 0);
142 spin_lock_bh(&txq->axq_lock);
143
144 tid->paused--;
145
146 if (tid->paused > 0) {
147 spin_unlock_bh(&txq->axq_lock);
148 return;
149 }
150
151 while (!list_empty(&tid->buf_q)) {
152 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
153 ASSERT(!bf_isretried(bf));
154 list_move_tail(&bf->list, &bf_head);
155 ath_tx_send_normal(sc, txq, tid, &bf_head);
156 }
157
158 spin_unlock_bh(&txq->axq_lock);
159 }
160
161 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
162 int seqno)
163 {
164 int index, cindex;
165
166 index = ATH_BA_INDEX(tid->seq_start, seqno);
167 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
168
169 tid->tx_buf[cindex] = NULL;
170
171 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
172 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
173 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
174 }
175 }
176
177 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
178 struct ath_buf *bf)
179 {
180 int index, cindex;
181
182 if (bf_isretried(bf))
183 return;
184
185 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
187
188 ASSERT(tid->tx_buf[cindex] == NULL);
189 tid->tx_buf[cindex] = bf;
190
191 if (index >= ((tid->baw_tail - tid->baw_head) &
192 (ATH_TID_MAX_BUFS - 1))) {
193 tid->baw_tail = cindex;
194 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
195 }
196 }
197
198 /*
199 * TODO: For frame(s) that are in the retry state, we will reuse the
200 * sequence number(s) without setting the retry bit. The
201 * alternative is to give up on these and BAR the receiver's window
202 * forward.
203 */
204 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
205 struct ath_atx_tid *tid)
206
207 {
208 struct ath_buf *bf;
209 struct list_head bf_head;
210 INIT_LIST_HEAD(&bf_head);
211
212 for (;;) {
213 if (list_empty(&tid->buf_q))
214 break;
215
216 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
217 list_move_tail(&bf->list, &bf_head);
218
219 if (bf_isretried(bf))
220 ath_tx_update_baw(sc, tid, bf->bf_seqno);
221
222 spin_unlock(&txq->axq_lock);
223 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
224 spin_lock(&txq->axq_lock);
225 }
226
227 tid->seq_next = tid->seq_start;
228 tid->baw_tail = tid->baw_head;
229 }
230
231 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
232 {
233 struct sk_buff *skb;
234 struct ieee80211_hdr *hdr;
235
236 bf->bf_state.bf_type |= BUF_RETRY;
237 bf->bf_retries++;
238
239 skb = bf->bf_mpdu;
240 hdr = (struct ieee80211_hdr *)skb->data;
241 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
242 }
243
244 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
245 {
246 struct ath_buf *tbf;
247
248 spin_lock_bh(&sc->tx.txbuflock);
249 ASSERT(!list_empty((&sc->tx.txbuf)));
250 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
251 list_del(&tbf->list);
252 spin_unlock_bh(&sc->tx.txbuflock);
253
254 ATH_TXBUF_RESET(tbf);
255
256 tbf->bf_mpdu = bf->bf_mpdu;
257 tbf->bf_buf_addr = bf->bf_buf_addr;
258 *(tbf->bf_desc) = *(bf->bf_desc);
259 tbf->bf_state = bf->bf_state;
260 tbf->bf_dmacontext = bf->bf_dmacontext;
261
262 return tbf;
263 }
264
265 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
266 struct ath_buf *bf, struct list_head *bf_q,
267 int txok)
268 {
269 struct ath_node *an = NULL;
270 struct sk_buff *skb;
271 struct ieee80211_sta *sta;
272 struct ieee80211_hdr *hdr;
273 struct ath_atx_tid *tid = NULL;
274 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
275 struct ath_desc *ds = bf_last->bf_desc;
276 struct list_head bf_head, bf_pending;
277 u16 seq_st = 0;
278 u32 ba[WME_BA_BMP_SIZE >> 5];
279 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
280
281 skb = (struct sk_buff *)bf->bf_mpdu;
282 hdr = (struct ieee80211_hdr *)skb->data;
283
284 rcu_read_lock();
285
286 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
287 if (!sta) {
288 rcu_read_unlock();
289 return;
290 }
291
292 an = (struct ath_node *)sta->drv_priv;
293 tid = ATH_AN_2_TID(an, bf->bf_tidno);
294
295 isaggr = bf_isaggr(bf);
296 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
297
298 if (isaggr && txok) {
299 if (ATH_DS_TX_BA(ds)) {
300 seq_st = ATH_DS_BA_SEQ(ds);
301 memcpy(ba, ATH_DS_BA_BITMAP(ds),
302 WME_BA_BMP_SIZE >> 3);
303 } else {
304 /*
305 * AR5416 can become deaf/mute when BA
306 * issue happens. Chip needs to be reset.
307 * But AP code may have sychronization issues
308 * when perform internal reset in this routine.
309 * Only enable reset in STA mode for now.
310 */
311 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION)
312 needreset = 1;
313 }
314 }
315
316 INIT_LIST_HEAD(&bf_pending);
317 INIT_LIST_HEAD(&bf_head);
318
319 while (bf) {
320 txfail = txpending = 0;
321 bf_next = bf->bf_next;
322
323 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
324 /* transmit completion, subframe is
325 * acked by block ack */
326 } else if (!isaggr && txok) {
327 /* transmit completion */
328 } else {
329 if (!(tid->state & AGGR_CLEANUP) &&
330 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
331 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
332 ath_tx_set_retry(sc, bf);
333 txpending = 1;
334 } else {
335 bf->bf_state.bf_type |= BUF_XRETRY;
336 txfail = 1;
337 sendbar = 1;
338 }
339 } else {
340 /*
341 * cleanup in progress, just fail
342 * the un-acked sub-frames
343 */
344 txfail = 1;
345 }
346 }
347
348 if (bf_next == NULL) {
349 INIT_LIST_HEAD(&bf_head);
350 } else {
351 ASSERT(!list_empty(bf_q));
352 list_move_tail(&bf->list, &bf_head);
353 }
354
355 if (!txpending) {
356 /*
357 * complete the acked-ones/xretried ones; update
358 * block-ack window
359 */
360 spin_lock_bh(&txq->axq_lock);
361 ath_tx_update_baw(sc, tid, bf->bf_seqno);
362 spin_unlock_bh(&txq->axq_lock);
363
364 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
365 } else {
366 /* retry the un-acked ones */
367 if (bf->bf_next == NULL &&
368 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
369 struct ath_buf *tbf;
370
371 tbf = ath_clone_txbuf(sc, bf_last);
372 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
373 list_add_tail(&tbf->list, &bf_head);
374 } else {
375 /*
376 * Clear descriptor status words for
377 * software retry
378 */
379 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
380 }
381
382 /*
383 * Put this buffer to the temporary pending
384 * queue to retain ordering
385 */
386 list_splice_tail_init(&bf_head, &bf_pending);
387 }
388
389 bf = bf_next;
390 }
391
392 if (tid->state & AGGR_CLEANUP) {
393 if (tid->baw_head == tid->baw_tail) {
394 tid->state &= ~AGGR_ADDBA_COMPLETE;
395 tid->addba_exchangeattempts = 0;
396 tid->state &= ~AGGR_CLEANUP;
397
398 /* send buffered frames as singles */
399 ath_tx_flush_tid(sc, tid);
400 }
401 rcu_read_unlock();
402 return;
403 }
404
405 /* prepend un-acked frames to the beginning of the pending frame queue */
406 if (!list_empty(&bf_pending)) {
407 spin_lock_bh(&txq->axq_lock);
408 list_splice(&bf_pending, &tid->buf_q);
409 ath_tx_queue_tid(txq, tid);
410 spin_unlock_bh(&txq->axq_lock);
411 }
412
413 rcu_read_unlock();
414
415 if (needreset)
416 ath_reset(sc, false);
417 }
418
419 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
420 struct ath_atx_tid *tid)
421 {
422 struct ath_rate_table *rate_table = sc->cur_rate_table;
423 struct sk_buff *skb;
424 struct ieee80211_tx_info *tx_info;
425 struct ieee80211_tx_rate *rates;
426 struct ath_tx_info_priv *tx_info_priv;
427 u32 max_4ms_framelen, frmlen;
428 u16 aggr_limit, legacy = 0, maxampdu;
429 int i;
430
431 skb = (struct sk_buff *)bf->bf_mpdu;
432 tx_info = IEEE80211_SKB_CB(skb);
433 rates = tx_info->control.rates;
434 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
435
436 /*
437 * Find the lowest frame length among the rate series that will have a
438 * 4ms transmit duration.
439 * TODO - TXOP limit needs to be considered.
440 */
441 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
442
443 for (i = 0; i < 4; i++) {
444 if (rates[i].count) {
445 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
446 legacy = 1;
447 break;
448 }
449
450 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
451 max_4ms_framelen = min(max_4ms_framelen, frmlen);
452 }
453 }
454
455 /*
456 * limit aggregate size by the minimum rate if rate selected is
457 * not a probe rate, if rate selected is a probe rate then
458 * avoid aggregation of this packet.
459 */
460 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
461 return 0;
462
463 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
464
465 /*
466 * h/w can accept aggregates upto 16 bit lengths (65535).
467 * The IE, however can hold upto 65536, which shows up here
468 * as zero. Ignore 65536 since we are constrained by hw.
469 */
470 maxampdu = tid->an->maxampdu;
471 if (maxampdu)
472 aggr_limit = min(aggr_limit, maxampdu);
473
474 return aggr_limit;
475 }
476
477 /*
478 * Returns the number of delimiters to be added to
479 * meet the minimum required mpdudensity.
480 * caller should make sure that the rate is HT rate .
481 */
482 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
483 struct ath_buf *bf, u16 frmlen)
484 {
485 struct ath_rate_table *rt = sc->cur_rate_table;
486 struct sk_buff *skb = bf->bf_mpdu;
487 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
488 u32 nsymbits, nsymbols, mpdudensity;
489 u16 minlen;
490 u8 rc, flags, rix;
491 int width, half_gi, ndelim, mindelim;
492
493 /* Select standard number of delimiters based on frame length alone */
494 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
495
496 /*
497 * If encryption enabled, hardware requires some more padding between
498 * subframes.
499 * TODO - this could be improved to be dependent on the rate.
500 * The hardware can keep up at lower rates, but not higher rates
501 */
502 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
503 ndelim += ATH_AGGR_ENCRYPTDELIM;
504
505 /*
506 * Convert desired mpdu density from microeconds to bytes based
507 * on highest rate in rate series (i.e. first rate) to determine
508 * required minimum length for subframe. Take into account
509 * whether high rate is 20 or 40Mhz and half or full GI.
510 */
511 mpdudensity = tid->an->mpdudensity;
512
513 /*
514 * If there is no mpdu density restriction, no further calculation
515 * is needed.
516 */
517 if (mpdudensity == 0)
518 return ndelim;
519
520 rix = tx_info->control.rates[0].idx;
521 flags = tx_info->control.rates[0].flags;
522 rc = rt->info[rix].ratecode;
523 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
524 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
525
526 if (half_gi)
527 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
528 else
529 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
530
531 if (nsymbols == 0)
532 nsymbols = 1;
533
534 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
535 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
536
537 if (frmlen < minlen) {
538 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
539 ndelim = max(mindelim, ndelim);
540 }
541
542 return ndelim;
543 }
544
545 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
546 struct ath_atx_tid *tid,
547 struct list_head *bf_q)
548 {
549 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
550 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
551 int rl = 0, nframes = 0, ndelim, prev_al = 0;
552 u16 aggr_limit = 0, al = 0, bpad = 0,
553 al_delta, h_baw = tid->baw_size / 2;
554 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
555
556 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
557
558 do {
559 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
560
561 /* do not step over block-ack window */
562 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
563 status = ATH_AGGR_BAW_CLOSED;
564 break;
565 }
566
567 if (!rl) {
568 aggr_limit = ath_lookup_rate(sc, bf, tid);
569 rl = 1;
570 }
571
572 /* do not exceed aggregation limit */
573 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
574
575 if (nframes &&
576 (aggr_limit < (al + bpad + al_delta + prev_al))) {
577 status = ATH_AGGR_LIMITED;
578 break;
579 }
580
581 /* do not exceed subframe limit */
582 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
583 status = ATH_AGGR_LIMITED;
584 break;
585 }
586 nframes++;
587
588 /* add padding for previous frame to aggregation length */
589 al += bpad + al_delta;
590
591 /*
592 * Get the delimiters needed to meet the MPDU
593 * density for this node.
594 */
595 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
596 bpad = PADBYTES(al_delta) + (ndelim << 2);
597
598 bf->bf_next = NULL;
599 bf->bf_desc->ds_link = 0;
600
601 /* link buffers of this frame to the aggregate */
602 ath_tx_addto_baw(sc, tid, bf);
603 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
604 list_move_tail(&bf->list, bf_q);
605 if (bf_prev) {
606 bf_prev->bf_next = bf;
607 bf_prev->bf_desc->ds_link = bf->bf_daddr;
608 }
609 bf_prev = bf;
610 } while (!list_empty(&tid->buf_q));
611
612 bf_first->bf_al = al;
613 bf_first->bf_nframes = nframes;
614
615 return status;
616 #undef PADBYTES
617 }
618
619 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
620 struct ath_atx_tid *tid)
621 {
622 struct ath_buf *bf;
623 enum ATH_AGGR_STATUS status;
624 struct list_head bf_q;
625
626 do {
627 if (list_empty(&tid->buf_q))
628 return;
629
630 INIT_LIST_HEAD(&bf_q);
631
632 status = ath_tx_form_aggr(sc, tid, &bf_q);
633
634 /*
635 * no frames picked up to be aggregated;
636 * block-ack window is not open.
637 */
638 if (list_empty(&bf_q))
639 break;
640
641 bf = list_first_entry(&bf_q, struct ath_buf, list);
642 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
643
644 /* if only one frame, send as non-aggregate */
645 if (bf->bf_nframes == 1) {
646 bf->bf_state.bf_type &= ~BUF_AGGR;
647 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
648 ath_buf_set_rate(sc, bf);
649 ath_tx_txqaddbuf(sc, txq, &bf_q);
650 continue;
651 }
652
653 /* setup first desc of aggregate */
654 bf->bf_state.bf_type |= BUF_AGGR;
655 ath_buf_set_rate(sc, bf);
656 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
657
658 /* anchor last desc of aggregate */
659 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
660
661 txq->axq_aggr_depth++;
662 ath_tx_txqaddbuf(sc, txq, &bf_q);
663
664 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
665 status != ATH_AGGR_BAW_CLOSED);
666 }
667
668 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
669 u16 tid, u16 *ssn)
670 {
671 struct ath_atx_tid *txtid;
672 struct ath_node *an;
673
674 an = (struct ath_node *)sta->drv_priv;
675
676 if (sc->sc_flags & SC_OP_TXAGGR) {
677 txtid = ATH_AN_2_TID(an, tid);
678 txtid->state |= AGGR_ADDBA_PROGRESS;
679 ath_tx_pause_tid(sc, txtid);
680 }
681
682 return 0;
683 }
684
685 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
686 {
687 struct ath_node *an = (struct ath_node *)sta->drv_priv;
688 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
689 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
690 struct ath_buf *bf;
691 struct list_head bf_head;
692 INIT_LIST_HEAD(&bf_head);
693
694 if (txtid->state & AGGR_CLEANUP)
695 return 0;
696
697 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
698 txtid->addba_exchangeattempts = 0;
699 return 0;
700 }
701
702 ath_tx_pause_tid(sc, txtid);
703
704 /* drop all software retried frames and mark this TID */
705 spin_lock_bh(&txq->axq_lock);
706 while (!list_empty(&txtid->buf_q)) {
707 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
708 if (!bf_isretried(bf)) {
709 /*
710 * NB: it's based on the assumption that
711 * software retried frame will always stay
712 * at the head of software queue.
713 */
714 break;
715 }
716 list_move_tail(&bf->list, &bf_head);
717 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
718 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
719 }
720 spin_unlock_bh(&txq->axq_lock);
721
722 if (txtid->baw_head != txtid->baw_tail) {
723 txtid->state |= AGGR_CLEANUP;
724 } else {
725 txtid->state &= ~AGGR_ADDBA_COMPLETE;
726 txtid->addba_exchangeattempts = 0;
727 ath_tx_flush_tid(sc, txtid);
728 }
729
730 return 0;
731 }
732
733 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
734 {
735 struct ath_atx_tid *txtid;
736 struct ath_node *an;
737
738 an = (struct ath_node *)sta->drv_priv;
739
740 if (sc->sc_flags & SC_OP_TXAGGR) {
741 txtid = ATH_AN_2_TID(an, tid);
742 txtid->baw_size =
743 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
744 txtid->state |= AGGR_ADDBA_COMPLETE;
745 txtid->state &= ~AGGR_ADDBA_PROGRESS;
746 ath_tx_resume_tid(sc, txtid);
747 }
748 }
749
750 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
751 {
752 struct ath_atx_tid *txtid;
753
754 if (!(sc->sc_flags & SC_OP_TXAGGR))
755 return false;
756
757 txtid = ATH_AN_2_TID(an, tidno);
758
759 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
760 if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
761 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
762 txtid->addba_exchangeattempts++;
763 return true;
764 }
765 }
766
767 return false;
768 }
769
770 /********************/
771 /* Queue Management */
772 /********************/
773
774 static u32 ath_txq_depth(struct ath_softc *sc, int qnum)
775 {
776 return sc->tx.txq[qnum].axq_depth;
777 }
778
779 static void ath_get_beaconconfig(struct ath_softc *sc, int if_id,
780 struct ath_beacon_config *conf)
781 {
782 struct ieee80211_hw *hw = sc->hw;
783
784 /* fill in beacon config data */
785
786 conf->beacon_interval = hw->conf.beacon_int;
787 conf->listen_interval = 100;
788 conf->dtim_count = 1;
789 conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
790 }
791
792 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
793 struct ath_txq *txq)
794 {
795 struct ath_atx_ac *ac, *ac_tmp;
796 struct ath_atx_tid *tid, *tid_tmp;
797
798 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
799 list_del(&ac->list);
800 ac->sched = false;
801 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
802 list_del(&tid->list);
803 tid->sched = false;
804 ath_tid_drain(sc, txq, tid);
805 }
806 }
807 }
808
809 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
810 {
811 struct ath_hal *ah = sc->sc_ah;
812 struct ath9k_tx_queue_info qi;
813 int qnum;
814
815 memset(&qi, 0, sizeof(qi));
816 qi.tqi_subtype = subtype;
817 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
818 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
819 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
820 qi.tqi_physCompBuf = 0;
821
822 /*
823 * Enable interrupts only for EOL and DESC conditions.
824 * We mark tx descriptors to receive a DESC interrupt
825 * when a tx queue gets deep; otherwise waiting for the
826 * EOL to reap descriptors. Note that this is done to
827 * reduce interrupt load and this only defers reaping
828 * descriptors, never transmitting frames. Aside from
829 * reducing interrupts this also permits more concurrency.
830 * The only potential downside is if the tx queue backs
831 * up in which case the top half of the kernel may backup
832 * due to a lack of tx descriptors.
833 *
834 * The UAPSD queue is an exception, since we take a desc-
835 * based intr on the EOSP frames.
836 */
837 if (qtype == ATH9K_TX_QUEUE_UAPSD)
838 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
839 else
840 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
841 TXQ_FLAG_TXDESCINT_ENABLE;
842 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
843 if (qnum == -1) {
844 /*
845 * NB: don't print a message, this happens
846 * normally on parts with too few tx queues
847 */
848 return NULL;
849 }
850 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
851 DPRINTF(sc, ATH_DBG_FATAL,
852 "qnum %u out of range, max %u!\n",
853 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
854 ath9k_hw_releasetxqueue(ah, qnum);
855 return NULL;
856 }
857 if (!ATH_TXQ_SETUP(sc, qnum)) {
858 struct ath_txq *txq = &sc->tx.txq[qnum];
859
860 txq->axq_qnum = qnum;
861 txq->axq_link = NULL;
862 INIT_LIST_HEAD(&txq->axq_q);
863 INIT_LIST_HEAD(&txq->axq_acq);
864 spin_lock_init(&txq->axq_lock);
865 txq->axq_depth = 0;
866 txq->axq_aggr_depth = 0;
867 txq->axq_totalqueued = 0;
868 txq->axq_linkbuf = NULL;
869 sc->tx.txqsetup |= 1<<qnum;
870 }
871 return &sc->tx.txq[qnum];
872 }
873
874 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
875 {
876 int qnum;
877
878 switch (qtype) {
879 case ATH9K_TX_QUEUE_DATA:
880 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
881 DPRINTF(sc, ATH_DBG_FATAL,
882 "HAL AC %u out of range, max %zu!\n",
883 haltype, ARRAY_SIZE(sc->tx.hwq_map));
884 return -1;
885 }
886 qnum = sc->tx.hwq_map[haltype];
887 break;
888 case ATH9K_TX_QUEUE_BEACON:
889 qnum = sc->beacon.beaconq;
890 break;
891 case ATH9K_TX_QUEUE_CAB:
892 qnum = sc->beacon.cabq->axq_qnum;
893 break;
894 default:
895 qnum = -1;
896 }
897 return qnum;
898 }
899
900 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
901 {
902 struct ath_txq *txq = NULL;
903 int qnum;
904
905 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
906 txq = &sc->tx.txq[qnum];
907
908 spin_lock_bh(&txq->axq_lock);
909
910 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
911 DPRINTF(sc, ATH_DBG_FATAL,
912 "TX queue: %d is full, depth: %d\n",
913 qnum, txq->axq_depth);
914 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
915 txq->stopped = 1;
916 spin_unlock_bh(&txq->axq_lock);
917 return NULL;
918 }
919
920 spin_unlock_bh(&txq->axq_lock);
921
922 return txq;
923 }
924
925 int ath_txq_update(struct ath_softc *sc, int qnum,
926 struct ath9k_tx_queue_info *qinfo)
927 {
928 struct ath_hal *ah = sc->sc_ah;
929 int error = 0;
930 struct ath9k_tx_queue_info qi;
931
932 if (qnum == sc->beacon.beaconq) {
933 /*
934 * XXX: for beacon queue, we just save the parameter.
935 * It will be picked up by ath_beaconq_config when
936 * it's necessary.
937 */
938 sc->beacon.beacon_qi = *qinfo;
939 return 0;
940 }
941
942 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
943
944 ath9k_hw_get_txq_props(ah, qnum, &qi);
945 qi.tqi_aifs = qinfo->tqi_aifs;
946 qi.tqi_cwmin = qinfo->tqi_cwmin;
947 qi.tqi_cwmax = qinfo->tqi_cwmax;
948 qi.tqi_burstTime = qinfo->tqi_burstTime;
949 qi.tqi_readyTime = qinfo->tqi_readyTime;
950
951 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
952 DPRINTF(sc, ATH_DBG_FATAL,
953 "Unable to update hardware queue %u!\n", qnum);
954 error = -EIO;
955 } else {
956 ath9k_hw_resettxqueue(ah, qnum);
957 }
958
959 return error;
960 }
961
962 int ath_cabq_update(struct ath_softc *sc)
963 {
964 struct ath9k_tx_queue_info qi;
965 int qnum = sc->beacon.cabq->axq_qnum;
966 struct ath_beacon_config conf;
967
968 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
969 /*
970 * Ensure the readytime % is within the bounds.
971 */
972 if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
973 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
974 else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
975 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
976
977 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
978 qi.tqi_readyTime =
979 (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100;
980 ath_txq_update(sc, qnum, &qi);
981
982 return 0;
983 }
984
985 /*
986 * Drain a given TX queue (could be Beacon or Data)
987 *
988 * This assumes output has been stopped and
989 * we do not need to block ath_tx_tasklet.
990 */
991 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
992 {
993 struct ath_buf *bf, *lastbf;
994 struct list_head bf_head;
995
996 INIT_LIST_HEAD(&bf_head);
997
998 for (;;) {
999 spin_lock_bh(&txq->axq_lock);
1000
1001 if (list_empty(&txq->axq_q)) {
1002 txq->axq_link = NULL;
1003 txq->axq_linkbuf = NULL;
1004 spin_unlock_bh(&txq->axq_lock);
1005 break;
1006 }
1007
1008 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1009
1010 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1011 list_del(&bf->list);
1012 spin_unlock_bh(&txq->axq_lock);
1013
1014 spin_lock_bh(&sc->tx.txbuflock);
1015 list_add_tail(&bf->list, &sc->tx.txbuf);
1016 spin_unlock_bh(&sc->tx.txbuflock);
1017 continue;
1018 }
1019
1020 lastbf = bf->bf_lastbf;
1021 if (!retry_tx)
1022 lastbf->bf_desc->ds_txstat.ts_flags =
1023 ATH9K_TX_SW_ABORTED;
1024
1025 /* remove ath_buf's of the same mpdu from txq */
1026 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1027 txq->axq_depth--;
1028
1029 spin_unlock_bh(&txq->axq_lock);
1030
1031 if (bf_isampdu(bf))
1032 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1033 else
1034 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1035 }
1036
1037 /* flush any pending frames if aggregation is enabled */
1038 if (sc->sc_flags & SC_OP_TXAGGR) {
1039 if (!retry_tx) {
1040 spin_lock_bh(&txq->axq_lock);
1041 ath_txq_drain_pending_buffers(sc, txq);
1042 spin_unlock_bh(&txq->axq_lock);
1043 }
1044 }
1045 }
1046
1047 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1048 {
1049 struct ath_hal *ah = sc->sc_ah;
1050 struct ath_txq *txq;
1051 int i, npend = 0;
1052
1053 if (sc->sc_flags & SC_OP_INVALID)
1054 return;
1055
1056 /* Stop beacon queue */
1057 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1058
1059 /* Stop data queues */
1060 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1061 if (ATH_TXQ_SETUP(sc, i)) {
1062 txq = &sc->tx.txq[i];
1063 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1064 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1065 }
1066 }
1067
1068 if (npend) {
1069 int r;
1070
1071 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1072
1073 spin_lock_bh(&sc->sc_resetlock);
1074 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, true);
1075 if (r)
1076 DPRINTF(sc, ATH_DBG_FATAL,
1077 "Unable to reset hardware; reset status %u\n",
1078 r);
1079 spin_unlock_bh(&sc->sc_resetlock);
1080 }
1081
1082 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1083 if (ATH_TXQ_SETUP(sc, i))
1084 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1085 }
1086 }
1087
1088 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1089 {
1090 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1091 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1092 }
1093
1094 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1095 {
1096 struct ath_atx_ac *ac;
1097 struct ath_atx_tid *tid;
1098
1099 if (list_empty(&txq->axq_acq))
1100 return;
1101
1102 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1103 list_del(&ac->list);
1104 ac->sched = false;
1105
1106 do {
1107 if (list_empty(&ac->tid_q))
1108 return;
1109
1110 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1111 list_del(&tid->list);
1112 tid->sched = false;
1113
1114 if (tid->paused)
1115 continue;
1116
1117 if ((txq->axq_depth % 2) == 0)
1118 ath_tx_sched_aggr(sc, txq, tid);
1119
1120 /*
1121 * add tid to round-robin queue if more frames
1122 * are pending for the tid
1123 */
1124 if (!list_empty(&tid->buf_q))
1125 ath_tx_queue_tid(txq, tid);
1126
1127 break;
1128 } while (!list_empty(&ac->tid_q));
1129
1130 if (!list_empty(&ac->tid_q)) {
1131 if (!ac->sched) {
1132 ac->sched = true;
1133 list_add_tail(&ac->list, &txq->axq_acq);
1134 }
1135 }
1136 }
1137
1138 int ath_tx_setup(struct ath_softc *sc, int haltype)
1139 {
1140 struct ath_txq *txq;
1141
1142 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1143 DPRINTF(sc, ATH_DBG_FATAL,
1144 "HAL AC %u out of range, max %zu!\n",
1145 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1146 return 0;
1147 }
1148 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1149 if (txq != NULL) {
1150 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1151 return 1;
1152 } else
1153 return 0;
1154 }
1155
1156 /***********/
1157 /* TX, DMA */
1158 /***********/
1159
1160 /*
1161 * Insert a chain of ath_buf (descriptors) on a txq and
1162 * assume the descriptors are already chained together by caller.
1163 */
1164 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1165 struct list_head *head)
1166 {
1167 struct ath_hal *ah = sc->sc_ah;
1168 struct ath_buf *bf;
1169
1170 /*
1171 * Insert the frame on the outbound list and
1172 * pass it on to the hardware.
1173 */
1174
1175 if (list_empty(head))
1176 return;
1177
1178 bf = list_first_entry(head, struct ath_buf, list);
1179
1180 list_splice_tail_init(head, &txq->axq_q);
1181 txq->axq_depth++;
1182 txq->axq_totalqueued++;
1183 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1184
1185 DPRINTF(sc, ATH_DBG_QUEUE,
1186 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1187
1188 if (txq->axq_link == NULL) {
1189 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1190 DPRINTF(sc, ATH_DBG_XMIT,
1191 "TXDP[%u] = %llx (%p)\n",
1192 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1193 } else {
1194 *txq->axq_link = bf->bf_daddr;
1195 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1196 txq->axq_qnum, txq->axq_link,
1197 ito64(bf->bf_daddr), bf->bf_desc);
1198 }
1199 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1200 ath9k_hw_txstart(ah, txq->axq_qnum);
1201 }
1202
1203 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1204 {
1205 struct ath_buf *bf = NULL;
1206
1207 spin_lock_bh(&sc->tx.txbuflock);
1208
1209 if (unlikely(list_empty(&sc->tx.txbuf))) {
1210 spin_unlock_bh(&sc->tx.txbuflock);
1211 return NULL;
1212 }
1213
1214 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1215 list_del(&bf->list);
1216
1217 spin_unlock_bh(&sc->tx.txbuflock);
1218
1219 return bf;
1220 }
1221
1222 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1223 struct list_head *bf_head,
1224 struct ath_tx_control *txctl)
1225 {
1226 struct ath_buf *bf;
1227
1228 bf = list_first_entry(bf_head, struct ath_buf, list);
1229 bf->bf_state.bf_type |= BUF_AMPDU;
1230
1231 /*
1232 * Do not queue to h/w when any of the following conditions is true:
1233 * - there are pending frames in software queue
1234 * - the TID is currently paused for ADDBA/BAR request
1235 * - seqno is not within block-ack window
1236 * - h/w queue depth exceeds low water mark
1237 */
1238 if (!list_empty(&tid->buf_q) || tid->paused ||
1239 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1240 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1241 /*
1242 * Add this frame to software queue for scheduling later
1243 * for aggregation.
1244 */
1245 list_move_tail(&bf->list, &tid->buf_q);
1246 ath_tx_queue_tid(txctl->txq, tid);
1247 return;
1248 }
1249
1250 /* Add sub-frame to BAW */
1251 ath_tx_addto_baw(sc, tid, bf);
1252
1253 /* Queue to h/w without aggregation */
1254 bf->bf_nframes = 1;
1255 bf->bf_lastbf = bf;
1256 ath_buf_set_rate(sc, bf);
1257 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1258 }
1259
1260 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1261 struct ath_atx_tid *tid,
1262 struct list_head *bf_head)
1263 {
1264 struct ath_buf *bf;
1265
1266 bf = list_first_entry(bf_head, struct ath_buf, list);
1267 bf->bf_state.bf_type &= ~BUF_AMPDU;
1268
1269 /* update starting sequence number for subsequent ADDBA request */
1270 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1271
1272 bf->bf_nframes = 1;
1273 bf->bf_lastbf = bf;
1274 ath_buf_set_rate(sc, bf);
1275 ath_tx_txqaddbuf(sc, txq, bf_head);
1276 }
1277
1278 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1279 {
1280 struct ieee80211_hdr *hdr;
1281 enum ath9k_pkt_type htype;
1282 __le16 fc;
1283
1284 hdr = (struct ieee80211_hdr *)skb->data;
1285 fc = hdr->frame_control;
1286
1287 if (ieee80211_is_beacon(fc))
1288 htype = ATH9K_PKT_TYPE_BEACON;
1289 else if (ieee80211_is_probe_resp(fc))
1290 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1291 else if (ieee80211_is_atim(fc))
1292 htype = ATH9K_PKT_TYPE_ATIM;
1293 else if (ieee80211_is_pspoll(fc))
1294 htype = ATH9K_PKT_TYPE_PSPOLL;
1295 else
1296 htype = ATH9K_PKT_TYPE_NORMAL;
1297
1298 return htype;
1299 }
1300
1301 static bool is_pae(struct sk_buff *skb)
1302 {
1303 struct ieee80211_hdr *hdr;
1304 __le16 fc;
1305
1306 hdr = (struct ieee80211_hdr *)skb->data;
1307 fc = hdr->frame_control;
1308
1309 if (ieee80211_is_data(fc)) {
1310 if (ieee80211_is_nullfunc(fc) ||
1311 /* Port Access Entity (IEEE 802.1X) */
1312 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1313 return true;
1314 }
1315 }
1316
1317 return false;
1318 }
1319
1320 static int get_hw_crypto_keytype(struct sk_buff *skb)
1321 {
1322 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1323
1324 if (tx_info->control.hw_key) {
1325 if (tx_info->control.hw_key->alg == ALG_WEP)
1326 return ATH9K_KEY_TYPE_WEP;
1327 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1328 return ATH9K_KEY_TYPE_TKIP;
1329 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1330 return ATH9K_KEY_TYPE_AES;
1331 }
1332
1333 return ATH9K_KEY_TYPE_CLEAR;
1334 }
1335
1336 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1337 struct ath_buf *bf)
1338 {
1339 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1340 struct ieee80211_hdr *hdr;
1341 struct ath_node *an;
1342 struct ath_atx_tid *tid;
1343 __le16 fc;
1344 u8 *qc;
1345
1346 if (!tx_info->control.sta)
1347 return;
1348
1349 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1350 hdr = (struct ieee80211_hdr *)skb->data;
1351 fc = hdr->frame_control;
1352
1353 if (ieee80211_is_data_qos(fc)) {
1354 qc = ieee80211_get_qos_ctl(hdr);
1355 bf->bf_tidno = qc[0] & 0xf;
1356 }
1357
1358 /*
1359 * For HT capable stations, we save tidno for later use.
1360 * We also override seqno set by upper layer with the one
1361 * in tx aggregation state.
1362 *
1363 * If fragmentation is on, the sequence number is
1364 * not overridden, since it has been
1365 * incremented by the fragmentation routine.
1366 *
1367 * FIXME: check if the fragmentation threshold exceeds
1368 * IEEE80211 max.
1369 */
1370 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1371 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1372 IEEE80211_SEQ_SEQ_SHIFT);
1373 bf->bf_seqno = tid->seq_next;
1374 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1375 }
1376
1377 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1378 struct ath_txq *txq)
1379 {
1380 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1381 int flags = 0;
1382
1383 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1384 flags |= ATH9K_TXDESC_INTREQ;
1385
1386 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1387 flags |= ATH9K_TXDESC_NOACK;
1388 if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1389 flags |= ATH9K_TXDESC_RTSENA;
1390
1391 return flags;
1392 }
1393
1394 /*
1395 * rix - rate index
1396 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1397 * width - 0 for 20 MHz, 1 for 40 MHz
1398 * half_gi - to use 4us v/s 3.6 us for symbol time
1399 */
1400 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1401 int width, int half_gi, bool shortPreamble)
1402 {
1403 struct ath_rate_table *rate_table = sc->cur_rate_table;
1404 u32 nbits, nsymbits, duration, nsymbols;
1405 u8 rc;
1406 int streams, pktlen;
1407
1408 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1409 rc = rate_table->info[rix].ratecode;
1410
1411 /* for legacy rates, use old function to compute packet duration */
1412 if (!IS_HT_RATE(rc))
1413 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1414 rix, shortPreamble);
1415
1416 /* find number of symbols: PLCP + data */
1417 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1418 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1419 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1420
1421 if (!half_gi)
1422 duration = SYMBOL_TIME(nsymbols);
1423 else
1424 duration = SYMBOL_TIME_HALFGI(nsymbols);
1425
1426 /* addup duration for legacy/ht training and signal fields */
1427 streams = HT_RC_2_STREAMS(rc);
1428 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1429
1430 return duration;
1431 }
1432
1433 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1434 {
1435 struct ath_hal *ah = sc->sc_ah;
1436 struct ath_rate_table *rt;
1437 struct ath_desc *ds = bf->bf_desc;
1438 struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
1439 struct ath9k_11n_rate_series series[4];
1440 struct sk_buff *skb;
1441 struct ieee80211_tx_info *tx_info;
1442 struct ieee80211_tx_rate *rates;
1443 struct ieee80211_hdr *hdr;
1444 struct ieee80211_hw *hw = sc->hw;
1445 int i, flags, rtsctsena = 0, enable_g_protection = 0;
1446 u32 ctsduration = 0;
1447 u8 rix = 0, cix, ctsrate = 0;
1448 __le16 fc;
1449
1450 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1451
1452 skb = (struct sk_buff *)bf->bf_mpdu;
1453 hdr = (struct ieee80211_hdr *)skb->data;
1454 fc = hdr->frame_control;
1455 tx_info = IEEE80211_SKB_CB(skb);
1456 rates = tx_info->control.rates;
1457
1458 if (ieee80211_has_morefrags(fc) ||
1459 (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
1460 rates[1].count = rates[2].count = rates[3].count = 0;
1461 rates[1].idx = rates[2].idx = rates[3].idx = 0;
1462 rates[0].count = ATH_TXMAXTRY;
1463 }
1464
1465 /* get the cix for the lowest valid rix */
1466 rt = sc->cur_rate_table;
1467 for (i = 3; i >= 0; i--) {
1468 if (rates[i].count && (rates[i].idx >= 0)) {
1469 rix = rates[i].idx;
1470 break;
1471 }
1472 }
1473
1474 flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
1475 cix = rt->info[rix].ctrl_rate;
1476
1477 /* All protection frames are transmited at 2Mb/s for 802.11g,
1478 * otherwise we transmit them at 1Mb/s */
1479 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ &&
1480 !conf_is_ht(&hw->conf))
1481 enable_g_protection = 1;
1482
1483 /*
1484 * If 802.11g protection is enabled, determine whether to use RTS/CTS or
1485 * just CTS. Note that this is only done for OFDM/HT unicast frames.
1486 */
1487 if (sc->sc_protmode != PROT_M_NONE && !(bf->bf_flags & ATH9K_TXDESC_NOACK)
1488 && (rt->info[rix].phy == WLAN_RC_PHY_OFDM ||
1489 WLAN_RC_PHY_HT(rt->info[rix].phy))) {
1490 if (sc->sc_protmode == PROT_M_RTSCTS)
1491 flags = ATH9K_TXDESC_RTSENA;
1492 else if (sc->sc_protmode == PROT_M_CTSONLY)
1493 flags = ATH9K_TXDESC_CTSENA;
1494
1495 cix = rt->info[enable_g_protection].ctrl_rate;
1496 rtsctsena = 1;
1497 }
1498
1499 /* For 11n, the default behavior is to enable RTS for hw retried frames.
1500 * We enable the global flag here and let rate series flags determine
1501 * which rates will actually use RTS.
1502 */
1503 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) {
1504 /* 802.11g protection not needed, use our default behavior */
1505 if (!rtsctsena)
1506 flags = ATH9K_TXDESC_RTSENA;
1507 }
1508
1509 /* Set protection if aggregate protection on */
1510 if (sc->sc_config.ath_aggr_prot &&
1511 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1512 flags = ATH9K_TXDESC_RTSENA;
1513 cix = rt->info[enable_g_protection].ctrl_rate;
1514 rtsctsena = 1;
1515 }
1516
1517 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1518 if (bf_isaggr(bf) && (bf->bf_al > ah->ah_caps.rts_aggr_limit))
1519 flags &= ~(ATH9K_TXDESC_RTSENA);
1520
1521 /*
1522 * CTS transmit rate is derived from the transmit rate by looking in the
1523 * h/w rate table. We must also factor in whether or not a short
1524 * preamble is to be used. NB: cix is set above where RTS/CTS is enabled
1525 */
1526 ctsrate = rt->info[cix].ratecode |
1527 (bf_isshpreamble(bf) ? rt->info[cix].short_preamble : 0);
1528
1529 for (i = 0; i < 4; i++) {
1530 if (!rates[i].count || (rates[i].idx < 0))
1531 continue;
1532
1533 rix = rates[i].idx;
1534
1535 series[i].Rate = rt->info[rix].ratecode |
1536 (bf_isshpreamble(bf) ? rt->info[rix].short_preamble : 0);
1537
1538 series[i].Tries = rates[i].count;
1539
1540 series[i].RateFlags = (
1541 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) ?
1542 ATH9K_RATESERIES_RTS_CTS : 0) |
1543 ((rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ?
1544 ATH9K_RATESERIES_2040 : 0) |
1545 ((rates[i].flags & IEEE80211_TX_RC_SHORT_GI) ?
1546 ATH9K_RATESERIES_HALFGI : 0);
1547
1548 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1549 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1550 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1551 bf_isshpreamble(bf));
1552
1553 series[i].ChSel = sc->sc_tx_chainmask;
1554
1555 if (rtsctsena)
1556 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1557 }
1558
1559 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1560 ath9k_hw_set11n_ratescenario(ah, ds, lastds, !bf_ispspoll(bf),
1561 ctsrate, ctsduration,
1562 series, 4, flags);
1563
1564 if (sc->sc_config.ath_aggr_prot && flags)
1565 ath9k_hw_set11n_burstduration(ah, ds, 8192);
1566 }
1567
1568 static int ath_tx_setup_buffer(struct ath_softc *sc, struct ath_buf *bf,
1569 struct sk_buff *skb,
1570 struct ath_tx_control *txctl)
1571 {
1572 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1573 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1574 struct ath_tx_info_priv *tx_info_priv;
1575 int hdrlen;
1576 __le16 fc;
1577
1578 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1579 if (unlikely(!tx_info_priv))
1580 return -ENOMEM;
1581 tx_info->rate_driver_data[0] = tx_info_priv;
1582 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1583 fc = hdr->frame_control;
1584
1585 ATH_TXBUF_RESET(bf);
1586
1587 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1588
1589 if (ieee80211_is_data(fc))
1590 bf->bf_state.bf_type |= BUF_DATA;
1591 if (ieee80211_is_back_req(fc))
1592 bf->bf_state.bf_type |= BUF_BAR;
1593 if (ieee80211_is_pspoll(fc))
1594 bf->bf_state.bf_type |= BUF_PSPOLL;
1595 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1596 bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE;
1597 if ((conf_is_ht(&sc->hw->conf) && !is_pae(skb) &&
1598 (tx_info->flags & IEEE80211_TX_CTL_AMPDU)))
1599 bf->bf_state.bf_type |= BUF_HT;
1600
1601 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1602
1603 bf->bf_keytype = get_hw_crypto_keytype(skb);
1604 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1605 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1606 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1607 } else {
1608 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1609 }
1610
1611 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1612 assign_aggr_tid_seqno(skb, bf);
1613
1614 bf->bf_mpdu = skb;
1615
1616 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1617 skb->len, DMA_TO_DEVICE);
1618 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1619 bf->bf_mpdu = NULL;
1620 DPRINTF(sc, ATH_DBG_CONFIG,
1621 "dma_mapping_error() on TX\n");
1622 return -ENOMEM;
1623 }
1624
1625 bf->bf_buf_addr = bf->bf_dmacontext;
1626 return 0;
1627 }
1628
1629 /* FIXME: tx power */
1630 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1631 struct ath_tx_control *txctl)
1632 {
1633 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1634 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1635 struct ath_node *an = NULL;
1636 struct list_head bf_head;
1637 struct ath_desc *ds;
1638 struct ath_atx_tid *tid;
1639 struct ath_hal *ah = sc->sc_ah;
1640 int frm_type;
1641
1642 frm_type = get_hw_packet_type(skb);
1643
1644 INIT_LIST_HEAD(&bf_head);
1645 list_add_tail(&bf->list, &bf_head);
1646
1647 ds = bf->bf_desc;
1648 ds->ds_link = 0;
1649 ds->ds_data = bf->bf_buf_addr;
1650
1651 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1652 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1653
1654 ath9k_hw_filltxdesc(ah, ds,
1655 skb->len, /* segment length */
1656 true, /* first segment */
1657 true, /* last segment */
1658 ds); /* first descriptor */
1659
1660 spin_lock_bh(&txctl->txq->axq_lock);
1661
1662 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1663 tx_info->control.sta) {
1664 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1665 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1666
1667 if (ath_aggr_query(sc, an, bf->bf_tidno)) {
1668 /*
1669 * Try aggregation if it's a unicast data frame
1670 * and the destination is HT capable.
1671 */
1672 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1673 } else {
1674 /*
1675 * Send this frame as regular when ADDBA
1676 * exchange is neither complete nor pending.
1677 */
1678 ath_tx_send_normal(sc, txctl->txq,
1679 tid, &bf_head);
1680 }
1681 } else {
1682 bf->bf_lastbf = bf;
1683 bf->bf_nframes = 1;
1684
1685 ath_buf_set_rate(sc, bf);
1686 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1687 }
1688
1689 spin_unlock_bh(&txctl->txq->axq_lock);
1690 }
1691
1692 /* Upon failure caller should free skb */
1693 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
1694 struct ath_tx_control *txctl)
1695 {
1696 struct ath_buf *bf;
1697 int r;
1698
1699 bf = ath_tx_get_buffer(sc);
1700 if (!bf) {
1701 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1702 return -1;
1703 }
1704
1705 r = ath_tx_setup_buffer(sc, bf, skb, txctl);
1706 if (unlikely(r)) {
1707 struct ath_txq *txq = txctl->txq;
1708
1709 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1710
1711 /* upon ath_tx_processq() this TX queue will be resumed, we
1712 * guarantee this will happen by knowing beforehand that
1713 * we will at least have to run TX completionon one buffer
1714 * on the queue */
1715 spin_lock_bh(&txq->axq_lock);
1716 if (ath_txq_depth(sc, txq->axq_qnum) > 1) {
1717 ieee80211_stop_queue(sc->hw,
1718 skb_get_queue_mapping(skb));
1719 txq->stopped = 1;
1720 }
1721 spin_unlock_bh(&txq->axq_lock);
1722
1723 spin_lock_bh(&sc->tx.txbuflock);
1724 list_add_tail(&bf->list, &sc->tx.txbuf);
1725 spin_unlock_bh(&sc->tx.txbuflock);
1726
1727 return r;
1728 }
1729
1730 ath_tx_start_dma(sc, bf, txctl);
1731
1732 return 0;
1733 }
1734
1735 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
1736 {
1737 int hdrlen, padsize;
1738 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1739 struct ath_tx_control txctl;
1740
1741 memset(&txctl, 0, sizeof(struct ath_tx_control));
1742
1743 /*
1744 * As a temporary workaround, assign seq# here; this will likely need
1745 * to be cleaned up to work better with Beacon transmission and virtual
1746 * BSSes.
1747 */
1748 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1749 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1750 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1751 sc->tx.seq_no += 0x10;
1752 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1753 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1754 }
1755
1756 /* Add the padding after the header if this is not already done */
1757 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1758 if (hdrlen & 3) {
1759 padsize = hdrlen % 4;
1760 if (skb_headroom(skb) < padsize) {
1761 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
1762 dev_kfree_skb_any(skb);
1763 return;
1764 }
1765 skb_push(skb, padsize);
1766 memmove(skb->data, skb->data + padsize, hdrlen);
1767 }
1768
1769 txctl.txq = sc->beacon.cabq;
1770
1771 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1772
1773 if (ath_tx_start(sc, skb, &txctl) != 0) {
1774 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
1775 goto exit;
1776 }
1777
1778 return;
1779 exit:
1780 dev_kfree_skb_any(skb);
1781 }
1782
1783 /*****************/
1784 /* TX Completion */
1785 /*****************/
1786
1787 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1788 struct ath_xmit_status *tx_status)
1789 {
1790 struct ieee80211_hw *hw = sc->hw;
1791 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1792 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1793 int hdrlen, padsize;
1794
1795 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1796
1797 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1798 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1799 kfree(tx_info_priv);
1800 tx_info->rate_driver_data[0] = NULL;
1801 }
1802
1803 if (tx_status->flags & ATH_TX_BAR) {
1804 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1805 tx_status->flags &= ~ATH_TX_BAR;
1806 }
1807
1808 if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1809 /* Frame was ACKed */
1810 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1811 }
1812
1813 tx_info->status.rates[0].count = tx_status->retries + 1;
1814
1815 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1816 padsize = hdrlen & 3;
1817 if (padsize && hdrlen >= 24) {
1818 /*
1819 * Remove MAC header padding before giving the frame back to
1820 * mac80211.
1821 */
1822 memmove(skb->data + padsize, skb->data, hdrlen);
1823 skb_pull(skb, padsize);
1824 }
1825
1826 ieee80211_tx_status(hw, skb);
1827 }
1828
1829 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1830 struct list_head *bf_q,
1831 int txok, int sendbar)
1832 {
1833 struct sk_buff *skb = bf->bf_mpdu;
1834 struct ath_xmit_status tx_status;
1835 unsigned long flags;
1836
1837 /*
1838 * Set retry information.
1839 * NB: Don't use the information in the descriptor, because the frame
1840 * could be software retried.
1841 */
1842 tx_status.retries = bf->bf_retries;
1843 tx_status.flags = 0;
1844
1845 if (sendbar)
1846 tx_status.flags = ATH_TX_BAR;
1847
1848 if (!txok) {
1849 tx_status.flags |= ATH_TX_ERROR;
1850
1851 if (bf_isxretried(bf))
1852 tx_status.flags |= ATH_TX_XRETRY;
1853 }
1854
1855 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1856 ath_tx_complete(sc, skb, &tx_status);
1857
1858 /*
1859 * Return the list of ath_buf of this mpdu to free queue
1860 */
1861 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1862 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1863 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1864 }
1865
1866 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1867 int txok)
1868 {
1869 struct ath_buf *bf_last = bf->bf_lastbf;
1870 struct ath_desc *ds = bf_last->bf_desc;
1871 u16 seq_st = 0;
1872 u32 ba[WME_BA_BMP_SIZE >> 5];
1873 int ba_index;
1874 int nbad = 0;
1875 int isaggr = 0;
1876
1877 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1878 return 0;
1879
1880 isaggr = bf_isaggr(bf);
1881 if (isaggr) {
1882 seq_st = ATH_DS_BA_SEQ(ds);
1883 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1884 }
1885
1886 while (bf) {
1887 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1888 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1889 nbad++;
1890
1891 bf = bf->bf_next;
1892 }
1893
1894 return nbad;
1895 }
1896
1897 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, int nbad)
1898 {
1899 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1900 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1901 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1902
1903 tx_info_priv->update_rc = false;
1904 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1905 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1906
1907 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1908 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
1909 if (bf_isdata(bf)) {
1910 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1911 sizeof(tx_info_priv->tx));
1912 tx_info_priv->n_frames = bf->bf_nframes;
1913 tx_info_priv->n_bad_frames = nbad;
1914 tx_info_priv->update_rc = true;
1915 }
1916 }
1917 }
1918
1919 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1920 {
1921 int qnum;
1922
1923 spin_lock_bh(&txq->axq_lock);
1924 if (txq->stopped &&
1925 ath_txq_depth(sc, txq->axq_qnum) <= (ATH_TXBUF - 20)) {
1926 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1927 if (qnum != -1) {
1928 ieee80211_wake_queue(sc->hw, qnum);
1929 txq->stopped = 0;
1930 }
1931 }
1932 spin_unlock_bh(&txq->axq_lock);
1933 }
1934
1935 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1936 {
1937 struct ath_hal *ah = sc->sc_ah;
1938 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1939 struct list_head bf_head;
1940 struct ath_desc *ds;
1941 int txok, nbad = 0;
1942 int status;
1943
1944 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1945 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1946 txq->axq_link);
1947
1948 for (;;) {
1949 spin_lock_bh(&txq->axq_lock);
1950 if (list_empty(&txq->axq_q)) {
1951 txq->axq_link = NULL;
1952 txq->axq_linkbuf = NULL;
1953 spin_unlock_bh(&txq->axq_lock);
1954 break;
1955 }
1956 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1957
1958 /*
1959 * There is a race condition that a BH gets scheduled
1960 * after sw writes TxE and before hw re-load the last
1961 * descriptor to get the newly chained one.
1962 * Software must keep the last DONE descriptor as a
1963 * holding descriptor - software does so by marking
1964 * it with the STALE flag.
1965 */
1966 bf_held = NULL;
1967 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1968 bf_held = bf;
1969 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1970 txq->axq_link = NULL;
1971 txq->axq_linkbuf = NULL;
1972 spin_unlock_bh(&txq->axq_lock);
1973
1974 /*
1975 * The holding descriptor is the last
1976 * descriptor in queue. It's safe to remove
1977 * the last holding descriptor in BH context.
1978 */
1979 spin_lock_bh(&sc->tx.txbuflock);
1980 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1981 spin_unlock_bh(&sc->tx.txbuflock);
1982
1983 break;
1984 } else {
1985 bf = list_entry(bf_held->list.next,
1986 struct ath_buf, list);
1987 }
1988 }
1989
1990 lastbf = bf->bf_lastbf;
1991 ds = lastbf->bf_desc;
1992
1993 status = ath9k_hw_txprocdesc(ah, ds);
1994 if (status == -EINPROGRESS) {
1995 spin_unlock_bh(&txq->axq_lock);
1996 break;
1997 }
1998 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1999 txq->axq_lastdsWithCTS = NULL;
2000 if (ds == txq->axq_gatingds)
2001 txq->axq_gatingds = NULL;
2002
2003 /*
2004 * Remove ath_buf's of the same transmit unit from txq,
2005 * however leave the last descriptor back as the holding
2006 * descriptor for hw.
2007 */
2008 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
2009 INIT_LIST_HEAD(&bf_head);
2010 if (!list_is_singular(&lastbf->list))
2011 list_cut_position(&bf_head,
2012 &txq->axq_q, lastbf->list.prev);
2013
2014 txq->axq_depth--;
2015 if (bf_isaggr(bf))
2016 txq->axq_aggr_depth--;
2017
2018 txok = (ds->ds_txstat.ts_status == 0);
2019 spin_unlock_bh(&txq->axq_lock);
2020
2021 if (bf_held) {
2022 spin_lock_bh(&sc->tx.txbuflock);
2023 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2024 spin_unlock_bh(&sc->tx.txbuflock);
2025 }
2026
2027 if (!bf_isampdu(bf)) {
2028 /*
2029 * This frame is sent out as a single frame.
2030 * Use hardware retry status for this frame.
2031 */
2032 bf->bf_retries = ds->ds_txstat.ts_longretry;
2033 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2034 bf->bf_state.bf_type |= BUF_XRETRY;
2035 nbad = 0;
2036 } else {
2037 nbad = ath_tx_num_badfrms(sc, bf, txok);
2038 }
2039
2040 ath_tx_rc_status(bf, ds, nbad);
2041
2042 if (bf_isampdu(bf))
2043 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2044 else
2045 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
2046
2047 ath_wake_mac80211_queue(sc, txq);
2048
2049 spin_lock_bh(&txq->axq_lock);
2050 if (sc->sc_flags & SC_OP_TXAGGR)
2051 ath_txq_schedule(sc, txq);
2052 spin_unlock_bh(&txq->axq_lock);
2053 }
2054 }
2055
2056
2057 void ath_tx_tasklet(struct ath_softc *sc)
2058 {
2059 int i;
2060 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2061
2062 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2063
2064 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2065 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2066 ath_tx_processq(sc, &sc->tx.txq[i]);
2067 }
2068 }
2069
2070 /*****************/
2071 /* Init, Cleanup */
2072 /*****************/
2073
2074 int ath_tx_init(struct ath_softc *sc, int nbufs)
2075 {
2076 int error = 0;
2077
2078 do {
2079 spin_lock_init(&sc->tx.txbuflock);
2080
2081 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2082 "tx", nbufs, 1);
2083 if (error != 0) {
2084 DPRINTF(sc, ATH_DBG_FATAL,
2085 "Failed to allocate tx descriptors: %d\n",
2086 error);
2087 break;
2088 }
2089
2090 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2091 "beacon", ATH_BCBUF, 1);
2092 if (error != 0) {
2093 DPRINTF(sc, ATH_DBG_FATAL,
2094 "Failed to allocate beacon descriptors: %d\n",
2095 error);
2096 break;
2097 }
2098
2099 } while (0);
2100
2101 if (error != 0)
2102 ath_tx_cleanup(sc);
2103
2104 return error;
2105 }
2106
2107 int ath_tx_cleanup(struct ath_softc *sc)
2108 {
2109 if (sc->beacon.bdma.dd_desc_len != 0)
2110 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2111
2112 if (sc->tx.txdma.dd_desc_len != 0)
2113 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2114
2115 return 0;
2116 }
2117
2118 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2119 {
2120 struct ath_atx_tid *tid;
2121 struct ath_atx_ac *ac;
2122 int tidno, acno;
2123
2124 for (tidno = 0, tid = &an->tid[tidno];
2125 tidno < WME_NUM_TID;
2126 tidno++, tid++) {
2127 tid->an = an;
2128 tid->tidno = tidno;
2129 tid->seq_start = tid->seq_next = 0;
2130 tid->baw_size = WME_MAX_BA;
2131 tid->baw_head = tid->baw_tail = 0;
2132 tid->sched = false;
2133 tid->paused = false;
2134 tid->state &= ~AGGR_CLEANUP;
2135 INIT_LIST_HEAD(&tid->buf_q);
2136 acno = TID_TO_WME_AC(tidno);
2137 tid->ac = &an->ac[acno];
2138 tid->state &= ~AGGR_ADDBA_COMPLETE;
2139 tid->state &= ~AGGR_ADDBA_PROGRESS;
2140 tid->addba_exchangeattempts = 0;
2141 }
2142
2143 for (acno = 0, ac = &an->ac[acno];
2144 acno < WME_NUM_AC; acno++, ac++) {
2145 ac->sched = false;
2146 INIT_LIST_HEAD(&ac->tid_q);
2147
2148 switch (acno) {
2149 case WME_AC_BE:
2150 ac->qnum = ath_tx_get_qnum(sc,
2151 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2152 break;
2153 case WME_AC_BK:
2154 ac->qnum = ath_tx_get_qnum(sc,
2155 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2156 break;
2157 case WME_AC_VI:
2158 ac->qnum = ath_tx_get_qnum(sc,
2159 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2160 break;
2161 case WME_AC_VO:
2162 ac->qnum = ath_tx_get_qnum(sc,
2163 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2164 break;
2165 }
2166 }
2167 }
2168
2169 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2170 {
2171 int i;
2172 struct ath_atx_ac *ac, *ac_tmp;
2173 struct ath_atx_tid *tid, *tid_tmp;
2174 struct ath_txq *txq;
2175
2176 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2177 if (ATH_TXQ_SETUP(sc, i)) {
2178 txq = &sc->tx.txq[i];
2179
2180 spin_lock(&txq->axq_lock);
2181
2182 list_for_each_entry_safe(ac,
2183 ac_tmp, &txq->axq_acq, list) {
2184 tid = list_first_entry(&ac->tid_q,
2185 struct ath_atx_tid, list);
2186 if (tid && tid->an != an)
2187 continue;
2188 list_del(&ac->list);
2189 ac->sched = false;
2190
2191 list_for_each_entry_safe(tid,
2192 tid_tmp, &ac->tid_q, list) {
2193 list_del(&tid->list);
2194 tid->sched = false;
2195 ath_tid_drain(sc, txq, tid);
2196 tid->state &= ~AGGR_ADDBA_COMPLETE;
2197 tid->addba_exchangeattempts = 0;
2198 tid->state &= ~AGGR_CLEANUP;
2199 }
2200 }
2201
2202 spin_unlock(&txq->axq_lock);
2203 }
2204 }
2205 }
Linux kernel - Deliverables
This page took 0.075494 seconds and 6 git commands to generate.