2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol
[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
59 * Insert a chain of ath_buf (descriptors) on a txq and
60 * assume the descriptors are already chained together by caller.
61 * NB: must be called with txq lock held
64 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
65 struct list_head
*head
)
67 struct ath_hal
*ah
= sc
->sc_ah
;
71 * Insert the frame on the outbound list and
72 * pass it on to the hardware.
78 bf
= list_first_entry(head
, struct ath_buf
, list
);
80 list_splice_tail_init(head
, &txq
->axq_q
);
82 txq
->axq_totalqueued
++;
83 txq
->axq_linkbuf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
85 DPRINTF(sc
, ATH_DBG_QUEUE
,
86 "qnum: %d, txq depth: %d\n", txq
->axq_qnum
, txq
->axq_depth
);
88 if (txq
->axq_link
== NULL
) {
89 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
90 DPRINTF(sc
, ATH_DBG_XMIT
,
91 "TXDP[%u] = %llx (%p)\n",
92 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
94 *txq
->axq_link
= bf
->bf_daddr
;
95 DPRINTF(sc
, ATH_DBG_XMIT
, "link[%u] (%p)=%llx (%p)\n",
96 txq
->axq_qnum
, txq
->axq_link
,
97 ito64(bf
->bf_daddr
), bf
->bf_desc
);
99 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
100 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
103 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
104 struct ath_xmit_status
*tx_status
)
106 struct ieee80211_hw
*hw
= sc
->hw
;
107 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
108 struct ath_tx_info_priv
*tx_info_priv
= ATH_TX_INFO_PRIV(tx_info
);
111 DPRINTF(sc
, ATH_DBG_XMIT
, "TX complete: skb: %p\n", skb
);
113 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
||
114 tx_info
->flags
& IEEE80211_TX_STAT_TX_FILTERED
) {
116 tx_info
->rate_driver_data
[0] = NULL
;
119 if (tx_status
->flags
& ATH_TX_BAR
) {
120 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
121 tx_status
->flags
&= ~ATH_TX_BAR
;
124 if (!(tx_status
->flags
& (ATH_TX_ERROR
| ATH_TX_XRETRY
))) {
125 /* Frame was ACKed */
126 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
129 tx_info
->status
.rates
[0].count
= tx_status
->retries
+ 1;
131 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
132 padsize
= hdrlen
& 3;
133 if (padsize
&& hdrlen
>= 24) {
135 * Remove MAC header padding before giving the frame back to
138 memmove(skb
->data
+ padsize
, skb
->data
, hdrlen
);
139 skb_pull(skb
, padsize
);
142 ieee80211_tx_status(hw
, skb
);
145 /* Check if it's okay to send out aggregates */
147 static int ath_aggr_query(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
149 struct ath_atx_tid
*tid
;
150 tid
= ATH_AN_2_TID(an
, tidno
);
152 if (tid
->state
& AGGR_ADDBA_COMPLETE
||
153 tid
->state
& AGGR_ADDBA_PROGRESS
)
159 static void ath_get_beaconconfig(struct ath_softc
*sc
, int if_id
,
160 struct ath_beacon_config
*conf
)
162 struct ieee80211_hw
*hw
= sc
->hw
;
164 /* fill in beacon config data */
166 conf
->beacon_interval
= hw
->conf
.beacon_int
;
167 conf
->listen_interval
= 100;
168 conf
->dtim_count
= 1;
169 conf
->bmiss_timeout
= ATH_DEFAULT_BMISS_LIMIT
* conf
->listen_interval
;
172 /* Calculate Atheros packet type from IEEE80211 packet header */
174 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
176 struct ieee80211_hdr
*hdr
;
177 enum ath9k_pkt_type htype
;
180 hdr
= (struct ieee80211_hdr
*)skb
->data
;
181 fc
= hdr
->frame_control
;
183 if (ieee80211_is_beacon(fc
))
184 htype
= ATH9K_PKT_TYPE_BEACON
;
185 else if (ieee80211_is_probe_resp(fc
))
186 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
187 else if (ieee80211_is_atim(fc
))
188 htype
= ATH9K_PKT_TYPE_ATIM
;
189 else if (ieee80211_is_pspoll(fc
))
190 htype
= ATH9K_PKT_TYPE_PSPOLL
;
192 htype
= ATH9K_PKT_TYPE_NORMAL
;
197 static bool is_pae(struct sk_buff
*skb
)
199 struct ieee80211_hdr
*hdr
;
202 hdr
= (struct ieee80211_hdr
*)skb
->data
;
203 fc
= hdr
->frame_control
;
205 if (ieee80211_is_data(fc
)) {
206 if (ieee80211_is_nullfunc(fc
) ||
207 /* Port Access Entity (IEEE 802.1X) */
208 (skb
->protocol
== cpu_to_be16(ETH_P_PAE
))) {
216 static int get_hw_crypto_keytype(struct sk_buff
*skb
)
218 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
220 if (tx_info
->control
.hw_key
) {
221 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
222 return ATH9K_KEY_TYPE_WEP
;
223 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
224 return ATH9K_KEY_TYPE_TKIP
;
225 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
226 return ATH9K_KEY_TYPE_AES
;
229 return ATH9K_KEY_TYPE_CLEAR
;
232 /* Called only when tx aggregation is enabled and HT is supported */
234 static void assign_aggr_tid_seqno(struct sk_buff
*skb
,
237 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
238 struct ieee80211_hdr
*hdr
;
240 struct ath_atx_tid
*tid
;
244 if (!tx_info
->control
.sta
)
247 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
248 hdr
= (struct ieee80211_hdr
*)skb
->data
;
249 fc
= hdr
->frame_control
;
253 if (ieee80211_is_data_qos(fc
)) {
254 qc
= ieee80211_get_qos_ctl(hdr
);
255 bf
->bf_tidno
= qc
[0] & 0xf;
259 /* For HT capable stations, we save tidno for later use.
260 * We also override seqno set by upper layer with the one
261 * in tx aggregation state.
263 * If fragmentation is on, the sequence number is
264 * not overridden, since it has been
265 * incremented by the fragmentation routine.
267 * FIXME: check if the fragmentation threshold exceeds
270 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
271 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<<
272 IEEE80211_SEQ_SEQ_SHIFT
);
273 bf
->bf_seqno
= tid
->seq_next
;
274 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
277 static int setup_tx_flags(struct ath_softc
*sc
, struct sk_buff
*skb
,
280 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
283 flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
284 flags
|= ATH9K_TXDESC_INTREQ
;
286 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
287 flags
|= ATH9K_TXDESC_NOACK
;
288 if (tx_info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
289 flags
|= ATH9K_TXDESC_RTSENA
;
294 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
296 struct ath_buf
*bf
= NULL
;
298 spin_lock_bh(&sc
->tx
.txbuflock
);
300 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
301 spin_unlock_bh(&sc
->tx
.txbuflock
);
305 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
308 spin_unlock_bh(&sc
->tx
.txbuflock
);
313 /* To complete a chain of buffers associated a frame */
315 static void ath_tx_complete_buf(struct ath_softc
*sc
,
317 struct list_head
*bf_q
,
318 int txok
, int sendbar
)
320 struct sk_buff
*skb
= bf
->bf_mpdu
;
321 struct ath_xmit_status tx_status
;
325 * Set retry information.
326 * NB: Don't use the information in the descriptor, because the frame
327 * could be software retried.
329 tx_status
.retries
= bf
->bf_retries
;
333 tx_status
.flags
= ATH_TX_BAR
;
336 tx_status
.flags
|= ATH_TX_ERROR
;
338 if (bf_isxretried(bf
))
339 tx_status
.flags
|= ATH_TX_XRETRY
;
342 /* Unmap this frame */
343 pci_unmap_single(sc
->pdev
,
347 /* complete this frame */
348 ath_tx_complete(sc
, skb
, &tx_status
);
351 * Return the list of ath_buf of this mpdu to free queue
353 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
354 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
355 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
359 * queue up a dest/ac pair for tx scheduling
360 * NB: must be called with txq lock held
363 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
365 struct ath_atx_ac
*ac
= tid
->ac
;
368 * if tid is paused, hold off
374 * add tid to ac atmost once
380 list_add_tail(&tid
->list
, &ac
->tid_q
);
383 * add node ac to txq atmost once
389 list_add_tail(&ac
->list
, &txq
->axq_acq
);
394 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
396 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
398 spin_lock_bh(&txq
->axq_lock
);
402 spin_unlock_bh(&txq
->axq_lock
);
405 /* resume a tid and schedule aggregate */
407 void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
409 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
411 ASSERT(tid
->paused
> 0);
412 spin_lock_bh(&txq
->axq_lock
);
419 if (list_empty(&tid
->buf_q
))
423 * Add this TID to scheduler and try to send out aggregates
425 ath_tx_queue_tid(txq
, tid
);
426 ath_txq_schedule(sc
, txq
);
428 spin_unlock_bh(&txq
->axq_lock
);
431 /* Compute the number of bad frames */
433 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
436 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
437 struct ath_desc
*ds
= bf_last
->bf_desc
;
439 u32 ba
[WME_BA_BMP_SIZE
>> 5];
444 if (ds
->ds_txstat
.ts_flags
== ATH9K_TX_SW_ABORTED
)
447 isaggr
= bf_isaggr(bf
);
449 seq_st
= ATH_DS_BA_SEQ(ds
);
450 memcpy(ba
, ATH_DS_BA_BITMAP(ds
), WME_BA_BMP_SIZE
>> 3);
454 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
455 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
464 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_buf
*bf
)
467 struct ieee80211_hdr
*hdr
;
469 bf
->bf_state
.bf_type
|= BUF_RETRY
;
473 hdr
= (struct ieee80211_hdr
*)skb
->data
;
474 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
477 /* Update block ack window */
479 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
484 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
485 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
487 tid
->tx_buf
[cindex
] = NULL
;
489 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
490 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
491 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
496 * ath_pkt_dur - compute packet duration (NB: not NAV)
499 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
500 * width - 0 for 20 MHz, 1 for 40 MHz
501 * half_gi - to use 4us v/s 3.6 us for symbol time
503 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, struct ath_buf
*bf
,
504 int width
, int half_gi
, bool shortPreamble
)
506 struct ath_rate_table
*rate_table
= sc
->cur_rate_table
;
507 u32 nbits
, nsymbits
, duration
, nsymbols
;
511 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
512 rc
= rate_table
->info
[rix
].ratecode
;
514 /* for legacy rates, use old function to compute packet duration */
516 return ath9k_hw_computetxtime(sc
->sc_ah
, rate_table
, pktlen
,
519 /* find number of symbols: PLCP + data */
520 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
521 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
522 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
525 duration
= SYMBOL_TIME(nsymbols
);
527 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
529 /* addup duration for legacy/ht training and signal fields */
530 streams
= HT_RC_2_STREAMS(rc
);
531 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
536 /* Rate module function to set rate related fields in tx descriptor */
538 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
540 struct ath_hal
*ah
= sc
->sc_ah
;
541 struct ath_rate_table
*rt
;
542 struct ath_desc
*ds
= bf
->bf_desc
;
543 struct ath_desc
*lastds
= bf
->bf_lastbf
->bf_desc
;
544 struct ath9k_11n_rate_series series
[4];
546 struct ieee80211_tx_info
*tx_info
;
547 struct ieee80211_tx_rate
*rates
;
548 struct ieee80211_hdr
*hdr
;
549 int i
, flags
, rtsctsena
= 0;
551 u8 rix
= 0, cix
, ctsrate
= 0;
554 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
556 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
557 hdr
= (struct ieee80211_hdr
*)skb
->data
;
558 fc
= hdr
->frame_control
;
559 tx_info
= IEEE80211_SKB_CB(skb
);
560 rates
= tx_info
->control
.rates
;
562 if (ieee80211_has_morefrags(fc
) ||
563 (le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
)) {
564 rates
[1].count
= rates
[2].count
= rates
[3].count
= 0;
565 rates
[1].idx
= rates
[2].idx
= rates
[3].idx
= 0;
566 rates
[0].count
= ATH_TXMAXTRY
;
569 /* get the cix for the lowest valid rix */
570 rt
= sc
->cur_rate_table
;
571 for (i
= 3; i
>= 0; i
--) {
572 if (rates
[i
].count
&& (rates
[i
].idx
>= 0)) {
578 flags
= (bf
->bf_flags
& (ATH9K_TXDESC_RTSENA
| ATH9K_TXDESC_CTSENA
));
579 cix
= rt
->info
[rix
].ctrl_rate
;
582 * If 802.11g protection is enabled, determine whether to use RTS/CTS or
583 * just CTS. Note that this is only done for OFDM/HT unicast frames.
585 if (sc
->sc_protmode
!= PROT_M_NONE
&& !(bf
->bf_flags
& ATH9K_TXDESC_NOACK
)
586 && (rt
->info
[rix
].phy
== WLAN_RC_PHY_OFDM
||
587 WLAN_RC_PHY_HT(rt
->info
[rix
].phy
))) {
588 if (sc
->sc_protmode
== PROT_M_RTSCTS
)
589 flags
= ATH9K_TXDESC_RTSENA
;
590 else if (sc
->sc_protmode
== PROT_M_CTSONLY
)
591 flags
= ATH9K_TXDESC_CTSENA
;
593 cix
= rt
->info
[sc
->sc_protrix
].ctrl_rate
;
597 /* For 11n, the default behavior is to enable RTS for hw retried frames.
598 * We enable the global flag here and let rate series flags determine
599 * which rates will actually use RTS.
601 if ((ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) && bf_isdata(bf
)) {
602 /* 802.11g protection not needed, use our default behavior */
604 flags
= ATH9K_TXDESC_RTSENA
;
607 /* Set protection if aggregate protection on */
608 if (sc
->sc_config
.ath_aggr_prot
&&
609 (!bf_isaggr(bf
) || (bf_isaggr(bf
) && bf
->bf_al
< 8192))) {
610 flags
= ATH9K_TXDESC_RTSENA
;
611 cix
= rt
->info
[sc
->sc_protrix
].ctrl_rate
;
615 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
616 if (bf_isaggr(bf
) && (bf
->bf_al
> ah
->ah_caps
.rts_aggr_limit
))
617 flags
&= ~(ATH9K_TXDESC_RTSENA
);
620 * CTS transmit rate is derived from the transmit rate by looking in the
621 * h/w rate table. We must also factor in whether or not a short
622 * preamble is to be used. NB: cix is set above where RTS/CTS is enabled
624 ctsrate
= rt
->info
[cix
].ratecode
|
625 (bf_isshpreamble(bf
) ? rt
->info
[cix
].short_preamble
: 0);
627 for (i
= 0; i
< 4; i
++) {
628 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
633 series
[i
].Rate
= rt
->info
[rix
].ratecode
|
634 (bf_isshpreamble(bf
) ? rt
->info
[rix
].short_preamble
: 0);
636 series
[i
].Tries
= rates
[i
].count
;
638 series
[i
].RateFlags
= (
639 (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) ?
640 ATH9K_RATESERIES_RTS_CTS
: 0) |
641 ((rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ?
642 ATH9K_RATESERIES_2040
: 0) |
643 ((rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
) ?
644 ATH9K_RATESERIES_HALFGI
: 0);
646 series
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, bf
,
647 (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) != 0,
648 (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
),
649 bf_isshpreamble(bf
));
651 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
654 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
657 /* set dur_update_en for l-sig computation except for PS-Poll frames */
658 ath9k_hw_set11n_ratescenario(ah
, ds
, lastds
, !bf_ispspoll(bf
),
659 ctsrate
, ctsduration
,
662 if (sc
->sc_config
.ath_aggr_prot
&& flags
)
663 ath9k_hw_set11n_burstduration(ah
, ds
, 8192);
667 * Function to send a normal HT (non-AMPDU) frame
668 * NB: must be called with txq lock held
670 static int ath_tx_send_normal(struct ath_softc
*sc
,
672 struct ath_atx_tid
*tid
,
673 struct list_head
*bf_head
)
677 BUG_ON(list_empty(bf_head
));
679 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
680 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
; /* regular HT frame */
682 /* update starting sequence number for subsequent ADDBA request */
683 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
685 /* Queue to h/w without aggregation */
687 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
688 ath_buf_set_rate(sc
, bf
);
689 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
694 /* flush tid's software queue and send frames as non-ampdu's */
696 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
698 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
700 struct list_head bf_head
;
701 INIT_LIST_HEAD(&bf_head
);
703 ASSERT(tid
->paused
> 0);
704 spin_lock_bh(&txq
->axq_lock
);
708 if (tid
->paused
> 0) {
709 spin_unlock_bh(&txq
->axq_lock
);
713 while (!list_empty(&tid
->buf_q
)) {
714 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
715 ASSERT(!bf_isretried(bf
));
716 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
717 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
720 spin_unlock_bh(&txq
->axq_lock
);
723 /* Completion routine of an aggregate */
725 static void ath_tx_complete_aggr_rifs(struct ath_softc
*sc
,
728 struct list_head
*bf_q
,
731 struct ath_node
*an
= NULL
;
733 struct ieee80211_tx_info
*tx_info
;
734 struct ath_atx_tid
*tid
= NULL
;
735 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
736 struct ath_desc
*ds
= bf_last
->bf_desc
;
737 struct ath_buf
*bf_next
, *bf_lastq
= NULL
;
738 struct list_head bf_head
, bf_pending
;
740 u32 ba
[WME_BA_BMP_SIZE
>> 5];
741 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0;
743 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
744 tx_info
= IEEE80211_SKB_CB(skb
);
746 if (tx_info
->control
.sta
) {
747 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
748 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
751 isaggr
= bf_isaggr(bf
);
754 if (ATH_DS_TX_BA(ds
)) {
756 * extract starting sequence and
759 seq_st
= ATH_DS_BA_SEQ(ds
);
761 ATH_DS_BA_BITMAP(ds
),
762 WME_BA_BMP_SIZE
>> 3);
764 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
767 * AR5416 can become deaf/mute when BA
768 * issue happens. Chip needs to be reset.
769 * But AP code may have sychronization issues
770 * when perform internal reset in this routine.
771 * Only enable reset in STA mode for now.
773 if (sc
->sc_ah
->ah_opmode
==
774 NL80211_IFTYPE_STATION
)
778 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
782 INIT_LIST_HEAD(&bf_pending
);
783 INIT_LIST_HEAD(&bf_head
);
786 txfail
= txpending
= 0;
787 bf_next
= bf
->bf_next
;
789 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
790 /* transmit completion, subframe is
791 * acked by block ack */
792 } else if (!isaggr
&& txok
) {
793 /* transmit completion */
796 if (!(tid
->state
& AGGR_CLEANUP
) &&
797 ds
->ds_txstat
.ts_flags
!= ATH9K_TX_SW_ABORTED
) {
798 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
799 ath_tx_set_retry(sc
, bf
);
802 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
808 * cleanup in progress, just fail
809 * the un-acked sub-frames
815 * Remove ath_buf's of this sub-frame from aggregate queue.
817 if (bf_next
== NULL
) { /* last subframe in the aggregate */
818 ASSERT(bf
->bf_lastfrm
== bf_last
);
821 * The last descriptor of the last sub frame could be
822 * a holding descriptor for h/w. If that's the case,
823 * bf->bf_lastfrm won't be in the bf_q.
824 * Make sure we handle bf_q properly here.
827 if (!list_empty(bf_q
)) {
828 bf_lastq
= list_entry(bf_q
->prev
,
829 struct ath_buf
, list
);
830 list_cut_position(&bf_head
,
831 bf_q
, &bf_lastq
->list
);
834 * XXX: if the last subframe only has one
835 * descriptor which is also being used as
836 * a holding descriptor. Then the ath_buf
837 * is not in the bf_q at all.
839 INIT_LIST_HEAD(&bf_head
);
842 ASSERT(!list_empty(bf_q
));
843 list_cut_position(&bf_head
,
844 bf_q
, &bf
->bf_lastfrm
->list
);
849 * complete the acked-ones/xretried ones; update
852 spin_lock_bh(&txq
->axq_lock
);
853 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
854 spin_unlock_bh(&txq
->axq_lock
);
856 /* complete this sub-frame */
857 ath_tx_complete_buf(sc
, bf
, &bf_head
, !txfail
, sendbar
);
860 * retry the un-acked ones
863 * XXX: if the last descriptor is holding descriptor,
864 * in order to requeue the frame to software queue, we
865 * need to allocate a new descriptor and
866 * copy the content of holding descriptor to it.
868 if (bf
->bf_next
== NULL
&&
869 bf_last
->bf_status
& ATH_BUFSTATUS_STALE
) {
872 /* allocate new descriptor */
873 spin_lock_bh(&sc
->tx
.txbuflock
);
874 ASSERT(!list_empty((&sc
->tx
.txbuf
)));
875 tbf
= list_first_entry(&sc
->tx
.txbuf
,
876 struct ath_buf
, list
);
877 list_del(&tbf
->list
);
878 spin_unlock_bh(&sc
->tx
.txbuflock
);
880 ATH_TXBUF_RESET(tbf
);
882 /* copy descriptor content */
883 tbf
->bf_mpdu
= bf_last
->bf_mpdu
;
884 tbf
->bf_buf_addr
= bf_last
->bf_buf_addr
;
885 *(tbf
->bf_desc
) = *(bf_last
->bf_desc
);
887 /* link it to the frame */
889 bf_lastq
->bf_desc
->ds_link
=
891 bf
->bf_lastfrm
= tbf
;
892 ath9k_hw_cleartxdesc(sc
->sc_ah
,
893 bf
->bf_lastfrm
->bf_desc
);
895 tbf
->bf_state
= bf_last
->bf_state
;
896 tbf
->bf_lastfrm
= tbf
;
897 ath9k_hw_cleartxdesc(sc
->sc_ah
,
898 tbf
->bf_lastfrm
->bf_desc
);
900 /* copy the DMA context */
902 bf_last
->bf_dmacontext
;
904 list_add_tail(&tbf
->list
, &bf_head
);
907 * Clear descriptor status words for
910 ath9k_hw_cleartxdesc(sc
->sc_ah
,
911 bf
->bf_lastfrm
->bf_desc
);
915 * Put this buffer to the temporary pending
916 * queue to retain ordering
918 list_splice_tail_init(&bf_head
, &bf_pending
);
924 if (tid
->state
& AGGR_CLEANUP
) {
925 /* check to see if we're done with cleaning the h/w queue */
926 spin_lock_bh(&txq
->axq_lock
);
928 if (tid
->baw_head
== tid
->baw_tail
) {
929 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
930 tid
->addba_exchangeattempts
= 0;
931 spin_unlock_bh(&txq
->axq_lock
);
933 tid
->state
&= ~AGGR_CLEANUP
;
935 /* send buffered frames as singles */
936 ath_tx_flush_tid(sc
, tid
);
938 spin_unlock_bh(&txq
->axq_lock
);
944 * prepend un-acked frames to the beginning of the pending frame queue
946 if (!list_empty(&bf_pending
)) {
947 spin_lock_bh(&txq
->axq_lock
);
948 /* Note: we _prepend_, we _do_not_ at to
949 * the end of the queue ! */
950 list_splice(&bf_pending
, &tid
->buf_q
);
951 ath_tx_queue_tid(txq
, tid
);
952 spin_unlock_bh(&txq
->axq_lock
);
956 ath_reset(sc
, false);
961 static void ath_tx_rc_status(struct ath_buf
*bf
, struct ath_desc
*ds
, int nbad
)
963 struct sk_buff
*skb
= (struct sk_buff
*)bf
->bf_mpdu
;
964 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
965 struct ath_tx_info_priv
*tx_info_priv
= ATH_TX_INFO_PRIV(tx_info
);
967 tx_info_priv
->update_rc
= false;
968 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
)
969 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
971 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
) == 0 &&
972 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
974 memcpy(&tx_info_priv
->tx
, &ds
->ds_txstat
,
975 sizeof(tx_info_priv
->tx
));
976 tx_info_priv
->n_frames
= bf
->bf_nframes
;
977 tx_info_priv
->n_bad_frames
= nbad
;
978 tx_info_priv
->update_rc
= true;
983 /* Process completed xmit descriptors from the specified queue */
985 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
987 struct ath_hal
*ah
= sc
->sc_ah
;
988 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
989 struct list_head bf_head
;
994 DPRINTF(sc
, ATH_DBG_QUEUE
, "tx queue %d (%x), link %p\n",
995 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
999 spin_lock_bh(&txq
->axq_lock
);
1000 if (list_empty(&txq
->axq_q
)) {
1001 txq
->axq_link
= NULL
;
1002 txq
->axq_linkbuf
= NULL
;
1003 spin_unlock_bh(&txq
->axq_lock
);
1006 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
1009 * There is a race condition that a BH gets scheduled
1010 * after sw writes TxE and before hw re-load the last
1011 * descriptor to get the newly chained one.
1012 * Software must keep the last DONE descriptor as a
1013 * holding descriptor - software does so by marking
1014 * it with the STALE flag.
1017 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
1019 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
1021 * The holding descriptor is the last
1022 * descriptor in queue. It's safe to remove
1023 * the last holding descriptor in BH context.
1025 spin_unlock_bh(&txq
->axq_lock
);
1028 /* Lets work with the next buffer now */
1029 bf
= list_entry(bf_held
->list
.next
,
1030 struct ath_buf
, list
);
1034 lastbf
= bf
->bf_lastbf
;
1035 ds
= lastbf
->bf_desc
; /* NB: last decriptor */
1037 status
= ath9k_hw_txprocdesc(ah
, ds
);
1038 if (status
== -EINPROGRESS
) {
1039 spin_unlock_bh(&txq
->axq_lock
);
1042 if (bf
->bf_desc
== txq
->axq_lastdsWithCTS
)
1043 txq
->axq_lastdsWithCTS
= NULL
;
1044 if (ds
== txq
->axq_gatingds
)
1045 txq
->axq_gatingds
= NULL
;
1048 * Remove ath_buf's of the same transmit unit from txq,
1049 * however leave the last descriptor back as the holding
1050 * descriptor for hw.
1052 lastbf
->bf_status
|= ATH_BUFSTATUS_STALE
;
1053 INIT_LIST_HEAD(&bf_head
);
1055 if (!list_is_singular(&lastbf
->list
))
1056 list_cut_position(&bf_head
,
1057 &txq
->axq_q
, lastbf
->list
.prev
);
1062 txq
->axq_aggr_depth
--;
1064 txok
= (ds
->ds_txstat
.ts_status
== 0);
1066 spin_unlock_bh(&txq
->axq_lock
);
1069 list_del(&bf_held
->list
);
1070 spin_lock_bh(&sc
->tx
.txbuflock
);
1071 list_add_tail(&bf_held
->list
, &sc
->tx
.txbuf
);
1072 spin_unlock_bh(&sc
->tx
.txbuflock
);
1075 if (!bf_isampdu(bf
)) {
1077 * This frame is sent out as a single frame.
1078 * Use hardware retry status for this frame.
1080 bf
->bf_retries
= ds
->ds_txstat
.ts_longretry
;
1081 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
)
1082 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
1085 nbad
= ath_tx_num_badfrms(sc
, bf
, txok
);
1088 ath_tx_rc_status(bf
, ds
, nbad
);
1091 * Complete this transmit unit
1094 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, txok
);
1096 ath_tx_complete_buf(sc
, bf
, &bf_head
, txok
, 0);
1098 /* Wake up mac80211 queue */
1100 spin_lock_bh(&txq
->axq_lock
);
1101 if (txq
->stopped
&& ath_txq_depth(sc
, txq
->axq_qnum
) <=
1104 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
1106 ieee80211_wake_queue(sc
->hw
, qnum
);
1113 * schedule any pending packets if aggregation is enabled
1115 if (sc
->sc_flags
& SC_OP_TXAGGR
)
1116 ath_txq_schedule(sc
, txq
);
1117 spin_unlock_bh(&txq
->axq_lock
);
1121 static void ath_tx_stopdma(struct ath_softc
*sc
, struct ath_txq
*txq
)
1123 struct ath_hal
*ah
= sc
->sc_ah
;
1125 (void) ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1126 DPRINTF(sc
, ATH_DBG_XMIT
, "tx queue [%u] %x, link %p\n",
1127 txq
->axq_qnum
, ath9k_hw_gettxbuf(ah
, txq
->axq_qnum
),
1131 /* Drain only the data queues */
1133 static void ath_drain_txdataq(struct ath_softc
*sc
, bool retry_tx
)
1135 struct ath_hal
*ah
= sc
->sc_ah
;
1136 int i
, status
, npend
= 0;
1138 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
1139 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1140 if (ATH_TXQ_SETUP(sc
, i
)) {
1141 ath_tx_stopdma(sc
, &sc
->tx
.txq
[i
]);
1142 /* The TxDMA may not really be stopped.
1143 * Double check the hal tx pending count */
1144 npend
+= ath9k_hw_numtxpending(ah
,
1145 sc
->tx
.txq
[i
].axq_qnum
);
1151 /* TxDMA not stopped, reset the hal */
1152 DPRINTF(sc
, ATH_DBG_XMIT
, "Unable to stop TxDMA. Reset HAL!\n");
1154 spin_lock_bh(&sc
->sc_resetlock
);
1155 if (!ath9k_hw_reset(ah
,
1156 sc
->sc_ah
->ah_curchan
,
1158 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
1159 sc
->sc_ht_extprotspacing
, true, &status
)) {
1161 DPRINTF(sc
, ATH_DBG_FATAL
,
1162 "Unable to reset hardware; hal status %u\n",
1165 spin_unlock_bh(&sc
->sc_resetlock
);
1168 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1169 if (ATH_TXQ_SETUP(sc
, i
))
1170 ath_tx_draintxq(sc
, &sc
->tx
.txq
[i
], retry_tx
);
1174 /* Add a sub-frame to block ack window */
1176 static void ath_tx_addto_baw(struct ath_softc
*sc
,
1177 struct ath_atx_tid
*tid
,
1182 if (bf_isretried(bf
))
1185 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
1186 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
1188 ASSERT(tid
->tx_buf
[cindex
] == NULL
);
1189 tid
->tx_buf
[cindex
] = bf
;
1191 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
1192 (ATH_TID_MAX_BUFS
- 1))) {
1193 tid
->baw_tail
= cindex
;
1194 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
1199 * Function to send an A-MPDU
1200 * NB: must be called with txq lock held
1202 static int ath_tx_send_ampdu(struct ath_softc
*sc
,
1203 struct ath_atx_tid
*tid
,
1204 struct list_head
*bf_head
,
1205 struct ath_tx_control
*txctl
)
1209 BUG_ON(list_empty(bf_head
));
1211 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1212 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1215 * Do not queue to h/w when any of the following conditions is true:
1216 * - there are pending frames in software queue
1217 * - the TID is currently paused for ADDBA/BAR request
1218 * - seqno is not within block-ack window
1219 * - h/w queue depth exceeds low water mark
1221 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1222 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1223 txctl
->txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1225 * Add this frame to software queue for scheduling later
1228 list_splice_tail_init(bf_head
, &tid
->buf_q
);
1229 ath_tx_queue_tid(txctl
->txq
, tid
);
1233 /* Add sub-frame to BAW */
1234 ath_tx_addto_baw(sc
, tid
, bf
);
1236 /* Queue to h/w without aggregation */
1238 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
1239 ath_buf_set_rate(sc
, bf
);
1240 ath_tx_txqaddbuf(sc
, txctl
->txq
, bf_head
);
1247 * returns aggr limit based on lowest of the rates
1249 static u32
ath_lookup_rate(struct ath_softc
*sc
,
1251 struct ath_atx_tid
*tid
)
1253 struct ath_rate_table
*rate_table
= sc
->cur_rate_table
;
1254 struct sk_buff
*skb
;
1255 struct ieee80211_tx_info
*tx_info
;
1256 struct ieee80211_tx_rate
*rates
;
1257 struct ath_tx_info_priv
*tx_info_priv
;
1258 u32 max_4ms_framelen
, frame_length
;
1259 u16 aggr_limit
, legacy
= 0, maxampdu
;
1262 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1263 tx_info
= IEEE80211_SKB_CB(skb
);
1264 rates
= tx_info
->control
.rates
;
1266 (struct ath_tx_info_priv
*)tx_info
->rate_driver_data
[0];
1269 * Find the lowest frame length among the rate series that will have a
1270 * 4ms transmit duration.
1271 * TODO - TXOP limit needs to be considered.
1273 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
1275 for (i
= 0; i
< 4; i
++) {
1276 if (rates
[i
].count
) {
1277 if (!WLAN_RC_PHY_HT(rate_table
->info
[rates
[i
].idx
].phy
)) {
1283 rate_table
->info
[rates
[i
].idx
].max_4ms_framelen
;
1284 max_4ms_framelen
= min(max_4ms_framelen
, frame_length
);
1289 * limit aggregate size by the minimum rate if rate selected is
1290 * not a probe rate, if rate selected is a probe rate then
1291 * avoid aggregation of this packet.
1293 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
1296 aggr_limit
= min(max_4ms_framelen
,
1297 (u32
)ATH_AMPDU_LIMIT_DEFAULT
);
1300 * h/w can accept aggregates upto 16 bit lengths (65535).
1301 * The IE, however can hold upto 65536, which shows up here
1302 * as zero. Ignore 65536 since we are constrained by hw.
1304 maxampdu
= tid
->an
->maxampdu
;
1306 aggr_limit
= min(aggr_limit
, maxampdu
);
1312 * returns the number of delimiters to be added to
1313 * meet the minimum required mpdudensity.
1314 * caller should make sure that the rate is HT rate .
1316 static int ath_compute_num_delims(struct ath_softc
*sc
,
1317 struct ath_atx_tid
*tid
,
1321 struct ath_rate_table
*rt
= sc
->cur_rate_table
;
1322 struct sk_buff
*skb
= bf
->bf_mpdu
;
1323 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1324 u32 nsymbits
, nsymbols
, mpdudensity
;
1327 int width
, half_gi
, ndelim
, mindelim
;
1329 /* Select standard number of delimiters based on frame length alone */
1330 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
1333 * If encryption enabled, hardware requires some more padding between
1335 * TODO - this could be improved to be dependent on the rate.
1336 * The hardware can keep up at lower rates, but not higher rates
1338 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
1339 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
1342 * Convert desired mpdu density from microeconds to bytes based
1343 * on highest rate in rate series (i.e. first rate) to determine
1344 * required minimum length for subframe. Take into account
1345 * whether high rate is 20 or 40Mhz and half or full GI.
1347 mpdudensity
= tid
->an
->mpdudensity
;
1350 * If there is no mpdu density restriction, no further calculation
1353 if (mpdudensity
== 0)
1356 rix
= tx_info
->control
.rates
[0].idx
;
1357 flags
= tx_info
->control
.rates
[0].flags
;
1358 rc
= rt
->info
[rix
].ratecode
;
1359 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
1360 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
1363 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity
);
1365 nsymbols
= NUM_SYMBOLS_PER_USEC(mpdudensity
);
1370 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
1371 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
1373 /* Is frame shorter than required minimum length? */
1374 if (frmlen
< minlen
) {
1375 /* Get the minimum number of delimiters required. */
1376 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
1377 ndelim
= max(mindelim
, ndelim
);
1384 * For aggregation from software buffer queue.
1385 * NB: must be called with txq lock held
1387 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
1388 struct ath_atx_tid
*tid
,
1389 struct list_head
*bf_q
,
1390 struct ath_buf
**bf_last
,
1391 struct aggr_rifs_param
*param
,
1394 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1395 struct ath_buf
*bf
, *tbf
, *bf_first
, *bf_prev
= NULL
;
1396 struct list_head bf_head
;
1397 int rl
= 0, nframes
= 0, ndelim
;
1398 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
1399 al_delta
, h_baw
= tid
->baw_size
/ 2;
1400 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
1402 INIT_LIST_HEAD(&bf_head
);
1404 BUG_ON(list_empty(&tid
->buf_q
));
1406 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1409 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1412 * do not step over block-ack window
1414 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
1415 status
= ATH_AGGR_BAW_CLOSED
;
1420 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
1425 * do not exceed aggregation limit
1427 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
1429 if (nframes
&& (aggr_limit
<
1430 (al
+ bpad
+ al_delta
+ prev_al
))) {
1431 status
= ATH_AGGR_LIMITED
;
1436 * do not exceed subframe limit
1438 if ((nframes
+ *prev_frames
) >=
1439 min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
1440 status
= ATH_AGGR_LIMITED
;
1445 * add padding for previous frame to aggregation length
1447 al
+= bpad
+ al_delta
;
1450 * Get the delimiters needed to meet the MPDU
1451 * density for this node.
1453 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, bf
->bf_frmlen
);
1455 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
1458 bf
->bf_lastfrm
->bf_desc
->ds_link
= 0;
1461 * this packet is part of an aggregate
1462 * - remove all descriptors belonging to this frame from
1464 * - add it to block ack window
1465 * - set up descriptors for aggregation
1467 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1468 ath_tx_addto_baw(sc
, tid
, bf
);
1470 list_for_each_entry(tbf
, &bf_head
, list
) {
1471 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
,
1472 tbf
->bf_desc
, ndelim
);
1476 * link buffers of this frame to the aggregate
1478 list_splice_tail_init(&bf_head
, bf_q
);
1482 bf_prev
->bf_next
= bf
;
1483 bf_prev
->bf_lastfrm
->bf_desc
->ds_link
= bf
->bf_daddr
;
1489 * terminate aggregation on a small packet boundary
1491 if (bf
->bf_frmlen
< ATH_AGGR_MINPLEN
) {
1492 status
= ATH_AGGR_SHORTPKT
;
1496 } while (!list_empty(&tid
->buf_q
));
1498 bf_first
->bf_al
= al
;
1499 bf_first
->bf_nframes
= nframes
;
1506 * process pending frames possibly doing a-mpdu aggregation
1507 * NB: must be called with txq lock held
1509 static void ath_tx_sched_aggr(struct ath_softc
*sc
,
1510 struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
1512 struct ath_buf
*bf
, *tbf
, *bf_last
, *bf_lastaggr
= NULL
;
1513 enum ATH_AGGR_STATUS status
;
1514 struct list_head bf_q
;
1515 struct aggr_rifs_param param
= {0, 0, 0, 0, NULL
};
1516 int prev_frames
= 0;
1519 if (list_empty(&tid
->buf_q
))
1522 INIT_LIST_HEAD(&bf_q
);
1524 status
= ath_tx_form_aggr(sc
, tid
, &bf_q
, &bf_lastaggr
, ¶m
,
1528 * no frames picked up to be aggregated; block-ack
1529 * window is not open
1531 if (list_empty(&bf_q
))
1534 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1535 bf_last
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1536 bf
->bf_lastbf
= bf_last
;
1539 * if only one frame, send as non-aggregate
1541 if (bf
->bf_nframes
== 1) {
1542 ASSERT(bf
->bf_lastfrm
== bf_last
);
1544 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1546 * clear aggr bits for every descriptor
1547 * XXX TODO: is there a way to optimize it?
1549 list_for_each_entry(tbf
, &bf_q
, list
) {
1550 ath9k_hw_clr11n_aggr(sc
->sc_ah
, tbf
->bf_desc
);
1553 ath_buf_set_rate(sc
, bf
);
1554 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1559 * setup first desc with rate and aggr info
1561 bf
->bf_state
.bf_type
|= BUF_AGGR
;
1562 ath_buf_set_rate(sc
, bf
);
1563 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
1566 * anchor last frame of aggregate correctly
1568 ASSERT(bf_lastaggr
);
1569 ASSERT(bf_lastaggr
->bf_lastfrm
== bf_last
);
1571 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1573 /* XXX: We don't enter into this loop, consider removing this */
1574 while (!list_empty(&bf_q
) && !list_is_last(&tbf
->list
, &bf_q
)) {
1575 tbf
= list_entry(tbf
->list
.next
, struct ath_buf
, list
);
1576 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1579 txq
->axq_aggr_depth
++;
1582 * Normal aggregate, queue to hardware
1584 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1586 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
1587 status
!= ATH_AGGR_BAW_CLOSED
);
1590 /* Called with txq lock held */
1592 static void ath_tid_drain(struct ath_softc
*sc
,
1593 struct ath_txq
*txq
,
1594 struct ath_atx_tid
*tid
)
1598 struct list_head bf_head
;
1599 INIT_LIST_HEAD(&bf_head
);
1602 if (list_empty(&tid
->buf_q
))
1604 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1606 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1608 /* update baw for software retried frame */
1609 if (bf_isretried(bf
))
1610 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1613 * do not indicate packets while holding txq spinlock.
1614 * unlock is intentional here
1616 spin_unlock(&txq
->axq_lock
);
1618 /* complete this sub-frame */
1619 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
1621 spin_lock(&txq
->axq_lock
);
1625 * TODO: For frame(s) that are in the retry state, we will reuse the
1626 * sequence number(s) without setting the retry bit. The
1627 * alternative is to give up on these and BAR the receiver's window
1630 tid
->seq_next
= tid
->seq_start
;
1631 tid
->baw_tail
= tid
->baw_head
;
1635 * Drain all pending buffers
1636 * NB: must be called with txq lock held
1638 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
1639 struct ath_txq
*txq
)
1641 struct ath_atx_ac
*ac
, *ac_tmp
;
1642 struct ath_atx_tid
*tid
, *tid_tmp
;
1644 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1645 list_del(&ac
->list
);
1647 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
1648 list_del(&tid
->list
);
1650 ath_tid_drain(sc
, txq
, tid
);
1655 static int ath_tx_setup_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
,
1656 struct sk_buff
*skb
,
1657 struct ath_tx_control
*txctl
)
1659 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1660 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1661 struct ath_tx_info_priv
*tx_info_priv
;
1665 tx_info_priv
= kzalloc(sizeof(*tx_info_priv
), GFP_ATOMIC
);
1666 if (unlikely(!tx_info_priv
))
1668 tx_info
->rate_driver_data
[0] = tx_info_priv
;
1669 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1670 fc
= hdr
->frame_control
;
1672 ATH_TXBUF_RESET(bf
);
1676 bf
->bf_frmlen
= skb
->len
+ FCS_LEN
- (hdrlen
& 3);
1678 ieee80211_is_data(fc
) ?
1679 (bf
->bf_state
.bf_type
|= BUF_DATA
) :
1680 (bf
->bf_state
.bf_type
&= ~BUF_DATA
);
1681 ieee80211_is_back_req(fc
) ?
1682 (bf
->bf_state
.bf_type
|= BUF_BAR
) :
1683 (bf
->bf_state
.bf_type
&= ~BUF_BAR
);
1684 ieee80211_is_pspoll(fc
) ?
1685 (bf
->bf_state
.bf_type
|= BUF_PSPOLL
) :
1686 (bf
->bf_state
.bf_type
&= ~BUF_PSPOLL
);
1687 (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
) ?
1688 (bf
->bf_state
.bf_type
|= BUF_SHORT_PREAMBLE
) :
1689 (bf
->bf_state
.bf_type
&= ~BUF_SHORT_PREAMBLE
);
1690 (sc
->hw
->conf
.ht
.enabled
&& !is_pae(skb
) &&
1691 (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) ?
1692 (bf
->bf_state
.bf_type
|= BUF_HT
) :
1693 (bf
->bf_state
.bf_type
&= ~BUF_HT
);
1695 bf
->bf_flags
= setup_tx_flags(sc
, skb
, txctl
->txq
);
1699 bf
->bf_keytype
= get_hw_crypto_keytype(skb
);
1701 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
) {
1702 bf
->bf_frmlen
+= tx_info
->control
.hw_key
->icv_len
;
1703 bf
->bf_keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
1705 bf
->bf_keyix
= ATH9K_TXKEYIX_INVALID
;
1708 /* Assign seqno, tidno */
1710 if (ieee80211_is_data_qos(fc
) && (sc
->sc_flags
& SC_OP_TXAGGR
))
1711 assign_aggr_tid_seqno(skb
, bf
);
1716 bf
->bf_dmacontext
= pci_map_single(sc
->pdev
, skb
->data
,
1717 skb
->len
, PCI_DMA_TODEVICE
);
1718 if (unlikely(pci_dma_mapping_error(sc
->pdev
, bf
->bf_dmacontext
))) {
1720 DPRINTF(sc
, ATH_DBG_CONFIG
,
1721 "pci_dma_mapping_error() on TX\n");
1725 bf
->bf_buf_addr
= bf
->bf_dmacontext
;
1729 /* FIXME: tx power */
1730 static void ath_tx_start_dma(struct ath_softc
*sc
, struct ath_buf
*bf
,
1731 struct ath_tx_control
*txctl
)
1733 struct sk_buff
*skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1734 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1735 struct ath_node
*an
= NULL
;
1736 struct list_head bf_head
;
1737 struct ath_desc
*ds
;
1738 struct ath_atx_tid
*tid
;
1739 struct ath_hal
*ah
= sc
->sc_ah
;
1742 frm_type
= get_hw_packet_type(skb
);
1744 INIT_LIST_HEAD(&bf_head
);
1745 list_add_tail(&bf
->list
, &bf_head
);
1747 /* setup descriptor */
1751 ds
->ds_data
= bf
->bf_buf_addr
;
1753 /* Formulate first tx descriptor with tx controls */
1755 ath9k_hw_set11n_txdesc(ah
, ds
, bf
->bf_frmlen
, frm_type
, MAX_RATE_POWER
,
1756 bf
->bf_keyix
, bf
->bf_keytype
, bf
->bf_flags
);
1758 ath9k_hw_filltxdesc(ah
, ds
,
1759 skb
->len
, /* segment length */
1760 true, /* first segment */
1761 true, /* last segment */
1762 ds
); /* first descriptor */
1764 bf
->bf_lastfrm
= bf
;
1766 spin_lock_bh(&txctl
->txq
->axq_lock
);
1768 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
) &&
1769 tx_info
->control
.sta
) {
1770 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1771 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1773 if (ath_aggr_query(sc
, an
, bf
->bf_tidno
)) {
1775 * Try aggregation if it's a unicast data frame
1776 * and the destination is HT capable.
1778 ath_tx_send_ampdu(sc
, tid
, &bf_head
, txctl
);
1781 * Send this frame as regular when ADDBA
1782 * exchange is neither complete nor pending.
1784 ath_tx_send_normal(sc
, txctl
->txq
,
1791 ath_buf_set_rate(sc
, bf
);
1792 ath_tx_txqaddbuf(sc
, txctl
->txq
, &bf_head
);
1795 spin_unlock_bh(&txctl
->txq
->axq_lock
);
1798 /* Upon failure caller should free skb */
1799 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
,
1800 struct ath_tx_control
*txctl
)
1805 /* Check if a tx buffer is available */
1807 bf
= ath_tx_get_buffer(sc
);
1809 DPRINTF(sc
, ATH_DBG_XMIT
, "TX buffers are full\n");
1813 r
= ath_tx_setup_buffer(sc
, bf
, skb
, txctl
);
1815 struct ath_txq
*txq
= txctl
->txq
;
1817 DPRINTF(sc
, ATH_DBG_FATAL
, "TX mem alloc failure\n");
1819 /* upon ath_tx_processq() this TX queue will be resumed, we
1820 * guarantee this will happen by knowing beforehand that
1821 * we will at least have to run TX completionon one buffer
1823 spin_lock_bh(&txq
->axq_lock
);
1824 if (ath_txq_depth(sc
, txq
->axq_qnum
) > 1) {
1825 ieee80211_stop_queue(sc
->hw
,
1826 skb_get_queue_mapping(skb
));
1829 spin_unlock_bh(&txq
->axq_lock
);
1831 spin_lock_bh(&sc
->tx
.txbuflock
);
1832 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
1833 spin_unlock_bh(&sc
->tx
.txbuflock
);
1838 ath_tx_start_dma(sc
, bf
, txctl
);
1843 /* Initialize TX queue and h/w */
1845 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
1850 spin_lock_init(&sc
->tx
.txbuflock
);
1852 /* Setup tx descriptors */
1853 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
1856 DPRINTF(sc
, ATH_DBG_FATAL
,
1857 "Failed to allocate tx descriptors: %d\n",
1862 /* XXX allocate beacon state together with vap */
1863 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
1864 "beacon", ATH_BCBUF
, 1);
1866 DPRINTF(sc
, ATH_DBG_FATAL
,
1867 "Failed to allocate beacon descriptors: %d\n",
1880 /* Reclaim all tx queue resources */
1882 int ath_tx_cleanup(struct ath_softc
*sc
)
1884 /* cleanup beacon descriptors */
1885 if (sc
->beacon
.bdma
.dd_desc_len
!= 0)
1886 ath_descdma_cleanup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
);
1888 /* cleanup tx descriptors */
1889 if (sc
->tx
.txdma
.dd_desc_len
!= 0)
1890 ath_descdma_cleanup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
);
1895 /* Setup a h/w transmit queue */
1897 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1899 struct ath_hal
*ah
= sc
->sc_ah
;
1900 struct ath9k_tx_queue_info qi
;
1903 memset(&qi
, 0, sizeof(qi
));
1904 qi
.tqi_subtype
= subtype
;
1905 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1906 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1907 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1908 qi
.tqi_physCompBuf
= 0;
1911 * Enable interrupts only for EOL and DESC conditions.
1912 * We mark tx descriptors to receive a DESC interrupt
1913 * when a tx queue gets deep; otherwise waiting for the
1914 * EOL to reap descriptors. Note that this is done to
1915 * reduce interrupt load and this only defers reaping
1916 * descriptors, never transmitting frames. Aside from
1917 * reducing interrupts this also permits more concurrency.
1918 * The only potential downside is if the tx queue backs
1919 * up in which case the top half of the kernel may backup
1920 * due to a lack of tx descriptors.
1922 * The UAPSD queue is an exception, since we take a desc-
1923 * based intr on the EOSP frames.
1925 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1926 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1928 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1929 TXQ_FLAG_TXDESCINT_ENABLE
;
1930 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1933 * NB: don't print a message, this happens
1934 * normally on parts with too few tx queues
1938 if (qnum
>= ARRAY_SIZE(sc
->tx
.txq
)) {
1939 DPRINTF(sc
, ATH_DBG_FATAL
,
1940 "qnum %u out of range, max %u!\n",
1941 qnum
, (unsigned int)ARRAY_SIZE(sc
->tx
.txq
));
1942 ath9k_hw_releasetxqueue(ah
, qnum
);
1945 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
1946 struct ath_txq
*txq
= &sc
->tx
.txq
[qnum
];
1948 txq
->axq_qnum
= qnum
;
1949 txq
->axq_link
= NULL
;
1950 INIT_LIST_HEAD(&txq
->axq_q
);
1951 INIT_LIST_HEAD(&txq
->axq_acq
);
1952 spin_lock_init(&txq
->axq_lock
);
1954 txq
->axq_aggr_depth
= 0;
1955 txq
->axq_totalqueued
= 0;
1956 txq
->axq_linkbuf
= NULL
;
1957 sc
->tx
.txqsetup
|= 1<<qnum
;
1959 return &sc
->tx
.txq
[qnum
];
1962 /* Reclaim resources for a setup queue */
1964 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1966 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1967 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1971 * Setup a hardware data transmit queue for the specified
1972 * access control. The hal may not support all requested
1973 * queues in which case it will return a reference to a
1974 * previously setup queue. We record the mapping from ac's
1975 * to h/w queues for use by ath_tx_start and also track
1976 * the set of h/w queues being used to optimize work in the
1977 * transmit interrupt handler and related routines.
1980 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
1982 struct ath_txq
*txq
;
1984 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
1985 DPRINTF(sc
, ATH_DBG_FATAL
,
1986 "HAL AC %u out of range, max %zu!\n",
1987 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
1990 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
1992 sc
->tx
.hwq_map
[haltype
] = txq
->axq_qnum
;
1998 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
2003 case ATH9K_TX_QUEUE_DATA
:
2004 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
2005 DPRINTF(sc
, ATH_DBG_FATAL
,
2006 "HAL AC %u out of range, max %zu!\n",
2007 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
2010 qnum
= sc
->tx
.hwq_map
[haltype
];
2012 case ATH9K_TX_QUEUE_BEACON
:
2013 qnum
= sc
->beacon
.beaconq
;
2015 case ATH9K_TX_QUEUE_CAB
:
2016 qnum
= sc
->beacon
.cabq
->axq_qnum
;
2024 /* Get a transmit queue, if available */
2026 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2028 struct ath_txq
*txq
= NULL
;
2031 qnum
= ath_get_hal_qnum(skb_get_queue_mapping(skb
), sc
);
2032 txq
= &sc
->tx
.txq
[qnum
];
2034 spin_lock_bh(&txq
->axq_lock
);
2036 /* Try to avoid running out of descriptors */
2037 if (txq
->axq_depth
>= (ATH_TXBUF
- 20)) {
2038 DPRINTF(sc
, ATH_DBG_FATAL
,
2039 "TX queue: %d is full, depth: %d\n",
2040 qnum
, txq
->axq_depth
);
2041 ieee80211_stop_queue(sc
->hw
, skb_get_queue_mapping(skb
));
2043 spin_unlock_bh(&txq
->axq_lock
);
2047 spin_unlock_bh(&txq
->axq_lock
);
2052 /* Update parameters for a transmit queue */
2054 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
2055 struct ath9k_tx_queue_info
*qinfo
)
2057 struct ath_hal
*ah
= sc
->sc_ah
;
2059 struct ath9k_tx_queue_info qi
;
2061 if (qnum
== sc
->beacon
.beaconq
) {
2063 * XXX: for beacon queue, we just save the parameter.
2064 * It will be picked up by ath_beaconq_config when
2067 sc
->beacon
.beacon_qi
= *qinfo
;
2071 ASSERT(sc
->tx
.txq
[qnum
].axq_qnum
== qnum
);
2073 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
2074 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
2075 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
2076 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
2077 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
2078 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
2080 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
2081 DPRINTF(sc
, ATH_DBG_FATAL
,
2082 "Unable to update hardware queue %u!\n", qnum
);
2085 ath9k_hw_resettxqueue(ah
, qnum
); /* push to h/w */
2091 int ath_cabq_update(struct ath_softc
*sc
)
2093 struct ath9k_tx_queue_info qi
;
2094 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
2095 struct ath_beacon_config conf
;
2097 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
2099 * Ensure the readytime % is within the bounds.
2101 if (sc
->sc_config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
2102 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
2103 else if (sc
->sc_config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
2104 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
2106 ath_get_beaconconfig(sc
, ATH_IF_ID_ANY
, &conf
);
2108 (conf
.beacon_interval
* sc
->sc_config
.cabqReadytime
) / 100;
2109 ath_txq_update(sc
, qnum
, &qi
);
2114 /* Deferred processing of transmit interrupt */
2116 void ath_tx_tasklet(struct ath_softc
*sc
)
2119 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2121 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2124 * Process each active queue.
2126 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2127 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2128 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2132 void ath_tx_draintxq(struct ath_softc
*sc
,
2133 struct ath_txq
*txq
, bool retry_tx
)
2135 struct ath_buf
*bf
, *lastbf
;
2136 struct list_head bf_head
;
2138 INIT_LIST_HEAD(&bf_head
);
2141 * NB: this assumes output has been stopped and
2142 * we do not need to block ath_tx_tasklet
2145 spin_lock_bh(&txq
->axq_lock
);
2147 if (list_empty(&txq
->axq_q
)) {
2148 txq
->axq_link
= NULL
;
2149 txq
->axq_linkbuf
= NULL
;
2150 spin_unlock_bh(&txq
->axq_lock
);
2154 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2156 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
2157 list_del(&bf
->list
);
2158 spin_unlock_bh(&txq
->axq_lock
);
2160 spin_lock_bh(&sc
->tx
.txbuflock
);
2161 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
2162 spin_unlock_bh(&sc
->tx
.txbuflock
);
2166 lastbf
= bf
->bf_lastbf
;
2168 lastbf
->bf_desc
->ds_txstat
.ts_flags
=
2169 ATH9K_TX_SW_ABORTED
;
2171 /* remove ath_buf's of the same mpdu from txq */
2172 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
2175 spin_unlock_bh(&txq
->axq_lock
);
2178 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, 0);
2180 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2183 /* flush any pending frames if aggregation is enabled */
2184 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2186 spin_lock_bh(&txq
->axq_lock
);
2187 ath_txq_drain_pending_buffers(sc
, txq
);
2188 spin_unlock_bh(&txq
->axq_lock
);
2193 /* Drain the transmit queues and reclaim resources */
2195 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
)
2197 /* stop beacon queue. The beacon will be freed when
2198 * we go to INIT state */
2199 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2200 (void) ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2201 DPRINTF(sc
, ATH_DBG_XMIT
, "beacon queue %x\n",
2202 ath9k_hw_gettxbuf(sc
->sc_ah
, sc
->beacon
.beaconq
));
2205 ath_drain_txdataq(sc
, retry_tx
);
2208 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
)
2210 return sc
->tx
.txq
[qnum
].axq_depth
;
2213 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
)
2215 return sc
->tx
.txq
[qnum
].axq_aggr_depth
;
2218 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
2220 struct ath_atx_tid
*txtid
;
2222 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
2225 txtid
= ATH_AN_2_TID(an
, tidno
);
2227 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
2228 if (!(txtid
->state
& AGGR_ADDBA_PROGRESS
) &&
2229 (txtid
->addba_exchangeattempts
< ADDBA_EXCHANGE_ATTEMPTS
)) {
2230 txtid
->addba_exchangeattempts
++;
2238 /* Start TX aggregation */
2240 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
2243 struct ath_atx_tid
*txtid
;
2244 struct ath_node
*an
;
2246 an
= (struct ath_node
*)sta
->drv_priv
;
2248 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2249 txtid
= ATH_AN_2_TID(an
, tid
);
2250 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
2251 ath_tx_pause_tid(sc
, txtid
);
2257 /* Stop tx aggregation */
2259 int ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
2261 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
2263 ath_tx_aggr_teardown(sc
, an
, tid
);
2267 /* Resume tx aggregation */
2269 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
2271 struct ath_atx_tid
*txtid
;
2272 struct ath_node
*an
;
2274 an
= (struct ath_node
*)sta
->drv_priv
;
2276 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2277 txtid
= ATH_AN_2_TID(an
, tid
);
2279 IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
2280 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
2281 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2282 ath_tx_resume_tid(sc
, txtid
);
2287 * Performs transmit side cleanup when TID changes from aggregated to
2289 * - Pause the TID and mark cleanup in progress
2290 * - Discard all retry frames from the s/w queue.
2293 void ath_tx_aggr_teardown(struct ath_softc
*sc
, struct ath_node
*an
, u8 tid
)
2295 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
2296 struct ath_txq
*txq
= &sc
->tx
.txq
[txtid
->ac
->qnum
];
2298 struct list_head bf_head
;
2299 INIT_LIST_HEAD(&bf_head
);
2301 if (txtid
->state
& AGGR_CLEANUP
) /* cleanup is in progress */
2304 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
2305 txtid
->addba_exchangeattempts
= 0;
2309 /* TID must be paused first */
2310 ath_tx_pause_tid(sc
, txtid
);
2312 /* drop all software retried frames and mark this TID */
2313 spin_lock_bh(&txq
->axq_lock
);
2314 while (!list_empty(&txtid
->buf_q
)) {
2315 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
2316 if (!bf_isretried(bf
)) {
2318 * NB: it's based on the assumption that
2319 * software retried frame will always stay
2320 * at the head of software queue.
2324 list_cut_position(&bf_head
,
2325 &txtid
->buf_q
, &bf
->bf_lastfrm
->list
);
2326 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
2328 /* complete this sub-frame */
2329 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2332 if (txtid
->baw_head
!= txtid
->baw_tail
) {
2333 spin_unlock_bh(&txq
->axq_lock
);
2334 txtid
->state
|= AGGR_CLEANUP
;
2336 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2337 txtid
->addba_exchangeattempts
= 0;
2338 spin_unlock_bh(&txq
->axq_lock
);
2339 ath_tx_flush_tid(sc
, txtid
);
2344 * Tx scheduling logic
2345 * NB: must be called with txq lock held
2348 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
2350 struct ath_atx_ac
*ac
;
2351 struct ath_atx_tid
*tid
;
2353 /* nothing to schedule */
2354 if (list_empty(&txq
->axq_acq
))
2357 * get the first node/ac pair on the queue
2359 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
2360 list_del(&ac
->list
);
2364 * process a single tid per destination
2367 /* nothing to schedule */
2368 if (list_empty(&ac
->tid_q
))
2371 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
2372 list_del(&tid
->list
);
2375 if (tid
->paused
) /* check next tid to keep h/w busy */
2378 if ((txq
->axq_depth
% 2) == 0)
2379 ath_tx_sched_aggr(sc
, txq
, tid
);
2382 * add tid to round-robin queue if more frames
2383 * are pending for the tid
2385 if (!list_empty(&tid
->buf_q
))
2386 ath_tx_queue_tid(txq
, tid
);
2388 /* only schedule one TID at a time */
2390 } while (!list_empty(&ac
->tid_q
));
2393 * schedule AC if more TIDs need processing
2395 if (!list_empty(&ac
->tid_q
)) {
2397 * add dest ac to txq if not already added
2401 list_add_tail(&ac
->list
, &txq
->axq_acq
);
2406 /* Initialize per-node transmit state */
2408 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2410 struct ath_atx_tid
*tid
;
2411 struct ath_atx_ac
*ac
;
2415 * Init per tid tx state
2417 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2418 tidno
< WME_NUM_TID
;
2422 tid
->seq_start
= tid
->seq_next
= 0;
2423 tid
->baw_size
= WME_MAX_BA
;
2424 tid
->baw_head
= tid
->baw_tail
= 0;
2426 tid
->paused
= false;
2427 tid
->state
&= ~AGGR_CLEANUP
;
2428 INIT_LIST_HEAD(&tid
->buf_q
);
2430 acno
= TID_TO_WME_AC(tidno
);
2431 tid
->ac
= &an
->ac
[acno
];
2434 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2435 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2436 tid
->addba_exchangeattempts
= 0;
2440 * Init per ac tx state
2442 for (acno
= 0, ac
= &an
->ac
[acno
];
2443 acno
< WME_NUM_AC
; acno
++, ac
++) {
2445 INIT_LIST_HEAD(&ac
->tid_q
);
2449 ac
->qnum
= ath_tx_get_qnum(sc
,
2450 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2453 ac
->qnum
= ath_tx_get_qnum(sc
,
2454 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2457 ac
->qnum
= ath_tx_get_qnum(sc
,
2458 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2461 ac
->qnum
= ath_tx_get_qnum(sc
,
2462 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2468 /* Cleanupthe pending buffers for the node. */
2470 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2473 struct ath_atx_ac
*ac
, *ac_tmp
;
2474 struct ath_atx_tid
*tid
, *tid_tmp
;
2475 struct ath_txq
*txq
;
2476 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2477 if (ATH_TXQ_SETUP(sc
, i
)) {
2478 txq
= &sc
->tx
.txq
[i
];
2480 spin_lock(&txq
->axq_lock
);
2482 list_for_each_entry_safe(ac
,
2483 ac_tmp
, &txq
->axq_acq
, list
) {
2484 tid
= list_first_entry(&ac
->tid_q
,
2485 struct ath_atx_tid
, list
);
2486 if (tid
&& tid
->an
!= an
)
2488 list_del(&ac
->list
);
2491 list_for_each_entry_safe(tid
,
2492 tid_tmp
, &ac
->tid_q
, list
) {
2493 list_del(&tid
->list
);
2495 ath_tid_drain(sc
, txq
, tid
);
2496 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2497 tid
->addba_exchangeattempts
= 0;
2498 tid
->state
&= ~AGGR_CLEANUP
;
2502 spin_unlock(&txq
->axq_lock
);
2507 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2509 int hdrlen
, padsize
;
2510 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2511 struct ath_tx_control txctl
;
2513 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2516 * As a temporary workaround, assign seq# here; this will likely need
2517 * to be cleaned up to work better with Beacon transmission and virtual
2520 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2521 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2522 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2523 sc
->tx
.seq_no
+= 0x10;
2524 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2525 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
2528 /* Add the padding after the header if this is not already done */
2529 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2531 padsize
= hdrlen
% 4;
2532 if (skb_headroom(skb
) < padsize
) {
2533 DPRINTF(sc
, ATH_DBG_XMIT
, "TX CABQ padding failed\n");
2534 dev_kfree_skb_any(skb
);
2537 skb_push(skb
, padsize
);
2538 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
2541 txctl
.txq
= sc
->beacon
.cabq
;
2543 DPRINTF(sc
, ATH_DBG_XMIT
, "transmitting CABQ packet, skb: %p\n", skb
);
2545 if (ath_tx_start(sc
, skb
, &txctl
) != 0) {
2546 DPRINTF(sc
, ATH_DBG_XMIT
, "CABQ TX failed\n");
2552 dev_kfree_skb_any(skb
);