3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/moduleparam.h>
37 #include <linux/if_arp.h>
38 #include <linux/etherdevice.h>
39 #include <linux/firmware.h>
40 #include <linux/workqueue.h>
41 #include <linux/skbuff.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <asm/unaligned.h>
50 #include "phy_common.h"
60 #include <linux/mmc/sdio_func.h>
62 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63 MODULE_AUTHOR("Martin Langer");
64 MODULE_AUTHOR("Stefano Brivio");
65 MODULE_AUTHOR("Michael Buesch");
66 MODULE_AUTHOR("Gábor Stefanik");
67 MODULE_LICENSE("GPL");
69 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID
);
70 MODULE_FIRMWARE("b43/ucode11.fw");
71 MODULE_FIRMWARE("b43/ucode13.fw");
72 MODULE_FIRMWARE("b43/ucode14.fw");
73 MODULE_FIRMWARE("b43/ucode15.fw");
74 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
75 MODULE_FIRMWARE("b43/ucode5.fw");
76 MODULE_FIRMWARE("b43/ucode9.fw");
78 static int modparam_bad_frames_preempt
;
79 module_param_named(bad_frames_preempt
, modparam_bad_frames_preempt
, int, 0444);
80 MODULE_PARM_DESC(bad_frames_preempt
,
81 "enable(1) / disable(0) Bad Frames Preemption");
83 static char modparam_fwpostfix
[16];
84 module_param_string(fwpostfix
, modparam_fwpostfix
, 16, 0444);
85 MODULE_PARM_DESC(fwpostfix
, "Postfix for the .fw files to load.");
87 static int modparam_hwpctl
;
88 module_param_named(hwpctl
, modparam_hwpctl
, int, 0444);
89 MODULE_PARM_DESC(hwpctl
, "Enable hardware-side power control (default off)");
91 static int modparam_nohwcrypt
;
92 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
93 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
95 static int modparam_hwtkip
;
96 module_param_named(hwtkip
, modparam_hwtkip
, int, 0444);
97 MODULE_PARM_DESC(hwtkip
, "Enable hardware tkip.");
99 static int modparam_qos
= 1;
100 module_param_named(qos
, modparam_qos
, int, 0444);
101 MODULE_PARM_DESC(qos
, "Enable QOS support (default on)");
103 static int modparam_btcoex
= 1;
104 module_param_named(btcoex
, modparam_btcoex
, int, 0444);
105 MODULE_PARM_DESC(btcoex
, "Enable Bluetooth coexistence (default on)");
107 int b43_modparam_verbose
= B43_VERBOSITY_DEFAULT
;
108 module_param_named(verbose
, b43_modparam_verbose
, int, 0644);
109 MODULE_PARM_DESC(verbose
, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111 static int b43_modparam_pio
= B43_PIO_DEFAULT
;
112 module_param_named(pio
, b43_modparam_pio
, int, 0644);
113 MODULE_PARM_DESC(pio
, "Use PIO accesses by default: 0=DMA, 1=PIO");
115 #ifdef CONFIG_B43_BCMA
116 static const struct bcma_device_id b43_bcma_tbl
[] = {
117 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_80211
, 0x11, BCMA_ANY_CLASS
),
118 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_80211
, 0x17, BCMA_ANY_CLASS
),
119 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_80211
, 0x18, BCMA_ANY_CLASS
),
120 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_80211
, 0x1D, BCMA_ANY_CLASS
),
123 MODULE_DEVICE_TABLE(bcma
, b43_bcma_tbl
);
126 #ifdef CONFIG_B43_SSB
127 static const struct ssb_device_id b43_ssb_tbl
[] = {
128 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 5),
129 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 6),
130 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 7),
131 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 9),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 10),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 11),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 12),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 13),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 15),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 16),
140 MODULE_DEVICE_TABLE(ssb
, b43_ssb_tbl
);
143 /* Channel and ratetables are shared for all devices.
144 * They can't be const, because ieee80211 puts some precalculated
145 * data in there. This data is the same for all devices, so we don't
146 * get concurrency issues */
147 #define RATETAB_ENT(_rateid, _flags) \
149 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
150 .hw_value = (_rateid), \
155 * NOTE: When changing this, sync with xmit.c's
156 * b43_plcp_get_bitrate_idx_* functions!
158 static struct ieee80211_rate __b43_ratetable
[] = {
159 RATETAB_ENT(B43_CCK_RATE_1MB
, 0),
160 RATETAB_ENT(B43_CCK_RATE_2MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
161 RATETAB_ENT(B43_CCK_RATE_5MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
162 RATETAB_ENT(B43_CCK_RATE_11MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
163 RATETAB_ENT(B43_OFDM_RATE_6MB
, 0),
164 RATETAB_ENT(B43_OFDM_RATE_9MB
, 0),
165 RATETAB_ENT(B43_OFDM_RATE_12MB
, 0),
166 RATETAB_ENT(B43_OFDM_RATE_18MB
, 0),
167 RATETAB_ENT(B43_OFDM_RATE_24MB
, 0),
168 RATETAB_ENT(B43_OFDM_RATE_36MB
, 0),
169 RATETAB_ENT(B43_OFDM_RATE_48MB
, 0),
170 RATETAB_ENT(B43_OFDM_RATE_54MB
, 0),
173 #define b43_a_ratetable (__b43_ratetable + 4)
174 #define b43_a_ratetable_size 8
175 #define b43_b_ratetable (__b43_ratetable + 0)
176 #define b43_b_ratetable_size 4
177 #define b43_g_ratetable (__b43_ratetable + 0)
178 #define b43_g_ratetable_size 12
180 #define CHAN4G(_channel, _freq, _flags) { \
181 .band = IEEE80211_BAND_2GHZ, \
182 .center_freq = (_freq), \
183 .hw_value = (_channel), \
185 .max_antenna_gain = 0, \
188 static struct ieee80211_channel b43_2ghz_chantable
[] = {
206 #define CHAN5G(_channel, _flags) { \
207 .band = IEEE80211_BAND_5GHZ, \
208 .center_freq = 5000 + (5 * (_channel)), \
209 .hw_value = (_channel), \
211 .max_antenna_gain = 0, \
214 static struct ieee80211_channel b43_5ghz_nphy_chantable
[] = {
215 CHAN5G(32, 0), CHAN5G(34, 0),
216 CHAN5G(36, 0), CHAN5G(38, 0),
217 CHAN5G(40, 0), CHAN5G(42, 0),
218 CHAN5G(44, 0), CHAN5G(46, 0),
219 CHAN5G(48, 0), CHAN5G(50, 0),
220 CHAN5G(52, 0), CHAN5G(54, 0),
221 CHAN5G(56, 0), CHAN5G(58, 0),
222 CHAN5G(60, 0), CHAN5G(62, 0),
223 CHAN5G(64, 0), CHAN5G(66, 0),
224 CHAN5G(68, 0), CHAN5G(70, 0),
225 CHAN5G(72, 0), CHAN5G(74, 0),
226 CHAN5G(76, 0), CHAN5G(78, 0),
227 CHAN5G(80, 0), CHAN5G(82, 0),
228 CHAN5G(84, 0), CHAN5G(86, 0),
229 CHAN5G(88, 0), CHAN5G(90, 0),
230 CHAN5G(92, 0), CHAN5G(94, 0),
231 CHAN5G(96, 0), CHAN5G(98, 0),
232 CHAN5G(100, 0), CHAN5G(102, 0),
233 CHAN5G(104, 0), CHAN5G(106, 0),
234 CHAN5G(108, 0), CHAN5G(110, 0),
235 CHAN5G(112, 0), CHAN5G(114, 0),
236 CHAN5G(116, 0), CHAN5G(118, 0),
237 CHAN5G(120, 0), CHAN5G(122, 0),
238 CHAN5G(124, 0), CHAN5G(126, 0),
239 CHAN5G(128, 0), CHAN5G(130, 0),
240 CHAN5G(132, 0), CHAN5G(134, 0),
241 CHAN5G(136, 0), CHAN5G(138, 0),
242 CHAN5G(140, 0), CHAN5G(142, 0),
243 CHAN5G(144, 0), CHAN5G(145, 0),
244 CHAN5G(146, 0), CHAN5G(147, 0),
245 CHAN5G(148, 0), CHAN5G(149, 0),
246 CHAN5G(150, 0), CHAN5G(151, 0),
247 CHAN5G(152, 0), CHAN5G(153, 0),
248 CHAN5G(154, 0), CHAN5G(155, 0),
249 CHAN5G(156, 0), CHAN5G(157, 0),
250 CHAN5G(158, 0), CHAN5G(159, 0),
251 CHAN5G(160, 0), CHAN5G(161, 0),
252 CHAN5G(162, 0), CHAN5G(163, 0),
253 CHAN5G(164, 0), CHAN5G(165, 0),
254 CHAN5G(166, 0), CHAN5G(168, 0),
255 CHAN5G(170, 0), CHAN5G(172, 0),
256 CHAN5G(174, 0), CHAN5G(176, 0),
257 CHAN5G(178, 0), CHAN5G(180, 0),
258 CHAN5G(182, 0), CHAN5G(184, 0),
259 CHAN5G(186, 0), CHAN5G(188, 0),
260 CHAN5G(190, 0), CHAN5G(192, 0),
261 CHAN5G(194, 0), CHAN5G(196, 0),
262 CHAN5G(198, 0), CHAN5G(200, 0),
263 CHAN5G(202, 0), CHAN5G(204, 0),
264 CHAN5G(206, 0), CHAN5G(208, 0),
265 CHAN5G(210, 0), CHAN5G(212, 0),
266 CHAN5G(214, 0), CHAN5G(216, 0),
267 CHAN5G(218, 0), CHAN5G(220, 0),
268 CHAN5G(222, 0), CHAN5G(224, 0),
269 CHAN5G(226, 0), CHAN5G(228, 0),
272 static struct ieee80211_channel b43_5ghz_aphy_chantable
[] = {
273 CHAN5G(34, 0), CHAN5G(36, 0),
274 CHAN5G(38, 0), CHAN5G(40, 0),
275 CHAN5G(42, 0), CHAN5G(44, 0),
276 CHAN5G(46, 0), CHAN5G(48, 0),
277 CHAN5G(52, 0), CHAN5G(56, 0),
278 CHAN5G(60, 0), CHAN5G(64, 0),
279 CHAN5G(100, 0), CHAN5G(104, 0),
280 CHAN5G(108, 0), CHAN5G(112, 0),
281 CHAN5G(116, 0), CHAN5G(120, 0),
282 CHAN5G(124, 0), CHAN5G(128, 0),
283 CHAN5G(132, 0), CHAN5G(136, 0),
284 CHAN5G(140, 0), CHAN5G(149, 0),
285 CHAN5G(153, 0), CHAN5G(157, 0),
286 CHAN5G(161, 0), CHAN5G(165, 0),
287 CHAN5G(184, 0), CHAN5G(188, 0),
288 CHAN5G(192, 0), CHAN5G(196, 0),
289 CHAN5G(200, 0), CHAN5G(204, 0),
290 CHAN5G(208, 0), CHAN5G(212, 0),
295 static struct ieee80211_supported_band b43_band_5GHz_nphy
= {
296 .band
= IEEE80211_BAND_5GHZ
,
297 .channels
= b43_5ghz_nphy_chantable
,
298 .n_channels
= ARRAY_SIZE(b43_5ghz_nphy_chantable
),
299 .bitrates
= b43_a_ratetable
,
300 .n_bitrates
= b43_a_ratetable_size
,
303 static struct ieee80211_supported_band b43_band_5GHz_aphy
= {
304 .band
= IEEE80211_BAND_5GHZ
,
305 .channels
= b43_5ghz_aphy_chantable
,
306 .n_channels
= ARRAY_SIZE(b43_5ghz_aphy_chantable
),
307 .bitrates
= b43_a_ratetable
,
308 .n_bitrates
= b43_a_ratetable_size
,
311 static struct ieee80211_supported_band b43_band_2GHz
= {
312 .band
= IEEE80211_BAND_2GHZ
,
313 .channels
= b43_2ghz_chantable
,
314 .n_channels
= ARRAY_SIZE(b43_2ghz_chantable
),
315 .bitrates
= b43_g_ratetable
,
316 .n_bitrates
= b43_g_ratetable_size
,
319 static void b43_wireless_core_exit(struct b43_wldev
*dev
);
320 static int b43_wireless_core_init(struct b43_wldev
*dev
);
321 static struct b43_wldev
* b43_wireless_core_stop(struct b43_wldev
*dev
);
322 static int b43_wireless_core_start(struct b43_wldev
*dev
);
323 static void b43_op_bss_info_changed(struct ieee80211_hw
*hw
,
324 struct ieee80211_vif
*vif
,
325 struct ieee80211_bss_conf
*conf
,
328 static int b43_ratelimit(struct b43_wl
*wl
)
330 if (!wl
|| !wl
->current_dev
)
332 if (b43_status(wl
->current_dev
) < B43_STAT_STARTED
)
334 /* We are up and running.
335 * Ratelimit the messages to avoid DoS over the net. */
336 return net_ratelimit();
339 void b43info(struct b43_wl
*wl
, const char *fmt
, ...)
341 struct va_format vaf
;
344 if (b43_modparam_verbose
< B43_VERBOSITY_INFO
)
346 if (!b43_ratelimit(wl
))
354 printk(KERN_INFO
"b43-%s: %pV",
355 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan", &vaf
);
360 void b43err(struct b43_wl
*wl
, const char *fmt
, ...)
362 struct va_format vaf
;
365 if (b43_modparam_verbose
< B43_VERBOSITY_ERROR
)
367 if (!b43_ratelimit(wl
))
375 printk(KERN_ERR
"b43-%s ERROR: %pV",
376 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan", &vaf
);
381 void b43warn(struct b43_wl
*wl
, const char *fmt
, ...)
383 struct va_format vaf
;
386 if (b43_modparam_verbose
< B43_VERBOSITY_WARN
)
388 if (!b43_ratelimit(wl
))
396 printk(KERN_WARNING
"b43-%s warning: %pV",
397 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan", &vaf
);
402 void b43dbg(struct b43_wl
*wl
, const char *fmt
, ...)
404 struct va_format vaf
;
407 if (b43_modparam_verbose
< B43_VERBOSITY_DEBUG
)
415 printk(KERN_DEBUG
"b43-%s debug: %pV",
416 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan", &vaf
);
421 static void b43_ram_write(struct b43_wldev
*dev
, u16 offset
, u32 val
)
425 B43_WARN_ON(offset
% 4 != 0);
427 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
428 if (macctl
& B43_MACCTL_BE
)
431 b43_write32(dev
, B43_MMIO_RAM_CONTROL
, offset
);
433 b43_write32(dev
, B43_MMIO_RAM_DATA
, val
);
436 static inline void b43_shm_control_word(struct b43_wldev
*dev
,
437 u16 routing
, u16 offset
)
441 /* "offset" is the WORD offset. */
445 b43_write32(dev
, B43_MMIO_SHM_CONTROL
, control
);
448 u32
b43_shm_read32(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
452 if (routing
== B43_SHM_SHARED
) {
453 B43_WARN_ON(offset
& 0x0001);
454 if (offset
& 0x0003) {
455 /* Unaligned access */
456 b43_shm_control_word(dev
, routing
, offset
>> 2);
457 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
458 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
459 ret
|= ((u32
)b43_read16(dev
, B43_MMIO_SHM_DATA
)) << 16;
465 b43_shm_control_word(dev
, routing
, offset
);
466 ret
= b43_read32(dev
, B43_MMIO_SHM_DATA
);
471 u16
b43_shm_read16(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
475 if (routing
== B43_SHM_SHARED
) {
476 B43_WARN_ON(offset
& 0x0001);
477 if (offset
& 0x0003) {
478 /* Unaligned access */
479 b43_shm_control_word(dev
, routing
, offset
>> 2);
480 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
486 b43_shm_control_word(dev
, routing
, offset
);
487 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA
);
492 void b43_shm_write32(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u32 value
)
494 if (routing
== B43_SHM_SHARED
) {
495 B43_WARN_ON(offset
& 0x0001);
496 if (offset
& 0x0003) {
497 /* Unaligned access */
498 b43_shm_control_word(dev
, routing
, offset
>> 2);
499 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
,
501 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
502 b43_write16(dev
, B43_MMIO_SHM_DATA
,
503 (value
>> 16) & 0xFFFF);
508 b43_shm_control_word(dev
, routing
, offset
);
509 b43_write32(dev
, B43_MMIO_SHM_DATA
, value
);
512 void b43_shm_write16(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u16 value
)
514 if (routing
== B43_SHM_SHARED
) {
515 B43_WARN_ON(offset
& 0x0001);
516 if (offset
& 0x0003) {
517 /* Unaligned access */
518 b43_shm_control_word(dev
, routing
, offset
>> 2);
519 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
, value
);
524 b43_shm_control_word(dev
, routing
, offset
);
525 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
);
529 u64
b43_hf_read(struct b43_wldev
*dev
)
533 ret
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFHI
);
535 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFMI
);
537 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFLO
);
542 /* Write HostFlags */
543 void b43_hf_write(struct b43_wldev
*dev
, u64 value
)
547 lo
= (value
& 0x00000000FFFFULL
);
548 mi
= (value
& 0x0000FFFF0000ULL
) >> 16;
549 hi
= (value
& 0xFFFF00000000ULL
) >> 32;
550 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFLO
, lo
);
551 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFMI
, mi
);
552 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFHI
, hi
);
555 /* Read the firmware capabilities bitmask (Opensource firmware only) */
556 static u16
b43_fwcapa_read(struct b43_wldev
*dev
)
558 B43_WARN_ON(!dev
->fw
.opensource
);
559 return b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_FWCAPA
);
562 void b43_tsf_read(struct b43_wldev
*dev
, u64
*tsf
)
566 B43_WARN_ON(dev
->dev
->core_rev
< 3);
568 /* The hardware guarantees us an atomic read, if we
569 * read the low register first. */
570 low
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
);
571 high
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
578 static void b43_time_lock(struct b43_wldev
*dev
)
582 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
583 macctl
|= B43_MACCTL_TBTTHOLD
;
584 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
585 /* Commit the write */
586 b43_read32(dev
, B43_MMIO_MACCTL
);
589 static void b43_time_unlock(struct b43_wldev
*dev
)
593 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
594 macctl
&= ~B43_MACCTL_TBTTHOLD
;
595 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
596 /* Commit the write */
597 b43_read32(dev
, B43_MMIO_MACCTL
);
600 static void b43_tsf_write_locked(struct b43_wldev
*dev
, u64 tsf
)
604 B43_WARN_ON(dev
->dev
->core_rev
< 3);
608 /* The hardware guarantees us an atomic write, if we
609 * write the low register first. */
610 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, low
);
612 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
, high
);
616 void b43_tsf_write(struct b43_wldev
*dev
, u64 tsf
)
619 b43_tsf_write_locked(dev
, tsf
);
620 b43_time_unlock(dev
);
624 void b43_macfilter_set(struct b43_wldev
*dev
, u16 offset
, const u8
*mac
)
626 static const u8 zero_addr
[ETH_ALEN
] = { 0 };
633 b43_write16(dev
, B43_MMIO_MACFILTER_CONTROL
, offset
);
637 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
640 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
643 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
646 static void b43_write_mac_bssid_templates(struct b43_wldev
*dev
)
650 u8 mac_bssid
[ETH_ALEN
* 2];
654 bssid
= dev
->wl
->bssid
;
655 mac
= dev
->wl
->mac_addr
;
657 b43_macfilter_set(dev
, B43_MACFILTER_BSSID
, bssid
);
659 memcpy(mac_bssid
, mac
, ETH_ALEN
);
660 memcpy(mac_bssid
+ ETH_ALEN
, bssid
, ETH_ALEN
);
662 /* Write our MAC address and BSSID to template ram */
663 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
)) {
664 tmp
= (u32
) (mac_bssid
[i
+ 0]);
665 tmp
|= (u32
) (mac_bssid
[i
+ 1]) << 8;
666 tmp
|= (u32
) (mac_bssid
[i
+ 2]) << 16;
667 tmp
|= (u32
) (mac_bssid
[i
+ 3]) << 24;
668 b43_ram_write(dev
, 0x20 + i
, tmp
);
672 static void b43_upload_card_macaddress(struct b43_wldev
*dev
)
674 b43_write_mac_bssid_templates(dev
);
675 b43_macfilter_set(dev
, B43_MACFILTER_SELF
, dev
->wl
->mac_addr
);
678 static void b43_set_slot_time(struct b43_wldev
*dev
, u16 slot_time
)
680 /* slot_time is in usec. */
681 /* This test used to exit for all but a G PHY. */
682 if (b43_current_band(dev
->wl
) == IEEE80211_BAND_5GHZ
)
684 b43_write16(dev
, B43_MMIO_IFSSLOT
, 510 + slot_time
);
685 /* Shared memory location 0x0010 is the slot time and should be
686 * set to slot_time; however, this register is initially 0 and changing
687 * the value adversely affects the transmit rate for BCM4311
688 * devices. Until this behavior is unterstood, delete this step
690 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
694 static void b43_short_slot_timing_enable(struct b43_wldev
*dev
)
696 b43_set_slot_time(dev
, 9);
699 static void b43_short_slot_timing_disable(struct b43_wldev
*dev
)
701 b43_set_slot_time(dev
, 20);
704 /* DummyTransmission function, as documented on
705 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
707 void b43_dummy_transmission(struct b43_wldev
*dev
, bool ofdm
, bool pa_on
)
709 struct b43_phy
*phy
= &dev
->phy
;
710 unsigned int i
, max_loop
;
722 buffer
[0] = 0x000201CC;
725 buffer
[0] = 0x000B846E;
728 for (i
= 0; i
< 5; i
++)
729 b43_ram_write(dev
, i
* 4, buffer
[i
]);
731 b43_write16(dev
, 0x0568, 0x0000);
732 if (dev
->dev
->core_rev
< 11)
733 b43_write16(dev
, 0x07C0, 0x0000);
735 b43_write16(dev
, 0x07C0, 0x0100);
736 value
= (ofdm
? 0x41 : 0x40);
737 b43_write16(dev
, 0x050C, value
);
738 if ((phy
->type
== B43_PHYTYPE_N
) || (phy
->type
== B43_PHYTYPE_LP
))
739 b43_write16(dev
, 0x0514, 0x1A02);
740 b43_write16(dev
, 0x0508, 0x0000);
741 b43_write16(dev
, 0x050A, 0x0000);
742 b43_write16(dev
, 0x054C, 0x0000);
743 b43_write16(dev
, 0x056A, 0x0014);
744 b43_write16(dev
, 0x0568, 0x0826);
745 b43_write16(dev
, 0x0500, 0x0000);
746 if (!pa_on
&& (phy
->type
== B43_PHYTYPE_N
)) {
752 b43_write16(dev
, 0x0502, 0x00D0);
755 b43_write16(dev
, 0x0502, 0x0050);
758 b43_write16(dev
, 0x0502, 0x0030);
761 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
762 b43_radio_write16(dev
, 0x0051, 0x0017);
763 for (i
= 0x00; i
< max_loop
; i
++) {
764 value
= b43_read16(dev
, 0x050E);
769 for (i
= 0x00; i
< 0x0A; i
++) {
770 value
= b43_read16(dev
, 0x050E);
775 for (i
= 0x00; i
< 0x19; i
++) {
776 value
= b43_read16(dev
, 0x0690);
777 if (!(value
& 0x0100))
781 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
782 b43_radio_write16(dev
, 0x0051, 0x0037);
785 static void key_write(struct b43_wldev
*dev
,
786 u8 index
, u8 algorithm
, const u8
*key
)
793 /* Key index/algo block */
794 kidx
= b43_kidx_to_fw(dev
, index
);
795 value
= ((kidx
<< 4) | algorithm
);
796 b43_shm_write16(dev
, B43_SHM_SHARED
,
797 B43_SHM_SH_KEYIDXBLOCK
+ (kidx
* 2), value
);
799 /* Write the key to the Key Table Pointer offset */
800 offset
= dev
->ktp
+ (index
* B43_SEC_KEYSIZE
);
801 for (i
= 0; i
< B43_SEC_KEYSIZE
; i
+= 2) {
803 value
|= (u16
) (key
[i
+ 1]) << 8;
804 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
, value
);
808 static void keymac_write(struct b43_wldev
*dev
, u8 index
, const u8
*addr
)
810 u32 addrtmp
[2] = { 0, 0, };
811 u8 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
813 if (b43_new_kidx_api(dev
))
814 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
816 B43_WARN_ON(index
< pairwise_keys_start
);
817 /* We have four default TX keys and possibly four default RX keys.
818 * Physical mac 0 is mapped to physical key 4 or 8, depending
819 * on the firmware version.
820 * So we must adjust the index here.
822 index
-= pairwise_keys_start
;
823 B43_WARN_ON(index
>= B43_NR_PAIRWISE_KEYS
);
826 addrtmp
[0] = addr
[0];
827 addrtmp
[0] |= ((u32
) (addr
[1]) << 8);
828 addrtmp
[0] |= ((u32
) (addr
[2]) << 16);
829 addrtmp
[0] |= ((u32
) (addr
[3]) << 24);
830 addrtmp
[1] = addr
[4];
831 addrtmp
[1] |= ((u32
) (addr
[5]) << 8);
834 /* Receive match transmitter address (RCMTA) mechanism */
835 b43_shm_write32(dev
, B43_SHM_RCMTA
,
836 (index
* 2) + 0, addrtmp
[0]);
837 b43_shm_write16(dev
, B43_SHM_RCMTA
,
838 (index
* 2) + 1, addrtmp
[1]);
841 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
842 * When a packet is received, the iv32 is checked.
843 * - if it doesn't the packet is returned without modification (and software
844 * decryption can be done). That's what happen when iv16 wrap.
845 * - if it does, the rc4 key is computed, and decryption is tried.
846 * Either it will success and B43_RX_MAC_DEC is returned,
847 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
848 * and the packet is not usable (it got modified by the ucode).
849 * So in order to never have B43_RX_MAC_DECERR, we should provide
850 * a iv32 and phase1key that match. Because we drop packets in case of
851 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
852 * packets will be lost without higher layer knowing (ie no resync possible
855 * NOTE : this should support 50 key like RCMTA because
856 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
858 static void rx_tkip_phase1_write(struct b43_wldev
*dev
, u8 index
, u32 iv32
,
863 u8 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
865 if (!modparam_hwtkip
)
868 if (b43_new_kidx_api(dev
))
869 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
871 B43_WARN_ON(index
< pairwise_keys_start
);
872 /* We have four default TX keys and possibly four default RX keys.
873 * Physical mac 0 is mapped to physical key 4 or 8, depending
874 * on the firmware version.
875 * So we must adjust the index here.
877 index
-= pairwise_keys_start
;
878 B43_WARN_ON(index
>= B43_NR_PAIRWISE_KEYS
);
880 if (b43_debug(dev
, B43_DBG_KEYS
)) {
881 b43dbg(dev
->wl
, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
884 /* Write the key to the RX tkip shared mem */
885 offset
= B43_SHM_SH_TKIPTSCTTAK
+ index
* (10 + 4);
886 for (i
= 0; i
< 10; i
+= 2) {
887 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
,
888 phase1key
? phase1key
[i
/ 2] : 0);
890 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
, iv32
);
891 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
+ 2, iv32
>> 16);
894 static void b43_op_update_tkip_key(struct ieee80211_hw
*hw
,
895 struct ieee80211_vif
*vif
,
896 struct ieee80211_key_conf
*keyconf
,
897 struct ieee80211_sta
*sta
,
898 u32 iv32
, u16
*phase1key
)
900 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
901 struct b43_wldev
*dev
;
902 int index
= keyconf
->hw_key_idx
;
904 if (B43_WARN_ON(!modparam_hwtkip
))
907 /* This is only called from the RX path through mac80211, where
908 * our mutex is already locked. */
909 B43_WARN_ON(!mutex_is_locked(&wl
->mutex
));
910 dev
= wl
->current_dev
;
911 B43_WARN_ON(!dev
|| b43_status(dev
) < B43_STAT_INITIALIZED
);
913 keymac_write(dev
, index
, NULL
); /* First zero out mac to avoid race */
915 rx_tkip_phase1_write(dev
, index
, iv32
, phase1key
);
916 /* only pairwise TKIP keys are supported right now */
919 keymac_write(dev
, index
, sta
->addr
);
922 static void do_key_write(struct b43_wldev
*dev
,
923 u8 index
, u8 algorithm
,
924 const u8
*key
, size_t key_len
, const u8
*mac_addr
)
926 u8 buf
[B43_SEC_KEYSIZE
] = { 0, };
927 u8 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
929 if (b43_new_kidx_api(dev
))
930 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
932 B43_WARN_ON(index
>= ARRAY_SIZE(dev
->key
));
933 B43_WARN_ON(key_len
> B43_SEC_KEYSIZE
);
935 if (index
>= pairwise_keys_start
)
936 keymac_write(dev
, index
, NULL
); /* First zero out mac. */
937 if (algorithm
== B43_SEC_ALGO_TKIP
) {
939 * We should provide an initial iv32, phase1key pair.
940 * We could start with iv32=0 and compute the corresponding
941 * phase1key, but this means calling ieee80211_get_tkip_key
942 * with a fake skb (or export other tkip function).
943 * Because we are lazy we hope iv32 won't start with
944 * 0xffffffff and let's b43_op_update_tkip_key provide a
947 rx_tkip_phase1_write(dev
, index
, 0xffffffff, (u16
*)buf
);
948 } else if (index
>= pairwise_keys_start
) /* clear it */
949 rx_tkip_phase1_write(dev
, index
, 0, NULL
);
951 memcpy(buf
, key
, key_len
);
952 key_write(dev
, index
, algorithm
, buf
);
953 if (index
>= pairwise_keys_start
)
954 keymac_write(dev
, index
, mac_addr
);
956 dev
->key
[index
].algorithm
= algorithm
;
959 static int b43_key_write(struct b43_wldev
*dev
,
960 int index
, u8 algorithm
,
961 const u8
*key
, size_t key_len
,
963 struct ieee80211_key_conf
*keyconf
)
966 int pairwise_keys_start
;
968 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
969 * - Temporal Encryption Key (128 bits)
970 * - Temporal Authenticator Tx MIC Key (64 bits)
971 * - Temporal Authenticator Rx MIC Key (64 bits)
973 * Hardware only store TEK
975 if (algorithm
== B43_SEC_ALGO_TKIP
&& key_len
== 32)
977 if (key_len
> B43_SEC_KEYSIZE
)
979 for (i
= 0; i
< ARRAY_SIZE(dev
->key
); i
++) {
980 /* Check that we don't already have this key. */
981 B43_WARN_ON(dev
->key
[i
].keyconf
== keyconf
);
984 /* Pairwise key. Get an empty slot for the key. */
985 if (b43_new_kidx_api(dev
))
986 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
988 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
989 for (i
= pairwise_keys_start
;
990 i
< pairwise_keys_start
+ B43_NR_PAIRWISE_KEYS
;
992 B43_WARN_ON(i
>= ARRAY_SIZE(dev
->key
));
993 if (!dev
->key
[i
].keyconf
) {
1000 b43warn(dev
->wl
, "Out of hardware key memory\n");
1004 B43_WARN_ON(index
> 3);
1006 do_key_write(dev
, index
, algorithm
, key
, key_len
, mac_addr
);
1007 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
1008 /* Default RX key */
1009 B43_WARN_ON(mac_addr
);
1010 do_key_write(dev
, index
+ 4, algorithm
, key
, key_len
, NULL
);
1012 keyconf
->hw_key_idx
= index
;
1013 dev
->key
[index
].keyconf
= keyconf
;
1018 static int b43_key_clear(struct b43_wldev
*dev
, int index
)
1020 if (B43_WARN_ON((index
< 0) || (index
>= ARRAY_SIZE(dev
->key
))))
1022 do_key_write(dev
, index
, B43_SEC_ALGO_NONE
,
1023 NULL
, B43_SEC_KEYSIZE
, NULL
);
1024 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
1025 do_key_write(dev
, index
+ 4, B43_SEC_ALGO_NONE
,
1026 NULL
, B43_SEC_KEYSIZE
, NULL
);
1028 dev
->key
[index
].keyconf
= NULL
;
1033 static void b43_clear_keys(struct b43_wldev
*dev
)
1037 if (b43_new_kidx_api(dev
))
1038 count
= B43_NR_GROUP_KEYS
+ B43_NR_PAIRWISE_KEYS
;
1040 count
= B43_NR_GROUP_KEYS
* 2 + B43_NR_PAIRWISE_KEYS
;
1041 for (i
= 0; i
< count
; i
++)
1042 b43_key_clear(dev
, i
);
1045 static void b43_dump_keymemory(struct b43_wldev
*dev
)
1047 unsigned int i
, index
, count
, offset
, pairwise_keys_start
;
1053 struct b43_key
*key
;
1055 if (!b43_debug(dev
, B43_DBG_KEYS
))
1058 hf
= b43_hf_read(dev
);
1059 b43dbg(dev
->wl
, "Hardware key memory dump: USEDEFKEYS=%u\n",
1060 !!(hf
& B43_HF_USEDEFKEYS
));
1061 if (b43_new_kidx_api(dev
)) {
1062 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
1063 count
= B43_NR_GROUP_KEYS
+ B43_NR_PAIRWISE_KEYS
;
1065 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
1066 count
= B43_NR_GROUP_KEYS
* 2 + B43_NR_PAIRWISE_KEYS
;
1068 for (index
= 0; index
< count
; index
++) {
1069 key
= &(dev
->key
[index
]);
1070 printk(KERN_DEBUG
"Key slot %02u: %s",
1071 index
, (key
->keyconf
== NULL
) ? " " : "*");
1072 offset
= dev
->ktp
+ (index
* B43_SEC_KEYSIZE
);
1073 for (i
= 0; i
< B43_SEC_KEYSIZE
; i
+= 2) {
1074 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, offset
+ i
);
1075 printk("%02X%02X", (tmp
& 0xFF), ((tmp
>> 8) & 0xFF));
1078 algo
= b43_shm_read16(dev
, B43_SHM_SHARED
,
1079 B43_SHM_SH_KEYIDXBLOCK
+ (index
* 2));
1080 printk(" Algo: %04X/%02X", algo
, key
->algorithm
);
1082 if (index
>= pairwise_keys_start
) {
1083 if (key
->algorithm
== B43_SEC_ALGO_TKIP
) {
1085 offset
= B43_SHM_SH_TKIPTSCTTAK
+ (index
- 4) * (10 + 4);
1086 for (i
= 0; i
< 14; i
+= 2) {
1087 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, offset
+ i
);
1088 printk("%02X%02X", (tmp
& 0xFF), ((tmp
>> 8) & 0xFF));
1091 rcmta0
= b43_shm_read32(dev
, B43_SHM_RCMTA
,
1092 ((index
- pairwise_keys_start
) * 2) + 0);
1093 rcmta1
= b43_shm_read16(dev
, B43_SHM_RCMTA
,
1094 ((index
- pairwise_keys_start
) * 2) + 1);
1095 *((__le32
*)(&mac
[0])) = cpu_to_le32(rcmta0
);
1096 *((__le16
*)(&mac
[4])) = cpu_to_le16(rcmta1
);
1097 printk(" MAC: %pM", mac
);
1099 printk(" DEFAULT KEY");
1104 void b43_power_saving_ctl_bits(struct b43_wldev
*dev
, unsigned int ps_flags
)
1112 B43_WARN_ON((ps_flags
& B43_PS_ENABLED
) &&
1113 (ps_flags
& B43_PS_DISABLED
));
1114 B43_WARN_ON((ps_flags
& B43_PS_AWAKE
) && (ps_flags
& B43_PS_ASLEEP
));
1116 if (ps_flags
& B43_PS_ENABLED
) {
1118 } else if (ps_flags
& B43_PS_DISABLED
) {
1121 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1122 // and thus is not an AP and we are associated, set bit 25
1124 if (ps_flags
& B43_PS_AWAKE
) {
1126 } else if (ps_flags
& B43_PS_ASLEEP
) {
1129 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1130 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1131 // successful, set bit26
1134 /* FIXME: For now we force awake-on and hwps-off */
1138 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1140 macctl
|= B43_MACCTL_HWPS
;
1142 macctl
&= ~B43_MACCTL_HWPS
;
1144 macctl
|= B43_MACCTL_AWAKE
;
1146 macctl
&= ~B43_MACCTL_AWAKE
;
1147 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1149 b43_read32(dev
, B43_MMIO_MACCTL
);
1150 if (awake
&& dev
->dev
->core_rev
>= 5) {
1151 /* Wait for the microcode to wake up. */
1152 for (i
= 0; i
< 100; i
++) {
1153 ucstat
= b43_shm_read16(dev
, B43_SHM_SHARED
,
1154 B43_SHM_SH_UCODESTAT
);
1155 if (ucstat
!= B43_SHM_SH_UCODESTAT_SLEEP
)
1162 #ifdef CONFIG_B43_BCMA
1163 static void b43_bcma_phy_reset(struct b43_wldev
*dev
)
1167 /* Put PHY into reset */
1168 flags
= bcma_aread32(dev
->dev
->bdev
, BCMA_IOCTL
);
1169 flags
|= B43_BCMA_IOCTL_PHY_RESET
;
1170 flags
|= B43_BCMA_IOCTL_PHY_BW_20MHZ
; /* Make 20 MHz def */
1171 bcma_awrite32(dev
->dev
->bdev
, BCMA_IOCTL
, flags
);
1174 /* Take PHY out of reset */
1175 flags
= bcma_aread32(dev
->dev
->bdev
, BCMA_IOCTL
);
1176 flags
&= ~B43_BCMA_IOCTL_PHY_RESET
;
1177 flags
|= BCMA_IOCTL_FGC
;
1178 bcma_awrite32(dev
->dev
->bdev
, BCMA_IOCTL
, flags
);
1181 /* Do not force clock anymore */
1182 flags
= bcma_aread32(dev
->dev
->bdev
, BCMA_IOCTL
);
1183 flags
&= ~BCMA_IOCTL_FGC
;
1184 bcma_awrite32(dev
->dev
->bdev
, BCMA_IOCTL
, flags
);
1188 static void b43_bcma_wireless_core_reset(struct b43_wldev
*dev
, bool gmode
)
1190 b43_device_enable(dev
, B43_BCMA_IOCTL_PHY_CLKEN
);
1191 bcma_core_set_clockmode(dev
->dev
->bdev
, BCMA_CLKMODE_FAST
);
1192 b43_bcma_phy_reset(dev
);
1193 bcma_core_pll_ctl(dev
->dev
->bdev
, 0x300, 0x3000000, true);
1197 static void b43_ssb_wireless_core_reset(struct b43_wldev
*dev
, bool gmode
)
1199 struct ssb_device
*sdev
= dev
->dev
->sdev
;
1204 flags
|= B43_TMSLOW_GMODE
;
1205 flags
|= B43_TMSLOW_PHYCLKEN
;
1206 flags
|= B43_TMSLOW_PHYRESET
;
1207 if (dev
->phy
.type
== B43_PHYTYPE_N
)
1208 flags
|= B43_TMSLOW_PHY_BANDWIDTH_20MHZ
; /* Make 20 MHz def */
1209 b43_device_enable(dev
, flags
);
1210 msleep(2); /* Wait for the PLL to turn on. */
1212 /* Now take the PHY out of Reset again */
1213 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
1214 tmslow
|= SSB_TMSLOW_FGC
;
1215 tmslow
&= ~B43_TMSLOW_PHYRESET
;
1216 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
1217 ssb_read32(sdev
, SSB_TMSLOW
); /* flush */
1219 tmslow
&= ~SSB_TMSLOW_FGC
;
1220 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
1221 ssb_read32(sdev
, SSB_TMSLOW
); /* flush */
1225 void b43_wireless_core_reset(struct b43_wldev
*dev
, bool gmode
)
1229 switch (dev
->dev
->bus_type
) {
1230 #ifdef CONFIG_B43_BCMA
1232 b43_bcma_wireless_core_reset(dev
, gmode
);
1235 #ifdef CONFIG_B43_SSB
1237 b43_ssb_wireless_core_reset(dev
, gmode
);
1242 /* Turn Analog ON, but only if we already know the PHY-type.
1243 * This protects against very early setup where we don't know the
1244 * PHY-type, yet. wireless_core_reset will be called once again later,
1245 * when we know the PHY-type. */
1247 dev
->phy
.ops
->switch_analog(dev
, 1);
1249 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1250 macctl
&= ~B43_MACCTL_GMODE
;
1252 macctl
|= B43_MACCTL_GMODE
;
1253 macctl
|= B43_MACCTL_IHR_ENABLED
;
1254 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1257 static void handle_irq_transmit_status(struct b43_wldev
*dev
)
1261 struct b43_txstatus stat
;
1264 v0
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
1265 if (!(v0
& 0x00000001))
1267 v1
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
1269 stat
.cookie
= (v0
>> 16);
1270 stat
.seq
= (v1
& 0x0000FFFF);
1271 stat
.phy_stat
= ((v1
& 0x00FF0000) >> 16);
1272 tmp
= (v0
& 0x0000FFFF);
1273 stat
.frame_count
= ((tmp
& 0xF000) >> 12);
1274 stat
.rts_count
= ((tmp
& 0x0F00) >> 8);
1275 stat
.supp_reason
= ((tmp
& 0x001C) >> 2);
1276 stat
.pm_indicated
= !!(tmp
& 0x0080);
1277 stat
.intermediate
= !!(tmp
& 0x0040);
1278 stat
.for_ampdu
= !!(tmp
& 0x0020);
1279 stat
.acked
= !!(tmp
& 0x0002);
1281 b43_handle_txstatus(dev
, &stat
);
1285 static void drain_txstatus_queue(struct b43_wldev
*dev
)
1289 if (dev
->dev
->core_rev
< 5)
1291 /* Read all entries from the microcode TXstatus FIFO
1292 * and throw them away.
1295 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
1296 if (!(dummy
& 0x00000001))
1298 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
1302 static u32
b43_jssi_read(struct b43_wldev
*dev
)
1306 val
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x08A);
1308 val
|= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x088);
1313 static void b43_jssi_write(struct b43_wldev
*dev
, u32 jssi
)
1315 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x088, (jssi
& 0x0000FFFF));
1316 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x08A, (jssi
& 0xFFFF0000) >> 16);
1319 static void b43_generate_noise_sample(struct b43_wldev
*dev
)
1321 b43_jssi_write(dev
, 0x7F7F7F7F);
1322 b43_write32(dev
, B43_MMIO_MACCMD
,
1323 b43_read32(dev
, B43_MMIO_MACCMD
) | B43_MACCMD_BGNOISE
);
1326 static void b43_calculate_link_quality(struct b43_wldev
*dev
)
1328 /* Top half of Link Quality calculation. */
1330 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
1332 if (dev
->noisecalc
.calculation_running
)
1334 dev
->noisecalc
.calculation_running
= 1;
1335 dev
->noisecalc
.nr_samples
= 0;
1337 b43_generate_noise_sample(dev
);
1340 static void handle_irq_noise(struct b43_wldev
*dev
)
1342 struct b43_phy_g
*phy
= dev
->phy
.g
;
1348 /* Bottom half of Link Quality calculation. */
1350 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
1353 /* Possible race condition: It might be possible that the user
1354 * changed to a different channel in the meantime since we
1355 * started the calculation. We ignore that fact, since it's
1356 * not really that much of a problem. The background noise is
1357 * an estimation only anyway. Slightly wrong results will get damped
1358 * by the averaging of the 8 sample rounds. Additionally the
1359 * value is shortlived. So it will be replaced by the next noise
1360 * calculation round soon. */
1362 B43_WARN_ON(!dev
->noisecalc
.calculation_running
);
1363 *((__le32
*)noise
) = cpu_to_le32(b43_jssi_read(dev
));
1364 if (noise
[0] == 0x7F || noise
[1] == 0x7F ||
1365 noise
[2] == 0x7F || noise
[3] == 0x7F)
1368 /* Get the noise samples. */
1369 B43_WARN_ON(dev
->noisecalc
.nr_samples
>= 8);
1370 i
= dev
->noisecalc
.nr_samples
;
1371 noise
[0] = clamp_val(noise
[0], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1372 noise
[1] = clamp_val(noise
[1], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1373 noise
[2] = clamp_val(noise
[2], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1374 noise
[3] = clamp_val(noise
[3], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1375 dev
->noisecalc
.samples
[i
][0] = phy
->nrssi_lt
[noise
[0]];
1376 dev
->noisecalc
.samples
[i
][1] = phy
->nrssi_lt
[noise
[1]];
1377 dev
->noisecalc
.samples
[i
][2] = phy
->nrssi_lt
[noise
[2]];
1378 dev
->noisecalc
.samples
[i
][3] = phy
->nrssi_lt
[noise
[3]];
1379 dev
->noisecalc
.nr_samples
++;
1380 if (dev
->noisecalc
.nr_samples
== 8) {
1381 /* Calculate the Link Quality by the noise samples. */
1383 for (i
= 0; i
< 8; i
++) {
1384 for (j
= 0; j
< 4; j
++)
1385 average
+= dev
->noisecalc
.samples
[i
][j
];
1391 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x40C);
1392 tmp
= (tmp
/ 128) & 0x1F;
1402 dev
->stats
.link_noise
= average
;
1403 dev
->noisecalc
.calculation_running
= 0;
1407 b43_generate_noise_sample(dev
);
1410 static void handle_irq_tbtt_indication(struct b43_wldev
*dev
)
1412 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_AP
)) {
1415 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1416 b43_power_saving_ctl_bits(dev
, 0);
1418 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_ADHOC
))
1422 static void handle_irq_atim_end(struct b43_wldev
*dev
)
1424 if (dev
->dfq_valid
) {
1425 b43_write32(dev
, B43_MMIO_MACCMD
,
1426 b43_read32(dev
, B43_MMIO_MACCMD
)
1427 | B43_MACCMD_DFQ_VALID
);
1432 static void handle_irq_pmq(struct b43_wldev
*dev
)
1439 tmp
= b43_read32(dev
, B43_MMIO_PS_STATUS
);
1440 if (!(tmp
& 0x00000008))
1443 /* 16bit write is odd, but correct. */
1444 b43_write16(dev
, B43_MMIO_PS_STATUS
, 0x0002);
1447 static void b43_write_template_common(struct b43_wldev
*dev
,
1448 const u8
*data
, u16 size
,
1450 u16 shm_size_offset
, u8 rate
)
1453 struct b43_plcp_hdr4 plcp
;
1456 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1457 b43_ram_write(dev
, ram_offset
, le32_to_cpu(plcp
.data
));
1458 ram_offset
+= sizeof(u32
);
1459 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1460 * So leave the first two bytes of the next write blank.
1462 tmp
= (u32
) (data
[0]) << 16;
1463 tmp
|= (u32
) (data
[1]) << 24;
1464 b43_ram_write(dev
, ram_offset
, tmp
);
1465 ram_offset
+= sizeof(u32
);
1466 for (i
= 2; i
< size
; i
+= sizeof(u32
)) {
1467 tmp
= (u32
) (data
[i
+ 0]);
1469 tmp
|= (u32
) (data
[i
+ 1]) << 8;
1471 tmp
|= (u32
) (data
[i
+ 2]) << 16;
1473 tmp
|= (u32
) (data
[i
+ 3]) << 24;
1474 b43_ram_write(dev
, ram_offset
+ i
- 2, tmp
);
1476 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_size_offset
,
1477 size
+ sizeof(struct b43_plcp_hdr6
));
1480 /* Check if the use of the antenna that ieee80211 told us to
1481 * use is possible. This will fall back to DEFAULT.
1482 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1483 u8
b43_ieee80211_antenna_sanitize(struct b43_wldev
*dev
,
1488 if (antenna_nr
== 0) {
1489 /* Zero means "use default antenna". That's always OK. */
1493 /* Get the mask of available antennas. */
1495 antenna_mask
= dev
->dev
->bus_sprom
->ant_available_bg
;
1497 antenna_mask
= dev
->dev
->bus_sprom
->ant_available_a
;
1499 if (!(antenna_mask
& (1 << (antenna_nr
- 1)))) {
1500 /* This antenna is not available. Fall back to default. */
1507 /* Convert a b43 antenna number value to the PHY TX control value. */
1508 static u16
b43_antenna_to_phyctl(int antenna
)
1512 return B43_TXH_PHY_ANT0
;
1514 return B43_TXH_PHY_ANT1
;
1516 return B43_TXH_PHY_ANT2
;
1518 return B43_TXH_PHY_ANT3
;
1519 case B43_ANTENNA_AUTO0
:
1520 case B43_ANTENNA_AUTO1
:
1521 return B43_TXH_PHY_ANT01AUTO
;
1527 static void b43_write_beacon_template(struct b43_wldev
*dev
,
1529 u16 shm_size_offset
)
1531 unsigned int i
, len
, variable_len
;
1532 const struct ieee80211_mgmt
*bcn
;
1538 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(dev
->wl
->current_beacon
);
1540 bcn
= (const struct ieee80211_mgmt
*)(dev
->wl
->current_beacon
->data
);
1541 len
= min((size_t) dev
->wl
->current_beacon
->len
,
1542 0x200 - sizeof(struct b43_plcp_hdr6
));
1543 rate
= ieee80211_get_tx_rate(dev
->wl
->hw
, info
)->hw_value
;
1545 b43_write_template_common(dev
, (const u8
*)bcn
,
1546 len
, ram_offset
, shm_size_offset
, rate
);
1548 /* Write the PHY TX control parameters. */
1549 antenna
= B43_ANTENNA_DEFAULT
;
1550 antenna
= b43_antenna_to_phyctl(antenna
);
1551 ctl
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
);
1552 /* We can't send beacons with short preamble. Would get PHY errors. */
1553 ctl
&= ~B43_TXH_PHY_SHORTPRMBL
;
1554 ctl
&= ~B43_TXH_PHY_ANT
;
1555 ctl
&= ~B43_TXH_PHY_ENC
;
1557 if (b43_is_cck_rate(rate
))
1558 ctl
|= B43_TXH_PHY_ENC_CCK
;
1560 ctl
|= B43_TXH_PHY_ENC_OFDM
;
1561 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, ctl
);
1563 /* Find the position of the TIM and the DTIM_period value
1564 * and write them to SHM. */
1565 ie
= bcn
->u
.beacon
.variable
;
1566 variable_len
= len
- offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1567 for (i
= 0; i
< variable_len
- 2; ) {
1568 uint8_t ie_id
, ie_len
;
1575 /* This is the TIM Information Element */
1577 /* Check whether the ie_len is in the beacon data range. */
1578 if (variable_len
< ie_len
+ 2 + i
)
1580 /* A valid TIM is at least 4 bytes long. */
1585 tim_position
= sizeof(struct b43_plcp_hdr6
);
1586 tim_position
+= offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1589 dtim_period
= ie
[i
+ 3];
1591 b43_shm_write16(dev
, B43_SHM_SHARED
,
1592 B43_SHM_SH_TIMBPOS
, tim_position
);
1593 b43_shm_write16(dev
, B43_SHM_SHARED
,
1594 B43_SHM_SH_DTIMPER
, dtim_period
);
1601 * If ucode wants to modify TIM do it behind the beacon, this
1602 * will happen, for example, when doing mesh networking.
1604 b43_shm_write16(dev
, B43_SHM_SHARED
,
1606 len
+ sizeof(struct b43_plcp_hdr6
));
1607 b43_shm_write16(dev
, B43_SHM_SHARED
,
1608 B43_SHM_SH_DTIMPER
, 0);
1610 b43dbg(dev
->wl
, "Updated beacon template at 0x%x\n", ram_offset
);
1613 static void b43_upload_beacon0(struct b43_wldev
*dev
)
1615 struct b43_wl
*wl
= dev
->wl
;
1617 if (wl
->beacon0_uploaded
)
1619 b43_write_beacon_template(dev
, 0x68, 0x18);
1620 wl
->beacon0_uploaded
= 1;
1623 static void b43_upload_beacon1(struct b43_wldev
*dev
)
1625 struct b43_wl
*wl
= dev
->wl
;
1627 if (wl
->beacon1_uploaded
)
1629 b43_write_beacon_template(dev
, 0x468, 0x1A);
1630 wl
->beacon1_uploaded
= 1;
1633 static void handle_irq_beacon(struct b43_wldev
*dev
)
1635 struct b43_wl
*wl
= dev
->wl
;
1636 u32 cmd
, beacon0_valid
, beacon1_valid
;
1638 if (!b43_is_mode(wl
, NL80211_IFTYPE_AP
) &&
1639 !b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
))
1642 /* This is the bottom half of the asynchronous beacon update. */
1644 /* Ignore interrupt in the future. */
1645 dev
->irq_mask
&= ~B43_IRQ_BEACON
;
1647 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1648 beacon0_valid
= (cmd
& B43_MACCMD_BEACON0_VALID
);
1649 beacon1_valid
= (cmd
& B43_MACCMD_BEACON1_VALID
);
1651 /* Schedule interrupt manually, if busy. */
1652 if (beacon0_valid
&& beacon1_valid
) {
1653 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_BEACON
);
1654 dev
->irq_mask
|= B43_IRQ_BEACON
;
1658 if (unlikely(wl
->beacon_templates_virgin
)) {
1659 /* We never uploaded a beacon before.
1660 * Upload both templates now, but only mark one valid. */
1661 wl
->beacon_templates_virgin
= 0;
1662 b43_upload_beacon0(dev
);
1663 b43_upload_beacon1(dev
);
1664 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1665 cmd
|= B43_MACCMD_BEACON0_VALID
;
1666 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1668 if (!beacon0_valid
) {
1669 b43_upload_beacon0(dev
);
1670 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1671 cmd
|= B43_MACCMD_BEACON0_VALID
;
1672 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1673 } else if (!beacon1_valid
) {
1674 b43_upload_beacon1(dev
);
1675 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1676 cmd
|= B43_MACCMD_BEACON1_VALID
;
1677 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1682 static void b43_do_beacon_update_trigger_work(struct b43_wldev
*dev
)
1684 u32 old_irq_mask
= dev
->irq_mask
;
1686 /* update beacon right away or defer to irq */
1687 handle_irq_beacon(dev
);
1688 if (old_irq_mask
!= dev
->irq_mask
) {
1689 /* The handler updated the IRQ mask. */
1690 B43_WARN_ON(!dev
->irq_mask
);
1691 if (b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
)) {
1692 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, dev
->irq_mask
);
1694 /* Device interrupts are currently disabled. That means
1695 * we just ran the hardirq handler and scheduled the
1696 * IRQ thread. The thread will write the IRQ mask when
1697 * it finished, so there's nothing to do here. Writing
1698 * the mask _here_ would incorrectly re-enable IRQs. */
1703 static void b43_beacon_update_trigger_work(struct work_struct
*work
)
1705 struct b43_wl
*wl
= container_of(work
, struct b43_wl
,
1706 beacon_update_trigger
);
1707 struct b43_wldev
*dev
;
1709 mutex_lock(&wl
->mutex
);
1710 dev
= wl
->current_dev
;
1711 if (likely(dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
))) {
1712 if (b43_bus_host_is_sdio(dev
->dev
)) {
1713 /* wl->mutex is enough. */
1714 b43_do_beacon_update_trigger_work(dev
);
1717 spin_lock_irq(&wl
->hardirq_lock
);
1718 b43_do_beacon_update_trigger_work(dev
);
1720 spin_unlock_irq(&wl
->hardirq_lock
);
1723 mutex_unlock(&wl
->mutex
);
1726 /* Asynchronously update the packet templates in template RAM.
1727 * Locking: Requires wl->mutex to be locked. */
1728 static void b43_update_templates(struct b43_wl
*wl
)
1730 struct sk_buff
*beacon
;
1732 /* This is the top half of the ansynchronous beacon update.
1733 * The bottom half is the beacon IRQ.
1734 * Beacon update must be asynchronous to avoid sending an
1735 * invalid beacon. This can happen for example, if the firmware
1736 * transmits a beacon while we are updating it. */
1738 /* We could modify the existing beacon and set the aid bit in
1739 * the TIM field, but that would probably require resizing and
1740 * moving of data within the beacon template.
1741 * Simply request a new beacon and let mac80211 do the hard work. */
1742 beacon
= ieee80211_beacon_get(wl
->hw
, wl
->vif
);
1743 if (unlikely(!beacon
))
1746 if (wl
->current_beacon
)
1747 dev_kfree_skb_any(wl
->current_beacon
);
1748 wl
->current_beacon
= beacon
;
1749 wl
->beacon0_uploaded
= 0;
1750 wl
->beacon1_uploaded
= 0;
1751 ieee80211_queue_work(wl
->hw
, &wl
->beacon_update_trigger
);
1754 static void b43_set_beacon_int(struct b43_wldev
*dev
, u16 beacon_int
)
1757 if (dev
->dev
->core_rev
>= 3) {
1758 b43_write32(dev
, B43_MMIO_TSF_CFP_REP
, (beacon_int
<< 16));
1759 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, (beacon_int
<< 10));
1761 b43_write16(dev
, 0x606, (beacon_int
>> 6));
1762 b43_write16(dev
, 0x610, beacon_int
);
1764 b43_time_unlock(dev
);
1765 b43dbg(dev
->wl
, "Set beacon interval to %u\n", beacon_int
);
1768 static void b43_handle_firmware_panic(struct b43_wldev
*dev
)
1772 /* Read the register that contains the reason code for the panic. */
1773 reason
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, B43_FWPANIC_REASON_REG
);
1774 b43err(dev
->wl
, "Whoopsy, firmware panic! Reason: %u\n", reason
);
1778 b43dbg(dev
->wl
, "The panic reason is unknown.\n");
1780 case B43_FWPANIC_DIE
:
1781 /* Do not restart the controller or firmware.
1782 * The device is nonfunctional from now on.
1783 * Restarting would result in this panic to trigger again,
1784 * so we avoid that recursion. */
1786 case B43_FWPANIC_RESTART
:
1787 b43_controller_restart(dev
, "Microcode panic");
1792 static void handle_irq_ucode_debug(struct b43_wldev
*dev
)
1794 unsigned int i
, cnt
;
1795 u16 reason
, marker_id
, marker_line
;
1798 /* The proprietary firmware doesn't have this IRQ. */
1799 if (!dev
->fw
.opensource
)
1802 /* Read the register that contains the reason code for this IRQ. */
1803 reason
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, B43_DEBUGIRQ_REASON_REG
);
1806 case B43_DEBUGIRQ_PANIC
:
1807 b43_handle_firmware_panic(dev
);
1809 case B43_DEBUGIRQ_DUMP_SHM
:
1811 break; /* Only with driver debugging enabled. */
1812 buf
= kmalloc(4096, GFP_ATOMIC
);
1814 b43dbg(dev
->wl
, "SHM-dump: Failed to allocate memory\n");
1817 for (i
= 0; i
< 4096; i
+= 2) {
1818 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, i
);
1819 buf
[i
/ 2] = cpu_to_le16(tmp
);
1821 b43info(dev
->wl
, "Shared memory dump:\n");
1822 print_hex_dump(KERN_INFO
, "", DUMP_PREFIX_OFFSET
,
1823 16, 2, buf
, 4096, 1);
1826 case B43_DEBUGIRQ_DUMP_REGS
:
1828 break; /* Only with driver debugging enabled. */
1829 b43info(dev
->wl
, "Microcode register dump:\n");
1830 for (i
= 0, cnt
= 0; i
< 64; i
++) {
1831 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, i
);
1834 printk("r%02u: 0x%04X ", i
, tmp
);
1843 case B43_DEBUGIRQ_MARKER
:
1845 break; /* Only with driver debugging enabled. */
1846 marker_id
= b43_shm_read16(dev
, B43_SHM_SCRATCH
,
1848 marker_line
= b43_shm_read16(dev
, B43_SHM_SCRATCH
,
1849 B43_MARKER_LINE_REG
);
1850 b43info(dev
->wl
, "The firmware just executed the MARKER(%u) "
1851 "at line number %u\n",
1852 marker_id
, marker_line
);
1855 b43dbg(dev
->wl
, "Debug-IRQ triggered for unknown reason: %u\n",
1859 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1860 b43_shm_write16(dev
, B43_SHM_SCRATCH
,
1861 B43_DEBUGIRQ_REASON_REG
, B43_DEBUGIRQ_ACK
);
1864 static void b43_do_interrupt_thread(struct b43_wldev
*dev
)
1867 u32 dma_reason
[ARRAY_SIZE(dev
->dma_reason
)];
1868 u32 merged_dma_reason
= 0;
1871 if (unlikely(b43_status(dev
) != B43_STAT_STARTED
))
1874 reason
= dev
->irq_reason
;
1875 for (i
= 0; i
< ARRAY_SIZE(dma_reason
); i
++) {
1876 dma_reason
[i
] = dev
->dma_reason
[i
];
1877 merged_dma_reason
|= dma_reason
[i
];
1880 if (unlikely(reason
& B43_IRQ_MAC_TXERR
))
1881 b43err(dev
->wl
, "MAC transmission error\n");
1883 if (unlikely(reason
& B43_IRQ_PHY_TXERR
)) {
1884 b43err(dev
->wl
, "PHY transmission error\n");
1886 if (unlikely(atomic_dec_and_test(&dev
->phy
.txerr_cnt
))) {
1887 atomic_set(&dev
->phy
.txerr_cnt
,
1888 B43_PHY_TX_BADNESS_LIMIT
);
1889 b43err(dev
->wl
, "Too many PHY TX errors, "
1890 "restarting the controller\n");
1891 b43_controller_restart(dev
, "PHY TX errors");
1895 if (unlikely(merged_dma_reason
& (B43_DMAIRQ_FATALMASK
|
1896 B43_DMAIRQ_NONFATALMASK
))) {
1897 if (merged_dma_reason
& B43_DMAIRQ_FATALMASK
) {
1898 b43err(dev
->wl
, "Fatal DMA error: "
1899 "0x%08X, 0x%08X, 0x%08X, "
1900 "0x%08X, 0x%08X, 0x%08X\n",
1901 dma_reason
[0], dma_reason
[1],
1902 dma_reason
[2], dma_reason
[3],
1903 dma_reason
[4], dma_reason
[5]);
1904 b43err(dev
->wl
, "This device does not support DMA "
1905 "on your system. It will now be switched to PIO.\n");
1906 /* Fall back to PIO transfers if we get fatal DMA errors! */
1908 b43_controller_restart(dev
, "DMA error");
1911 if (merged_dma_reason
& B43_DMAIRQ_NONFATALMASK
) {
1912 b43err(dev
->wl
, "DMA error: "
1913 "0x%08X, 0x%08X, 0x%08X, "
1914 "0x%08X, 0x%08X, 0x%08X\n",
1915 dma_reason
[0], dma_reason
[1],
1916 dma_reason
[2], dma_reason
[3],
1917 dma_reason
[4], dma_reason
[5]);
1921 if (unlikely(reason
& B43_IRQ_UCODE_DEBUG
))
1922 handle_irq_ucode_debug(dev
);
1923 if (reason
& B43_IRQ_TBTT_INDI
)
1924 handle_irq_tbtt_indication(dev
);
1925 if (reason
& B43_IRQ_ATIM_END
)
1926 handle_irq_atim_end(dev
);
1927 if (reason
& B43_IRQ_BEACON
)
1928 handle_irq_beacon(dev
);
1929 if (reason
& B43_IRQ_PMQ
)
1930 handle_irq_pmq(dev
);
1931 if (reason
& B43_IRQ_TXFIFO_FLUSH_OK
)
1933 if (reason
& B43_IRQ_NOISESAMPLE_OK
)
1934 handle_irq_noise(dev
);
1936 /* Check the DMA reason registers for received data. */
1937 if (dma_reason
[0] & B43_DMAIRQ_RX_DONE
) {
1938 if (b43_using_pio_transfers(dev
))
1939 b43_pio_rx(dev
->pio
.rx_queue
);
1941 b43_dma_rx(dev
->dma
.rx_ring
);
1943 B43_WARN_ON(dma_reason
[1] & B43_DMAIRQ_RX_DONE
);
1944 B43_WARN_ON(dma_reason
[2] & B43_DMAIRQ_RX_DONE
);
1945 B43_WARN_ON(dma_reason
[3] & B43_DMAIRQ_RX_DONE
);
1946 B43_WARN_ON(dma_reason
[4] & B43_DMAIRQ_RX_DONE
);
1947 B43_WARN_ON(dma_reason
[5] & B43_DMAIRQ_RX_DONE
);
1949 if (reason
& B43_IRQ_TX_OK
)
1950 handle_irq_transmit_status(dev
);
1952 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1953 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, dev
->irq_mask
);
1956 if (b43_debug(dev
, B43_DBG_VERBOSESTATS
)) {
1958 for (i
= 0; i
< ARRAY_SIZE(dev
->irq_bit_count
); i
++) {
1959 if (reason
& (1 << i
))
1960 dev
->irq_bit_count
[i
]++;
1966 /* Interrupt thread handler. Handles device interrupts in thread context. */
1967 static irqreturn_t
b43_interrupt_thread_handler(int irq
, void *dev_id
)
1969 struct b43_wldev
*dev
= dev_id
;
1971 mutex_lock(&dev
->wl
->mutex
);
1972 b43_do_interrupt_thread(dev
);
1974 mutex_unlock(&dev
->wl
->mutex
);
1979 static irqreturn_t
b43_do_interrupt(struct b43_wldev
*dev
)
1983 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1984 * On SDIO, this runs under wl->mutex. */
1986 reason
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1987 if (reason
== 0xffffffff) /* shared IRQ */
1989 reason
&= dev
->irq_mask
;
1993 dev
->dma_reason
[0] = b43_read32(dev
, B43_MMIO_DMA0_REASON
)
1995 dev
->dma_reason
[1] = b43_read32(dev
, B43_MMIO_DMA1_REASON
)
1997 dev
->dma_reason
[2] = b43_read32(dev
, B43_MMIO_DMA2_REASON
)
1999 dev
->dma_reason
[3] = b43_read32(dev
, B43_MMIO_DMA3_REASON
)
2001 dev
->dma_reason
[4] = b43_read32(dev
, B43_MMIO_DMA4_REASON
)
2004 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2008 /* ACK the interrupt. */
2009 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, reason
);
2010 b43_write32(dev
, B43_MMIO_DMA0_REASON
, dev
->dma_reason
[0]);
2011 b43_write32(dev
, B43_MMIO_DMA1_REASON
, dev
->dma_reason
[1]);
2012 b43_write32(dev
, B43_MMIO_DMA2_REASON
, dev
->dma_reason
[2]);
2013 b43_write32(dev
, B43_MMIO_DMA3_REASON
, dev
->dma_reason
[3]);
2014 b43_write32(dev
, B43_MMIO_DMA4_REASON
, dev
->dma_reason
[4]);
2016 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2019 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2020 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, 0);
2021 /* Save the reason bitmasks for the IRQ thread handler. */
2022 dev
->irq_reason
= reason
;
2024 return IRQ_WAKE_THREAD
;
2027 /* Interrupt handler top-half. This runs with interrupts disabled. */
2028 static irqreturn_t
b43_interrupt_handler(int irq
, void *dev_id
)
2030 struct b43_wldev
*dev
= dev_id
;
2033 if (unlikely(b43_status(dev
) < B43_STAT_STARTED
))
2036 spin_lock(&dev
->wl
->hardirq_lock
);
2037 ret
= b43_do_interrupt(dev
);
2039 spin_unlock(&dev
->wl
->hardirq_lock
);
2044 /* SDIO interrupt handler. This runs in process context. */
2045 static void b43_sdio_interrupt_handler(struct b43_wldev
*dev
)
2047 struct b43_wl
*wl
= dev
->wl
;
2050 mutex_lock(&wl
->mutex
);
2052 ret
= b43_do_interrupt(dev
);
2053 if (ret
== IRQ_WAKE_THREAD
)
2054 b43_do_interrupt_thread(dev
);
2056 mutex_unlock(&wl
->mutex
);
2059 void b43_do_release_fw(struct b43_firmware_file
*fw
)
2061 release_firmware(fw
->data
);
2063 fw
->filename
= NULL
;
2066 static void b43_release_firmware(struct b43_wldev
*dev
)
2068 b43_do_release_fw(&dev
->fw
.ucode
);
2069 b43_do_release_fw(&dev
->fw
.pcm
);
2070 b43_do_release_fw(&dev
->fw
.initvals
);
2071 b43_do_release_fw(&dev
->fw
.initvals_band
);
2074 static void b43_print_fw_helptext(struct b43_wl
*wl
, bool error
)
2078 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2079 "and download the correct firmware for this driver version. " \
2080 "Please carefully read all instructions on this website.\n";
2088 int b43_do_request_fw(struct b43_request_fw_context
*ctx
,
2090 struct b43_firmware_file
*fw
)
2092 const struct firmware
*blob
;
2093 struct b43_fw_header
*hdr
;
2098 /* Don't fetch anything. Free possibly cached firmware. */
2099 /* FIXME: We should probably keep it anyway, to save some headache
2100 * on suspend/resume with multiband devices. */
2101 b43_do_release_fw(fw
);
2105 if ((fw
->type
== ctx
->req_type
) &&
2106 (strcmp(fw
->filename
, name
) == 0))
2107 return 0; /* Already have this fw. */
2108 /* Free the cached firmware first. */
2109 /* FIXME: We should probably do this later after we successfully
2110 * got the new fw. This could reduce headache with multiband devices.
2111 * We could also redesign this to cache the firmware for all possible
2112 * bands all the time. */
2113 b43_do_release_fw(fw
);
2116 switch (ctx
->req_type
) {
2117 case B43_FWTYPE_PROPRIETARY
:
2118 snprintf(ctx
->fwname
, sizeof(ctx
->fwname
),
2120 modparam_fwpostfix
, name
);
2122 case B43_FWTYPE_OPENSOURCE
:
2123 snprintf(ctx
->fwname
, sizeof(ctx
->fwname
),
2125 modparam_fwpostfix
, name
);
2131 err
= request_firmware(&blob
, ctx
->fwname
, ctx
->dev
->dev
->dev
);
2132 if (err
== -ENOENT
) {
2133 snprintf(ctx
->errors
[ctx
->req_type
],
2134 sizeof(ctx
->errors
[ctx
->req_type
]),
2135 "Firmware file \"%s\" not found\n", ctx
->fwname
);
2138 snprintf(ctx
->errors
[ctx
->req_type
],
2139 sizeof(ctx
->errors
[ctx
->req_type
]),
2140 "Firmware file \"%s\" request failed (err=%d)\n",
2144 if (blob
->size
< sizeof(struct b43_fw_header
))
2146 hdr
= (struct b43_fw_header
*)(blob
->data
);
2147 switch (hdr
->type
) {
2148 case B43_FW_TYPE_UCODE
:
2149 case B43_FW_TYPE_PCM
:
2150 size
= be32_to_cpu(hdr
->size
);
2151 if (size
!= blob
->size
- sizeof(struct b43_fw_header
))
2154 case B43_FW_TYPE_IV
:
2163 fw
->filename
= name
;
2164 fw
->type
= ctx
->req_type
;
2169 snprintf(ctx
->errors
[ctx
->req_type
],
2170 sizeof(ctx
->errors
[ctx
->req_type
]),
2171 "Firmware file \"%s\" format error.\n", ctx
->fwname
);
2172 release_firmware(blob
);
2177 static int b43_try_request_fw(struct b43_request_fw_context
*ctx
)
2179 struct b43_wldev
*dev
= ctx
->dev
;
2180 struct b43_firmware
*fw
= &ctx
->dev
->fw
;
2181 const u8 rev
= ctx
->dev
->dev
->core_rev
;
2182 const char *filename
;
2186 /* Files for HT and LCN were found by trying one by one */
2189 if ((rev
>= 5) && (rev
<= 10)) {
2190 filename
= "ucode5";
2191 } else if ((rev
>= 11) && (rev
<= 12)) {
2192 filename
= "ucode11";
2193 } else if (rev
== 13) {
2194 filename
= "ucode13";
2195 } else if (rev
== 14) {
2196 filename
= "ucode14";
2197 } else if (rev
== 15) {
2198 filename
= "ucode15";
2200 switch (dev
->phy
.type
) {
2203 filename
= "ucode16_mimo";
2207 case B43_PHYTYPE_HT
:
2209 filename
= "ucode29_mimo";
2213 case B43_PHYTYPE_LCN
:
2215 filename
= "ucode24_mimo";
2223 err
= b43_do_request_fw(ctx
, filename
, &fw
->ucode
);
2228 if ((rev
>= 5) && (rev
<= 10))
2234 fw
->pcm_request_failed
= 0;
2235 err
= b43_do_request_fw(ctx
, filename
, &fw
->pcm
);
2236 if (err
== -ENOENT
) {
2237 /* We did not find a PCM file? Not fatal, but
2238 * core rev <= 10 must do without hwcrypto then. */
2239 fw
->pcm_request_failed
= 1;
2244 switch (dev
->phy
.type
) {
2246 if ((rev
>= 5) && (rev
<= 10)) {
2247 tmshigh
= ssb_read32(dev
->dev
->sdev
, SSB_TMSHIGH
);
2248 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
2249 filename
= "a0g1initvals5";
2251 filename
= "a0g0initvals5";
2253 goto err_no_initvals
;
2256 if ((rev
>= 5) && (rev
<= 10))
2257 filename
= "b0g0initvals5";
2259 filename
= "b0g0initvals13";
2261 goto err_no_initvals
;
2265 filename
= "n0initvals16";
2266 else if ((rev
>= 11) && (rev
<= 12))
2267 filename
= "n0initvals11";
2269 goto err_no_initvals
;
2271 case B43_PHYTYPE_LP
:
2273 filename
= "lp0initvals13";
2275 filename
= "lp0initvals14";
2277 filename
= "lp0initvals15";
2279 goto err_no_initvals
;
2281 case B43_PHYTYPE_HT
:
2283 filename
= "ht0initvals29";
2285 goto err_no_initvals
;
2287 case B43_PHYTYPE_LCN
:
2289 filename
= "lcn0initvals24";
2291 goto err_no_initvals
;
2294 goto err_no_initvals
;
2296 err
= b43_do_request_fw(ctx
, filename
, &fw
->initvals
);
2300 /* Get bandswitch initvals */
2301 switch (dev
->phy
.type
) {
2303 if ((rev
>= 5) && (rev
<= 10)) {
2304 tmshigh
= ssb_read32(dev
->dev
->sdev
, SSB_TMSHIGH
);
2305 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
2306 filename
= "a0g1bsinitvals5";
2308 filename
= "a0g0bsinitvals5";
2309 } else if (rev
>= 11)
2312 goto err_no_initvals
;
2315 if ((rev
>= 5) && (rev
<= 10))
2316 filename
= "b0g0bsinitvals5";
2320 goto err_no_initvals
;
2324 filename
= "n0bsinitvals16";
2325 else if ((rev
>= 11) && (rev
<= 12))
2326 filename
= "n0bsinitvals11";
2328 goto err_no_initvals
;
2330 case B43_PHYTYPE_LP
:
2332 filename
= "lp0bsinitvals13";
2334 filename
= "lp0bsinitvals14";
2336 filename
= "lp0bsinitvals15";
2338 goto err_no_initvals
;
2340 case B43_PHYTYPE_HT
:
2342 filename
= "ht0bsinitvals29";
2344 goto err_no_initvals
;
2346 case B43_PHYTYPE_LCN
:
2348 filename
= "lcn0bsinitvals24";
2350 goto err_no_initvals
;
2353 goto err_no_initvals
;
2355 err
= b43_do_request_fw(ctx
, filename
, &fw
->initvals_band
);
2362 err
= ctx
->fatal_failure
= -EOPNOTSUPP
;
2363 b43err(dev
->wl
, "The driver does not know which firmware (ucode) "
2364 "is required for your device (wl-core rev %u)\n", rev
);
2368 err
= ctx
->fatal_failure
= -EOPNOTSUPP
;
2369 b43err(dev
->wl
, "The driver does not know which firmware (PCM) "
2370 "is required for your device (wl-core rev %u)\n", rev
);
2374 err
= ctx
->fatal_failure
= -EOPNOTSUPP
;
2375 b43err(dev
->wl
, "The driver does not know which firmware (initvals) "
2376 "is required for your device (wl-core rev %u)\n", rev
);
2380 /* We failed to load this firmware image. The error message
2381 * already is in ctx->errors. Return and let our caller decide
2386 b43_release_firmware(dev
);
2390 static int b43_request_firmware(struct b43_wldev
*dev
)
2392 struct b43_request_fw_context
*ctx
;
2397 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
2402 ctx
->req_type
= B43_FWTYPE_PROPRIETARY
;
2403 err
= b43_try_request_fw(ctx
);
2405 goto out
; /* Successfully loaded it. */
2406 err
= ctx
->fatal_failure
;
2410 ctx
->req_type
= B43_FWTYPE_OPENSOURCE
;
2411 err
= b43_try_request_fw(ctx
);
2413 goto out
; /* Successfully loaded it. */
2414 err
= ctx
->fatal_failure
;
2418 /* Could not find a usable firmware. Print the errors. */
2419 for (i
= 0; i
< B43_NR_FWTYPES
; i
++) {
2420 errmsg
= ctx
->errors
[i
];
2422 b43err(dev
->wl
, errmsg
);
2424 b43_print_fw_helptext(dev
->wl
, 1);
2432 static int b43_upload_microcode(struct b43_wldev
*dev
)
2434 struct wiphy
*wiphy
= dev
->wl
->hw
->wiphy
;
2435 const size_t hdr_len
= sizeof(struct b43_fw_header
);
2437 unsigned int i
, len
;
2438 u16 fwrev
, fwpatch
, fwdate
, fwtime
;
2442 /* Jump the microcode PSM to offset 0 */
2443 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2444 B43_WARN_ON(macctl
& B43_MACCTL_PSM_RUN
);
2445 macctl
|= B43_MACCTL_PSM_JMP0
;
2446 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2447 /* Zero out all microcode PSM registers and shared memory. */
2448 for (i
= 0; i
< 64; i
++)
2449 b43_shm_write16(dev
, B43_SHM_SCRATCH
, i
, 0);
2450 for (i
= 0; i
< 4096; i
+= 2)
2451 b43_shm_write16(dev
, B43_SHM_SHARED
, i
, 0);
2453 /* Upload Microcode. */
2454 data
= (__be32
*) (dev
->fw
.ucode
.data
->data
+ hdr_len
);
2455 len
= (dev
->fw
.ucode
.data
->size
- hdr_len
) / sizeof(__be32
);
2456 b43_shm_control_word(dev
, B43_SHM_UCODE
| B43_SHM_AUTOINC_W
, 0x0000);
2457 for (i
= 0; i
< len
; i
++) {
2458 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
2462 if (dev
->fw
.pcm
.data
) {
2463 /* Upload PCM data. */
2464 data
= (__be32
*) (dev
->fw
.pcm
.data
->data
+ hdr_len
);
2465 len
= (dev
->fw
.pcm
.data
->size
- hdr_len
) / sizeof(__be32
);
2466 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EA);
2467 b43_write32(dev
, B43_MMIO_SHM_DATA
, 0x00004000);
2468 /* No need for autoinc bit in SHM_HW */
2469 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EB);
2470 for (i
= 0; i
< len
; i
++) {
2471 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
2476 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_ALL
);
2478 /* Start the microcode PSM */
2479 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2480 macctl
&= ~B43_MACCTL_PSM_JMP0
;
2481 macctl
|= B43_MACCTL_PSM_RUN
;
2482 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2484 /* Wait for the microcode to load and respond */
2487 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2488 if (tmp
== B43_IRQ_MAC_SUSPENDED
)
2492 b43err(dev
->wl
, "Microcode not responding\n");
2493 b43_print_fw_helptext(dev
->wl
, 1);
2499 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
); /* dummy read */
2501 /* Get and check the revisions. */
2502 fwrev
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEREV
);
2503 fwpatch
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEPATCH
);
2504 fwdate
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEDATE
);
2505 fwtime
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODETIME
);
2507 if (fwrev
<= 0x128) {
2508 b43err(dev
->wl
, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2509 "binary drivers older than version 4.x is unsupported. "
2510 "You must upgrade your firmware files.\n");
2511 b43_print_fw_helptext(dev
->wl
, 1);
2515 dev
->fw
.rev
= fwrev
;
2516 dev
->fw
.patch
= fwpatch
;
2517 if (dev
->fw
.rev
>= 410)
2518 dev
->fw
.hdr_format
= B43_FW_HDR_410
;
2520 dev
->fw
.hdr_format
= B43_FW_HDR_351
;
2521 dev
->fw
.opensource
= (fwdate
== 0xFFFF);
2523 /* Default to use-all-queues. */
2524 dev
->wl
->hw
->queues
= dev
->wl
->mac80211_initially_registered_queues
;
2525 dev
->qos_enabled
= !!modparam_qos
;
2526 /* Default to firmware/hardware crypto acceleration. */
2527 dev
->hwcrypto_enabled
= 1;
2529 if (dev
->fw
.opensource
) {
2532 /* Patchlevel info is encoded in the "time" field. */
2533 dev
->fw
.patch
= fwtime
;
2534 b43info(dev
->wl
, "Loading OpenSource firmware version %u.%u\n",
2535 dev
->fw
.rev
, dev
->fw
.patch
);
2537 fwcapa
= b43_fwcapa_read(dev
);
2538 if (!(fwcapa
& B43_FWCAPA_HWCRYPTO
) || dev
->fw
.pcm_request_failed
) {
2539 b43info(dev
->wl
, "Hardware crypto acceleration not supported by firmware\n");
2540 /* Disable hardware crypto and fall back to software crypto. */
2541 dev
->hwcrypto_enabled
= 0;
2543 if (!(fwcapa
& B43_FWCAPA_QOS
)) {
2544 b43info(dev
->wl
, "QoS not supported by firmware\n");
2545 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2546 * ieee80211_unregister to make sure the networking core can
2547 * properly free possible resources. */
2548 dev
->wl
->hw
->queues
= 1;
2549 dev
->qos_enabled
= 0;
2552 b43info(dev
->wl
, "Loading firmware version %u.%u "
2553 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2555 (fwdate
>> 12) & 0xF, (fwdate
>> 8) & 0xF, fwdate
& 0xFF,
2556 (fwtime
>> 11) & 0x1F, (fwtime
>> 5) & 0x3F, fwtime
& 0x1F);
2557 if (dev
->fw
.pcm_request_failed
) {
2558 b43warn(dev
->wl
, "No \"pcm5.fw\" firmware file found. "
2559 "Hardware accelerated cryptography is disabled.\n");
2560 b43_print_fw_helptext(dev
->wl
, 0);
2564 snprintf(wiphy
->fw_version
, sizeof(wiphy
->fw_version
), "%u.%u",
2565 dev
->fw
.rev
, dev
->fw
.patch
);
2566 wiphy
->hw_version
= dev
->dev
->core_id
;
2568 if (dev
->fw
.hdr_format
== B43_FW_HDR_351
) {
2569 /* We're over the deadline, but we keep support for old fw
2570 * until it turns out to be in major conflict with something new. */
2571 b43warn(dev
->wl
, "You are using an old firmware image. "
2572 "Support for old firmware will be removed soon "
2573 "(official deadline was July 2008).\n");
2574 b43_print_fw_helptext(dev
->wl
, 0);
2580 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2581 macctl
&= ~B43_MACCTL_PSM_RUN
;
2582 macctl
|= B43_MACCTL_PSM_JMP0
;
2583 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2588 static int b43_write_initvals(struct b43_wldev
*dev
,
2589 const struct b43_iv
*ivals
,
2593 const struct b43_iv
*iv
;
2598 BUILD_BUG_ON(sizeof(struct b43_iv
) != 6);
2600 for (i
= 0; i
< count
; i
++) {
2601 if (array_size
< sizeof(iv
->offset_size
))
2603 array_size
-= sizeof(iv
->offset_size
);
2604 offset
= be16_to_cpu(iv
->offset_size
);
2605 bit32
= !!(offset
& B43_IV_32BIT
);
2606 offset
&= B43_IV_OFFSET_MASK
;
2607 if (offset
>= 0x1000)
2612 if (array_size
< sizeof(iv
->data
.d32
))
2614 array_size
-= sizeof(iv
->data
.d32
);
2616 value
= get_unaligned_be32(&iv
->data
.d32
);
2617 b43_write32(dev
, offset
, value
);
2619 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
2625 if (array_size
< sizeof(iv
->data
.d16
))
2627 array_size
-= sizeof(iv
->data
.d16
);
2629 value
= be16_to_cpu(iv
->data
.d16
);
2630 b43_write16(dev
, offset
, value
);
2632 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
2643 b43err(dev
->wl
, "Initial Values Firmware file-format error.\n");
2644 b43_print_fw_helptext(dev
->wl
, 1);
2649 static int b43_upload_initvals(struct b43_wldev
*dev
)
2651 const size_t hdr_len
= sizeof(struct b43_fw_header
);
2652 const struct b43_fw_header
*hdr
;
2653 struct b43_firmware
*fw
= &dev
->fw
;
2654 const struct b43_iv
*ivals
;
2658 hdr
= (const struct b43_fw_header
*)(fw
->initvals
.data
->data
);
2659 ivals
= (const struct b43_iv
*)(fw
->initvals
.data
->data
+ hdr_len
);
2660 count
= be32_to_cpu(hdr
->size
);
2661 err
= b43_write_initvals(dev
, ivals
, count
,
2662 fw
->initvals
.data
->size
- hdr_len
);
2665 if (fw
->initvals_band
.data
) {
2666 hdr
= (const struct b43_fw_header
*)(fw
->initvals_band
.data
->data
);
2667 ivals
= (const struct b43_iv
*)(fw
->initvals_band
.data
->data
+ hdr_len
);
2668 count
= be32_to_cpu(hdr
->size
);
2669 err
= b43_write_initvals(dev
, ivals
, count
,
2670 fw
->initvals_band
.data
->size
- hdr_len
);
2679 /* Initialize the GPIOs
2680 * http://bcm-specs.sipsolutions.net/GPIO
2682 static struct ssb_device
*b43_ssb_gpio_dev(struct b43_wldev
*dev
)
2684 struct ssb_bus
*bus
= dev
->dev
->sdev
->bus
;
2686 #ifdef CONFIG_SSB_DRIVER_PCICORE
2687 return (bus
->chipco
.dev
? bus
->chipco
.dev
: bus
->pcicore
.dev
);
2689 return bus
->chipco
.dev
;
2693 static int b43_gpio_init(struct b43_wldev
*dev
)
2695 struct ssb_device
*gpiodev
;
2698 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2699 & ~B43_MACCTL_GPOUTSMSK
);
2701 b43_write16(dev
, B43_MMIO_GPIO_MASK
, b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2706 if (dev
->dev
->chip_id
== 0x4301) {
2710 if (0 /* FIXME: conditional unknown */ ) {
2711 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
2712 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2717 if (dev
->dev
->bus_sprom
->boardflags_lo
& B43_BFL_PACTRL
) {
2718 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
2719 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2724 if (dev
->dev
->core_rev
>= 2)
2725 mask
|= 0x0010; /* FIXME: This is redundant. */
2727 switch (dev
->dev
->bus_type
) {
2728 #ifdef CONFIG_B43_BCMA
2730 bcma_cc_write32(&dev
->dev
->bdev
->bus
->drv_cc
, BCMA_CC_GPIOCTL
,
2731 (bcma_cc_read32(&dev
->dev
->bdev
->bus
->drv_cc
,
2732 BCMA_CC_GPIOCTL
) & mask
) | set
);
2735 #ifdef CONFIG_B43_SSB
2737 gpiodev
= b43_ssb_gpio_dev(dev
);
2739 ssb_write32(gpiodev
, B43_GPIO_CONTROL
,
2740 (ssb_read32(gpiodev
, B43_GPIO_CONTROL
)
2749 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2750 static void b43_gpio_cleanup(struct b43_wldev
*dev
)
2752 struct ssb_device
*gpiodev
;
2754 switch (dev
->dev
->bus_type
) {
2755 #ifdef CONFIG_B43_BCMA
2757 bcma_cc_write32(&dev
->dev
->bdev
->bus
->drv_cc
, BCMA_CC_GPIOCTL
,
2761 #ifdef CONFIG_B43_SSB
2763 gpiodev
= b43_ssb_gpio_dev(dev
);
2765 ssb_write32(gpiodev
, B43_GPIO_CONTROL
, 0);
2771 /* http://bcm-specs.sipsolutions.net/EnableMac */
2772 void b43_mac_enable(struct b43_wldev
*dev
)
2774 if (b43_debug(dev
, B43_DBG_FIRMWARE
)) {
2777 fwstate
= b43_shm_read16(dev
, B43_SHM_SHARED
,
2778 B43_SHM_SH_UCODESTAT
);
2779 if ((fwstate
!= B43_SHM_SH_UCODESTAT_SUSP
) &&
2780 (fwstate
!= B43_SHM_SH_UCODESTAT_SLEEP
)) {
2781 b43err(dev
->wl
, "b43_mac_enable(): The firmware "
2782 "should be suspended, but current state is %u\n",
2787 dev
->mac_suspended
--;
2788 B43_WARN_ON(dev
->mac_suspended
< 0);
2789 if (dev
->mac_suspended
== 0) {
2790 b43_write32(dev
, B43_MMIO_MACCTL
,
2791 b43_read32(dev
, B43_MMIO_MACCTL
)
2792 | B43_MACCTL_ENABLED
);
2793 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
,
2794 B43_IRQ_MAC_SUSPENDED
);
2796 b43_read32(dev
, B43_MMIO_MACCTL
);
2797 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2798 b43_power_saving_ctl_bits(dev
, 0);
2802 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2803 void b43_mac_suspend(struct b43_wldev
*dev
)
2809 B43_WARN_ON(dev
->mac_suspended
< 0);
2811 if (dev
->mac_suspended
== 0) {
2812 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
2813 b43_write32(dev
, B43_MMIO_MACCTL
,
2814 b43_read32(dev
, B43_MMIO_MACCTL
)
2815 & ~B43_MACCTL_ENABLED
);
2816 /* force pci to flush the write */
2817 b43_read32(dev
, B43_MMIO_MACCTL
);
2818 for (i
= 35; i
; i
--) {
2819 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2820 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2824 /* Hm, it seems this will take some time. Use msleep(). */
2825 for (i
= 40; i
; i
--) {
2826 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2827 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2831 b43err(dev
->wl
, "MAC suspend failed\n");
2834 dev
->mac_suspended
++;
2837 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2838 void b43_mac_phy_clock_set(struct b43_wldev
*dev
, bool on
)
2842 switch (dev
->dev
->bus_type
) {
2843 #ifdef CONFIG_B43_BCMA
2845 tmp
= bcma_aread32(dev
->dev
->bdev
, BCMA_IOCTL
);
2847 tmp
|= B43_BCMA_IOCTL_MACPHYCLKEN
;
2849 tmp
&= ~B43_BCMA_IOCTL_MACPHYCLKEN
;
2850 bcma_awrite32(dev
->dev
->bdev
, BCMA_IOCTL
, tmp
);
2853 #ifdef CONFIG_B43_SSB
2855 tmp
= ssb_read32(dev
->dev
->sdev
, SSB_TMSLOW
);
2857 tmp
|= B43_TMSLOW_MACPHYCLKEN
;
2859 tmp
&= ~B43_TMSLOW_MACPHYCLKEN
;
2860 ssb_write32(dev
->dev
->sdev
, SSB_TMSLOW
, tmp
);
2866 static void b43_adjust_opmode(struct b43_wldev
*dev
)
2868 struct b43_wl
*wl
= dev
->wl
;
2872 ctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2873 /* Reset status to STA infrastructure mode. */
2874 ctl
&= ~B43_MACCTL_AP
;
2875 ctl
&= ~B43_MACCTL_KEEP_CTL
;
2876 ctl
&= ~B43_MACCTL_KEEP_BADPLCP
;
2877 ctl
&= ~B43_MACCTL_KEEP_BAD
;
2878 ctl
&= ~B43_MACCTL_PROMISC
;
2879 ctl
&= ~B43_MACCTL_BEACPROMISC
;
2880 ctl
|= B43_MACCTL_INFRA
;
2882 if (b43_is_mode(wl
, NL80211_IFTYPE_AP
) ||
2883 b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
))
2884 ctl
|= B43_MACCTL_AP
;
2885 else if (b43_is_mode(wl
, NL80211_IFTYPE_ADHOC
))
2886 ctl
&= ~B43_MACCTL_INFRA
;
2888 if (wl
->filter_flags
& FIF_CONTROL
)
2889 ctl
|= B43_MACCTL_KEEP_CTL
;
2890 if (wl
->filter_flags
& FIF_FCSFAIL
)
2891 ctl
|= B43_MACCTL_KEEP_BAD
;
2892 if (wl
->filter_flags
& FIF_PLCPFAIL
)
2893 ctl
|= B43_MACCTL_KEEP_BADPLCP
;
2894 if (wl
->filter_flags
& FIF_PROMISC_IN_BSS
)
2895 ctl
|= B43_MACCTL_PROMISC
;
2896 if (wl
->filter_flags
& FIF_BCN_PRBRESP_PROMISC
)
2897 ctl
|= B43_MACCTL_BEACPROMISC
;
2899 /* Workaround: On old hardware the HW-MAC-address-filter
2900 * doesn't work properly, so always run promisc in filter
2901 * it in software. */
2902 if (dev
->dev
->core_rev
<= 4)
2903 ctl
|= B43_MACCTL_PROMISC
;
2905 b43_write32(dev
, B43_MMIO_MACCTL
, ctl
);
2908 if ((ctl
& B43_MACCTL_INFRA
) && !(ctl
& B43_MACCTL_AP
)) {
2909 if (dev
->dev
->chip_id
== 0x4306 &&
2910 dev
->dev
->chip_rev
== 3)
2915 b43_write16(dev
, 0x612, cfp_pretbtt
);
2917 /* FIXME: We don't currently implement the PMQ mechanism,
2918 * so always disable it. If we want to implement PMQ,
2919 * we need to enable it here (clear DISCPMQ) in AP mode.
2921 if (0 /* ctl & B43_MACCTL_AP */) {
2922 b43_write32(dev
, B43_MMIO_MACCTL
,
2923 b43_read32(dev
, B43_MMIO_MACCTL
)
2924 & ~B43_MACCTL_DISCPMQ
);
2926 b43_write32(dev
, B43_MMIO_MACCTL
,
2927 b43_read32(dev
, B43_MMIO_MACCTL
)
2928 | B43_MACCTL_DISCPMQ
);
2932 static void b43_rate_memory_write(struct b43_wldev
*dev
, u16 rate
, int is_ofdm
)
2938 offset
+= (b43_plcp_get_ratecode_ofdm(rate
) & 0x000F) * 2;
2941 offset
+= (b43_plcp_get_ratecode_cck(rate
) & 0x000F) * 2;
2943 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ 0x20,
2944 b43_shm_read16(dev
, B43_SHM_SHARED
, offset
));
2947 static void b43_rate_memory_init(struct b43_wldev
*dev
)
2949 switch (dev
->phy
.type
) {
2953 case B43_PHYTYPE_LP
:
2954 b43_rate_memory_write(dev
, B43_OFDM_RATE_6MB
, 1);
2955 b43_rate_memory_write(dev
, B43_OFDM_RATE_12MB
, 1);
2956 b43_rate_memory_write(dev
, B43_OFDM_RATE_18MB
, 1);
2957 b43_rate_memory_write(dev
, B43_OFDM_RATE_24MB
, 1);
2958 b43_rate_memory_write(dev
, B43_OFDM_RATE_36MB
, 1);
2959 b43_rate_memory_write(dev
, B43_OFDM_RATE_48MB
, 1);
2960 b43_rate_memory_write(dev
, B43_OFDM_RATE_54MB
, 1);
2961 if (dev
->phy
.type
== B43_PHYTYPE_A
)
2965 b43_rate_memory_write(dev
, B43_CCK_RATE_1MB
, 0);
2966 b43_rate_memory_write(dev
, B43_CCK_RATE_2MB
, 0);
2967 b43_rate_memory_write(dev
, B43_CCK_RATE_5MB
, 0);
2968 b43_rate_memory_write(dev
, B43_CCK_RATE_11MB
, 0);
2975 /* Set the default values for the PHY TX Control Words. */
2976 static void b43_set_phytxctl_defaults(struct b43_wldev
*dev
)
2980 ctl
|= B43_TXH_PHY_ENC_CCK
;
2981 ctl
|= B43_TXH_PHY_ANT01AUTO
;
2982 ctl
|= B43_TXH_PHY_TXPWR
;
2984 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, ctl
);
2985 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, ctl
);
2986 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, ctl
);
2989 /* Set the TX-Antenna for management frames sent by firmware. */
2990 static void b43_mgmtframe_txantenna(struct b43_wldev
*dev
, int antenna
)
2995 ant
= b43_antenna_to_phyctl(antenna
);
2998 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
);
2999 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
3000 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, tmp
);
3001 /* For Probe Resposes */
3002 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
);
3003 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
3004 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, tmp
);
3007 /* This is the opposite of b43_chip_init() */
3008 static void b43_chip_exit(struct b43_wldev
*dev
)
3011 b43_gpio_cleanup(dev
);
3012 /* firmware is released later */
3015 /* Initialize the chip
3016 * http://bcm-specs.sipsolutions.net/ChipInit
3018 static int b43_chip_init(struct b43_wldev
*dev
)
3020 struct b43_phy
*phy
= &dev
->phy
;
3025 /* Initialize the MAC control */
3026 macctl
= B43_MACCTL_IHR_ENABLED
| B43_MACCTL_SHM_ENABLED
;
3028 macctl
|= B43_MACCTL_GMODE
;
3029 macctl
|= B43_MACCTL_INFRA
;
3030 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
3032 err
= b43_request_firmware(dev
);
3035 err
= b43_upload_microcode(dev
);
3037 goto out
; /* firmware is released later */
3039 err
= b43_gpio_init(dev
);
3041 goto out
; /* firmware is released later */
3043 err
= b43_upload_initvals(dev
);
3045 goto err_gpio_clean
;
3047 /* Turn the Analog on and initialize the PHY. */
3048 phy
->ops
->switch_analog(dev
, 1);
3049 err
= b43_phy_init(dev
);
3051 goto err_gpio_clean
;
3053 /* Disable Interference Mitigation. */
3054 if (phy
->ops
->interf_mitigation
)
3055 phy
->ops
->interf_mitigation(dev
, B43_INTERFMODE_NONE
);
3057 /* Select the antennae */
3058 if (phy
->ops
->set_rx_antenna
)
3059 phy
->ops
->set_rx_antenna(dev
, B43_ANTENNA_DEFAULT
);
3060 b43_mgmtframe_txantenna(dev
, B43_ANTENNA_DEFAULT
);
3062 if (phy
->type
== B43_PHYTYPE_B
) {
3063 value16
= b43_read16(dev
, 0x005E);
3065 b43_write16(dev
, 0x005E, value16
);
3067 b43_write32(dev
, 0x0100, 0x01000000);
3068 if (dev
->dev
->core_rev
< 5)
3069 b43_write32(dev
, 0x010C, 0x01000000);
3071 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
3072 & ~B43_MACCTL_INFRA
);
3073 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
3074 | B43_MACCTL_INFRA
);
3076 /* Probe Response Timeout value */
3077 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3078 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0074, 0x0000);
3080 /* Initially set the wireless operation mode. */
3081 b43_adjust_opmode(dev
);
3083 if (dev
->dev
->core_rev
< 3) {
3084 b43_write16(dev
, 0x060E, 0x0000);
3085 b43_write16(dev
, 0x0610, 0x8000);
3086 b43_write16(dev
, 0x0604, 0x0000);
3087 b43_write16(dev
, 0x0606, 0x0200);
3089 b43_write32(dev
, 0x0188, 0x80000000);
3090 b43_write32(dev
, 0x018C, 0x02000000);
3092 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, 0x00004000);
3093 b43_write32(dev
, B43_MMIO_DMA0_IRQ_MASK
, 0x0001DC00);
3094 b43_write32(dev
, B43_MMIO_DMA1_IRQ_MASK
, 0x0000DC00);
3095 b43_write32(dev
, B43_MMIO_DMA2_IRQ_MASK
, 0x0000DC00);
3096 b43_write32(dev
, B43_MMIO_DMA3_IRQ_MASK
, 0x0001DC00);
3097 b43_write32(dev
, B43_MMIO_DMA4_IRQ_MASK
, 0x0000DC00);
3098 b43_write32(dev
, B43_MMIO_DMA5_IRQ_MASK
, 0x0000DC00);
3100 b43_mac_phy_clock_set(dev
, true);
3102 switch (dev
->dev
->bus_type
) {
3103 #ifdef CONFIG_B43_BCMA
3105 /* FIXME: 0xE74 is quite common, but should be read from CC */
3106 b43_write16(dev
, B43_MMIO_POWERUP_DELAY
, 0xE74);
3109 #ifdef CONFIG_B43_SSB
3111 b43_write16(dev
, B43_MMIO_POWERUP_DELAY
,
3112 dev
->dev
->sdev
->bus
->chipco
.fast_pwrup_delay
);
3118 b43dbg(dev
->wl
, "Chip initialized\n");
3123 b43_gpio_cleanup(dev
);
3127 static void b43_periodic_every60sec(struct b43_wldev
*dev
)
3129 const struct b43_phy_operations
*ops
= dev
->phy
.ops
;
3131 if (ops
->pwork_60sec
)
3132 ops
->pwork_60sec(dev
);
3134 /* Force check the TX power emission now. */
3135 b43_phy_txpower_check(dev
, B43_TXPWR_IGNORE_TIME
);
3138 static void b43_periodic_every30sec(struct b43_wldev
*dev
)
3140 /* Update device statistics. */
3141 b43_calculate_link_quality(dev
);
3144 static void b43_periodic_every15sec(struct b43_wldev
*dev
)
3146 struct b43_phy
*phy
= &dev
->phy
;
3149 if (dev
->fw
.opensource
) {
3150 /* Check if the firmware is still alive.
3151 * It will reset the watchdog counter to 0 in its idle loop. */
3152 wdr
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, B43_WATCHDOG_REG
);
3153 if (unlikely(wdr
)) {
3154 b43err(dev
->wl
, "Firmware watchdog: The firmware died!\n");
3155 b43_controller_restart(dev
, "Firmware watchdog");
3158 b43_shm_write16(dev
, B43_SHM_SCRATCH
,
3159 B43_WATCHDOG_REG
, 1);
3163 if (phy
->ops
->pwork_15sec
)
3164 phy
->ops
->pwork_15sec(dev
);
3166 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
3170 if (b43_debug(dev
, B43_DBG_VERBOSESTATS
)) {
3173 b43dbg(dev
->wl
, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3174 dev
->irq_count
/ 15,
3176 dev
->rx_count
/ 15);
3180 for (i
= 0; i
< ARRAY_SIZE(dev
->irq_bit_count
); i
++) {
3181 if (dev
->irq_bit_count
[i
]) {
3182 b43dbg(dev
->wl
, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3183 dev
->irq_bit_count
[i
] / 15, i
, (1 << i
));
3184 dev
->irq_bit_count
[i
] = 0;
3191 static void do_periodic_work(struct b43_wldev
*dev
)
3195 state
= dev
->periodic_state
;
3197 b43_periodic_every60sec(dev
);
3199 b43_periodic_every30sec(dev
);
3200 b43_periodic_every15sec(dev
);
3203 /* Periodic work locking policy:
3204 * The whole periodic work handler is protected by
3205 * wl->mutex. If another lock is needed somewhere in the
3206 * pwork callchain, it's acquired in-place, where it's needed.
3208 static void b43_periodic_work_handler(struct work_struct
*work
)
3210 struct b43_wldev
*dev
= container_of(work
, struct b43_wldev
,
3211 periodic_work
.work
);
3212 struct b43_wl
*wl
= dev
->wl
;
3213 unsigned long delay
;
3215 mutex_lock(&wl
->mutex
);
3217 if (unlikely(b43_status(dev
) != B43_STAT_STARTED
))
3219 if (b43_debug(dev
, B43_DBG_PWORK_STOP
))
3222 do_periodic_work(dev
);
3224 dev
->periodic_state
++;
3226 if (b43_debug(dev
, B43_DBG_PWORK_FAST
))
3227 delay
= msecs_to_jiffies(50);
3229 delay
= round_jiffies_relative(HZ
* 15);
3230 ieee80211_queue_delayed_work(wl
->hw
, &dev
->periodic_work
, delay
);
3232 mutex_unlock(&wl
->mutex
);
3235 static void b43_periodic_tasks_setup(struct b43_wldev
*dev
)
3237 struct delayed_work
*work
= &dev
->periodic_work
;
3239 dev
->periodic_state
= 0;
3240 INIT_DELAYED_WORK(work
, b43_periodic_work_handler
);
3241 ieee80211_queue_delayed_work(dev
->wl
->hw
, work
, 0);
3244 /* Check if communication with the device works correctly. */
3245 static int b43_validate_chipaccess(struct b43_wldev
*dev
)
3247 u32 v
, backup0
, backup4
;
3249 backup0
= b43_shm_read32(dev
, B43_SHM_SHARED
, 0);
3250 backup4
= b43_shm_read32(dev
, B43_SHM_SHARED
, 4);
3252 /* Check for read/write and endianness problems. */
3253 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0x55AAAA55);
3254 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0x55AAAA55)
3256 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0xAA5555AA);
3257 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0xAA5555AA)
3260 /* Check if unaligned 32bit SHM_SHARED access works properly.
3261 * However, don't bail out on failure, because it's noncritical. */
3262 b43_shm_write16(dev
, B43_SHM_SHARED
, 0, 0x1122);
3263 b43_shm_write16(dev
, B43_SHM_SHARED
, 2, 0x3344);
3264 b43_shm_write16(dev
, B43_SHM_SHARED
, 4, 0x5566);
3265 b43_shm_write16(dev
, B43_SHM_SHARED
, 6, 0x7788);
3266 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 2) != 0x55663344)
3267 b43warn(dev
->wl
, "Unaligned 32bit SHM read access is broken\n");
3268 b43_shm_write32(dev
, B43_SHM_SHARED
, 2, 0xAABBCCDD);
3269 if (b43_shm_read16(dev
, B43_SHM_SHARED
, 0) != 0x1122 ||
3270 b43_shm_read16(dev
, B43_SHM_SHARED
, 2) != 0xCCDD ||
3271 b43_shm_read16(dev
, B43_SHM_SHARED
, 4) != 0xAABB ||
3272 b43_shm_read16(dev
, B43_SHM_SHARED
, 6) != 0x7788)
3273 b43warn(dev
->wl
, "Unaligned 32bit SHM write access is broken\n");
3275 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, backup0
);
3276 b43_shm_write32(dev
, B43_SHM_SHARED
, 4, backup4
);
3278 if ((dev
->dev
->core_rev
>= 3) && (dev
->dev
->core_rev
<= 10)) {
3279 /* The 32bit register shadows the two 16bit registers
3280 * with update sideeffects. Validate this. */
3281 b43_write16(dev
, B43_MMIO_TSF_CFP_START
, 0xAAAA);
3282 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0xCCCCBBBB);
3283 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_LOW
) != 0xBBBB)
3285 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_HIGH
) != 0xCCCC)
3288 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0);
3290 v
= b43_read32(dev
, B43_MMIO_MACCTL
);
3291 v
|= B43_MACCTL_GMODE
;
3292 if (v
!= (B43_MACCTL_GMODE
| B43_MACCTL_IHR_ENABLED
))
3297 b43err(dev
->wl
, "Failed to validate the chipaccess\n");
3301 static void b43_security_init(struct b43_wldev
*dev
)
3303 dev
->ktp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_KTP
);
3304 /* KTP is a word address, but we address SHM bytewise.
3305 * So multiply by two.
3308 /* Number of RCMTA address slots */
3309 b43_write16(dev
, B43_MMIO_RCMTA_COUNT
, B43_NR_PAIRWISE_KEYS
);
3310 /* Clear the key memory. */
3311 b43_clear_keys(dev
);
3314 #ifdef CONFIG_B43_HWRNG
3315 static int b43_rng_read(struct hwrng
*rng
, u32
*data
)
3317 struct b43_wl
*wl
= (struct b43_wl
*)rng
->priv
;
3318 struct b43_wldev
*dev
;
3319 int count
= -ENODEV
;
3321 mutex_lock(&wl
->mutex
);
3322 dev
= wl
->current_dev
;
3323 if (likely(dev
&& b43_status(dev
) >= B43_STAT_INITIALIZED
)) {
3324 *data
= b43_read16(dev
, B43_MMIO_RNG
);
3325 count
= sizeof(u16
);
3327 mutex_unlock(&wl
->mutex
);
3331 #endif /* CONFIG_B43_HWRNG */
3333 static void b43_rng_exit(struct b43_wl
*wl
)
3335 #ifdef CONFIG_B43_HWRNG
3336 if (wl
->rng_initialized
)
3337 hwrng_unregister(&wl
->rng
);
3338 #endif /* CONFIG_B43_HWRNG */
3341 static int b43_rng_init(struct b43_wl
*wl
)
3345 #ifdef CONFIG_B43_HWRNG
3346 snprintf(wl
->rng_name
, ARRAY_SIZE(wl
->rng_name
),
3347 "%s_%s", KBUILD_MODNAME
, wiphy_name(wl
->hw
->wiphy
));
3348 wl
->rng
.name
= wl
->rng_name
;
3349 wl
->rng
.data_read
= b43_rng_read
;
3350 wl
->rng
.priv
= (unsigned long)wl
;
3351 wl
->rng_initialized
= 1;
3352 err
= hwrng_register(&wl
->rng
);
3354 wl
->rng_initialized
= 0;
3355 b43err(wl
, "Failed to register the random "
3356 "number generator (%d)\n", err
);
3358 #endif /* CONFIG_B43_HWRNG */
3363 static void b43_tx_work(struct work_struct
*work
)
3365 struct b43_wl
*wl
= container_of(work
, struct b43_wl
, tx_work
);
3366 struct b43_wldev
*dev
;
3367 struct sk_buff
*skb
;
3370 mutex_lock(&wl
->mutex
);
3371 dev
= wl
->current_dev
;
3372 if (unlikely(!dev
|| b43_status(dev
) < B43_STAT_STARTED
)) {
3373 mutex_unlock(&wl
->mutex
);
3377 while (skb_queue_len(&wl
->tx_queue
)) {
3378 skb
= skb_dequeue(&wl
->tx_queue
);
3380 if (b43_using_pio_transfers(dev
))
3381 err
= b43_pio_tx(dev
, skb
);
3383 err
= b43_dma_tx(dev
, skb
);
3385 dev_kfree_skb(skb
); /* Drop it */
3391 mutex_unlock(&wl
->mutex
);
3394 static void b43_op_tx(struct ieee80211_hw
*hw
,
3395 struct sk_buff
*skb
)
3397 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3399 if (unlikely(skb
->len
< 2 + 2 + 6)) {
3400 /* Too short, this can't be a valid frame. */
3401 dev_kfree_skb_any(skb
);
3404 B43_WARN_ON(skb_shinfo(skb
)->nr_frags
);
3406 skb_queue_tail(&wl
->tx_queue
, skb
);
3407 ieee80211_queue_work(wl
->hw
, &wl
->tx_work
);
3410 static void b43_qos_params_upload(struct b43_wldev
*dev
,
3411 const struct ieee80211_tx_queue_params
*p
,
3414 u16 params
[B43_NR_QOSPARAMS
];
3418 if (!dev
->qos_enabled
)
3421 bslots
= b43_read16(dev
, B43_MMIO_RNG
) & p
->cw_min
;
3423 memset(¶ms
, 0, sizeof(params
));
3425 params
[B43_QOSPARAM_TXOP
] = p
->txop
* 32;
3426 params
[B43_QOSPARAM_CWMIN
] = p
->cw_min
;
3427 params
[B43_QOSPARAM_CWMAX
] = p
->cw_max
;
3428 params
[B43_QOSPARAM_CWCUR
] = p
->cw_min
;
3429 params
[B43_QOSPARAM_AIFS
] = p
->aifs
;
3430 params
[B43_QOSPARAM_BSLOTS
] = bslots
;
3431 params
[B43_QOSPARAM_REGGAP
] = bslots
+ p
->aifs
;
3433 for (i
= 0; i
< ARRAY_SIZE(params
); i
++) {
3434 if (i
== B43_QOSPARAM_STATUS
) {
3435 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
,
3436 shm_offset
+ (i
* 2));
3437 /* Mark the parameters as updated. */
3439 b43_shm_write16(dev
, B43_SHM_SHARED
,
3440 shm_offset
+ (i
* 2),
3443 b43_shm_write16(dev
, B43_SHM_SHARED
,
3444 shm_offset
+ (i
* 2),
3450 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3451 static const u16 b43_qos_shm_offsets
[] = {
3452 /* [mac80211-queue-nr] = SHM_OFFSET, */
3453 [0] = B43_QOS_VOICE
,
3454 [1] = B43_QOS_VIDEO
,
3455 [2] = B43_QOS_BESTEFFORT
,
3456 [3] = B43_QOS_BACKGROUND
,
3459 /* Update all QOS parameters in hardware. */
3460 static void b43_qos_upload_all(struct b43_wldev
*dev
)
3462 struct b43_wl
*wl
= dev
->wl
;
3463 struct b43_qos_params
*params
;
3466 if (!dev
->qos_enabled
)
3469 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets
) !=
3470 ARRAY_SIZE(wl
->qos_params
));
3472 b43_mac_suspend(dev
);
3473 for (i
= 0; i
< ARRAY_SIZE(wl
->qos_params
); i
++) {
3474 params
= &(wl
->qos_params
[i
]);
3475 b43_qos_params_upload(dev
, &(params
->p
),
3476 b43_qos_shm_offsets
[i
]);
3478 b43_mac_enable(dev
);
3481 static void b43_qos_clear(struct b43_wl
*wl
)
3483 struct b43_qos_params
*params
;
3486 /* Initialize QoS parameters to sane defaults. */
3488 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets
) !=
3489 ARRAY_SIZE(wl
->qos_params
));
3491 for (i
= 0; i
< ARRAY_SIZE(wl
->qos_params
); i
++) {
3492 params
= &(wl
->qos_params
[i
]);
3494 switch (b43_qos_shm_offsets
[i
]) {
3498 params
->p
.cw_min
= 0x0001;
3499 params
->p
.cw_max
= 0x0001;
3504 params
->p
.cw_min
= 0x0001;
3505 params
->p
.cw_max
= 0x0001;
3507 case B43_QOS_BESTEFFORT
:
3510 params
->p
.cw_min
= 0x0001;
3511 params
->p
.cw_max
= 0x03FF;
3513 case B43_QOS_BACKGROUND
:
3516 params
->p
.cw_min
= 0x0001;
3517 params
->p
.cw_max
= 0x03FF;
3525 /* Initialize the core's QOS capabilities */
3526 static void b43_qos_init(struct b43_wldev
*dev
)
3528 if (!dev
->qos_enabled
) {
3529 /* Disable QOS support. */
3530 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_EDCF
);
3531 b43_write16(dev
, B43_MMIO_IFSCTL
,
3532 b43_read16(dev
, B43_MMIO_IFSCTL
)
3533 & ~B43_MMIO_IFSCTL_USE_EDCF
);
3534 b43dbg(dev
->wl
, "QoS disabled\n");
3538 /* Upload the current QOS parameters. */
3539 b43_qos_upload_all(dev
);
3541 /* Enable QOS support. */
3542 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_EDCF
);
3543 b43_write16(dev
, B43_MMIO_IFSCTL
,
3544 b43_read16(dev
, B43_MMIO_IFSCTL
)
3545 | B43_MMIO_IFSCTL_USE_EDCF
);
3546 b43dbg(dev
->wl
, "QoS enabled\n");
3549 static int b43_op_conf_tx(struct ieee80211_hw
*hw
, u16 _queue
,
3550 const struct ieee80211_tx_queue_params
*params
)
3552 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3553 struct b43_wldev
*dev
;
3554 unsigned int queue
= (unsigned int)_queue
;
3557 if (queue
>= ARRAY_SIZE(wl
->qos_params
)) {
3558 /* Queue not available or don't support setting
3559 * params on this queue. Return success to not
3560 * confuse mac80211. */
3563 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets
) !=
3564 ARRAY_SIZE(wl
->qos_params
));
3566 mutex_lock(&wl
->mutex
);
3567 dev
= wl
->current_dev
;
3568 if (unlikely(!dev
|| (b43_status(dev
) < B43_STAT_INITIALIZED
)))
3571 memcpy(&(wl
->qos_params
[queue
].p
), params
, sizeof(*params
));
3572 b43_mac_suspend(dev
);
3573 b43_qos_params_upload(dev
, &(wl
->qos_params
[queue
].p
),
3574 b43_qos_shm_offsets
[queue
]);
3575 b43_mac_enable(dev
);
3579 mutex_unlock(&wl
->mutex
);
3584 static int b43_op_get_stats(struct ieee80211_hw
*hw
,
3585 struct ieee80211_low_level_stats
*stats
)
3587 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3589 mutex_lock(&wl
->mutex
);
3590 memcpy(stats
, &wl
->ieee_stats
, sizeof(*stats
));
3591 mutex_unlock(&wl
->mutex
);
3596 static u64
b43_op_get_tsf(struct ieee80211_hw
*hw
)
3598 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3599 struct b43_wldev
*dev
;
3602 mutex_lock(&wl
->mutex
);
3603 dev
= wl
->current_dev
;
3605 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
))
3606 b43_tsf_read(dev
, &tsf
);
3610 mutex_unlock(&wl
->mutex
);
3615 static void b43_op_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
3617 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3618 struct b43_wldev
*dev
;
3620 mutex_lock(&wl
->mutex
);
3621 dev
= wl
->current_dev
;
3623 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
))
3624 b43_tsf_write(dev
, tsf
);
3626 mutex_unlock(&wl
->mutex
);
3629 static void b43_put_phy_into_reset(struct b43_wldev
*dev
)
3633 switch (dev
->dev
->bus_type
) {
3634 #ifdef CONFIG_B43_BCMA
3637 "Putting PHY into reset not supported on BCMA\n");
3640 #ifdef CONFIG_B43_SSB
3642 tmp
= ssb_read32(dev
->dev
->sdev
, SSB_TMSLOW
);
3643 tmp
&= ~B43_TMSLOW_GMODE
;
3644 tmp
|= B43_TMSLOW_PHYRESET
;
3645 tmp
|= SSB_TMSLOW_FGC
;
3646 ssb_write32(dev
->dev
->sdev
, SSB_TMSLOW
, tmp
);
3649 tmp
= ssb_read32(dev
->dev
->sdev
, SSB_TMSLOW
);
3650 tmp
&= ~SSB_TMSLOW_FGC
;
3651 tmp
|= B43_TMSLOW_PHYRESET
;
3652 ssb_write32(dev
->dev
->sdev
, SSB_TMSLOW
, tmp
);
3660 static const char *band_to_string(enum ieee80211_band band
)
3663 case IEEE80211_BAND_5GHZ
:
3665 case IEEE80211_BAND_2GHZ
:
3674 /* Expects wl->mutex locked */
3675 static int b43_switch_band(struct b43_wl
*wl
, struct ieee80211_channel
*chan
)
3677 struct b43_wldev
*up_dev
= NULL
;
3678 struct b43_wldev
*down_dev
;
3679 struct b43_wldev
*d
;
3681 bool uninitialized_var(gmode
);
3684 /* Find a device and PHY which supports the band. */
3685 list_for_each_entry(d
, &wl
->devlist
, list
) {
3686 switch (chan
->band
) {
3687 case IEEE80211_BAND_5GHZ
:
3688 if (d
->phy
.supports_5ghz
) {
3693 case IEEE80211_BAND_2GHZ
:
3694 if (d
->phy
.supports_2ghz
) {
3707 b43err(wl
, "Could not find a device for %s-GHz band operation\n",
3708 band_to_string(chan
->band
));
3711 if ((up_dev
== wl
->current_dev
) &&
3712 (!!wl
->current_dev
->phy
.gmode
== !!gmode
)) {
3713 /* This device is already running. */
3716 b43dbg(wl
, "Switching to %s-GHz band\n",
3717 band_to_string(chan
->band
));
3718 down_dev
= wl
->current_dev
;
3720 prev_status
= b43_status(down_dev
);
3721 /* Shutdown the currently running core. */
3722 if (prev_status
>= B43_STAT_STARTED
)
3723 down_dev
= b43_wireless_core_stop(down_dev
);
3724 if (prev_status
>= B43_STAT_INITIALIZED
)
3725 b43_wireless_core_exit(down_dev
);
3727 if (down_dev
!= up_dev
) {
3728 /* We switch to a different core, so we put PHY into
3729 * RESET on the old core. */
3730 b43_put_phy_into_reset(down_dev
);
3733 /* Now start the new core. */
3734 up_dev
->phy
.gmode
= gmode
;
3735 if (prev_status
>= B43_STAT_INITIALIZED
) {
3736 err
= b43_wireless_core_init(up_dev
);
3738 b43err(wl
, "Fatal: Could not initialize device for "
3739 "selected %s-GHz band\n",
3740 band_to_string(chan
->band
));
3744 if (prev_status
>= B43_STAT_STARTED
) {
3745 err
= b43_wireless_core_start(up_dev
);
3747 b43err(wl
, "Fatal: Coult not start device for "
3748 "selected %s-GHz band\n",
3749 band_to_string(chan
->band
));
3750 b43_wireless_core_exit(up_dev
);
3754 B43_WARN_ON(b43_status(up_dev
) != prev_status
);
3756 wl
->current_dev
= up_dev
;
3760 /* Whoops, failed to init the new core. No core is operating now. */
3761 wl
->current_dev
= NULL
;
3765 /* Write the short and long frame retry limit values. */
3766 static void b43_set_retry_limits(struct b43_wldev
*dev
,
3767 unsigned int short_retry
,
3768 unsigned int long_retry
)
3770 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3771 * the chip-internal counter. */
3772 short_retry
= min(short_retry
, (unsigned int)0xF);
3773 long_retry
= min(long_retry
, (unsigned int)0xF);
3775 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_SRLIMIT
,
3777 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_LRLIMIT
,
3781 static int b43_op_config(struct ieee80211_hw
*hw
, u32 changed
)
3783 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3784 struct b43_wldev
*dev
;
3785 struct b43_phy
*phy
;
3786 struct ieee80211_conf
*conf
= &hw
->conf
;
3789 bool reload_bss
= false;
3791 mutex_lock(&wl
->mutex
);
3793 dev
= wl
->current_dev
;
3795 /* Switch the band (if necessary). This might change the active core. */
3796 err
= b43_switch_band(wl
, conf
->channel
);
3798 goto out_unlock_mutex
;
3800 /* Need to reload all settings if the core changed */
3801 if (dev
!= wl
->current_dev
) {
3802 dev
= wl
->current_dev
;
3809 if (conf_is_ht(conf
))
3811 (conf_is_ht40_minus(conf
) || conf_is_ht40_plus(conf
));
3813 phy
->is_40mhz
= false;
3815 b43_mac_suspend(dev
);
3817 if (changed
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
3818 b43_set_retry_limits(dev
, conf
->short_frame_max_tx_count
,
3819 conf
->long_frame_max_tx_count
);
3820 changed
&= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS
;
3822 goto out_mac_enable
;
3824 /* Switch to the requested channel.
3825 * The firmware takes care of races with the TX handler. */
3826 if (conf
->channel
->hw_value
!= phy
->channel
)
3827 b43_switch_channel(dev
, conf
->channel
->hw_value
);
3829 dev
->wl
->radiotap_enabled
= !!(conf
->flags
& IEEE80211_CONF_MONITOR
);
3831 /* Adjust the desired TX power level. */
3832 if (conf
->power_level
!= 0) {
3833 if (conf
->power_level
!= phy
->desired_txpower
) {
3834 phy
->desired_txpower
= conf
->power_level
;
3835 b43_phy_txpower_check(dev
, B43_TXPWR_IGNORE_TIME
|
3836 B43_TXPWR_IGNORE_TSSI
);
3840 /* Antennas for RX and management frame TX. */
3841 antenna
= B43_ANTENNA_DEFAULT
;
3842 b43_mgmtframe_txantenna(dev
, antenna
);
3843 antenna
= B43_ANTENNA_DEFAULT
;
3844 if (phy
->ops
->set_rx_antenna
)
3845 phy
->ops
->set_rx_antenna(dev
, antenna
);
3847 if (wl
->radio_enabled
!= phy
->radio_on
) {
3848 if (wl
->radio_enabled
) {
3849 b43_software_rfkill(dev
, false);
3850 b43info(dev
->wl
, "Radio turned on by software\n");
3851 if (!dev
->radio_hw_enable
) {
3852 b43info(dev
->wl
, "The hardware RF-kill button "
3853 "still turns the radio physically off. "
3854 "Press the button to turn it on.\n");
3857 b43_software_rfkill(dev
, true);
3858 b43info(dev
->wl
, "Radio turned off by software\n");
3863 b43_mac_enable(dev
);
3865 mutex_unlock(&wl
->mutex
);
3867 if (wl
->vif
&& reload_bss
)
3868 b43_op_bss_info_changed(hw
, wl
->vif
, &wl
->vif
->bss_conf
, ~0);
3873 static void b43_update_basic_rates(struct b43_wldev
*dev
, u32 brates
)
3875 struct ieee80211_supported_band
*sband
=
3876 dev
->wl
->hw
->wiphy
->bands
[b43_current_band(dev
->wl
)];
3877 struct ieee80211_rate
*rate
;
3879 u16 basic
, direct
, offset
, basic_offset
, rateptr
;
3881 for (i
= 0; i
< sband
->n_bitrates
; i
++) {
3882 rate
= &sband
->bitrates
[i
];
3884 if (b43_is_cck_rate(rate
->hw_value
)) {
3885 direct
= B43_SHM_SH_CCKDIRECT
;
3886 basic
= B43_SHM_SH_CCKBASIC
;
3887 offset
= b43_plcp_get_ratecode_cck(rate
->hw_value
);
3890 direct
= B43_SHM_SH_OFDMDIRECT
;
3891 basic
= B43_SHM_SH_OFDMBASIC
;
3892 offset
= b43_plcp_get_ratecode_ofdm(rate
->hw_value
);
3896 rate
= ieee80211_get_response_rate(sband
, brates
, rate
->bitrate
);
3898 if (b43_is_cck_rate(rate
->hw_value
)) {
3899 basic_offset
= b43_plcp_get_ratecode_cck(rate
->hw_value
);
3900 basic_offset
&= 0xF;
3902 basic_offset
= b43_plcp_get_ratecode_ofdm(rate
->hw_value
);
3903 basic_offset
&= 0xF;
3907 * Get the pointer that we need to point to
3908 * from the direct map
3910 rateptr
= b43_shm_read16(dev
, B43_SHM_SHARED
,
3911 direct
+ 2 * basic_offset
);
3912 /* and write it to the basic map */
3913 b43_shm_write16(dev
, B43_SHM_SHARED
, basic
+ 2 * offset
,
3918 static void b43_op_bss_info_changed(struct ieee80211_hw
*hw
,
3919 struct ieee80211_vif
*vif
,
3920 struct ieee80211_bss_conf
*conf
,
3923 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3924 struct b43_wldev
*dev
;
3926 mutex_lock(&wl
->mutex
);
3928 dev
= wl
->current_dev
;
3929 if (!dev
|| b43_status(dev
) < B43_STAT_STARTED
)
3930 goto out_unlock_mutex
;
3932 B43_WARN_ON(wl
->vif
!= vif
);
3934 if (changed
& BSS_CHANGED_BSSID
) {
3936 memcpy(wl
->bssid
, conf
->bssid
, ETH_ALEN
);
3938 memset(wl
->bssid
, 0, ETH_ALEN
);
3941 if (b43_status(dev
) >= B43_STAT_INITIALIZED
) {
3942 if (changed
& BSS_CHANGED_BEACON
&&
3943 (b43_is_mode(wl
, NL80211_IFTYPE_AP
) ||
3944 b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
) ||
3945 b43_is_mode(wl
, NL80211_IFTYPE_ADHOC
)))
3946 b43_update_templates(wl
);
3948 if (changed
& BSS_CHANGED_BSSID
)
3949 b43_write_mac_bssid_templates(dev
);
3952 b43_mac_suspend(dev
);
3954 /* Update templates for AP/mesh mode. */
3955 if (changed
& BSS_CHANGED_BEACON_INT
&&
3956 (b43_is_mode(wl
, NL80211_IFTYPE_AP
) ||
3957 b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
) ||
3958 b43_is_mode(wl
, NL80211_IFTYPE_ADHOC
)) &&
3960 b43_set_beacon_int(dev
, conf
->beacon_int
);
3962 if (changed
& BSS_CHANGED_BASIC_RATES
)
3963 b43_update_basic_rates(dev
, conf
->basic_rates
);
3965 if (changed
& BSS_CHANGED_ERP_SLOT
) {
3966 if (conf
->use_short_slot
)
3967 b43_short_slot_timing_enable(dev
);
3969 b43_short_slot_timing_disable(dev
);
3972 b43_mac_enable(dev
);
3974 mutex_unlock(&wl
->mutex
);
3977 static int b43_op_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3978 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
3979 struct ieee80211_key_conf
*key
)
3981 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3982 struct b43_wldev
*dev
;
3986 static const u8 bcast_addr
[ETH_ALEN
] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3988 if (modparam_nohwcrypt
)
3989 return -ENOSPC
; /* User disabled HW-crypto */
3991 mutex_lock(&wl
->mutex
);
3993 dev
= wl
->current_dev
;
3995 if (!dev
|| b43_status(dev
) < B43_STAT_INITIALIZED
)
3998 if (dev
->fw
.pcm_request_failed
|| !dev
->hwcrypto_enabled
) {
3999 /* We don't have firmware for the crypto engine.
4000 * Must use software-crypto. */
4006 switch (key
->cipher
) {
4007 case WLAN_CIPHER_SUITE_WEP40
:
4008 algorithm
= B43_SEC_ALGO_WEP40
;
4010 case WLAN_CIPHER_SUITE_WEP104
:
4011 algorithm
= B43_SEC_ALGO_WEP104
;
4013 case WLAN_CIPHER_SUITE_TKIP
:
4014 algorithm
= B43_SEC_ALGO_TKIP
;
4016 case WLAN_CIPHER_SUITE_CCMP
:
4017 algorithm
= B43_SEC_ALGO_AES
;
4023 index
= (u8
) (key
->keyidx
);
4029 if (algorithm
== B43_SEC_ALGO_TKIP
&&
4030 (!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
) ||
4031 !modparam_hwtkip
)) {
4032 /* We support only pairwise key */
4037 if (key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
) {
4038 if (WARN_ON(!sta
)) {
4042 /* Pairwise key with an assigned MAC address. */
4043 err
= b43_key_write(dev
, -1, algorithm
,
4044 key
->key
, key
->keylen
,
4048 err
= b43_key_write(dev
, index
, algorithm
,
4049 key
->key
, key
->keylen
, NULL
, key
);
4054 if (algorithm
== B43_SEC_ALGO_WEP40
||
4055 algorithm
== B43_SEC_ALGO_WEP104
) {
4056 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_USEDEFKEYS
);
4059 b43_hf_read(dev
) & ~B43_HF_USEDEFKEYS
);
4061 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
4062 if (algorithm
== B43_SEC_ALGO_TKIP
)
4063 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
4066 err
= b43_key_clear(dev
, key
->hw_key_idx
);
4077 b43dbg(wl
, "%s hardware based encryption for keyidx: %d, "
4079 cmd
== SET_KEY
? "Using" : "Disabling", key
->keyidx
,
4080 sta
? sta
->addr
: bcast_addr
);
4081 b43_dump_keymemory(dev
);
4083 mutex_unlock(&wl
->mutex
);
4088 static void b43_op_configure_filter(struct ieee80211_hw
*hw
,
4089 unsigned int changed
, unsigned int *fflags
,
4092 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4093 struct b43_wldev
*dev
;
4095 mutex_lock(&wl
->mutex
);
4096 dev
= wl
->current_dev
;
4102 *fflags
&= FIF_PROMISC_IN_BSS
|
4108 FIF_BCN_PRBRESP_PROMISC
;
4110 changed
&= FIF_PROMISC_IN_BSS
|
4116 FIF_BCN_PRBRESP_PROMISC
;
4118 wl
->filter_flags
= *fflags
;
4120 if (changed
&& b43_status(dev
) >= B43_STAT_INITIALIZED
)
4121 b43_adjust_opmode(dev
);
4124 mutex_unlock(&wl
->mutex
);
4127 /* Locking: wl->mutex
4128 * Returns the current dev. This might be different from the passed in dev,
4129 * because the core might be gone away while we unlocked the mutex. */
4130 static struct b43_wldev
* b43_wireless_core_stop(struct b43_wldev
*dev
)
4132 struct b43_wl
*wl
= dev
->wl
;
4133 struct b43_wldev
*orig_dev
;
4137 if (!dev
|| b43_status(dev
) < B43_STAT_STARTED
)
4140 /* Cancel work. Unlock to avoid deadlocks. */
4141 mutex_unlock(&wl
->mutex
);
4142 cancel_delayed_work_sync(&dev
->periodic_work
);
4143 cancel_work_sync(&wl
->tx_work
);
4144 mutex_lock(&wl
->mutex
);
4145 dev
= wl
->current_dev
;
4146 if (!dev
|| b43_status(dev
) < B43_STAT_STARTED
) {
4147 /* Whoops, aliens ate up the device while we were unlocked. */
4151 /* Disable interrupts on the device. */
4152 b43_set_status(dev
, B43_STAT_INITIALIZED
);
4153 if (b43_bus_host_is_sdio(dev
->dev
)) {
4154 /* wl->mutex is locked. That is enough. */
4155 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, 0);
4156 b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
); /* Flush */
4158 spin_lock_irq(&wl
->hardirq_lock
);
4159 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, 0);
4160 b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
); /* Flush */
4161 spin_unlock_irq(&wl
->hardirq_lock
);
4163 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4165 mutex_unlock(&wl
->mutex
);
4166 if (b43_bus_host_is_sdio(dev
->dev
)) {
4167 b43_sdio_free_irq(dev
);
4169 synchronize_irq(dev
->dev
->irq
);
4170 free_irq(dev
->dev
->irq
, dev
);
4172 mutex_lock(&wl
->mutex
);
4173 dev
= wl
->current_dev
;
4176 if (dev
!= orig_dev
) {
4177 if (b43_status(dev
) >= B43_STAT_STARTED
)
4181 mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
4182 B43_WARN_ON(mask
!= 0xFFFFFFFF && mask
);
4184 /* Drain the TX queue */
4185 while (skb_queue_len(&wl
->tx_queue
))
4186 dev_kfree_skb(skb_dequeue(&wl
->tx_queue
));
4188 b43_mac_suspend(dev
);
4190 b43dbg(wl
, "Wireless interface stopped\n");
4195 /* Locking: wl->mutex */
4196 static int b43_wireless_core_start(struct b43_wldev
*dev
)
4200 B43_WARN_ON(b43_status(dev
) != B43_STAT_INITIALIZED
);
4202 drain_txstatus_queue(dev
);
4203 if (b43_bus_host_is_sdio(dev
->dev
)) {
4204 err
= b43_sdio_request_irq(dev
, b43_sdio_interrupt_handler
);
4206 b43err(dev
->wl
, "Cannot request SDIO IRQ\n");
4210 err
= request_threaded_irq(dev
->dev
->irq
, b43_interrupt_handler
,
4211 b43_interrupt_thread_handler
,
4212 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
4214 b43err(dev
->wl
, "Cannot request IRQ-%d\n",
4220 /* We are ready to run. */
4221 ieee80211_wake_queues(dev
->wl
->hw
);
4222 b43_set_status(dev
, B43_STAT_STARTED
);
4224 /* Start data flow (TX/RX). */
4225 b43_mac_enable(dev
);
4226 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, dev
->irq_mask
);
4228 /* Start maintenance work */
4229 b43_periodic_tasks_setup(dev
);
4233 b43dbg(dev
->wl
, "Wireless interface started\n");
4238 /* Get PHY and RADIO versioning numbers */
4239 static int b43_phy_versioning(struct b43_wldev
*dev
)
4241 struct b43_phy
*phy
= &dev
->phy
;
4249 int unsupported
= 0;
4251 /* Get PHY versioning */
4252 tmp
= b43_read16(dev
, B43_MMIO_PHY_VER
);
4253 analog_type
= (tmp
& B43_PHYVER_ANALOG
) >> B43_PHYVER_ANALOG_SHIFT
;
4254 phy_type
= (tmp
& B43_PHYVER_TYPE
) >> B43_PHYVER_TYPE_SHIFT
;
4255 phy_rev
= (tmp
& B43_PHYVER_VERSION
);
4262 if (phy_rev
!= 2 && phy_rev
!= 4 && phy_rev
!= 6
4270 #ifdef CONFIG_B43_PHY_N
4276 #ifdef CONFIG_B43_PHY_LP
4277 case B43_PHYTYPE_LP
:
4282 #ifdef CONFIG_B43_PHY_HT
4283 case B43_PHYTYPE_HT
:
4288 #ifdef CONFIG_B43_PHY_LCN
4289 case B43_PHYTYPE_LCN
:
4298 b43err(dev
->wl
, "FOUND UNSUPPORTED PHY "
4299 "(Analog %u, Type %u, Revision %u)\n",
4300 analog_type
, phy_type
, phy_rev
);
4303 b43dbg(dev
->wl
, "Found PHY: Analog %u, Type %u, Revision %u\n",
4304 analog_type
, phy_type
, phy_rev
);
4306 /* Get RADIO versioning */
4307 if (dev
->dev
->core_rev
>= 24) {
4310 for (tmp
= 0; tmp
< 3; tmp
++) {
4311 b43_write16(dev
, B43_MMIO_RADIO24_CONTROL
, tmp
);
4312 radio24
[tmp
] = b43_read16(dev
, B43_MMIO_RADIO24_DATA
);
4315 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4316 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4318 radio_manuf
= 0x17F;
4319 radio_ver
= (radio24
[2] << 8) | radio24
[1];
4320 radio_rev
= (radio24
[0] & 0xF);
4322 if (dev
->dev
->chip_id
== 0x4317) {
4323 if (dev
->dev
->chip_rev
== 0)
4325 else if (dev
->dev
->chip_rev
== 1)
4330 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
,
4332 tmp
= b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
4333 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
,
4335 tmp
|= (u32
)b43_read16(dev
, B43_MMIO_RADIO_DATA_HIGH
)
4338 radio_manuf
= (tmp
& 0x00000FFF);
4339 radio_ver
= (tmp
& 0x0FFFF000) >> 12;
4340 radio_rev
= (tmp
& 0xF0000000) >> 28;
4343 if (radio_manuf
!= 0x17F /* Broadcom */)
4347 if (radio_ver
!= 0x2060)
4351 if (radio_manuf
!= 0x17F)
4355 if ((radio_ver
& 0xFFF0) != 0x2050)
4359 if (radio_ver
!= 0x2050)
4363 if (radio_ver
!= 0x2055 && radio_ver
!= 0x2056)
4366 case B43_PHYTYPE_LP
:
4367 if (radio_ver
!= 0x2062 && radio_ver
!= 0x2063)
4370 case B43_PHYTYPE_HT
:
4371 if (radio_ver
!= 0x2059)
4374 case B43_PHYTYPE_LCN
:
4375 if (radio_ver
!= 0x2064)
4382 b43err(dev
->wl
, "FOUND UNSUPPORTED RADIO "
4383 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4384 radio_manuf
, radio_ver
, radio_rev
);
4387 b43dbg(dev
->wl
, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4388 radio_manuf
, radio_ver
, radio_rev
);
4390 phy
->radio_manuf
= radio_manuf
;
4391 phy
->radio_ver
= radio_ver
;
4392 phy
->radio_rev
= radio_rev
;
4394 phy
->analog
= analog_type
;
4395 phy
->type
= phy_type
;
4401 static void setup_struct_phy_for_init(struct b43_wldev
*dev
,
4402 struct b43_phy
*phy
)
4404 phy
->hardware_power_control
= !!modparam_hwpctl
;
4405 phy
->next_txpwr_check_time
= jiffies
;
4406 /* PHY TX errors counter. */
4407 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
4410 phy
->phy_locked
= 0;
4411 phy
->radio_locked
= 0;
4415 static void setup_struct_wldev_for_init(struct b43_wldev
*dev
)
4419 /* Assume the radio is enabled. If it's not enabled, the state will
4420 * immediately get fixed on the first periodic work run. */
4421 dev
->radio_hw_enable
= 1;
4424 memset(&dev
->stats
, 0, sizeof(dev
->stats
));
4426 setup_struct_phy_for_init(dev
, &dev
->phy
);
4428 /* IRQ related flags */
4429 dev
->irq_reason
= 0;
4430 memset(dev
->dma_reason
, 0, sizeof(dev
->dma_reason
));
4431 dev
->irq_mask
= B43_IRQ_MASKTEMPLATE
;
4432 if (b43_modparam_verbose
< B43_VERBOSITY_DEBUG
)
4433 dev
->irq_mask
&= ~B43_IRQ_PHY_TXERR
;
4435 dev
->mac_suspended
= 1;
4437 /* Noise calculation context */
4438 memset(&dev
->noisecalc
, 0, sizeof(dev
->noisecalc
));
4441 static void b43_bluetooth_coext_enable(struct b43_wldev
*dev
)
4443 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
4446 if (!modparam_btcoex
)
4448 if (!(sprom
->boardflags_lo
& B43_BFL_BTCOEXIST
))
4450 if (dev
->phy
.type
!= B43_PHYTYPE_B
&& !dev
->phy
.gmode
)
4453 hf
= b43_hf_read(dev
);
4454 if (sprom
->boardflags_lo
& B43_BFL_BTCMOD
)
4455 hf
|= B43_HF_BTCOEXALT
;
4457 hf
|= B43_HF_BTCOEX
;
4458 b43_hf_write(dev
, hf
);
4461 static void b43_bluetooth_coext_disable(struct b43_wldev
*dev
)
4463 if (!modparam_btcoex
)
4468 static void b43_imcfglo_timeouts_workaround(struct b43_wldev
*dev
)
4470 struct ssb_bus
*bus
;
4473 if (dev
->dev
->bus_type
!= B43_BUS_SSB
)
4476 bus
= dev
->dev
->sdev
->bus
;
4478 if ((bus
->chip_id
== 0x4311 && bus
->chip_rev
== 2) ||
4479 (bus
->chip_id
== 0x4312)) {
4480 tmp
= ssb_read32(dev
->dev
->sdev
, SSB_IMCFGLO
);
4481 tmp
&= ~SSB_IMCFGLO_REQTO
;
4482 tmp
&= ~SSB_IMCFGLO_SERTO
;
4484 ssb_write32(dev
->dev
->sdev
, SSB_IMCFGLO
, tmp
);
4485 ssb_commit_settings(bus
);
4489 static void b43_set_synth_pu_delay(struct b43_wldev
*dev
, bool idle
)
4493 /* The time value is in microseconds. */
4494 if (dev
->phy
.type
== B43_PHYTYPE_A
)
4498 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_ADHOC
) || idle
)
4500 if ((dev
->phy
.radio_ver
== 0x2050) && (dev
->phy
.radio_rev
== 8))
4501 pu_delay
= max(pu_delay
, (u16
)2400);
4503 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SPUWKUP
, pu_delay
);
4506 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4507 static void b43_set_pretbtt(struct b43_wldev
*dev
)
4511 /* The time value is in microseconds. */
4512 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_ADHOC
)) {
4515 if (dev
->phy
.type
== B43_PHYTYPE_A
)
4520 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRETBTT
, pretbtt
);
4521 b43_write16(dev
, B43_MMIO_TSF_CFP_PRETBTT
, pretbtt
);
4524 /* Shutdown a wireless core */
4525 /* Locking: wl->mutex */
4526 static void b43_wireless_core_exit(struct b43_wldev
*dev
)
4530 B43_WARN_ON(dev
&& b43_status(dev
) > B43_STAT_INITIALIZED
);
4531 if (!dev
|| b43_status(dev
) != B43_STAT_INITIALIZED
)
4534 /* Unregister HW RNG driver */
4535 b43_rng_exit(dev
->wl
);
4537 b43_set_status(dev
, B43_STAT_UNINIT
);
4539 /* Stop the microcode PSM. */
4540 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
4541 macctl
&= ~B43_MACCTL_PSM_RUN
;
4542 macctl
|= B43_MACCTL_PSM_JMP0
;
4543 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
4548 dev
->phy
.ops
->switch_analog(dev
, 0);
4549 if (dev
->wl
->current_beacon
) {
4550 dev_kfree_skb_any(dev
->wl
->current_beacon
);
4551 dev
->wl
->current_beacon
= NULL
;
4554 b43_device_disable(dev
, 0);
4555 b43_bus_may_powerdown(dev
);
4558 /* Initialize a wireless core */
4559 static int b43_wireless_core_init(struct b43_wldev
*dev
)
4561 struct ssb_sprom
*sprom
= dev
->dev
->bus_sprom
;
4562 struct b43_phy
*phy
= &dev
->phy
;
4566 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
4568 err
= b43_bus_powerup(dev
, 0);
4571 if (!b43_device_is_enabled(dev
))
4572 b43_wireless_core_reset(dev
, phy
->gmode
);
4574 /* Reset all data structures. */
4575 setup_struct_wldev_for_init(dev
);
4576 phy
->ops
->prepare_structs(dev
);
4578 /* Enable IRQ routing to this device. */
4579 switch (dev
->dev
->bus_type
) {
4580 #ifdef CONFIG_B43_BCMA
4582 bcma_core_pci_irq_ctl(&dev
->dev
->bdev
->bus
->drv_pci
,
4583 dev
->dev
->bdev
, true);
4586 #ifdef CONFIG_B43_SSB
4588 ssb_pcicore_dev_irqvecs_enable(&dev
->dev
->sdev
->bus
->pcicore
,
4594 b43_imcfglo_timeouts_workaround(dev
);
4595 b43_bluetooth_coext_disable(dev
);
4596 if (phy
->ops
->prepare_hardware
) {
4597 err
= phy
->ops
->prepare_hardware(dev
);
4601 err
= b43_chip_init(dev
);
4604 b43_shm_write16(dev
, B43_SHM_SHARED
,
4605 B43_SHM_SH_WLCOREREV
, dev
->dev
->core_rev
);
4606 hf
= b43_hf_read(dev
);
4607 if (phy
->type
== B43_PHYTYPE_G
) {
4611 if (sprom
->boardflags_lo
& B43_BFL_PACTRL
)
4612 hf
|= B43_HF_OFDMPABOOST
;
4614 if (phy
->radio_ver
== 0x2050) {
4615 if (phy
->radio_rev
== 6)
4616 hf
|= B43_HF_4318TSSI
;
4617 if (phy
->radio_rev
< 6)
4618 hf
|= B43_HF_VCORECALC
;
4620 if (sprom
->boardflags_lo
& B43_BFL_XTAL_NOSLOW
)
4621 hf
|= B43_HF_DSCRQ
; /* Disable slowclock requests from ucode. */
4622 #ifdef CONFIG_SSB_DRIVER_PCICORE
4623 if (dev
->dev
->bus_type
== B43_BUS_SSB
&&
4624 dev
->dev
->sdev
->bus
->bustype
== SSB_BUSTYPE_PCI
&&
4625 dev
->dev
->sdev
->bus
->pcicore
.dev
->id
.revision
<= 10)
4626 hf
|= B43_HF_PCISCW
; /* PCI slow clock workaround. */
4628 hf
&= ~B43_HF_SKCFPUP
;
4629 b43_hf_write(dev
, hf
);
4631 b43_set_retry_limits(dev
, B43_DEFAULT_SHORT_RETRY_LIMIT
,
4632 B43_DEFAULT_LONG_RETRY_LIMIT
);
4633 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SFFBLIM
, 3);
4634 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_LFFBLIM
, 2);
4636 /* Disable sending probe responses from firmware.
4637 * Setting the MaxTime to one usec will always trigger
4638 * a timeout, so we never send any probe resp.
4639 * A timeout of zero is infinite. */
4640 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRMAXTIME
, 1);
4642 b43_rate_memory_init(dev
);
4643 b43_set_phytxctl_defaults(dev
);
4645 /* Minimum Contention Window */
4646 if (phy
->type
== B43_PHYTYPE_B
)
4647 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0x1F);
4649 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0xF);
4650 /* Maximum Contention Window */
4651 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MAXCONT
, 0x3FF);
4653 if (b43_bus_host_is_pcmcia(dev
->dev
) ||
4654 b43_bus_host_is_sdio(dev
->dev
) ||
4656 dev
->__using_pio_transfers
= 1;
4657 err
= b43_pio_init(dev
);
4659 dev
->__using_pio_transfers
= 0;
4660 err
= b43_dma_init(dev
);
4665 b43_set_synth_pu_delay(dev
, 1);
4666 b43_bluetooth_coext_enable(dev
);
4668 b43_bus_powerup(dev
, !(sprom
->boardflags_lo
& B43_BFL_XTAL_NOSLOW
));
4669 b43_upload_card_macaddress(dev
);
4670 b43_security_init(dev
);
4672 ieee80211_wake_queues(dev
->wl
->hw
);
4674 b43_set_status(dev
, B43_STAT_INITIALIZED
);
4676 /* Register HW RNG driver */
4677 b43_rng_init(dev
->wl
);
4685 b43_bus_may_powerdown(dev
);
4686 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
4690 static int b43_op_add_interface(struct ieee80211_hw
*hw
,
4691 struct ieee80211_vif
*vif
)
4693 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4694 struct b43_wldev
*dev
;
4695 int err
= -EOPNOTSUPP
;
4697 /* TODO: allow WDS/AP devices to coexist */
4699 if (vif
->type
!= NL80211_IFTYPE_AP
&&
4700 vif
->type
!= NL80211_IFTYPE_MESH_POINT
&&
4701 vif
->type
!= NL80211_IFTYPE_STATION
&&
4702 vif
->type
!= NL80211_IFTYPE_WDS
&&
4703 vif
->type
!= NL80211_IFTYPE_ADHOC
)
4706 mutex_lock(&wl
->mutex
);
4708 goto out_mutex_unlock
;
4710 b43dbg(wl
, "Adding Interface type %d\n", vif
->type
);
4712 dev
= wl
->current_dev
;
4715 wl
->if_type
= vif
->type
;
4716 memcpy(wl
->mac_addr
, vif
->addr
, ETH_ALEN
);
4718 b43_adjust_opmode(dev
);
4719 b43_set_pretbtt(dev
);
4720 b43_set_synth_pu_delay(dev
, 0);
4721 b43_upload_card_macaddress(dev
);
4725 mutex_unlock(&wl
->mutex
);
4728 b43_op_bss_info_changed(hw
, vif
, &vif
->bss_conf
, ~0);
4733 static void b43_op_remove_interface(struct ieee80211_hw
*hw
,
4734 struct ieee80211_vif
*vif
)
4736 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4737 struct b43_wldev
*dev
= wl
->current_dev
;
4739 b43dbg(wl
, "Removing Interface type %d\n", vif
->type
);
4741 mutex_lock(&wl
->mutex
);
4743 B43_WARN_ON(!wl
->operating
);
4744 B43_WARN_ON(wl
->vif
!= vif
);
4749 b43_adjust_opmode(dev
);
4750 memset(wl
->mac_addr
, 0, ETH_ALEN
);
4751 b43_upload_card_macaddress(dev
);
4753 mutex_unlock(&wl
->mutex
);
4756 static int b43_op_start(struct ieee80211_hw
*hw
)
4758 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4759 struct b43_wldev
*dev
= wl
->current_dev
;
4763 /* Kill all old instance specific information to make sure
4764 * the card won't use it in the short timeframe between start
4765 * and mac80211 reconfiguring it. */
4766 memset(wl
->bssid
, 0, ETH_ALEN
);
4767 memset(wl
->mac_addr
, 0, ETH_ALEN
);
4768 wl
->filter_flags
= 0;
4769 wl
->radiotap_enabled
= 0;
4771 wl
->beacon0_uploaded
= 0;
4772 wl
->beacon1_uploaded
= 0;
4773 wl
->beacon_templates_virgin
= 1;
4774 wl
->radio_enabled
= 1;
4776 mutex_lock(&wl
->mutex
);
4778 if (b43_status(dev
) < B43_STAT_INITIALIZED
) {
4779 err
= b43_wireless_core_init(dev
);
4781 goto out_mutex_unlock
;
4785 if (b43_status(dev
) < B43_STAT_STARTED
) {
4786 err
= b43_wireless_core_start(dev
);
4789 b43_wireless_core_exit(dev
);
4790 goto out_mutex_unlock
;
4794 /* XXX: only do if device doesn't support rfkill irq */
4795 wiphy_rfkill_start_polling(hw
->wiphy
);
4798 mutex_unlock(&wl
->mutex
);
4800 /* reload configuration */
4801 b43_op_config(hw
, ~0);
4806 static void b43_op_stop(struct ieee80211_hw
*hw
)
4808 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4809 struct b43_wldev
*dev
= wl
->current_dev
;
4811 cancel_work_sync(&(wl
->beacon_update_trigger
));
4813 mutex_lock(&wl
->mutex
);
4814 if (b43_status(dev
) >= B43_STAT_STARTED
) {
4815 dev
= b43_wireless_core_stop(dev
);
4819 b43_wireless_core_exit(dev
);
4820 wl
->radio_enabled
= 0;
4823 mutex_unlock(&wl
->mutex
);
4825 cancel_work_sync(&(wl
->txpower_adjust_work
));
4828 static int b43_op_beacon_set_tim(struct ieee80211_hw
*hw
,
4829 struct ieee80211_sta
*sta
, bool set
)
4831 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4833 /* FIXME: add locking */
4834 b43_update_templates(wl
);
4839 static void b43_op_sta_notify(struct ieee80211_hw
*hw
,
4840 struct ieee80211_vif
*vif
,
4841 enum sta_notify_cmd notify_cmd
,
4842 struct ieee80211_sta
*sta
)
4844 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4846 B43_WARN_ON(!vif
|| wl
->vif
!= vif
);
4849 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw
*hw
)
4851 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4852 struct b43_wldev
*dev
;
4854 mutex_lock(&wl
->mutex
);
4855 dev
= wl
->current_dev
;
4856 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
)) {
4857 /* Disable CFP update during scan on other channels. */
4858 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_SKCFPUP
);
4860 mutex_unlock(&wl
->mutex
);
4863 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw
*hw
)
4865 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4866 struct b43_wldev
*dev
;
4868 mutex_lock(&wl
->mutex
);
4869 dev
= wl
->current_dev
;
4870 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
)) {
4871 /* Re-enable CFP update. */
4872 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_SKCFPUP
);
4874 mutex_unlock(&wl
->mutex
);
4877 static int b43_op_get_survey(struct ieee80211_hw
*hw
, int idx
,
4878 struct survey_info
*survey
)
4880 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4881 struct b43_wldev
*dev
= wl
->current_dev
;
4882 struct ieee80211_conf
*conf
= &hw
->conf
;
4887 survey
->channel
= conf
->channel
;
4888 survey
->filled
= SURVEY_INFO_NOISE_DBM
;
4889 survey
->noise
= dev
->stats
.link_noise
;
4894 static const struct ieee80211_ops b43_hw_ops
= {
4896 .conf_tx
= b43_op_conf_tx
,
4897 .add_interface
= b43_op_add_interface
,
4898 .remove_interface
= b43_op_remove_interface
,
4899 .config
= b43_op_config
,
4900 .bss_info_changed
= b43_op_bss_info_changed
,
4901 .configure_filter
= b43_op_configure_filter
,
4902 .set_key
= b43_op_set_key
,
4903 .update_tkip_key
= b43_op_update_tkip_key
,
4904 .get_stats
= b43_op_get_stats
,
4905 .get_tsf
= b43_op_get_tsf
,
4906 .set_tsf
= b43_op_set_tsf
,
4907 .start
= b43_op_start
,
4908 .stop
= b43_op_stop
,
4909 .set_tim
= b43_op_beacon_set_tim
,
4910 .sta_notify
= b43_op_sta_notify
,
4911 .sw_scan_start
= b43_op_sw_scan_start_notifier
,
4912 .sw_scan_complete
= b43_op_sw_scan_complete_notifier
,
4913 .get_survey
= b43_op_get_survey
,
4914 .rfkill_poll
= b43_rfkill_poll
,
4917 /* Hard-reset the chip. Do not call this directly.
4918 * Use b43_controller_restart()
4920 static void b43_chip_reset(struct work_struct
*work
)
4922 struct b43_wldev
*dev
=
4923 container_of(work
, struct b43_wldev
, restart_work
);
4924 struct b43_wl
*wl
= dev
->wl
;
4928 mutex_lock(&wl
->mutex
);
4930 prev_status
= b43_status(dev
);
4931 /* Bring the device down... */
4932 if (prev_status
>= B43_STAT_STARTED
) {
4933 dev
= b43_wireless_core_stop(dev
);
4939 if (prev_status
>= B43_STAT_INITIALIZED
)
4940 b43_wireless_core_exit(dev
);
4942 /* ...and up again. */
4943 if (prev_status
>= B43_STAT_INITIALIZED
) {
4944 err
= b43_wireless_core_init(dev
);
4948 if (prev_status
>= B43_STAT_STARTED
) {
4949 err
= b43_wireless_core_start(dev
);
4951 b43_wireless_core_exit(dev
);
4957 wl
->current_dev
= NULL
; /* Failed to init the dev. */
4958 mutex_unlock(&wl
->mutex
);
4961 b43err(wl
, "Controller restart FAILED\n");
4965 /* reload configuration */
4966 b43_op_config(wl
->hw
, ~0);
4968 b43_op_bss_info_changed(wl
->hw
, wl
->vif
, &wl
->vif
->bss_conf
, ~0);
4970 b43info(wl
, "Controller restarted\n");
4973 static int b43_setup_bands(struct b43_wldev
*dev
,
4974 bool have_2ghz_phy
, bool have_5ghz_phy
)
4976 struct ieee80211_hw
*hw
= dev
->wl
->hw
;
4979 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = &b43_band_2GHz
;
4980 if (dev
->phy
.type
== B43_PHYTYPE_N
) {
4982 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = &b43_band_5GHz_nphy
;
4985 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = &b43_band_5GHz_aphy
;
4988 dev
->phy
.supports_2ghz
= have_2ghz_phy
;
4989 dev
->phy
.supports_5ghz
= have_5ghz_phy
;
4994 static void b43_wireless_core_detach(struct b43_wldev
*dev
)
4996 /* We release firmware that late to not be required to re-request
4997 * is all the time when we reinit the core. */
4998 b43_release_firmware(dev
);
5002 static int b43_wireless_core_attach(struct b43_wldev
*dev
)
5004 struct b43_wl
*wl
= dev
->wl
;
5005 struct pci_dev
*pdev
= NULL
;
5008 bool have_2ghz_phy
= 0, have_5ghz_phy
= 0;
5010 /* Do NOT do any device initialization here.
5011 * Do it in wireless_core_init() instead.
5012 * This function is for gathering basic information about the HW, only.
5013 * Also some structs may be set up here. But most likely you want to have
5014 * that in core_init(), too.
5017 #ifdef CONFIG_B43_SSB
5018 if (dev
->dev
->bus_type
== B43_BUS_SSB
&&
5019 dev
->dev
->sdev
->bus
->bustype
== SSB_BUSTYPE_PCI
)
5020 pdev
= dev
->dev
->sdev
->bus
->host_pci
;
5023 err
= b43_bus_powerup(dev
, 0);
5025 b43err(wl
, "Bus powerup failed\n");
5029 /* Get the PHY type. */
5030 switch (dev
->dev
->bus_type
) {
5031 #ifdef CONFIG_B43_BCMA
5033 tmp
= bcma_aread32(dev
->dev
->bdev
, BCMA_IOST
);
5034 have_2ghz_phy
= !!(tmp
& B43_BCMA_IOST_2G_PHY
);
5035 have_5ghz_phy
= !!(tmp
& B43_BCMA_IOST_5G_PHY
);
5038 #ifdef CONFIG_B43_SSB
5040 if (dev
->dev
->core_rev
>= 5) {
5041 tmp
= ssb_read32(dev
->dev
->sdev
, SSB_TMSHIGH
);
5042 have_2ghz_phy
= !!(tmp
& B43_TMSHIGH_HAVE_2GHZ_PHY
);
5043 have_5ghz_phy
= !!(tmp
& B43_TMSHIGH_HAVE_5GHZ_PHY
);
5050 dev
->phy
.gmode
= have_2ghz_phy
;
5051 dev
->phy
.radio_on
= 1;
5052 b43_wireless_core_reset(dev
, dev
->phy
.gmode
);
5054 err
= b43_phy_versioning(dev
);
5057 /* Check if this device supports multiband. */
5059 (pdev
->device
!= 0x4312 &&
5060 pdev
->device
!= 0x4319 && pdev
->device
!= 0x4324)) {
5061 /* No multiband support. */
5064 switch (dev
->phy
.type
) {
5068 case B43_PHYTYPE_LP
: //FIXME not always!
5069 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
5074 case B43_PHYTYPE_HT
:
5075 case B43_PHYTYPE_LCN
:
5082 if (dev
->phy
.type
== B43_PHYTYPE_A
) {
5084 b43err(wl
, "IEEE 802.11a devices are unsupported\n");
5088 if (1 /* disable A-PHY */) {
5089 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
5090 if (dev
->phy
.type
!= B43_PHYTYPE_N
&&
5091 dev
->phy
.type
!= B43_PHYTYPE_LP
) {
5097 err
= b43_phy_allocate(dev
);
5101 dev
->phy
.gmode
= have_2ghz_phy
;
5102 b43_wireless_core_reset(dev
, dev
->phy
.gmode
);
5104 err
= b43_validate_chipaccess(dev
);
5107 err
= b43_setup_bands(dev
, have_2ghz_phy
, have_5ghz_phy
);
5111 /* Now set some default "current_dev" */
5112 if (!wl
->current_dev
)
5113 wl
->current_dev
= dev
;
5114 INIT_WORK(&dev
->restart_work
, b43_chip_reset
);
5116 dev
->phy
.ops
->switch_analog(dev
, 0);
5117 b43_device_disable(dev
, 0);
5118 b43_bus_may_powerdown(dev
);
5126 b43_bus_may_powerdown(dev
);
5130 static void b43_one_core_detach(struct b43_bus_dev
*dev
)
5132 struct b43_wldev
*wldev
;
5135 /* Do not cancel ieee80211-workqueue based work here.
5136 * See comment in b43_remove(). */
5138 wldev
= b43_bus_get_wldev(dev
);
5140 b43_debugfs_remove_device(wldev
);
5141 b43_wireless_core_detach(wldev
);
5142 list_del(&wldev
->list
);
5144 b43_bus_set_wldev(dev
, NULL
);
5148 static int b43_one_core_attach(struct b43_bus_dev
*dev
, struct b43_wl
*wl
)
5150 struct b43_wldev
*wldev
;
5153 wldev
= kzalloc(sizeof(*wldev
), GFP_KERNEL
);
5157 wldev
->use_pio
= b43_modparam_pio
;
5160 b43_set_status(wldev
, B43_STAT_UNINIT
);
5161 wldev
->bad_frames_preempt
= modparam_bad_frames_preempt
;
5162 INIT_LIST_HEAD(&wldev
->list
);
5164 err
= b43_wireless_core_attach(wldev
);
5166 goto err_kfree_wldev
;
5168 list_add(&wldev
->list
, &wl
->devlist
);
5170 b43_bus_set_wldev(dev
, wldev
);
5171 b43_debugfs_add_device(wldev
);
5181 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5182 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5183 (pdev->device == _device) && \
5184 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5185 (pdev->subsystem_device == _subdevice) )
5187 static void b43_sprom_fixup(struct ssb_bus
*bus
)
5189 struct pci_dev
*pdev
;
5191 /* boardflags workarounds */
5192 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_DELL
&&
5193 bus
->chip_id
== 0x4301 && bus
->boardinfo
.rev
== 0x74)
5194 bus
->sprom
.boardflags_lo
|= B43_BFL_BTCOEXIST
;
5195 if (bus
->boardinfo
.vendor
== PCI_VENDOR_ID_APPLE
&&
5196 bus
->boardinfo
.type
== 0x4E && bus
->boardinfo
.rev
> 0x40)
5197 bus
->sprom
.boardflags_lo
|= B43_BFL_PACTRL
;
5198 if (bus
->bustype
== SSB_BUSTYPE_PCI
) {
5199 pdev
= bus
->host_pci
;
5200 if (IS_PDEV(pdev
, BROADCOM
, 0x4318, ASUSTEK
, 0x100F) ||
5201 IS_PDEV(pdev
, BROADCOM
, 0x4320, DELL
, 0x0003) ||
5202 IS_PDEV(pdev
, BROADCOM
, 0x4320, HP
, 0x12f8) ||
5203 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0015) ||
5204 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0014) ||
5205 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0013) ||
5206 IS_PDEV(pdev
, BROADCOM
, 0x4320, MOTOROLA
, 0x7010))
5207 bus
->sprom
.boardflags_lo
&= ~B43_BFL_BTCOEXIST
;
5211 static void b43_wireless_exit(struct b43_bus_dev
*dev
, struct b43_wl
*wl
)
5213 struct ieee80211_hw
*hw
= wl
->hw
;
5215 ssb_set_devtypedata(dev
->sdev
, NULL
);
5216 ieee80211_free_hw(hw
);
5219 static struct b43_wl
*b43_wireless_init(struct b43_bus_dev
*dev
)
5221 struct ssb_sprom
*sprom
= dev
->bus_sprom
;
5222 struct ieee80211_hw
*hw
;
5226 hw
= ieee80211_alloc_hw(sizeof(*wl
), &b43_hw_ops
);
5228 b43err(NULL
, "Could not allocate ieee80211 device\n");
5229 return ERR_PTR(-ENOMEM
);
5231 wl
= hw_to_b43_wl(hw
);
5234 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
5235 IEEE80211_HW_SIGNAL_DBM
;
5237 hw
->wiphy
->interface_modes
=
5238 BIT(NL80211_IFTYPE_AP
) |
5239 BIT(NL80211_IFTYPE_MESH_POINT
) |
5240 BIT(NL80211_IFTYPE_STATION
) |
5241 BIT(NL80211_IFTYPE_WDS
) |
5242 BIT(NL80211_IFTYPE_ADHOC
);
5244 hw
->queues
= modparam_qos
? 4 : 1;
5245 wl
->mac80211_initially_registered_queues
= hw
->queues
;
5247 SET_IEEE80211_DEV(hw
, dev
->dev
);
5248 if (is_valid_ether_addr(sprom
->et1mac
))
5249 SET_IEEE80211_PERM_ADDR(hw
, sprom
->et1mac
);
5251 SET_IEEE80211_PERM_ADDR(hw
, sprom
->il0mac
);
5253 /* Initialize struct b43_wl */
5255 mutex_init(&wl
->mutex
);
5256 spin_lock_init(&wl
->hardirq_lock
);
5257 INIT_LIST_HEAD(&wl
->devlist
);
5258 INIT_WORK(&wl
->beacon_update_trigger
, b43_beacon_update_trigger_work
);
5259 INIT_WORK(&wl
->txpower_adjust_work
, b43_phy_txpower_adjust_work
);
5260 INIT_WORK(&wl
->tx_work
, b43_tx_work
);
5261 skb_queue_head_init(&wl
->tx_queue
);
5263 snprintf(chip_name
, ARRAY_SIZE(chip_name
),
5264 (dev
->chip_id
> 0x9999) ? "%d" : "%04X", dev
->chip_id
);
5265 b43info(wl
, "Broadcom %s WLAN found (core revision %u)\n", chip_name
,
5270 #ifdef CONFIG_B43_BCMA
5271 static int b43_bcma_probe(struct bcma_device
*core
)
5273 struct b43_bus_dev
*dev
;
5277 dev
= b43_bus_dev_bcma_init(core
);
5281 wl
= b43_wireless_init(dev
);
5287 err
= b43_one_core_attach(dev
, wl
);
5289 goto bcma_err_wireless_exit
;
5291 err
= ieee80211_register_hw(wl
->hw
);
5293 goto bcma_err_one_core_detach
;
5294 b43_leds_register(wl
->current_dev
);
5299 bcma_err_one_core_detach
:
5300 b43_one_core_detach(dev
);
5301 bcma_err_wireless_exit
:
5302 ieee80211_free_hw(wl
->hw
);
5306 static void b43_bcma_remove(struct bcma_device
*core
)
5308 struct b43_wldev
*wldev
= bcma_get_drvdata(core
);
5309 struct b43_wl
*wl
= wldev
->wl
;
5311 /* We must cancel any work here before unregistering from ieee80211,
5312 * as the ieee80211 unreg will destroy the workqueue. */
5313 cancel_work_sync(&wldev
->restart_work
);
5315 /* Restore the queues count before unregistering, because firmware detect
5316 * might have modified it. Restoring is important, so the networking
5317 * stack can properly free resources. */
5318 wl
->hw
->queues
= wl
->mac80211_initially_registered_queues
;
5319 b43_leds_stop(wldev
);
5320 ieee80211_unregister_hw(wl
->hw
);
5322 b43_one_core_detach(wldev
->dev
);
5324 b43_leds_unregister(wl
);
5326 ieee80211_free_hw(wl
->hw
);
5329 static struct bcma_driver b43_bcma_driver
= {
5330 .name
= KBUILD_MODNAME
,
5331 .id_table
= b43_bcma_tbl
,
5332 .probe
= b43_bcma_probe
,
5333 .remove
= b43_bcma_remove
,
5337 #ifdef CONFIG_B43_SSB
5339 int b43_ssb_probe(struct ssb_device
*sdev
, const struct ssb_device_id
*id
)
5341 struct b43_bus_dev
*dev
;
5346 dev
= b43_bus_dev_ssb_init(sdev
);
5350 wl
= ssb_get_devtypedata(sdev
);
5352 /* Probing the first core. Must setup common struct b43_wl */
5354 b43_sprom_fixup(sdev
->bus
);
5355 wl
= b43_wireless_init(dev
);
5360 ssb_set_devtypedata(sdev
, wl
);
5361 B43_WARN_ON(ssb_get_devtypedata(sdev
) != wl
);
5363 err
= b43_one_core_attach(dev
, wl
);
5365 goto err_wireless_exit
;
5368 err
= ieee80211_register_hw(wl
->hw
);
5370 goto err_one_core_detach
;
5371 b43_leds_register(wl
->current_dev
);
5377 err_one_core_detach
:
5378 b43_one_core_detach(dev
);
5381 b43_wireless_exit(dev
, wl
);
5385 static void b43_ssb_remove(struct ssb_device
*sdev
)
5387 struct b43_wl
*wl
= ssb_get_devtypedata(sdev
);
5388 struct b43_wldev
*wldev
= ssb_get_drvdata(sdev
);
5389 struct b43_bus_dev
*dev
= wldev
->dev
;
5391 /* We must cancel any work here before unregistering from ieee80211,
5392 * as the ieee80211 unreg will destroy the workqueue. */
5393 cancel_work_sync(&wldev
->restart_work
);
5396 if (wl
->current_dev
== wldev
) {
5397 /* Restore the queues count before unregistering, because firmware detect
5398 * might have modified it. Restoring is important, so the networking
5399 * stack can properly free resources. */
5400 wl
->hw
->queues
= wl
->mac80211_initially_registered_queues
;
5401 b43_leds_stop(wldev
);
5402 ieee80211_unregister_hw(wl
->hw
);
5405 b43_one_core_detach(dev
);
5407 if (list_empty(&wl
->devlist
)) {
5408 b43_leds_unregister(wl
);
5409 /* Last core on the chip unregistered.
5410 * We can destroy common struct b43_wl.
5412 b43_wireless_exit(dev
, wl
);
5416 static struct ssb_driver b43_ssb_driver
= {
5417 .name
= KBUILD_MODNAME
,
5418 .id_table
= b43_ssb_tbl
,
5419 .probe
= b43_ssb_probe
,
5420 .remove
= b43_ssb_remove
,
5422 #endif /* CONFIG_B43_SSB */
5424 /* Perform a hardware reset. This can be called from any context. */
5425 void b43_controller_restart(struct b43_wldev
*dev
, const char *reason
)
5427 /* Must avoid requeueing, if we are in shutdown. */
5428 if (b43_status(dev
) < B43_STAT_INITIALIZED
)
5430 b43info(dev
->wl
, "Controller RESET (%s) ...\n", reason
);
5431 ieee80211_queue_work(dev
->wl
->hw
, &dev
->restart_work
);
5434 static void b43_print_driverinfo(void)
5436 const char *feat_pci
= "", *feat_pcmcia
= "", *feat_nphy
= "",
5437 *feat_leds
= "", *feat_sdio
= "";
5439 #ifdef CONFIG_B43_PCI_AUTOSELECT
5442 #ifdef CONFIG_B43_PCMCIA
5445 #ifdef CONFIG_B43_PHY_N
5448 #ifdef CONFIG_B43_LEDS
5451 #ifdef CONFIG_B43_SDIO
5454 printk(KERN_INFO
"Broadcom 43xx driver loaded "
5455 "[ Features: %s%s%s%s%s, Firmware-ID: "
5456 B43_SUPPORTED_FIRMWARE_ID
" ]\n",
5457 feat_pci
, feat_pcmcia
, feat_nphy
,
5458 feat_leds
, feat_sdio
);
5461 static int __init
b43_init(void)
5466 err
= b43_pcmcia_init();
5469 err
= b43_sdio_init();
5471 goto err_pcmcia_exit
;
5472 #ifdef CONFIG_B43_BCMA
5473 err
= bcma_driver_register(&b43_bcma_driver
);
5477 #ifdef CONFIG_B43_SSB
5478 err
= ssb_driver_register(&b43_ssb_driver
);
5480 goto err_bcma_driver_exit
;
5482 b43_print_driverinfo();
5486 #ifdef CONFIG_B43_SSB
5487 err_bcma_driver_exit
:
5489 #ifdef CONFIG_B43_BCMA
5490 bcma_driver_unregister(&b43_bcma_driver
);
5501 static void __exit
b43_exit(void)
5503 #ifdef CONFIG_B43_SSB
5504 ssb_driver_unregister(&b43_ssb_driver
);
5506 #ifdef CONFIG_B43_BCMA
5507 bcma_driver_unregister(&b43_bcma_driver
);
5514 module_init(b43_init
)
5515 module_exit(b43_exit
)