3 Broadcom B43 wireless driver
4 IEEE 802.11g PHY driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
31 #include "phy_common.h"
35 #include <linux/bitrev.h>
38 static const s8 b43_tssi2dbm_g_table
[] = {
57 const u8 b43_radio_channel_codes_bg
[] = {
65 static void b43_calc_nrssi_threshold(struct b43_wldev
*dev
);
68 #define bitrev4(tmp) (bitrev8(tmp) >> 4)
71 /* Get the freq, as it has to be written to the device. */
72 static inline u16
channel2freq_bg(u8 channel
)
74 B43_WARN_ON(!(channel
>= 1 && channel
<= 14));
76 return b43_radio_channel_codes_bg
[channel
- 1];
79 static void generate_rfatt_list(struct b43_wldev
*dev
,
80 struct b43_rfatt_list
*list
)
82 struct b43_phy
*phy
= &dev
->phy
;
84 /* APHY.rev < 5 || GPHY.rev < 6 */
85 static const struct b43_rfatt rfatt_0
[] = {
86 {.att
= 3,.with_padmix
= 0,},
87 {.att
= 1,.with_padmix
= 0,},
88 {.att
= 5,.with_padmix
= 0,},
89 {.att
= 7,.with_padmix
= 0,},
90 {.att
= 9,.with_padmix
= 0,},
91 {.att
= 2,.with_padmix
= 0,},
92 {.att
= 0,.with_padmix
= 0,},
93 {.att
= 4,.with_padmix
= 0,},
94 {.att
= 6,.with_padmix
= 0,},
95 {.att
= 8,.with_padmix
= 0,},
96 {.att
= 1,.with_padmix
= 1,},
97 {.att
= 2,.with_padmix
= 1,},
98 {.att
= 3,.with_padmix
= 1,},
99 {.att
= 4,.with_padmix
= 1,},
101 /* Radio.rev == 8 && Radio.version == 0x2050 */
102 static const struct b43_rfatt rfatt_1
[] = {
103 {.att
= 2,.with_padmix
= 1,},
104 {.att
= 4,.with_padmix
= 1,},
105 {.att
= 6,.with_padmix
= 1,},
106 {.att
= 8,.with_padmix
= 1,},
107 {.att
= 10,.with_padmix
= 1,},
108 {.att
= 12,.with_padmix
= 1,},
109 {.att
= 14,.with_padmix
= 1,},
112 static const struct b43_rfatt rfatt_2
[] = {
113 {.att
= 0,.with_padmix
= 1,},
114 {.att
= 2,.with_padmix
= 1,},
115 {.att
= 4,.with_padmix
= 1,},
116 {.att
= 6,.with_padmix
= 1,},
117 {.att
= 8,.with_padmix
= 1,},
118 {.att
= 9,.with_padmix
= 1,},
119 {.att
= 9,.with_padmix
= 1,},
122 if (!b43_has_hardware_pctl(dev
)) {
124 list
->list
= rfatt_0
;
125 list
->len
= ARRAY_SIZE(rfatt_0
);
130 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
== 8) {
132 list
->list
= rfatt_1
;
133 list
->len
= ARRAY_SIZE(rfatt_1
);
139 list
->list
= rfatt_2
;
140 list
->len
= ARRAY_SIZE(rfatt_2
);
145 static void generate_bbatt_list(struct b43_wldev
*dev
,
146 struct b43_bbatt_list
*list
)
148 static const struct b43_bbatt bbatt_0
[] = {
160 list
->list
= bbatt_0
;
161 list
->len
= ARRAY_SIZE(bbatt_0
);
166 static void b43_shm_clear_tssi(struct b43_wldev
*dev
)
168 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0058, 0x7F7F);
169 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x005a, 0x7F7F);
170 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0070, 0x7F7F);
171 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0072, 0x7F7F);
174 /* Synthetic PU workaround */
175 static void b43_synth_pu_workaround(struct b43_wldev
*dev
, u8 channel
)
177 struct b43_phy
*phy
= &dev
->phy
;
181 if (phy
->radio_ver
!= 0x2050 || phy
->radio_rev
>= 6) {
182 /* We do not need the workaround. */
187 b43_write16(dev
, B43_MMIO_CHANNEL
,
188 channel2freq_bg(channel
+ 4));
190 b43_write16(dev
, B43_MMIO_CHANNEL
, channel2freq_bg(1));
193 b43_write16(dev
, B43_MMIO_CHANNEL
, channel2freq_bg(channel
));
196 /* Set the baseband attenuation value on chip. */
197 void b43_gphy_set_baseband_attenuation(struct b43_wldev
*dev
,
198 u16 baseband_attenuation
)
200 struct b43_phy
*phy
= &dev
->phy
;
202 if (phy
->analog
== 0) {
203 b43_write16(dev
, B43_MMIO_PHY0
, (b43_read16(dev
, B43_MMIO_PHY0
)
205 baseband_attenuation
);
206 } else if (phy
->analog
> 1) {
207 b43_phy_write(dev
, B43_PHY_DACCTL
,
208 (b43_phy_read(dev
, B43_PHY_DACCTL
)
209 & 0xFFC3) | (baseband_attenuation
<< 2));
211 b43_phy_write(dev
, B43_PHY_DACCTL
,
212 (b43_phy_read(dev
, B43_PHY_DACCTL
)
213 & 0xFF87) | (baseband_attenuation
<< 3));
217 /* Adjust the transmission power output (G-PHY) */
218 void b43_set_txpower_g(struct b43_wldev
*dev
,
219 const struct b43_bbatt
*bbatt
,
220 const struct b43_rfatt
*rfatt
, u8 tx_control
)
222 struct b43_phy
*phy
= &dev
->phy
;
223 struct b43_phy_g
*gphy
= phy
->g
;
224 struct b43_txpower_lo_control
*lo
= gphy
->lo_control
;
226 u16 tx_bias
, tx_magn
;
230 tx_bias
= lo
->tx_bias
;
231 tx_magn
= lo
->tx_magn
;
232 if (unlikely(tx_bias
== 0xFF))
235 /* Save the values for later. Use memmove, because it's valid
236 * to pass &gphy->rfatt as rfatt pointer argument. Same for bbatt. */
237 gphy
->tx_control
= tx_control
;
238 memmove(&gphy
->rfatt
, rfatt
, sizeof(*rfatt
));
239 gphy
->rfatt
.with_padmix
= !!(tx_control
& B43_TXCTL_TXMIX
);
240 memmove(&gphy
->bbatt
, bbatt
, sizeof(*bbatt
));
242 if (b43_debug(dev
, B43_DBG_XMITPOWER
)) {
243 b43dbg(dev
->wl
, "Tuning TX-power to bbatt(%u), "
244 "rfatt(%u), tx_control(0x%02X), "
245 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
246 bb
, rf
, tx_control
, tx_bias
, tx_magn
);
249 b43_gphy_set_baseband_attenuation(dev
, bb
);
250 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_RFATT
, rf
);
251 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
== 8) {
252 b43_radio_write16(dev
, 0x43,
253 (rf
& 0x000F) | (tx_control
& 0x0070));
255 b43_radio_write16(dev
, 0x43, (b43_radio_read16(dev
, 0x43)
256 & 0xFFF0) | (rf
& 0x000F));
257 b43_radio_write16(dev
, 0x52, (b43_radio_read16(dev
, 0x52)
258 & ~0x0070) | (tx_control
&
261 if (has_tx_magnification(phy
)) {
262 b43_radio_write16(dev
, 0x52, tx_magn
| tx_bias
);
264 b43_radio_write16(dev
, 0x52, (b43_radio_read16(dev
, 0x52)
265 & 0xFFF0) | (tx_bias
& 0x000F));
267 b43_lo_g_adjust(dev
);
270 /* GPHY_TSSI_Power_Lookup_Table_Init */
271 static void b43_gphy_tssi_power_lt_init(struct b43_wldev
*dev
)
273 struct b43_phy_g
*gphy
= dev
->phy
.g
;
277 for (i
= 0; i
< 32; i
++)
278 b43_ofdmtab_write16(dev
, 0x3C20, i
, gphy
->tssi2dbm
[i
]);
279 for (i
= 32; i
< 64; i
++)
280 b43_ofdmtab_write16(dev
, 0x3C00, i
- 32, gphy
->tssi2dbm
[i
]);
281 for (i
= 0; i
< 64; i
+= 2) {
282 value
= (u16
) gphy
->tssi2dbm
[i
];
283 value
|= ((u16
) gphy
->tssi2dbm
[i
+ 1]) << 8;
284 b43_phy_write(dev
, 0x380 + (i
/ 2), value
);
288 /* GPHY_Gain_Lookup_Table_Init */
289 static void b43_gphy_gain_lt_init(struct b43_wldev
*dev
)
291 struct b43_phy
*phy
= &dev
->phy
;
292 struct b43_phy_g
*gphy
= phy
->g
;
293 struct b43_txpower_lo_control
*lo
= gphy
->lo_control
;
298 for (rf
= 0; rf
< lo
->rfatt_list
.len
; rf
++) {
299 for (bb
= 0; bb
< lo
->bbatt_list
.len
; bb
++) {
300 if (nr_written
>= 0x40)
302 tmp
= lo
->bbatt_list
.list
[bb
].att
;
304 if (phy
->radio_rev
== 8)
308 tmp
|= lo
->rfatt_list
.list
[rf
].att
;
309 b43_phy_write(dev
, 0x3C0 + nr_written
, tmp
);
315 static void b43_set_all_gains(struct b43_wldev
*dev
,
316 s16 first
, s16 second
, s16 third
)
318 struct b43_phy
*phy
= &dev
->phy
;
320 u16 start
= 0x08, end
= 0x18;
329 table
= B43_OFDMTAB_GAINX
;
331 table
= B43_OFDMTAB_GAINX_R1
;
332 for (i
= 0; i
< 4; i
++)
333 b43_ofdmtab_write16(dev
, table
, i
, first
);
335 for (i
= start
; i
< end
; i
++)
336 b43_ofdmtab_write16(dev
, table
, i
, second
);
339 tmp
= ((u16
) third
<< 14) | ((u16
) third
<< 6);
340 b43_phy_write(dev
, 0x04A0,
341 (b43_phy_read(dev
, 0x04A0) & 0xBFBF) | tmp
);
342 b43_phy_write(dev
, 0x04A1,
343 (b43_phy_read(dev
, 0x04A1) & 0xBFBF) | tmp
);
344 b43_phy_write(dev
, 0x04A2,
345 (b43_phy_read(dev
, 0x04A2) & 0xBFBF) | tmp
);
347 b43_dummy_transmission(dev
);
350 static void b43_set_original_gains(struct b43_wldev
*dev
)
352 struct b43_phy
*phy
= &dev
->phy
;
355 u16 start
= 0x0008, end
= 0x0018;
362 table
= B43_OFDMTAB_GAINX
;
364 table
= B43_OFDMTAB_GAINX_R1
;
365 for (i
= 0; i
< 4; i
++) {
367 tmp
|= (i
& 0x0001) << 1;
368 tmp
|= (i
& 0x0002) >> 1;
370 b43_ofdmtab_write16(dev
, table
, i
, tmp
);
373 for (i
= start
; i
< end
; i
++)
374 b43_ofdmtab_write16(dev
, table
, i
, i
- start
);
376 b43_phy_write(dev
, 0x04A0,
377 (b43_phy_read(dev
, 0x04A0) & 0xBFBF) | 0x4040);
378 b43_phy_write(dev
, 0x04A1,
379 (b43_phy_read(dev
, 0x04A1) & 0xBFBF) | 0x4040);
380 b43_phy_write(dev
, 0x04A2,
381 (b43_phy_read(dev
, 0x04A2) & 0xBFBF) | 0x4000);
382 b43_dummy_transmission(dev
);
385 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
386 void b43_nrssi_hw_write(struct b43_wldev
*dev
, u16 offset
, s16 val
)
388 b43_phy_write(dev
, B43_PHY_NRSSILT_CTRL
, offset
);
390 b43_phy_write(dev
, B43_PHY_NRSSILT_DATA
, (u16
) val
);
393 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
394 s16
b43_nrssi_hw_read(struct b43_wldev
*dev
, u16 offset
)
398 b43_phy_write(dev
, B43_PHY_NRSSILT_CTRL
, offset
);
399 val
= b43_phy_read(dev
, B43_PHY_NRSSILT_DATA
);
404 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
405 void b43_nrssi_hw_update(struct b43_wldev
*dev
, u16 val
)
410 for (i
= 0; i
< 64; i
++) {
411 tmp
= b43_nrssi_hw_read(dev
, i
);
413 tmp
= clamp_val(tmp
, -32, 31);
414 b43_nrssi_hw_write(dev
, i
, tmp
);
418 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
419 void b43_nrssi_mem_update(struct b43_wldev
*dev
)
421 struct b43_phy_g
*gphy
= dev
->phy
.g
;
425 delta
= 0x1F - gphy
->nrssi
[0];
426 for (i
= 0; i
< 64; i
++) {
427 tmp
= (i
- delta
) * gphy
->nrssislope
;
430 tmp
= clamp_val(tmp
, 0, 0x3F);
431 gphy
->nrssi_lt
[i
] = tmp
;
435 static void b43_calc_nrssi_offset(struct b43_wldev
*dev
)
437 struct b43_phy
*phy
= &dev
->phy
;
438 u16 backup
[20] = { 0 };
443 backup
[0] = b43_phy_read(dev
, 0x0001);
444 backup
[1] = b43_phy_read(dev
, 0x0811);
445 backup
[2] = b43_phy_read(dev
, 0x0812);
446 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
447 backup
[3] = b43_phy_read(dev
, 0x0814);
448 backup
[4] = b43_phy_read(dev
, 0x0815);
450 backup
[5] = b43_phy_read(dev
, 0x005A);
451 backup
[6] = b43_phy_read(dev
, 0x0059);
452 backup
[7] = b43_phy_read(dev
, 0x0058);
453 backup
[8] = b43_phy_read(dev
, 0x000A);
454 backup
[9] = b43_phy_read(dev
, 0x0003);
455 backup
[10] = b43_radio_read16(dev
, 0x007A);
456 backup
[11] = b43_radio_read16(dev
, 0x0043);
458 b43_phy_write(dev
, 0x0429, b43_phy_read(dev
, 0x0429) & 0x7FFF);
459 b43_phy_write(dev
, 0x0001,
460 (b43_phy_read(dev
, 0x0001) & 0x3FFF) | 0x4000);
461 b43_phy_write(dev
, 0x0811, b43_phy_read(dev
, 0x0811) | 0x000C);
462 b43_phy_write(dev
, 0x0812,
463 (b43_phy_read(dev
, 0x0812) & 0xFFF3) | 0x0004);
464 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) & ~(0x1 | 0x2));
466 backup
[12] = b43_phy_read(dev
, 0x002E);
467 backup
[13] = b43_phy_read(dev
, 0x002F);
468 backup
[14] = b43_phy_read(dev
, 0x080F);
469 backup
[15] = b43_phy_read(dev
, 0x0810);
470 backup
[16] = b43_phy_read(dev
, 0x0801);
471 backup
[17] = b43_phy_read(dev
, 0x0060);
472 backup
[18] = b43_phy_read(dev
, 0x0014);
473 backup
[19] = b43_phy_read(dev
, 0x0478);
475 b43_phy_write(dev
, 0x002E, 0);
476 b43_phy_write(dev
, 0x002F, 0);
477 b43_phy_write(dev
, 0x080F, 0);
478 b43_phy_write(dev
, 0x0810, 0);
479 b43_phy_write(dev
, 0x0478, b43_phy_read(dev
, 0x0478) | 0x0100);
480 b43_phy_write(dev
, 0x0801, b43_phy_read(dev
, 0x0801) | 0x0040);
481 b43_phy_write(dev
, 0x0060, b43_phy_read(dev
, 0x0060) | 0x0040);
482 b43_phy_write(dev
, 0x0014, b43_phy_read(dev
, 0x0014) | 0x0200);
484 b43_radio_write16(dev
, 0x007A, b43_radio_read16(dev
, 0x007A) | 0x0070);
485 b43_radio_write16(dev
, 0x007A, b43_radio_read16(dev
, 0x007A) | 0x0080);
488 v47F
= (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) & 0x003F);
492 for (i
= 7; i
>= 4; i
--) {
493 b43_radio_write16(dev
, 0x007B, i
);
496 (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) & 0x003F);
499 if (v47F
< 31 && saved
== 0xFFFF)
505 b43_radio_write16(dev
, 0x007A,
506 b43_radio_read16(dev
, 0x007A) & 0x007F);
507 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
508 b43_phy_write(dev
, 0x0814,
509 b43_phy_read(dev
, 0x0814) | 0x0001);
510 b43_phy_write(dev
, 0x0815,
511 b43_phy_read(dev
, 0x0815) & 0xFFFE);
513 b43_phy_write(dev
, 0x0811, b43_phy_read(dev
, 0x0811) | 0x000C);
514 b43_phy_write(dev
, 0x0812, b43_phy_read(dev
, 0x0812) | 0x000C);
515 b43_phy_write(dev
, 0x0811, b43_phy_read(dev
, 0x0811) | 0x0030);
516 b43_phy_write(dev
, 0x0812, b43_phy_read(dev
, 0x0812) | 0x0030);
517 b43_phy_write(dev
, 0x005A, 0x0480);
518 b43_phy_write(dev
, 0x0059, 0x0810);
519 b43_phy_write(dev
, 0x0058, 0x000D);
521 b43_phy_write(dev
, 0x0003, 0x0122);
523 b43_phy_write(dev
, 0x000A, b43_phy_read(dev
, 0x000A)
526 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
527 b43_phy_write(dev
, 0x0814,
528 b43_phy_read(dev
, 0x0814) | 0x0004);
529 b43_phy_write(dev
, 0x0815,
530 b43_phy_read(dev
, 0x0815) & 0xFFFB);
532 b43_phy_write(dev
, 0x0003, (b43_phy_read(dev
, 0x0003) & 0xFF9F)
534 b43_radio_write16(dev
, 0x007A,
535 b43_radio_read16(dev
, 0x007A) | 0x000F);
536 b43_set_all_gains(dev
, 3, 0, 1);
537 b43_radio_write16(dev
, 0x0043, (b43_radio_read16(dev
, 0x0043)
540 v47F
= (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) & 0x003F);
544 for (i
= 0; i
< 4; i
++) {
545 b43_radio_write16(dev
, 0x007B, i
);
548 (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) &
552 if (v47F
> -31 && saved
== 0xFFFF)
560 b43_radio_write16(dev
, 0x007B, saved
);
563 b43_phy_write(dev
, 0x002E, backup
[12]);
564 b43_phy_write(dev
, 0x002F, backup
[13]);
565 b43_phy_write(dev
, 0x080F, backup
[14]);
566 b43_phy_write(dev
, 0x0810, backup
[15]);
568 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
569 b43_phy_write(dev
, 0x0814, backup
[3]);
570 b43_phy_write(dev
, 0x0815, backup
[4]);
572 b43_phy_write(dev
, 0x005A, backup
[5]);
573 b43_phy_write(dev
, 0x0059, backup
[6]);
574 b43_phy_write(dev
, 0x0058, backup
[7]);
575 b43_phy_write(dev
, 0x000A, backup
[8]);
576 b43_phy_write(dev
, 0x0003, backup
[9]);
577 b43_radio_write16(dev
, 0x0043, backup
[11]);
578 b43_radio_write16(dev
, 0x007A, backup
[10]);
579 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) | 0x1 | 0x2);
580 b43_phy_write(dev
, 0x0429, b43_phy_read(dev
, 0x0429) | 0x8000);
581 b43_set_original_gains(dev
);
583 b43_phy_write(dev
, 0x0801, backup
[16]);
584 b43_phy_write(dev
, 0x0060, backup
[17]);
585 b43_phy_write(dev
, 0x0014, backup
[18]);
586 b43_phy_write(dev
, 0x0478, backup
[19]);
588 b43_phy_write(dev
, 0x0001, backup
[0]);
589 b43_phy_write(dev
, 0x0812, backup
[2]);
590 b43_phy_write(dev
, 0x0811, backup
[1]);
593 void b43_calc_nrssi_slope(struct b43_wldev
*dev
)
595 struct b43_phy
*phy
= &dev
->phy
;
596 struct b43_phy_g
*gphy
= phy
->g
;
597 u16 backup
[18] = { 0 };
601 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
603 if (phy
->radio_rev
>= 9)
605 if (phy
->radio_rev
== 8)
606 b43_calc_nrssi_offset(dev
);
608 b43_phy_write(dev
, B43_PHY_G_CRS
,
609 b43_phy_read(dev
, B43_PHY_G_CRS
) & 0x7FFF);
610 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) & 0xFFFC);
611 backup
[7] = b43_read16(dev
, 0x03E2);
612 b43_write16(dev
, 0x03E2, b43_read16(dev
, 0x03E2) | 0x8000);
613 backup
[0] = b43_radio_read16(dev
, 0x007A);
614 backup
[1] = b43_radio_read16(dev
, 0x0052);
615 backup
[2] = b43_radio_read16(dev
, 0x0043);
616 backup
[3] = b43_phy_read(dev
, 0x0015);
617 backup
[4] = b43_phy_read(dev
, 0x005A);
618 backup
[5] = b43_phy_read(dev
, 0x0059);
619 backup
[6] = b43_phy_read(dev
, 0x0058);
620 backup
[8] = b43_read16(dev
, 0x03E6);
621 backup
[9] = b43_read16(dev
, B43_MMIO_CHANNEL_EXT
);
623 backup
[10] = b43_phy_read(dev
, 0x002E);
624 backup
[11] = b43_phy_read(dev
, 0x002F);
625 backup
[12] = b43_phy_read(dev
, 0x080F);
626 backup
[13] = b43_phy_read(dev
, B43_PHY_G_LO_CONTROL
);
627 backup
[14] = b43_phy_read(dev
, 0x0801);
628 backup
[15] = b43_phy_read(dev
, 0x0060);
629 backup
[16] = b43_phy_read(dev
, 0x0014);
630 backup
[17] = b43_phy_read(dev
, 0x0478);
631 b43_phy_write(dev
, 0x002E, 0);
632 b43_phy_write(dev
, B43_PHY_G_LO_CONTROL
, 0);
637 b43_phy_write(dev
, 0x0478,
638 b43_phy_read(dev
, 0x0478)
640 b43_phy_write(dev
, 0x0801,
641 b43_phy_read(dev
, 0x0801)
646 b43_phy_write(dev
, 0x0801,
647 b43_phy_read(dev
, 0x0801)
651 b43_phy_write(dev
, 0x0060, b43_phy_read(dev
, 0x0060)
653 b43_phy_write(dev
, 0x0014, b43_phy_read(dev
, 0x0014)
656 b43_radio_write16(dev
, 0x007A,
657 b43_radio_read16(dev
, 0x007A) | 0x0070);
658 b43_set_all_gains(dev
, 0, 8, 0);
659 b43_radio_write16(dev
, 0x007A,
660 b43_radio_read16(dev
, 0x007A) & 0x00F7);
662 b43_phy_write(dev
, 0x0811,
663 (b43_phy_read(dev
, 0x0811) & 0xFFCF) |
665 b43_phy_write(dev
, 0x0812,
666 (b43_phy_read(dev
, 0x0812) & 0xFFCF) |
669 b43_radio_write16(dev
, 0x007A,
670 b43_radio_read16(dev
, 0x007A) | 0x0080);
673 nrssi0
= (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) & 0x003F);
674 if (nrssi0
>= 0x0020)
677 b43_radio_write16(dev
, 0x007A,
678 b43_radio_read16(dev
, 0x007A) & 0x007F);
680 b43_phy_write(dev
, 0x0003, (b43_phy_read(dev
, 0x0003)
684 b43_write16(dev
, B43_MMIO_CHANNEL_EXT
,
685 b43_read16(dev
, B43_MMIO_CHANNEL_EXT
)
687 b43_radio_write16(dev
, 0x007A,
688 b43_radio_read16(dev
, 0x007A) | 0x000F);
689 b43_phy_write(dev
, 0x0015, 0xF330);
691 b43_phy_write(dev
, 0x0812,
692 (b43_phy_read(dev
, 0x0812) & 0xFFCF) |
694 b43_phy_write(dev
, 0x0811,
695 (b43_phy_read(dev
, 0x0811) & 0xFFCF) |
699 b43_set_all_gains(dev
, 3, 0, 1);
700 if (phy
->radio_rev
== 8) {
701 b43_radio_write16(dev
, 0x0043, 0x001F);
703 tmp
= b43_radio_read16(dev
, 0x0052) & 0xFF0F;
704 b43_radio_write16(dev
, 0x0052, tmp
| 0x0060);
705 tmp
= b43_radio_read16(dev
, 0x0043) & 0xFFF0;
706 b43_radio_write16(dev
, 0x0043, tmp
| 0x0009);
708 b43_phy_write(dev
, 0x005A, 0x0480);
709 b43_phy_write(dev
, 0x0059, 0x0810);
710 b43_phy_write(dev
, 0x0058, 0x000D);
712 nrssi1
= (s16
) ((b43_phy_read(dev
, 0x047F) >> 8) & 0x003F);
713 if (nrssi1
>= 0x0020)
715 if (nrssi0
== nrssi1
)
716 gphy
->nrssislope
= 0x00010000;
718 gphy
->nrssislope
= 0x00400000 / (nrssi0
- nrssi1
);
720 gphy
->nrssi
[0] = nrssi1
;
721 gphy
->nrssi
[1] = nrssi0
;
724 b43_phy_write(dev
, 0x002E, backup
[10]);
725 b43_phy_write(dev
, 0x002F, backup
[11]);
726 b43_phy_write(dev
, 0x080F, backup
[12]);
727 b43_phy_write(dev
, B43_PHY_G_LO_CONTROL
, backup
[13]);
730 b43_phy_write(dev
, 0x0812,
731 b43_phy_read(dev
, 0x0812) & 0xFFCF);
732 b43_phy_write(dev
, 0x0811,
733 b43_phy_read(dev
, 0x0811) & 0xFFCF);
736 b43_radio_write16(dev
, 0x007A, backup
[0]);
737 b43_radio_write16(dev
, 0x0052, backup
[1]);
738 b43_radio_write16(dev
, 0x0043, backup
[2]);
739 b43_write16(dev
, 0x03E2, backup
[7]);
740 b43_write16(dev
, 0x03E6, backup
[8]);
741 b43_write16(dev
, B43_MMIO_CHANNEL_EXT
, backup
[9]);
742 b43_phy_write(dev
, 0x0015, backup
[3]);
743 b43_phy_write(dev
, 0x005A, backup
[4]);
744 b43_phy_write(dev
, 0x0059, backup
[5]);
745 b43_phy_write(dev
, 0x0058, backup
[6]);
746 b43_synth_pu_workaround(dev
, phy
->channel
);
747 b43_phy_write(dev
, 0x0802,
748 b43_phy_read(dev
, 0x0802) | (0x0001 | 0x0002));
749 b43_set_original_gains(dev
);
750 b43_phy_write(dev
, B43_PHY_G_CRS
,
751 b43_phy_read(dev
, B43_PHY_G_CRS
) | 0x8000);
753 b43_phy_write(dev
, 0x0801, backup
[14]);
754 b43_phy_write(dev
, 0x0060, backup
[15]);
755 b43_phy_write(dev
, 0x0014, backup
[16]);
756 b43_phy_write(dev
, 0x0478, backup
[17]);
758 b43_nrssi_mem_update(dev
);
759 b43_calc_nrssi_threshold(dev
);
762 static void b43_calc_nrssi_threshold(struct b43_wldev
*dev
)
764 struct b43_phy
*phy
= &dev
->phy
;
765 struct b43_phy_g
*gphy
= phy
->g
;
770 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
773 !(dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_RSSI
)) {
774 tmp16
= b43_nrssi_hw_read(dev
, 0x20);
778 b43_phy_write(dev
, 0x048A,
779 (b43_phy_read(dev
, 0x048A)
782 b43_phy_write(dev
, 0x048A,
783 (b43_phy_read(dev
, 0x048A)
787 if (gphy
->interfmode
== B43_INTERFMODE_NONWLAN
) {
790 } else if (!gphy
->aci_wlan_automatic
&& gphy
->aci_enable
) {
798 a
= a
* (gphy
->nrssi
[1] - gphy
->nrssi
[0]);
799 a
+= (gphy
->nrssi
[0] << 6);
805 a
= clamp_val(a
, -31, 31);
807 b
= b
* (gphy
->nrssi
[1] - gphy
->nrssi
[0]);
808 b
+= (gphy
->nrssi
[0] << 6);
814 b
= clamp_val(b
, -31, 31);
816 tmp_u16
= b43_phy_read(dev
, 0x048A) & 0xF000;
817 tmp_u16
|= ((u32
) b
& 0x0000003F);
818 tmp_u16
|= (((u32
) a
& 0x0000003F) << 6);
819 b43_phy_write(dev
, 0x048A, tmp_u16
);
823 /* Stack implementation to save/restore values from the
824 * interference mitigation code.
825 * It is save to restore values in random order.
827 static void _stack_save(u32
* _stackptr
, size_t * stackidx
,
828 u8 id
, u16 offset
, u16 value
)
830 u32
*stackptr
= &(_stackptr
[*stackidx
]);
832 B43_WARN_ON(offset
& 0xF000);
833 B43_WARN_ON(id
& 0xF0);
835 *stackptr
|= ((u32
) id
) << 12;
836 *stackptr
|= ((u32
) value
) << 16;
838 B43_WARN_ON(*stackidx
>= B43_INTERFSTACK_SIZE
);
841 static u16
_stack_restore(u32
* stackptr
, u8 id
, u16 offset
)
845 B43_WARN_ON(offset
& 0xF000);
846 B43_WARN_ON(id
& 0xF0);
847 for (i
= 0; i
< B43_INTERFSTACK_SIZE
; i
++, stackptr
++) {
848 if ((*stackptr
& 0x00000FFF) != offset
)
850 if (((*stackptr
& 0x0000F000) >> 12) != id
)
852 return ((*stackptr
& 0xFFFF0000) >> 16);
859 #define phy_stacksave(offset) \
861 _stack_save(stack, &stackidx, 0x1, (offset), \
862 b43_phy_read(dev, (offset))); \
864 #define phy_stackrestore(offset) \
866 b43_phy_write(dev, (offset), \
867 _stack_restore(stack, 0x1, \
870 #define radio_stacksave(offset) \
872 _stack_save(stack, &stackidx, 0x2, (offset), \
873 b43_radio_read16(dev, (offset))); \
875 #define radio_stackrestore(offset) \
877 b43_radio_write16(dev, (offset), \
878 _stack_restore(stack, 0x2, \
881 #define ofdmtab_stacksave(table, offset) \
883 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
884 b43_ofdmtab_read16(dev, (table), (offset))); \
886 #define ofdmtab_stackrestore(table, offset) \
888 b43_ofdmtab_write16(dev, (table), (offset), \
889 _stack_restore(stack, 0x3, \
890 (offset)|(table))); \
894 b43_radio_interference_mitigation_enable(struct b43_wldev
*dev
, int mode
)
896 struct b43_phy
*phy
= &dev
->phy
;
897 struct b43_phy_g
*gphy
= phy
->g
;
900 u32
*stack
= gphy
->interfstack
;
903 case B43_INTERFMODE_NONWLAN
:
905 b43_phy_write(dev
, 0x042B,
906 b43_phy_read(dev
, 0x042B) | 0x0800);
907 b43_phy_write(dev
, B43_PHY_G_CRS
,
909 B43_PHY_G_CRS
) & ~0x4000);
912 radio_stacksave(0x0078);
913 tmp
= (b43_radio_read16(dev
, 0x0078) & 0x001E);
914 B43_WARN_ON(tmp
> 15);
915 flipped
= bitrev4(tmp
);
916 if (flipped
< 10 && flipped
>= 8)
918 else if (flipped
>= 10)
920 flipped
= (bitrev4(flipped
) << 1) | 0x0020;
921 b43_radio_write16(dev
, 0x0078, flipped
);
923 b43_calc_nrssi_threshold(dev
);
925 phy_stacksave(0x0406);
926 b43_phy_write(dev
, 0x0406, 0x7E28);
928 b43_phy_write(dev
, 0x042B, b43_phy_read(dev
, 0x042B) | 0x0800);
929 b43_phy_write(dev
, B43_PHY_RADIO_BITFIELD
,
931 B43_PHY_RADIO_BITFIELD
) | 0x1000);
933 phy_stacksave(0x04A0);
934 b43_phy_write(dev
, 0x04A0,
935 (b43_phy_read(dev
, 0x04A0) & 0xC0C0) | 0x0008);
936 phy_stacksave(0x04A1);
937 b43_phy_write(dev
, 0x04A1,
938 (b43_phy_read(dev
, 0x04A1) & 0xC0C0) | 0x0605);
939 phy_stacksave(0x04A2);
940 b43_phy_write(dev
, 0x04A2,
941 (b43_phy_read(dev
, 0x04A2) & 0xC0C0) | 0x0204);
942 phy_stacksave(0x04A8);
943 b43_phy_write(dev
, 0x04A8,
944 (b43_phy_read(dev
, 0x04A8) & 0xC0C0) | 0x0803);
945 phy_stacksave(0x04AB);
946 b43_phy_write(dev
, 0x04AB,
947 (b43_phy_read(dev
, 0x04AB) & 0xC0C0) | 0x0605);
949 phy_stacksave(0x04A7);
950 b43_phy_write(dev
, 0x04A7, 0x0002);
951 phy_stacksave(0x04A3);
952 b43_phy_write(dev
, 0x04A3, 0x287A);
953 phy_stacksave(0x04A9);
954 b43_phy_write(dev
, 0x04A9, 0x2027);
955 phy_stacksave(0x0493);
956 b43_phy_write(dev
, 0x0493, 0x32F5);
957 phy_stacksave(0x04AA);
958 b43_phy_write(dev
, 0x04AA, 0x2027);
959 phy_stacksave(0x04AC);
960 b43_phy_write(dev
, 0x04AC, 0x32F5);
962 case B43_INTERFMODE_MANUALWLAN
:
963 if (b43_phy_read(dev
, 0x0033) & 0x0800)
966 gphy
->aci_enable
= 1;
968 phy_stacksave(B43_PHY_RADIO_BITFIELD
);
969 phy_stacksave(B43_PHY_G_CRS
);
971 phy_stacksave(0x0406);
973 phy_stacksave(0x04C0);
974 phy_stacksave(0x04C1);
976 phy_stacksave(0x0033);
977 phy_stacksave(0x04A7);
978 phy_stacksave(0x04A3);
979 phy_stacksave(0x04A9);
980 phy_stacksave(0x04AA);
981 phy_stacksave(0x04AC);
982 phy_stacksave(0x0493);
983 phy_stacksave(0x04A1);
984 phy_stacksave(0x04A0);
985 phy_stacksave(0x04A2);
986 phy_stacksave(0x048A);
987 phy_stacksave(0x04A8);
988 phy_stacksave(0x04AB);
990 phy_stacksave(0x04AD);
991 phy_stacksave(0x04AE);
992 } else if (phy
->rev
>= 3) {
993 phy_stacksave(0x04AD);
994 phy_stacksave(0x0415);
995 phy_stacksave(0x0416);
996 phy_stacksave(0x0417);
997 ofdmtab_stacksave(0x1A00, 0x2);
998 ofdmtab_stacksave(0x1A00, 0x3);
1000 phy_stacksave(0x042B);
1001 phy_stacksave(0x048C);
1003 b43_phy_write(dev
, B43_PHY_RADIO_BITFIELD
,
1004 b43_phy_read(dev
, B43_PHY_RADIO_BITFIELD
)
1006 b43_phy_write(dev
, B43_PHY_G_CRS
,
1007 (b43_phy_read(dev
, B43_PHY_G_CRS
)
1008 & 0xFFFC) | 0x0002);
1010 b43_phy_write(dev
, 0x0033, 0x0800);
1011 b43_phy_write(dev
, 0x04A3, 0x2027);
1012 b43_phy_write(dev
, 0x04A9, 0x1CA8);
1013 b43_phy_write(dev
, 0x0493, 0x287A);
1014 b43_phy_write(dev
, 0x04AA, 0x1CA8);
1015 b43_phy_write(dev
, 0x04AC, 0x287A);
1017 b43_phy_write(dev
, 0x04A0, (b43_phy_read(dev
, 0x04A0)
1018 & 0xFFC0) | 0x001A);
1019 b43_phy_write(dev
, 0x04A7, 0x000D);
1022 b43_phy_write(dev
, 0x0406, 0xFF0D);
1023 } else if (phy
->rev
== 2) {
1024 b43_phy_write(dev
, 0x04C0, 0xFFFF);
1025 b43_phy_write(dev
, 0x04C1, 0x00A9);
1027 b43_phy_write(dev
, 0x04C0, 0x00C1);
1028 b43_phy_write(dev
, 0x04C1, 0x0059);
1031 b43_phy_write(dev
, 0x04A1, (b43_phy_read(dev
, 0x04A1)
1032 & 0xC0FF) | 0x1800);
1033 b43_phy_write(dev
, 0x04A1, (b43_phy_read(dev
, 0x04A1)
1034 & 0xFFC0) | 0x0015);
1035 b43_phy_write(dev
, 0x04A8, (b43_phy_read(dev
, 0x04A8)
1036 & 0xCFFF) | 0x1000);
1037 b43_phy_write(dev
, 0x04A8, (b43_phy_read(dev
, 0x04A8)
1038 & 0xF0FF) | 0x0A00);
1039 b43_phy_write(dev
, 0x04AB, (b43_phy_read(dev
, 0x04AB)
1040 & 0xCFFF) | 0x1000);
1041 b43_phy_write(dev
, 0x04AB, (b43_phy_read(dev
, 0x04AB)
1042 & 0xF0FF) | 0x0800);
1043 b43_phy_write(dev
, 0x04AB, (b43_phy_read(dev
, 0x04AB)
1044 & 0xFFCF) | 0x0010);
1045 b43_phy_write(dev
, 0x04AB, (b43_phy_read(dev
, 0x04AB)
1046 & 0xFFF0) | 0x0005);
1047 b43_phy_write(dev
, 0x04A8, (b43_phy_read(dev
, 0x04A8)
1048 & 0xFFCF) | 0x0010);
1049 b43_phy_write(dev
, 0x04A8, (b43_phy_read(dev
, 0x04A8)
1050 & 0xFFF0) | 0x0006);
1051 b43_phy_write(dev
, 0x04A2, (b43_phy_read(dev
, 0x04A2)
1052 & 0xF0FF) | 0x0800);
1053 b43_phy_write(dev
, 0x04A0, (b43_phy_read(dev
, 0x04A0)
1054 & 0xF0FF) | 0x0500);
1055 b43_phy_write(dev
, 0x04A2, (b43_phy_read(dev
, 0x04A2)
1056 & 0xFFF0) | 0x000B);
1058 if (phy
->rev
>= 3) {
1059 b43_phy_write(dev
, 0x048A, b43_phy_read(dev
, 0x048A)
1061 b43_phy_write(dev
, 0x0415, (b43_phy_read(dev
, 0x0415)
1062 & 0x8000) | 0x36D8);
1063 b43_phy_write(dev
, 0x0416, (b43_phy_read(dev
, 0x0416)
1064 & 0x8000) | 0x36D8);
1065 b43_phy_write(dev
, 0x0417, (b43_phy_read(dev
, 0x0417)
1066 & 0xFE00) | 0x016D);
1068 b43_phy_write(dev
, 0x048A, b43_phy_read(dev
, 0x048A)
1070 b43_phy_write(dev
, 0x048A, (b43_phy_read(dev
, 0x048A)
1071 & 0x9FFF) | 0x2000);
1072 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_ACIW
);
1074 if (phy
->rev
>= 2) {
1075 b43_phy_write(dev
, 0x042B, b43_phy_read(dev
, 0x042B)
1078 b43_phy_write(dev
, 0x048C, (b43_phy_read(dev
, 0x048C)
1079 & 0xF0FF) | 0x0200);
1080 if (phy
->rev
== 2) {
1081 b43_phy_write(dev
, 0x04AE, (b43_phy_read(dev
, 0x04AE)
1082 & 0xFF00) | 0x007F);
1083 b43_phy_write(dev
, 0x04AD, (b43_phy_read(dev
, 0x04AD)
1084 & 0x00FF) | 0x1300);
1085 } else if (phy
->rev
>= 6) {
1086 b43_ofdmtab_write16(dev
, 0x1A00, 0x3, 0x007F);
1087 b43_ofdmtab_write16(dev
, 0x1A00, 0x2, 0x007F);
1088 b43_phy_write(dev
, 0x04AD, b43_phy_read(dev
, 0x04AD)
1091 b43_calc_nrssi_slope(dev
);
1099 b43_radio_interference_mitigation_disable(struct b43_wldev
*dev
, int mode
)
1101 struct b43_phy
*phy
= &dev
->phy
;
1102 struct b43_phy_g
*gphy
= phy
->g
;
1103 u32
*stack
= gphy
->interfstack
;
1106 case B43_INTERFMODE_NONWLAN
:
1107 if (phy
->rev
!= 1) {
1108 b43_phy_write(dev
, 0x042B,
1109 b43_phy_read(dev
, 0x042B) & ~0x0800);
1110 b43_phy_write(dev
, B43_PHY_G_CRS
,
1112 B43_PHY_G_CRS
) | 0x4000);
1115 radio_stackrestore(0x0078);
1116 b43_calc_nrssi_threshold(dev
);
1117 phy_stackrestore(0x0406);
1118 b43_phy_write(dev
, 0x042B, b43_phy_read(dev
, 0x042B) & ~0x0800);
1119 if (!dev
->bad_frames_preempt
) {
1120 b43_phy_write(dev
, B43_PHY_RADIO_BITFIELD
,
1121 b43_phy_read(dev
, B43_PHY_RADIO_BITFIELD
)
1124 b43_phy_write(dev
, B43_PHY_G_CRS
,
1125 b43_phy_read(dev
, B43_PHY_G_CRS
) | 0x4000);
1126 phy_stackrestore(0x04A0);
1127 phy_stackrestore(0x04A1);
1128 phy_stackrestore(0x04A2);
1129 phy_stackrestore(0x04A8);
1130 phy_stackrestore(0x04AB);
1131 phy_stackrestore(0x04A7);
1132 phy_stackrestore(0x04A3);
1133 phy_stackrestore(0x04A9);
1134 phy_stackrestore(0x0493);
1135 phy_stackrestore(0x04AA);
1136 phy_stackrestore(0x04AC);
1138 case B43_INTERFMODE_MANUALWLAN
:
1139 if (!(b43_phy_read(dev
, 0x0033) & 0x0800))
1142 gphy
->aci_enable
= 0;
1144 phy_stackrestore(B43_PHY_RADIO_BITFIELD
);
1145 phy_stackrestore(B43_PHY_G_CRS
);
1146 phy_stackrestore(0x0033);
1147 phy_stackrestore(0x04A3);
1148 phy_stackrestore(0x04A9);
1149 phy_stackrestore(0x0493);
1150 phy_stackrestore(0x04AA);
1151 phy_stackrestore(0x04AC);
1152 phy_stackrestore(0x04A0);
1153 phy_stackrestore(0x04A7);
1154 if (phy
->rev
>= 2) {
1155 phy_stackrestore(0x04C0);
1156 phy_stackrestore(0x04C1);
1158 phy_stackrestore(0x0406);
1159 phy_stackrestore(0x04A1);
1160 phy_stackrestore(0x04AB);
1161 phy_stackrestore(0x04A8);
1162 if (phy
->rev
== 2) {
1163 phy_stackrestore(0x04AD);
1164 phy_stackrestore(0x04AE);
1165 } else if (phy
->rev
>= 3) {
1166 phy_stackrestore(0x04AD);
1167 phy_stackrestore(0x0415);
1168 phy_stackrestore(0x0416);
1169 phy_stackrestore(0x0417);
1170 ofdmtab_stackrestore(0x1A00, 0x2);
1171 ofdmtab_stackrestore(0x1A00, 0x3);
1173 phy_stackrestore(0x04A2);
1174 phy_stackrestore(0x048A);
1175 phy_stackrestore(0x042B);
1176 phy_stackrestore(0x048C);
1177 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_ACIW
);
1178 b43_calc_nrssi_slope(dev
);
1185 #undef phy_stacksave
1186 #undef phy_stackrestore
1187 #undef radio_stacksave
1188 #undef radio_stackrestore
1189 #undef ofdmtab_stacksave
1190 #undef ofdmtab_stackrestore
1192 static u16
b43_radio_core_calibration_value(struct b43_wldev
*dev
)
1194 u16 reg
, index
, ret
;
1196 static const u8 rcc_table
[] = {
1197 0x02, 0x03, 0x01, 0x0F,
1198 0x06, 0x07, 0x05, 0x0F,
1199 0x0A, 0x0B, 0x09, 0x0F,
1200 0x0E, 0x0F, 0x0D, 0x0F,
1203 reg
= b43_radio_read16(dev
, 0x60);
1204 index
= (reg
& 0x001E) >> 1;
1205 ret
= rcc_table
[index
] << 1;
1206 ret
|= (reg
& 0x0001);
1212 #define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
1213 static u16
radio2050_rfover_val(struct b43_wldev
*dev
,
1214 u16 phy_register
, unsigned int lpd
)
1216 struct b43_phy
*phy
= &dev
->phy
;
1217 struct b43_phy_g
*gphy
= phy
->g
;
1218 struct ssb_sprom
*sprom
= &(dev
->dev
->bus
->sprom
);
1223 if (has_loopback_gain(phy
)) {
1224 int max_lb_gain
= gphy
->max_lb_gain
;
1228 if (phy
->radio_rev
== 8)
1229 max_lb_gain
+= 0x3E;
1231 max_lb_gain
+= 0x26;
1232 if (max_lb_gain
>= 0x46) {
1234 max_lb_gain
-= 0x46;
1235 } else if (max_lb_gain
>= 0x3A) {
1237 max_lb_gain
-= 0x3A;
1238 } else if (max_lb_gain
>= 0x2E) {
1240 max_lb_gain
-= 0x2E;
1243 max_lb_gain
-= 0x10;
1246 for (i
= 0; i
< 16; i
++) {
1247 max_lb_gain
-= (i
* 6);
1248 if (max_lb_gain
< 6)
1252 if ((phy
->rev
< 7) ||
1253 !(sprom
->boardflags_lo
& B43_BFL_EXTLNA
)) {
1254 if (phy_register
== B43_PHY_RFOVER
) {
1256 } else if (phy_register
== B43_PHY_RFOVERVAL
) {
1263 return (0x0092 | extlna
);
1265 return (0x0093 | extlna
);
1271 if (phy_register
== B43_PHY_RFOVER
) {
1273 } else if (phy_register
== B43_PHY_RFOVERVAL
) {
1281 return (0x8092 | extlna
);
1283 return (0x2092 | extlna
);
1285 return (0x2093 | extlna
);
1292 if ((phy
->rev
< 7) ||
1293 !(sprom
->boardflags_lo
& B43_BFL_EXTLNA
)) {
1294 if (phy_register
== B43_PHY_RFOVER
) {
1296 } else if (phy_register
== B43_PHY_RFOVERVAL
) {
1311 if (phy_register
== B43_PHY_RFOVER
) {
1313 } else if (phy_register
== B43_PHY_RFOVERVAL
) {
1332 struct init2050_saved_values
{
1333 /* Core registers */
1337 /* Radio registers */
1350 u16 phy_analogoverval
;
1358 u16
b43_radio_init2050(struct b43_wldev
*dev
)
1360 struct b43_phy
*phy
= &dev
->phy
;
1361 struct init2050_saved_values sav
;
1366 u32 tmp1
= 0, tmp2
= 0;
1368 memset(&sav
, 0, sizeof(sav
)); /* get rid of "may be used uninitialized..." */
1370 sav
.radio_43
= b43_radio_read16(dev
, 0x43);
1371 sav
.radio_51
= b43_radio_read16(dev
, 0x51);
1372 sav
.radio_52
= b43_radio_read16(dev
, 0x52);
1373 sav
.phy_pgactl
= b43_phy_read(dev
, B43_PHY_PGACTL
);
1374 sav
.phy_cck_5A
= b43_phy_read(dev
, B43_PHY_CCK(0x5A));
1375 sav
.phy_cck_59
= b43_phy_read(dev
, B43_PHY_CCK(0x59));
1376 sav
.phy_cck_58
= b43_phy_read(dev
, B43_PHY_CCK(0x58));
1378 if (phy
->type
== B43_PHYTYPE_B
) {
1379 sav
.phy_cck_30
= b43_phy_read(dev
, B43_PHY_CCK(0x30));
1380 sav
.reg_3EC
= b43_read16(dev
, 0x3EC);
1382 b43_phy_write(dev
, B43_PHY_CCK(0x30), 0xFF);
1383 b43_write16(dev
, 0x3EC, 0x3F3F);
1384 } else if (phy
->gmode
|| phy
->rev
>= 2) {
1385 sav
.phy_rfover
= b43_phy_read(dev
, B43_PHY_RFOVER
);
1386 sav
.phy_rfoverval
= b43_phy_read(dev
, B43_PHY_RFOVERVAL
);
1387 sav
.phy_analogover
= b43_phy_read(dev
, B43_PHY_ANALOGOVER
);
1388 sav
.phy_analogoverval
=
1389 b43_phy_read(dev
, B43_PHY_ANALOGOVERVAL
);
1390 sav
.phy_crs0
= b43_phy_read(dev
, B43_PHY_CRS0
);
1391 sav
.phy_classctl
= b43_phy_read(dev
, B43_PHY_CLASSCTL
);
1393 b43_phy_write(dev
, B43_PHY_ANALOGOVER
,
1394 b43_phy_read(dev
, B43_PHY_ANALOGOVER
)
1396 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
,
1397 b43_phy_read(dev
, B43_PHY_ANALOGOVERVAL
)
1399 b43_phy_write(dev
, B43_PHY_CRS0
, b43_phy_read(dev
, B43_PHY_CRS0
)
1401 b43_phy_write(dev
, B43_PHY_CLASSCTL
,
1402 b43_phy_read(dev
, B43_PHY_CLASSCTL
)
1404 if (has_loopback_gain(phy
)) {
1405 sav
.phy_lo_mask
= b43_phy_read(dev
, B43_PHY_LO_MASK
);
1406 sav
.phy_lo_ctl
= b43_phy_read(dev
, B43_PHY_LO_CTL
);
1409 b43_phy_write(dev
, B43_PHY_LO_MASK
, 0xC020);
1411 b43_phy_write(dev
, B43_PHY_LO_MASK
, 0x8020);
1412 b43_phy_write(dev
, B43_PHY_LO_CTL
, 0);
1415 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1416 radio2050_rfover_val(dev
, B43_PHY_RFOVERVAL
,
1418 b43_phy_write(dev
, B43_PHY_RFOVER
,
1419 radio2050_rfover_val(dev
, B43_PHY_RFOVER
, 0));
1421 b43_write16(dev
, 0x3E2, b43_read16(dev
, 0x3E2) | 0x8000);
1423 sav
.phy_syncctl
= b43_phy_read(dev
, B43_PHY_SYNCCTL
);
1424 b43_phy_write(dev
, B43_PHY_SYNCCTL
, b43_phy_read(dev
, B43_PHY_SYNCCTL
)
1426 sav
.reg_3E6
= b43_read16(dev
, 0x3E6);
1427 sav
.reg_3F4
= b43_read16(dev
, 0x3F4);
1429 if (phy
->analog
== 0) {
1430 b43_write16(dev
, 0x03E6, 0x0122);
1432 if (phy
->analog
>= 2) {
1433 b43_phy_write(dev
, B43_PHY_CCK(0x03),
1434 (b43_phy_read(dev
, B43_PHY_CCK(0x03))
1437 b43_write16(dev
, B43_MMIO_CHANNEL_EXT
,
1438 (b43_read16(dev
, B43_MMIO_CHANNEL_EXT
) | 0x2000));
1441 rcc
= b43_radio_core_calibration_value(dev
);
1443 if (phy
->type
== B43_PHYTYPE_B
)
1444 b43_radio_write16(dev
, 0x78, 0x26);
1445 if (phy
->gmode
|| phy
->rev
>= 2) {
1446 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1447 radio2050_rfover_val(dev
, B43_PHY_RFOVERVAL
,
1450 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xBFAF);
1451 b43_phy_write(dev
, B43_PHY_CCK(0x2B), 0x1403);
1452 if (phy
->gmode
|| phy
->rev
>= 2) {
1453 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1454 radio2050_rfover_val(dev
, B43_PHY_RFOVERVAL
,
1457 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xBFA0);
1458 b43_radio_write16(dev
, 0x51, b43_radio_read16(dev
, 0x51)
1460 if (phy
->radio_rev
== 8) {
1461 b43_radio_write16(dev
, 0x43, 0x1F);
1463 b43_radio_write16(dev
, 0x52, 0);
1464 b43_radio_write16(dev
, 0x43, (b43_radio_read16(dev
, 0x43)
1465 & 0xFFF0) | 0x0009);
1467 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0);
1469 for (i
= 0; i
< 16; i
++) {
1470 b43_phy_write(dev
, B43_PHY_CCK(0x5A), 0x0480);
1471 b43_phy_write(dev
, B43_PHY_CCK(0x59), 0xC810);
1472 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0x000D);
1473 if (phy
->gmode
|| phy
->rev
>= 2) {
1474 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1475 radio2050_rfover_val(dev
,
1479 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xAFB0);
1481 if (phy
->gmode
|| phy
->rev
>= 2) {
1482 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1483 radio2050_rfover_val(dev
,
1487 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xEFB0);
1489 if (phy
->gmode
|| phy
->rev
>= 2) {
1490 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1491 radio2050_rfover_val(dev
,
1495 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xFFF0);
1497 tmp1
+= b43_phy_read(dev
, B43_PHY_LO_LEAKAGE
);
1498 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0);
1499 if (phy
->gmode
|| phy
->rev
>= 2) {
1500 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1501 radio2050_rfover_val(dev
,
1505 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xAFB0);
1509 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0);
1513 for (i
= 0; i
< 16; i
++) {
1514 radio78
= (bitrev4(i
) << 1) | 0x0020;
1515 b43_radio_write16(dev
, 0x78, radio78
);
1517 for (j
= 0; j
< 16; j
++) {
1518 b43_phy_write(dev
, B43_PHY_CCK(0x5A), 0x0D80);
1519 b43_phy_write(dev
, B43_PHY_CCK(0x59), 0xC810);
1520 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0x000D);
1521 if (phy
->gmode
|| phy
->rev
>= 2) {
1522 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1523 radio2050_rfover_val(dev
,
1528 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xAFB0);
1530 if (phy
->gmode
|| phy
->rev
>= 2) {
1531 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1532 radio2050_rfover_val(dev
,
1537 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xEFB0);
1539 if (phy
->gmode
|| phy
->rev
>= 2) {
1540 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1541 radio2050_rfover_val(dev
,
1546 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xFFF0);
1548 tmp2
+= b43_phy_read(dev
, B43_PHY_LO_LEAKAGE
);
1549 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0);
1550 if (phy
->gmode
|| phy
->rev
>= 2) {
1551 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1552 radio2050_rfover_val(dev
,
1557 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xAFB0);
1565 /* Restore the registers */
1566 b43_phy_write(dev
, B43_PHY_PGACTL
, sav
.phy_pgactl
);
1567 b43_radio_write16(dev
, 0x51, sav
.radio_51
);
1568 b43_radio_write16(dev
, 0x52, sav
.radio_52
);
1569 b43_radio_write16(dev
, 0x43, sav
.radio_43
);
1570 b43_phy_write(dev
, B43_PHY_CCK(0x5A), sav
.phy_cck_5A
);
1571 b43_phy_write(dev
, B43_PHY_CCK(0x59), sav
.phy_cck_59
);
1572 b43_phy_write(dev
, B43_PHY_CCK(0x58), sav
.phy_cck_58
);
1573 b43_write16(dev
, 0x3E6, sav
.reg_3E6
);
1574 if (phy
->analog
!= 0)
1575 b43_write16(dev
, 0x3F4, sav
.reg_3F4
);
1576 b43_phy_write(dev
, B43_PHY_SYNCCTL
, sav
.phy_syncctl
);
1577 b43_synth_pu_workaround(dev
, phy
->channel
);
1578 if (phy
->type
== B43_PHYTYPE_B
) {
1579 b43_phy_write(dev
, B43_PHY_CCK(0x30), sav
.phy_cck_30
);
1580 b43_write16(dev
, 0x3EC, sav
.reg_3EC
);
1581 } else if (phy
->gmode
) {
1582 b43_write16(dev
, B43_MMIO_PHY_RADIO
,
1583 b43_read16(dev
, B43_MMIO_PHY_RADIO
)
1585 b43_phy_write(dev
, B43_PHY_RFOVER
, sav
.phy_rfover
);
1586 b43_phy_write(dev
, B43_PHY_RFOVERVAL
, sav
.phy_rfoverval
);
1587 b43_phy_write(dev
, B43_PHY_ANALOGOVER
, sav
.phy_analogover
);
1588 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
,
1589 sav
.phy_analogoverval
);
1590 b43_phy_write(dev
, B43_PHY_CRS0
, sav
.phy_crs0
);
1591 b43_phy_write(dev
, B43_PHY_CLASSCTL
, sav
.phy_classctl
);
1592 if (has_loopback_gain(phy
)) {
1593 b43_phy_write(dev
, B43_PHY_LO_MASK
, sav
.phy_lo_mask
);
1594 b43_phy_write(dev
, B43_PHY_LO_CTL
, sav
.phy_lo_ctl
);
1605 static void b43_phy_initb5(struct b43_wldev
*dev
)
1607 struct ssb_bus
*bus
= dev
->dev
->bus
;
1608 struct b43_phy
*phy
= &dev
->phy
;
1609 struct b43_phy_g
*gphy
= phy
->g
;
1613 if (phy
->analog
== 1) {
1614 b43_radio_write16(dev
, 0x007A, b43_radio_read16(dev
, 0x007A)
1617 if ((bus
->boardinfo
.vendor
!= SSB_BOARDVENDOR_BCM
) &&
1618 (bus
->boardinfo
.type
!= SSB_BOARD_BU4306
)) {
1620 for (offset
= 0x00A8; offset
< 0x00C7; offset
++) {
1621 b43_phy_write(dev
, offset
, value
);
1625 b43_phy_write(dev
, 0x0035, (b43_phy_read(dev
, 0x0035) & 0xF0FF)
1627 if (phy
->radio_ver
== 0x2050)
1628 b43_phy_write(dev
, 0x0038, 0x0667);
1630 if (phy
->gmode
|| phy
->rev
>= 2) {
1631 if (phy
->radio_ver
== 0x2050) {
1632 b43_radio_write16(dev
, 0x007A,
1633 b43_radio_read16(dev
, 0x007A)
1635 b43_radio_write16(dev
, 0x0051,
1636 b43_radio_read16(dev
, 0x0051)
1639 b43_write16(dev
, B43_MMIO_PHY_RADIO
, 0x0000);
1641 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) | 0x0100);
1642 b43_phy_write(dev
, 0x042B, b43_phy_read(dev
, 0x042B) | 0x2000);
1644 b43_phy_write(dev
, 0x001C, 0x186A);
1646 b43_phy_write(dev
, 0x0013,
1647 (b43_phy_read(dev
, 0x0013) & 0x00FF) | 0x1900);
1648 b43_phy_write(dev
, 0x0035,
1649 (b43_phy_read(dev
, 0x0035) & 0xFFC0) | 0x0064);
1650 b43_phy_write(dev
, 0x005D,
1651 (b43_phy_read(dev
, 0x005D) & 0xFF80) | 0x000A);
1654 if (dev
->bad_frames_preempt
) {
1655 b43_phy_write(dev
, B43_PHY_RADIO_BITFIELD
,
1657 B43_PHY_RADIO_BITFIELD
) | (1 << 11));
1660 if (phy
->analog
== 1) {
1661 b43_phy_write(dev
, 0x0026, 0xCE00);
1662 b43_phy_write(dev
, 0x0021, 0x3763);
1663 b43_phy_write(dev
, 0x0022, 0x1BC3);
1664 b43_phy_write(dev
, 0x0023, 0x06F9);
1665 b43_phy_write(dev
, 0x0024, 0x037E);
1667 b43_phy_write(dev
, 0x0026, 0xCC00);
1668 b43_phy_write(dev
, 0x0030, 0x00C6);
1669 b43_write16(dev
, 0x03EC, 0x3F22);
1671 if (phy
->analog
== 1)
1672 b43_phy_write(dev
, 0x0020, 0x3E1C);
1674 b43_phy_write(dev
, 0x0020, 0x301C);
1676 if (phy
->analog
== 0)
1677 b43_write16(dev
, 0x03E4, 0x3000);
1679 old_channel
= phy
->channel
;
1680 /* Force to channel 7, even if not supported. */
1681 b43_gphy_channel_switch(dev
, 7, 0);
1683 if (phy
->radio_ver
!= 0x2050) {
1684 b43_radio_write16(dev
, 0x0075, 0x0080);
1685 b43_radio_write16(dev
, 0x0079, 0x0081);
1688 b43_radio_write16(dev
, 0x0050, 0x0020);
1689 b43_radio_write16(dev
, 0x0050, 0x0023);
1691 if (phy
->radio_ver
== 0x2050) {
1692 b43_radio_write16(dev
, 0x0050, 0x0020);
1693 b43_radio_write16(dev
, 0x005A, 0x0070);
1696 b43_radio_write16(dev
, 0x005B, 0x007B);
1697 b43_radio_write16(dev
, 0x005C, 0x00B0);
1699 b43_radio_write16(dev
, 0x007A, b43_radio_read16(dev
, 0x007A) | 0x0007);
1701 b43_gphy_channel_switch(dev
, old_channel
, 0);
1703 b43_phy_write(dev
, 0x0014, 0x0080);
1704 b43_phy_write(dev
, 0x0032, 0x00CA);
1705 b43_phy_write(dev
, 0x002A, 0x88A3);
1707 b43_set_txpower_g(dev
, &gphy
->bbatt
, &gphy
->rfatt
, gphy
->tx_control
);
1709 if (phy
->radio_ver
== 0x2050)
1710 b43_radio_write16(dev
, 0x005D, 0x000D);
1712 b43_write16(dev
, 0x03E4, (b43_read16(dev
, 0x03E4) & 0xFFC0) | 0x0004);
1715 static void b43_phy_initb6(struct b43_wldev
*dev
)
1717 struct b43_phy
*phy
= &dev
->phy
;
1718 struct b43_phy_g
*gphy
= phy
->g
;
1722 b43_phy_write(dev
, 0x003E, 0x817A);
1723 b43_radio_write16(dev
, 0x007A,
1724 (b43_radio_read16(dev
, 0x007A) | 0x0058));
1725 if (phy
->radio_rev
== 4 || phy
->radio_rev
== 5) {
1726 b43_radio_write16(dev
, 0x51, 0x37);
1727 b43_radio_write16(dev
, 0x52, 0x70);
1728 b43_radio_write16(dev
, 0x53, 0xB3);
1729 b43_radio_write16(dev
, 0x54, 0x9B);
1730 b43_radio_write16(dev
, 0x5A, 0x88);
1731 b43_radio_write16(dev
, 0x5B, 0x88);
1732 b43_radio_write16(dev
, 0x5D, 0x88);
1733 b43_radio_write16(dev
, 0x5E, 0x88);
1734 b43_radio_write16(dev
, 0x7D, 0x88);
1735 b43_hf_write(dev
, b43_hf_read(dev
)
1736 | B43_HF_TSSIRPSMW
);
1738 B43_WARN_ON(phy
->radio_rev
== 6 || phy
->radio_rev
== 7); /* We had code for these revs here... */
1739 if (phy
->radio_rev
== 8) {
1740 b43_radio_write16(dev
, 0x51, 0);
1741 b43_radio_write16(dev
, 0x52, 0x40);
1742 b43_radio_write16(dev
, 0x53, 0xB7);
1743 b43_radio_write16(dev
, 0x54, 0x98);
1744 b43_radio_write16(dev
, 0x5A, 0x88);
1745 b43_radio_write16(dev
, 0x5B, 0x6B);
1746 b43_radio_write16(dev
, 0x5C, 0x0F);
1747 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_ALTIQ
) {
1748 b43_radio_write16(dev
, 0x5D, 0xFA);
1749 b43_radio_write16(dev
, 0x5E, 0xD8);
1751 b43_radio_write16(dev
, 0x5D, 0xF5);
1752 b43_radio_write16(dev
, 0x5E, 0xB8);
1754 b43_radio_write16(dev
, 0x0073, 0x0003);
1755 b43_radio_write16(dev
, 0x007D, 0x00A8);
1756 b43_radio_write16(dev
, 0x007C, 0x0001);
1757 b43_radio_write16(dev
, 0x007E, 0x0008);
1760 for (offset
= 0x0088; offset
< 0x0098; offset
++) {
1761 b43_phy_write(dev
, offset
, val
);
1765 for (offset
= 0x0098; offset
< 0x00A8; offset
++) {
1766 b43_phy_write(dev
, offset
, val
);
1770 for (offset
= 0x00A8; offset
< 0x00C8; offset
++) {
1771 b43_phy_write(dev
, offset
, (val
& 0x3F3F));
1774 if (phy
->type
== B43_PHYTYPE_G
) {
1775 b43_radio_write16(dev
, 0x007A,
1776 b43_radio_read16(dev
, 0x007A) | 0x0020);
1777 b43_radio_write16(dev
, 0x0051,
1778 b43_radio_read16(dev
, 0x0051) | 0x0004);
1779 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) | 0x0100);
1780 b43_phy_write(dev
, 0x042B, b43_phy_read(dev
, 0x042B) | 0x2000);
1781 b43_phy_write(dev
, 0x5B, 0);
1782 b43_phy_write(dev
, 0x5C, 0);
1785 old_channel
= phy
->channel
;
1786 if (old_channel
>= 8)
1787 b43_gphy_channel_switch(dev
, 1, 0);
1789 b43_gphy_channel_switch(dev
, 13, 0);
1791 b43_radio_write16(dev
, 0x0050, 0x0020);
1792 b43_radio_write16(dev
, 0x0050, 0x0023);
1794 if (phy
->radio_rev
< 6 || phy
->radio_rev
== 8) {
1795 b43_radio_write16(dev
, 0x7C, (b43_radio_read16(dev
, 0x7C)
1797 b43_radio_write16(dev
, 0x50, 0x20);
1799 if (phy
->radio_rev
<= 2) {
1800 b43_radio_write16(dev
, 0x7C, 0x20);
1801 b43_radio_write16(dev
, 0x5A, 0x70);
1802 b43_radio_write16(dev
, 0x5B, 0x7B);
1803 b43_radio_write16(dev
, 0x5C, 0xB0);
1805 b43_radio_write16(dev
, 0x007A,
1806 (b43_radio_read16(dev
, 0x007A) & 0x00F8) | 0x0007);
1808 b43_gphy_channel_switch(dev
, old_channel
, 0);
1810 b43_phy_write(dev
, 0x0014, 0x0200);
1811 if (phy
->radio_rev
>= 6)
1812 b43_phy_write(dev
, 0x2A, 0x88C2);
1814 b43_phy_write(dev
, 0x2A, 0x8AC0);
1815 b43_phy_write(dev
, 0x0038, 0x0668);
1816 b43_set_txpower_g(dev
, &gphy
->bbatt
, &gphy
->rfatt
, gphy
->tx_control
);
1817 if (phy
->radio_rev
<= 5) {
1818 b43_phy_write(dev
, 0x5D, (b43_phy_read(dev
, 0x5D)
1819 & 0xFF80) | 0x0003);
1821 if (phy
->radio_rev
<= 2)
1822 b43_radio_write16(dev
, 0x005D, 0x000D);
1824 if (phy
->analog
== 4) {
1825 b43_write16(dev
, 0x3E4, 9);
1826 b43_phy_write(dev
, 0x61, b43_phy_read(dev
, 0x61)
1829 b43_phy_write(dev
, 0x0002, (b43_phy_read(dev
, 0x0002) & 0xFFC0)
1832 if (phy
->type
== B43_PHYTYPE_B
)
1834 else if (phy
->type
== B43_PHYTYPE_G
)
1835 b43_write16(dev
, 0x03E6, 0x0);
1838 static void b43_calc_loopback_gain(struct b43_wldev
*dev
)
1840 struct b43_phy
*phy
= &dev
->phy
;
1841 struct b43_phy_g
*gphy
= phy
->g
;
1842 u16 backup_phy
[16] = { 0 };
1843 u16 backup_radio
[3];
1845 u16 i
, j
, loop_i_max
;
1847 u16 loop1_outer_done
, loop1_inner_done
;
1849 backup_phy
[0] = b43_phy_read(dev
, B43_PHY_CRS0
);
1850 backup_phy
[1] = b43_phy_read(dev
, B43_PHY_CCKBBANDCFG
);
1851 backup_phy
[2] = b43_phy_read(dev
, B43_PHY_RFOVER
);
1852 backup_phy
[3] = b43_phy_read(dev
, B43_PHY_RFOVERVAL
);
1853 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
1854 backup_phy
[4] = b43_phy_read(dev
, B43_PHY_ANALOGOVER
);
1855 backup_phy
[5] = b43_phy_read(dev
, B43_PHY_ANALOGOVERVAL
);
1857 backup_phy
[6] = b43_phy_read(dev
, B43_PHY_CCK(0x5A));
1858 backup_phy
[7] = b43_phy_read(dev
, B43_PHY_CCK(0x59));
1859 backup_phy
[8] = b43_phy_read(dev
, B43_PHY_CCK(0x58));
1860 backup_phy
[9] = b43_phy_read(dev
, B43_PHY_CCK(0x0A));
1861 backup_phy
[10] = b43_phy_read(dev
, B43_PHY_CCK(0x03));
1862 backup_phy
[11] = b43_phy_read(dev
, B43_PHY_LO_MASK
);
1863 backup_phy
[12] = b43_phy_read(dev
, B43_PHY_LO_CTL
);
1864 backup_phy
[13] = b43_phy_read(dev
, B43_PHY_CCK(0x2B));
1865 backup_phy
[14] = b43_phy_read(dev
, B43_PHY_PGACTL
);
1866 backup_phy
[15] = b43_phy_read(dev
, B43_PHY_LO_LEAKAGE
);
1867 backup_bband
= gphy
->bbatt
.att
;
1868 backup_radio
[0] = b43_radio_read16(dev
, 0x52);
1869 backup_radio
[1] = b43_radio_read16(dev
, 0x43);
1870 backup_radio
[2] = b43_radio_read16(dev
, 0x7A);
1872 b43_phy_write(dev
, B43_PHY_CRS0
,
1873 b43_phy_read(dev
, B43_PHY_CRS0
) & 0x3FFF);
1874 b43_phy_write(dev
, B43_PHY_CCKBBANDCFG
,
1875 b43_phy_read(dev
, B43_PHY_CCKBBANDCFG
) | 0x8000);
1876 b43_phy_write(dev
, B43_PHY_RFOVER
,
1877 b43_phy_read(dev
, B43_PHY_RFOVER
) | 0x0002);
1878 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1879 b43_phy_read(dev
, B43_PHY_RFOVERVAL
) & 0xFFFD);
1880 b43_phy_write(dev
, B43_PHY_RFOVER
,
1881 b43_phy_read(dev
, B43_PHY_RFOVER
) | 0x0001);
1882 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1883 b43_phy_read(dev
, B43_PHY_RFOVERVAL
) & 0xFFFE);
1884 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
1885 b43_phy_write(dev
, B43_PHY_ANALOGOVER
,
1886 b43_phy_read(dev
, B43_PHY_ANALOGOVER
) | 0x0001);
1887 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
,
1889 B43_PHY_ANALOGOVERVAL
) & 0xFFFE);
1890 b43_phy_write(dev
, B43_PHY_ANALOGOVER
,
1891 b43_phy_read(dev
, B43_PHY_ANALOGOVER
) | 0x0002);
1892 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
,
1894 B43_PHY_ANALOGOVERVAL
) & 0xFFFD);
1896 b43_phy_write(dev
, B43_PHY_RFOVER
,
1897 b43_phy_read(dev
, B43_PHY_RFOVER
) | 0x000C);
1898 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1899 b43_phy_read(dev
, B43_PHY_RFOVERVAL
) | 0x000C);
1900 b43_phy_write(dev
, B43_PHY_RFOVER
,
1901 b43_phy_read(dev
, B43_PHY_RFOVER
) | 0x0030);
1902 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1903 (b43_phy_read(dev
, B43_PHY_RFOVERVAL
)
1906 b43_phy_write(dev
, B43_PHY_CCK(0x5A), 0x0780);
1907 b43_phy_write(dev
, B43_PHY_CCK(0x59), 0xC810);
1908 b43_phy_write(dev
, B43_PHY_CCK(0x58), 0x000D);
1910 b43_phy_write(dev
, B43_PHY_CCK(0x0A),
1911 b43_phy_read(dev
, B43_PHY_CCK(0x0A)) | 0x2000);
1912 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
1913 b43_phy_write(dev
, B43_PHY_ANALOGOVER
,
1914 b43_phy_read(dev
, B43_PHY_ANALOGOVER
) | 0x0004);
1915 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
,
1917 B43_PHY_ANALOGOVERVAL
) & 0xFFFB);
1919 b43_phy_write(dev
, B43_PHY_CCK(0x03),
1920 (b43_phy_read(dev
, B43_PHY_CCK(0x03))
1923 if (phy
->radio_rev
== 8) {
1924 b43_radio_write16(dev
, 0x43, 0x000F);
1926 b43_radio_write16(dev
, 0x52, 0);
1927 b43_radio_write16(dev
, 0x43, (b43_radio_read16(dev
, 0x43)
1930 b43_gphy_set_baseband_attenuation(dev
, 11);
1933 b43_phy_write(dev
, B43_PHY_LO_MASK
, 0xC020);
1935 b43_phy_write(dev
, B43_PHY_LO_MASK
, 0x8020);
1936 b43_phy_write(dev
, B43_PHY_LO_CTL
, 0);
1938 b43_phy_write(dev
, B43_PHY_CCK(0x2B),
1939 (b43_phy_read(dev
, B43_PHY_CCK(0x2B))
1941 b43_phy_write(dev
, B43_PHY_CCK(0x2B),
1942 (b43_phy_read(dev
, B43_PHY_CCK(0x2B))
1945 b43_phy_write(dev
, B43_PHY_RFOVER
,
1946 b43_phy_read(dev
, B43_PHY_RFOVER
) | 0x0100);
1947 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1948 b43_phy_read(dev
, B43_PHY_RFOVERVAL
) & 0xCFFF);
1950 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_EXTLNA
) {
1951 if (phy
->rev
>= 7) {
1952 b43_phy_write(dev
, B43_PHY_RFOVER
,
1953 b43_phy_read(dev
, B43_PHY_RFOVER
)
1955 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1956 b43_phy_read(dev
, B43_PHY_RFOVERVAL
)
1960 b43_radio_write16(dev
, 0x7A, b43_radio_read16(dev
, 0x7A)
1964 loop_i_max
= (phy
->radio_rev
== 8) ? 15 : 9;
1965 for (i
= 0; i
< loop_i_max
; i
++) {
1966 for (j
= 0; j
< 16; j
++) {
1967 b43_radio_write16(dev
, 0x43, i
);
1968 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1969 (b43_phy_read(dev
, B43_PHY_RFOVERVAL
)
1970 & 0xF0FF) | (j
<< 8));
1971 b43_phy_write(dev
, B43_PHY_PGACTL
,
1972 (b43_phy_read(dev
, B43_PHY_PGACTL
)
1973 & 0x0FFF) | 0xA000);
1974 b43_phy_write(dev
, B43_PHY_PGACTL
,
1975 b43_phy_read(dev
, B43_PHY_PGACTL
)
1978 if (b43_phy_read(dev
, B43_PHY_LO_LEAKAGE
) >= 0xDFC)
1983 loop1_outer_done
= i
;
1984 loop1_inner_done
= j
;
1986 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1987 b43_phy_read(dev
, B43_PHY_RFOVERVAL
)
1990 for (j
= j
- 8; j
< 16; j
++) {
1991 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
1992 (b43_phy_read(dev
, B43_PHY_RFOVERVAL
)
1993 & 0xF0FF) | (j
<< 8));
1994 b43_phy_write(dev
, B43_PHY_PGACTL
,
1995 (b43_phy_read(dev
, B43_PHY_PGACTL
)
1996 & 0x0FFF) | 0xA000);
1997 b43_phy_write(dev
, B43_PHY_PGACTL
,
1998 b43_phy_read(dev
, B43_PHY_PGACTL
)
2002 if (b43_phy_read(dev
, B43_PHY_LO_LEAKAGE
) >= 0xDFC)
2009 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
2010 b43_phy_write(dev
, B43_PHY_ANALOGOVER
, backup_phy
[4]);
2011 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
, backup_phy
[5]);
2013 b43_phy_write(dev
, B43_PHY_CCK(0x5A), backup_phy
[6]);
2014 b43_phy_write(dev
, B43_PHY_CCK(0x59), backup_phy
[7]);
2015 b43_phy_write(dev
, B43_PHY_CCK(0x58), backup_phy
[8]);
2016 b43_phy_write(dev
, B43_PHY_CCK(0x0A), backup_phy
[9]);
2017 b43_phy_write(dev
, B43_PHY_CCK(0x03), backup_phy
[10]);
2018 b43_phy_write(dev
, B43_PHY_LO_MASK
, backup_phy
[11]);
2019 b43_phy_write(dev
, B43_PHY_LO_CTL
, backup_phy
[12]);
2020 b43_phy_write(dev
, B43_PHY_CCK(0x2B), backup_phy
[13]);
2021 b43_phy_write(dev
, B43_PHY_PGACTL
, backup_phy
[14]);
2023 b43_gphy_set_baseband_attenuation(dev
, backup_bband
);
2025 b43_radio_write16(dev
, 0x52, backup_radio
[0]);
2026 b43_radio_write16(dev
, 0x43, backup_radio
[1]);
2027 b43_radio_write16(dev
, 0x7A, backup_radio
[2]);
2029 b43_phy_write(dev
, B43_PHY_RFOVER
, backup_phy
[2] | 0x0003);
2031 b43_phy_write(dev
, B43_PHY_RFOVER
, backup_phy
[2]);
2032 b43_phy_write(dev
, B43_PHY_RFOVERVAL
, backup_phy
[3]);
2033 b43_phy_write(dev
, B43_PHY_CRS0
, backup_phy
[0]);
2034 b43_phy_write(dev
, B43_PHY_CCKBBANDCFG
, backup_phy
[1]);
2037 ((loop1_inner_done
* 6) - (loop1_outer_done
* 4)) - 11;
2038 gphy
->trsw_rx_gain
= trsw_rx
* 2;
2041 static void b43_hardware_pctl_early_init(struct b43_wldev
*dev
)
2043 struct b43_phy
*phy
= &dev
->phy
;
2045 if (!b43_has_hardware_pctl(dev
)) {
2046 b43_phy_write(dev
, 0x047A, 0xC111);
2050 b43_phy_write(dev
, 0x0036, b43_phy_read(dev
, 0x0036) & 0xFEFF);
2051 b43_phy_write(dev
, 0x002F, 0x0202);
2052 b43_phy_write(dev
, 0x047C, b43_phy_read(dev
, 0x047C) | 0x0002);
2053 b43_phy_write(dev
, 0x047A, b43_phy_read(dev
, 0x047A) | 0xF000);
2054 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
== 8) {
2055 b43_phy_write(dev
, 0x047A, (b43_phy_read(dev
, 0x047A)
2056 & 0xFF0F) | 0x0010);
2057 b43_phy_write(dev
, 0x005D, b43_phy_read(dev
, 0x005D)
2059 b43_phy_write(dev
, 0x004E, (b43_phy_read(dev
, 0x004E)
2060 & 0xFFC0) | 0x0010);
2061 b43_phy_write(dev
, 0x002E, 0xC07F);
2062 b43_phy_write(dev
, 0x0036, b43_phy_read(dev
, 0x0036)
2065 b43_phy_write(dev
, 0x0036, b43_phy_read(dev
, 0x0036)
2067 b43_phy_write(dev
, 0x0036, b43_phy_read(dev
, 0x0036)
2069 b43_phy_write(dev
, 0x005D, b43_phy_read(dev
, 0x005D)
2071 b43_phy_write(dev
, 0x004F, b43_phy_read(dev
, 0x004F)
2073 b43_phy_write(dev
, 0x004E, (b43_phy_read(dev
, 0x004E)
2074 & 0xFFC0) | 0x0010);
2075 b43_phy_write(dev
, 0x002E, 0xC07F);
2076 b43_phy_write(dev
, 0x047A, (b43_phy_read(dev
, 0x047A)
2077 & 0xFF0F) | 0x0010);
2081 /* Hardware power control for G-PHY */
2082 static void b43_hardware_pctl_init_gphy(struct b43_wldev
*dev
)
2084 struct b43_phy
*phy
= &dev
->phy
;
2085 struct b43_phy_g
*gphy
= phy
->g
;
2087 if (!b43_has_hardware_pctl(dev
)) {
2088 /* No hardware power control */
2089 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_HWPCTL
);
2093 b43_phy_write(dev
, 0x0036, (b43_phy_read(dev
, 0x0036) & 0xFFC0)
2094 | (gphy
->tgt_idle_tssi
- gphy
->cur_idle_tssi
));
2095 b43_phy_write(dev
, 0x0478, (b43_phy_read(dev
, 0x0478) & 0xFF00)
2096 | (gphy
->tgt_idle_tssi
- gphy
->cur_idle_tssi
));
2097 b43_gphy_tssi_power_lt_init(dev
);
2098 b43_gphy_gain_lt_init(dev
);
2099 b43_phy_write(dev
, 0x0060, b43_phy_read(dev
, 0x0060) & 0xFFBF);
2100 b43_phy_write(dev
, 0x0014, 0x0000);
2102 B43_WARN_ON(phy
->rev
< 6);
2103 b43_phy_write(dev
, 0x0478, b43_phy_read(dev
, 0x0478)
2105 b43_phy_write(dev
, 0x0478, b43_phy_read(dev
, 0x0478)
2107 b43_phy_write(dev
, 0x0801, b43_phy_read(dev
, 0x0801)
2110 b43_gphy_dc_lt_init(dev
, 1);
2112 /* Enable hardware pctl in firmware. */
2113 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_HWPCTL
);
2116 /* Intialize B/G PHY power control */
2117 static void b43_phy_init_pctl(struct b43_wldev
*dev
)
2119 struct ssb_bus
*bus
= dev
->dev
->bus
;
2120 struct b43_phy
*phy
= &dev
->phy
;
2121 struct b43_phy_g
*gphy
= phy
->g
;
2122 struct b43_rfatt old_rfatt
;
2123 struct b43_bbatt old_bbatt
;
2124 u8 old_tx_control
= 0;
2126 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
2128 if ((bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
) &&
2129 (bus
->boardinfo
.type
== SSB_BOARD_BU4306
))
2132 b43_phy_write(dev
, 0x0028, 0x8018);
2134 /* This does something with the Analog... */
2135 b43_write16(dev
, B43_MMIO_PHY0
, b43_read16(dev
, B43_MMIO_PHY0
)
2140 b43_hardware_pctl_early_init(dev
);
2141 if (gphy
->cur_idle_tssi
== 0) {
2142 if (phy
->radio_ver
== 0x2050 && phy
->analog
== 0) {
2143 b43_radio_write16(dev
, 0x0076,
2144 (b43_radio_read16(dev
, 0x0076)
2145 & 0x00F7) | 0x0084);
2147 struct b43_rfatt rfatt
;
2148 struct b43_bbatt bbatt
;
2150 memcpy(&old_rfatt
, &gphy
->rfatt
, sizeof(old_rfatt
));
2151 memcpy(&old_bbatt
, &gphy
->bbatt
, sizeof(old_bbatt
));
2152 old_tx_control
= gphy
->tx_control
;
2155 if (phy
->radio_rev
== 8) {
2157 rfatt
.with_padmix
= 1;
2160 rfatt
.with_padmix
= 0;
2162 b43_set_txpower_g(dev
, &bbatt
, &rfatt
, 0);
2164 b43_dummy_transmission(dev
);
2165 gphy
->cur_idle_tssi
= b43_phy_read(dev
, B43_PHY_ITSSI
);
2167 /* Current-Idle-TSSI sanity check. */
2168 if (abs(gphy
->cur_idle_tssi
- gphy
->tgt_idle_tssi
) >= 20) {
2170 "!WARNING! Idle-TSSI phy->cur_idle_tssi "
2171 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
2172 "adjustment.\n", gphy
->cur_idle_tssi
,
2173 gphy
->tgt_idle_tssi
);
2174 gphy
->cur_idle_tssi
= 0;
2177 if (phy
->radio_ver
== 0x2050 && phy
->analog
== 0) {
2178 b43_radio_write16(dev
, 0x0076,
2179 b43_radio_read16(dev
, 0x0076)
2182 b43_set_txpower_g(dev
, &old_bbatt
,
2183 &old_rfatt
, old_tx_control
);
2186 b43_hardware_pctl_init_gphy(dev
);
2187 b43_shm_clear_tssi(dev
);
2190 static void b43_phy_initg(struct b43_wldev
*dev
)
2192 struct b43_phy
*phy
= &dev
->phy
;
2193 struct b43_phy_g
*gphy
= phy
->g
;
2197 b43_phy_initb5(dev
);
2199 b43_phy_initb6(dev
);
2201 if (phy
->rev
>= 2 || phy
->gmode
)
2204 if (phy
->rev
>= 2) {
2205 b43_phy_write(dev
, B43_PHY_ANALOGOVER
, 0);
2206 b43_phy_write(dev
, B43_PHY_ANALOGOVERVAL
, 0);
2208 if (phy
->rev
== 2) {
2209 b43_phy_write(dev
, B43_PHY_RFOVER
, 0);
2210 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xC0);
2213 b43_phy_write(dev
, B43_PHY_RFOVER
, 0x400);
2214 b43_phy_write(dev
, B43_PHY_PGACTL
, 0xC0);
2216 if (phy
->gmode
|| phy
->rev
>= 2) {
2217 tmp
= b43_phy_read(dev
, B43_PHY_VERSION_OFDM
);
2218 tmp
&= B43_PHYVER_VERSION
;
2219 if (tmp
== 3 || tmp
== 5) {
2220 b43_phy_write(dev
, B43_PHY_OFDM(0xC2), 0x1816);
2221 b43_phy_write(dev
, B43_PHY_OFDM(0xC3), 0x8006);
2224 b43_phy_write(dev
, B43_PHY_OFDM(0xCC),
2225 (b43_phy_read(dev
, B43_PHY_OFDM(0xCC))
2226 & 0x00FF) | 0x1F00);
2229 if ((phy
->rev
<= 2 && phy
->gmode
) || phy
->rev
>= 2)
2230 b43_phy_write(dev
, B43_PHY_OFDM(0x7E), 0x78);
2231 if (phy
->radio_rev
== 8) {
2232 b43_phy_write(dev
, B43_PHY_EXTG(0x01),
2233 b43_phy_read(dev
, B43_PHY_EXTG(0x01))
2235 b43_phy_write(dev
, B43_PHY_OFDM(0x3E),
2236 b43_phy_read(dev
, B43_PHY_OFDM(0x3E))
2239 if (has_loopback_gain(phy
))
2240 b43_calc_loopback_gain(dev
);
2242 if (phy
->radio_rev
!= 8) {
2243 if (gphy
->initval
== 0xFFFF)
2244 gphy
->initval
= b43_radio_init2050(dev
);
2246 b43_radio_write16(dev
, 0x0078, gphy
->initval
);
2249 if (has_tx_magnification(phy
)) {
2250 b43_radio_write16(dev
, 0x52,
2251 (b43_radio_read16(dev
, 0x52) & 0xFF00)
2252 | gphy
->lo_control
->tx_bias
| gphy
->
2253 lo_control
->tx_magn
);
2255 b43_radio_write16(dev
, 0x52,
2256 (b43_radio_read16(dev
, 0x52) & 0xFFF0)
2257 | gphy
->lo_control
->tx_bias
);
2259 if (phy
->rev
>= 6) {
2260 b43_phy_write(dev
, B43_PHY_CCK(0x36),
2261 (b43_phy_read(dev
, B43_PHY_CCK(0x36))
2262 & 0x0FFF) | (gphy
->lo_control
->
2265 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_PACTRL
)
2266 b43_phy_write(dev
, B43_PHY_CCK(0x2E), 0x8075);
2268 b43_phy_write(dev
, B43_PHY_CCK(0x2E), 0x807F);
2270 b43_phy_write(dev
, B43_PHY_CCK(0x2F), 0x101);
2272 b43_phy_write(dev
, B43_PHY_CCK(0x2F), 0x202);
2273 if (phy
->gmode
|| phy
->rev
>= 2) {
2274 b43_lo_g_adjust(dev
);
2275 b43_phy_write(dev
, B43_PHY_LO_MASK
, 0x8078);
2278 if (!(dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_RSSI
)) {
2279 /* The specs state to update the NRSSI LT with
2280 * the value 0x7FFFFFFF here. I think that is some weird
2281 * compiler optimization in the original driver.
2282 * Essentially, what we do here is resetting all NRSSI LT
2283 * entries to -32 (see the clamp_val() in nrssi_hw_update())
2285 b43_nrssi_hw_update(dev
, 0xFFFF); //FIXME?
2286 b43_calc_nrssi_threshold(dev
);
2287 } else if (phy
->gmode
|| phy
->rev
>= 2) {
2288 if (gphy
->nrssi
[0] == -1000) {
2289 B43_WARN_ON(gphy
->nrssi
[1] != -1000);
2290 b43_calc_nrssi_slope(dev
);
2292 b43_calc_nrssi_threshold(dev
);
2294 if (phy
->radio_rev
== 8)
2295 b43_phy_write(dev
, B43_PHY_EXTG(0x05), 0x3230);
2296 b43_phy_init_pctl(dev
);
2297 /* FIXME: The spec says in the following if, the 0 should be replaced
2298 'if OFDM may not be used in the current locale'
2299 but OFDM is legal everywhere */
2300 if ((dev
->dev
->bus
->chip_id
== 0x4306
2301 && dev
->dev
->bus
->chip_package
== 2) || 0) {
2302 b43_phy_write(dev
, B43_PHY_CRS0
, b43_phy_read(dev
, B43_PHY_CRS0
)
2304 b43_phy_write(dev
, B43_PHY_OFDM(0xC3),
2305 b43_phy_read(dev
, B43_PHY_OFDM(0xC3))
2310 void b43_gphy_channel_switch(struct b43_wldev
*dev
,
2311 unsigned int channel
,
2312 bool synthetic_pu_workaround
)
2314 if (synthetic_pu_workaround
)
2315 b43_synth_pu_workaround(dev
, channel
);
2317 b43_write16(dev
, B43_MMIO_CHANNEL
, channel2freq_bg(channel
));
2319 if (channel
== 14) {
2320 if (dev
->dev
->bus
->sprom
.country_code
==
2321 SSB_SPROM1CCODE_JAPAN
)
2323 b43_hf_read(dev
) & ~B43_HF_ACPR
);
2326 b43_hf_read(dev
) | B43_HF_ACPR
);
2327 b43_write16(dev
, B43_MMIO_CHANNEL_EXT
,
2328 b43_read16(dev
, B43_MMIO_CHANNEL_EXT
)
2331 b43_write16(dev
, B43_MMIO_CHANNEL_EXT
,
2332 b43_read16(dev
, B43_MMIO_CHANNEL_EXT
)
2337 static void default_baseband_attenuation(struct b43_wldev
*dev
,
2338 struct b43_bbatt
*bb
)
2340 struct b43_phy
*phy
= &dev
->phy
;
2342 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
< 6)
2348 static void default_radio_attenuation(struct b43_wldev
*dev
,
2349 struct b43_rfatt
*rf
)
2351 struct ssb_bus
*bus
= dev
->dev
->bus
;
2352 struct b43_phy
*phy
= &dev
->phy
;
2354 rf
->with_padmix
= 0;
2356 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
&&
2357 bus
->boardinfo
.type
== SSB_BOARD_BCM4309G
) {
2358 if (bus
->boardinfo
.rev
< 0x43) {
2361 } else if (bus
->boardinfo
.rev
< 0x51) {
2367 if (phy
->type
== B43_PHYTYPE_A
) {
2372 switch (phy
->radio_ver
) {
2374 switch (phy
->radio_rev
) {
2381 switch (phy
->radio_rev
) {
2386 if (phy
->type
== B43_PHYTYPE_G
) {
2387 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
2388 && bus
->boardinfo
.type
== SSB_BOARD_BCM4309G
2389 && bus
->boardinfo
.rev
>= 30)
2391 else if (bus
->boardinfo
.vendor
==
2393 && bus
->boardinfo
.type
==
2399 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
2400 && bus
->boardinfo
.type
== SSB_BOARD_BCM4309G
2401 && bus
->boardinfo
.rev
>= 30)
2408 if (phy
->type
== B43_PHYTYPE_G
) {
2409 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
2410 && bus
->boardinfo
.type
== SSB_BOARD_BCM4309G
2411 && bus
->boardinfo
.rev
>= 30)
2413 else if (bus
->boardinfo
.vendor
==
2415 && bus
->boardinfo
.type
==
2418 else if (bus
->chip_id
== 0x4320)
2438 rf
->with_padmix
= 1;
2449 static u16
default_tx_control(struct b43_wldev
*dev
)
2451 struct b43_phy
*phy
= &dev
->phy
;
2453 if (phy
->radio_ver
!= 0x2050)
2455 if (phy
->radio_rev
== 1)
2456 return B43_TXCTL_PA2DB
| B43_TXCTL_TXMIX
;
2457 if (phy
->radio_rev
< 6)
2458 return B43_TXCTL_PA2DB
;
2459 if (phy
->radio_rev
== 8)
2460 return B43_TXCTL_TXMIX
;
2464 static u8
b43_gphy_aci_detect(struct b43_wldev
*dev
, u8 channel
)
2466 struct b43_phy
*phy
= &dev
->phy
;
2467 struct b43_phy_g
*gphy
= phy
->g
;
2469 u16 saved
, rssi
, temp
;
2472 saved
= b43_phy_read(dev
, 0x0403);
2473 b43_switch_channel(dev
, channel
);
2474 b43_phy_write(dev
, 0x0403, (saved
& 0xFFF8) | 5);
2475 if (gphy
->aci_hw_rssi
)
2476 rssi
= b43_phy_read(dev
, 0x048A) & 0x3F;
2478 rssi
= saved
& 0x3F;
2479 /* clamp temp to signed 5bit */
2482 for (i
= 0; i
< 100; i
++) {
2483 temp
= (b43_phy_read(dev
, 0x047F) >> 8) & 0x3F;
2491 b43_phy_write(dev
, 0x0403, saved
);
2496 static u8
b43_gphy_aci_scan(struct b43_wldev
*dev
)
2498 struct b43_phy
*phy
= &dev
->phy
;
2500 unsigned int channel
= phy
->channel
;
2501 unsigned int i
, j
, start
, end
;
2503 if (!((phy
->type
== B43_PHYTYPE_G
) && (phy
->rev
> 0)))
2507 b43_radio_lock(dev
);
2508 b43_phy_write(dev
, 0x0802, b43_phy_read(dev
, 0x0802) & 0xFFFC);
2509 b43_phy_write(dev
, B43_PHY_G_CRS
,
2510 b43_phy_read(dev
, B43_PHY_G_CRS
) & 0x7FFF);
2511 b43_set_all_gains(dev
, 3, 8, 1);
2513 start
= (channel
- 5 > 0) ? channel
- 5 : 1;
2514 end
= (channel
+ 5 < 14) ? channel
+ 5 : 13;
2516 for (i
= start
; i
<= end
; i
++) {
2517 if (abs(channel
- i
) > 2)
2518 ret
[i
- 1] = b43_gphy_aci_detect(dev
, i
);
2520 b43_switch_channel(dev
, channel
);
2521 b43_phy_write(dev
, 0x0802,
2522 (b43_phy_read(dev
, 0x0802) & 0xFFFC) | 0x0003);
2523 b43_phy_write(dev
, 0x0403, b43_phy_read(dev
, 0x0403) & 0xFFF8);
2524 b43_phy_write(dev
, B43_PHY_G_CRS
,
2525 b43_phy_read(dev
, B43_PHY_G_CRS
) | 0x8000);
2526 b43_set_original_gains(dev
);
2527 for (i
= 0; i
< 13; i
++) {
2530 end
= (i
+ 5 < 13) ? i
+ 5 : 13;
2531 for (j
= i
; j
< end
; j
++)
2534 b43_radio_unlock(dev
);
2535 b43_phy_unlock(dev
);
2537 return ret
[channel
- 1];
2540 static s32
b43_tssi2dbm_ad(s32 num
, s32 den
)
2545 return (num
+ den
/ 2) / den
;
2548 static s8
b43_tssi2dbm_entry(s8 entry
[], u8 index
,
2549 s16 pab0
, s16 pab1
, s16 pab2
)
2551 s32 m1
, m2
, f
= 256, q
, delta
;
2554 m1
= b43_tssi2dbm_ad(16 * pab0
+ index
* pab1
, 32);
2555 m2
= max(b43_tssi2dbm_ad(32768 + index
* pab2
, 256), 1);
2559 q
= b43_tssi2dbm_ad(f
* 4096 -
2560 b43_tssi2dbm_ad(m2
* f
, 16) * f
, 2048);
2564 } while (delta
>= 2);
2565 entry
[index
] = clamp_val(b43_tssi2dbm_ad(m1
* f
, 8192), -127, 128);
2569 u8
* b43_generate_dyn_tssi2dbm_tab(struct b43_wldev
*dev
,
2570 s16 pab0
, s16 pab1
, s16 pab2
)
2576 tab
= kmalloc(64, GFP_KERNEL
);
2578 b43err(dev
->wl
, "Could not allocate memory "
2579 "for tssi2dbm table\n");
2582 for (i
= 0; i
< 64; i
++) {
2583 err
= b43_tssi2dbm_entry(tab
, i
, pab0
, pab1
, pab2
);
2585 b43err(dev
->wl
, "Could not generate "
2586 "tssi2dBm table\n");
2595 /* Initialise the TSSI->dBm lookup table */
2596 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev
*dev
)
2598 struct b43_phy
*phy
= &dev
->phy
;
2599 struct b43_phy_g
*gphy
= phy
->g
;
2600 s16 pab0
, pab1
, pab2
;
2602 pab0
= (s16
) (dev
->dev
->bus
->sprom
.pa0b0
);
2603 pab1
= (s16
) (dev
->dev
->bus
->sprom
.pa0b1
);
2604 pab2
= (s16
) (dev
->dev
->bus
->sprom
.pa0b2
);
2606 B43_WARN_ON((dev
->dev
->bus
->chip_id
== 0x4301) &&
2607 (phy
->radio_ver
!= 0x2050)); /* Not supported anymore */
2609 gphy
->dyn_tssi_tbl
= 0;
2611 if (pab0
!= 0 && pab1
!= 0 && pab2
!= 0 &&
2612 pab0
!= -1 && pab1
!= -1 && pab2
!= -1) {
2613 /* The pabX values are set in SPROM. Use them. */
2614 if ((s8
) dev
->dev
->bus
->sprom
.itssi_bg
!= 0 &&
2615 (s8
) dev
->dev
->bus
->sprom
.itssi_bg
!= -1) {
2616 gphy
->tgt_idle_tssi
=
2617 (s8
) (dev
->dev
->bus
->sprom
.itssi_bg
);
2619 gphy
->tgt_idle_tssi
= 62;
2620 gphy
->tssi2dbm
= b43_generate_dyn_tssi2dbm_tab(dev
, pab0
,
2622 if (!gphy
->tssi2dbm
)
2624 gphy
->dyn_tssi_tbl
= 1;
2626 /* pabX values not set in SPROM. */
2627 gphy
->tgt_idle_tssi
= 52;
2628 gphy
->tssi2dbm
= b43_tssi2dbm_g_table
;
2634 static int b43_gphy_op_allocate(struct b43_wldev
*dev
)
2636 struct b43_phy_g
*gphy
;
2637 struct b43_txpower_lo_control
*lo
;
2640 gphy
= kzalloc(sizeof(*gphy
), GFP_KERNEL
);
2647 lo
= kzalloc(sizeof(*lo
), GFP_KERNEL
);
2652 gphy
->lo_control
= lo
;
2654 err
= b43_gphy_init_tssi2dbm_table(dev
);
2668 static void b43_gphy_op_prepare_structs(struct b43_wldev
*dev
)
2670 struct b43_phy
*phy
= &dev
->phy
;
2671 struct b43_phy_g
*gphy
= phy
->g
;
2672 const void *tssi2dbm
;
2674 struct b43_txpower_lo_control
*lo
;
2677 /* tssi2dbm table is constant, so it is initialized at alloc time.
2678 * Save a copy of the pointer. */
2679 tssi2dbm
= gphy
->tssi2dbm
;
2680 tgt_idle_tssi
= gphy
->tgt_idle_tssi
;
2681 /* Save the LO pointer. */
2682 lo
= gphy
->lo_control
;
2684 /* Zero out the whole PHY structure. */
2685 memset(gphy
, 0, sizeof(*gphy
));
2687 /* Restore pointers. */
2688 gphy
->tssi2dbm
= tssi2dbm
;
2689 gphy
->tgt_idle_tssi
= tgt_idle_tssi
;
2690 gphy
->lo_control
= lo
;
2692 memset(gphy
->minlowsig
, 0xFF, sizeof(gphy
->minlowsig
));
2695 for (i
= 0; i
< ARRAY_SIZE(gphy
->nrssi
); i
++)
2696 gphy
->nrssi
[i
] = -1000;
2697 for (i
= 0; i
< ARRAY_SIZE(gphy
->nrssi_lt
); i
++)
2698 gphy
->nrssi_lt
[i
] = i
;
2700 gphy
->lofcal
= 0xFFFF;
2701 gphy
->initval
= 0xFFFF;
2703 gphy
->interfmode
= B43_INTERFMODE_NONE
;
2705 /* OFDM-table address caching. */
2706 gphy
->ofdmtab_addr_direction
= B43_OFDMTAB_DIRECTION_UNKNOWN
;
2708 gphy
->average_tssi
= 0xFF;
2710 /* Local Osciallator structure */
2712 INIT_LIST_HEAD(&lo
->calib_list
);
2715 static void b43_gphy_op_free(struct b43_wldev
*dev
)
2717 struct b43_phy
*phy
= &dev
->phy
;
2718 struct b43_phy_g
*gphy
= phy
->g
;
2720 kfree(gphy
->lo_control
);
2722 if (gphy
->dyn_tssi_tbl
)
2723 kfree(gphy
->tssi2dbm
);
2724 gphy
->dyn_tssi_tbl
= 0;
2725 gphy
->tssi2dbm
= NULL
;
2731 static int b43_gphy_op_prepare_hardware(struct b43_wldev
*dev
)
2733 struct b43_phy
*phy
= &dev
->phy
;
2734 struct b43_phy_g
*gphy
= phy
->g
;
2735 struct b43_txpower_lo_control
*lo
= gphy
->lo_control
;
2737 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
2739 default_baseband_attenuation(dev
, &gphy
->bbatt
);
2740 default_radio_attenuation(dev
, &gphy
->rfatt
);
2741 gphy
->tx_control
= (default_tx_control(dev
) << 4);
2742 generate_rfatt_list(dev
, &lo
->rfatt_list
);
2743 generate_bbatt_list(dev
, &lo
->bbatt_list
);
2745 /* Commit previous writes */
2746 b43_read32(dev
, B43_MMIO_MACCTL
);
2748 if (phy
->rev
== 1) {
2749 /* Workaround: Temporarly disable gmode through the early init
2750 * phase, as the gmode stuff is not needed for phy rev 1 */
2752 b43_wireless_core_reset(dev
, 0);
2755 b43_wireless_core_reset(dev
, B43_TMSLOW_GMODE
);
2761 static int b43_gphy_op_init(struct b43_wldev
*dev
)
2768 static void b43_gphy_op_exit(struct b43_wldev
*dev
)
2770 b43_lo_g_cleanup(dev
);
2773 static u16
b43_gphy_op_read(struct b43_wldev
*dev
, u16 reg
)
2775 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
2776 return b43_read16(dev
, B43_MMIO_PHY_DATA
);
2779 static void b43_gphy_op_write(struct b43_wldev
*dev
, u16 reg
, u16 value
)
2781 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
2782 b43_write16(dev
, B43_MMIO_PHY_DATA
, value
);
2785 static u16
b43_gphy_op_radio_read(struct b43_wldev
*dev
, u16 reg
)
2787 /* Register 1 is a 32-bit register. */
2788 B43_WARN_ON(reg
== 1);
2789 /* G-PHY needs 0x80 for read access. */
2792 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, reg
);
2793 return b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
2796 static void b43_gphy_op_radio_write(struct b43_wldev
*dev
, u16 reg
, u16 value
)
2798 /* Register 1 is a 32-bit register. */
2799 B43_WARN_ON(reg
== 1);
2801 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, reg
);
2802 b43_write16(dev
, B43_MMIO_RADIO_DATA_LOW
, value
);
2805 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev
*dev
)
2807 return (dev
->phy
.rev
>= 6);
2810 static void b43_gphy_op_software_rfkill(struct b43_wldev
*dev
,
2811 enum rfkill_state state
)
2813 struct b43_phy
*phy
= &dev
->phy
;
2814 struct b43_phy_g
*gphy
= phy
->g
;
2815 unsigned int channel
;
2819 if (state
== RFKILL_STATE_UNBLOCKED
) {
2824 b43_phy_write(dev
, 0x0015, 0x8000);
2825 b43_phy_write(dev
, 0x0015, 0xCC00);
2826 b43_phy_write(dev
, 0x0015, (phy
->gmode
? 0x00C0 : 0x0000));
2827 if (gphy
->radio_off_context
.valid
) {
2828 /* Restore the RFover values. */
2829 b43_phy_write(dev
, B43_PHY_RFOVER
,
2830 gphy
->radio_off_context
.rfover
);
2831 b43_phy_write(dev
, B43_PHY_RFOVERVAL
,
2832 gphy
->radio_off_context
.rfoverval
);
2833 gphy
->radio_off_context
.valid
= 0;
2835 channel
= phy
->channel
;
2836 b43_gphy_channel_switch(dev
, 6, 1);
2837 b43_gphy_channel_switch(dev
, channel
, 0);
2839 /* Turn radio OFF */
2840 u16 rfover
, rfoverval
;
2842 rfover
= b43_phy_read(dev
, B43_PHY_RFOVER
);
2843 rfoverval
= b43_phy_read(dev
, B43_PHY_RFOVERVAL
);
2844 gphy
->radio_off_context
.rfover
= rfover
;
2845 gphy
->radio_off_context
.rfoverval
= rfoverval
;
2846 gphy
->radio_off_context
.valid
= 1;
2847 b43_phy_write(dev
, B43_PHY_RFOVER
, rfover
| 0x008C);
2848 b43_phy_write(dev
, B43_PHY_RFOVERVAL
, rfoverval
& 0xFF73);
2852 static int b43_gphy_op_switch_channel(struct b43_wldev
*dev
,
2853 unsigned int new_channel
)
2855 if ((new_channel
< 1) || (new_channel
> 14))
2857 b43_gphy_channel_switch(dev
, new_channel
, 0);
2862 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev
*dev
)
2864 return 1; /* Default to channel 1 */
2867 static void b43_gphy_op_set_rx_antenna(struct b43_wldev
*dev
, int antenna
)
2869 struct b43_phy
*phy
= &dev
->phy
;
2874 if (antenna
== B43_ANTENNA_AUTO0
|| antenna
== B43_ANTENNA_AUTO1
)
2877 hf
= b43_hf_read(dev
);
2878 hf
&= ~B43_HF_ANTDIVHELP
;
2879 b43_hf_write(dev
, hf
);
2881 tmp
= b43_phy_read(dev
, B43_PHY_BBANDCFG
);
2882 tmp
&= ~B43_PHY_BBANDCFG_RXANT
;
2883 tmp
|= (autodiv
? B43_ANTENNA_AUTO0
: antenna
)
2884 << B43_PHY_BBANDCFG_RXANT_SHIFT
;
2885 b43_phy_write(dev
, B43_PHY_BBANDCFG
, tmp
);
2888 tmp
= b43_phy_read(dev
, B43_PHY_ANTDWELL
);
2889 if (antenna
== B43_ANTENNA_AUTO0
)
2890 tmp
&= ~B43_PHY_ANTDWELL_AUTODIV1
;
2892 tmp
|= B43_PHY_ANTDWELL_AUTODIV1
;
2893 b43_phy_write(dev
, B43_PHY_ANTDWELL
, tmp
);
2895 tmp
= b43_phy_read(dev
, B43_PHY_ANTWRSETT
);
2897 tmp
|= B43_PHY_ANTWRSETT_ARXDIV
;
2899 tmp
&= ~B43_PHY_ANTWRSETT_ARXDIV
;
2900 b43_phy_write(dev
, B43_PHY_ANTWRSETT
, tmp
);
2901 if (phy
->rev
>= 2) {
2902 tmp
= b43_phy_read(dev
, B43_PHY_OFDM61
);
2903 tmp
|= B43_PHY_OFDM61_10
;
2904 b43_phy_write(dev
, B43_PHY_OFDM61
, tmp
);
2907 b43_phy_read(dev
, B43_PHY_DIVSRCHGAINBACK
);
2908 tmp
= (tmp
& 0xFF00) | 0x15;
2909 b43_phy_write(dev
, B43_PHY_DIVSRCHGAINBACK
,
2912 if (phy
->rev
== 2) {
2913 b43_phy_write(dev
, B43_PHY_ADIVRELATED
,
2918 B43_PHY_ADIVRELATED
);
2919 tmp
= (tmp
& 0xFF00) | 8;
2920 b43_phy_write(dev
, B43_PHY_ADIVRELATED
,
2925 b43_phy_write(dev
, B43_PHY_OFDM9B
, 0xDC);
2927 hf
|= B43_HF_ANTDIVHELP
;
2928 b43_hf_write(dev
, hf
);
2931 static int b43_gphy_op_interf_mitigation(struct b43_wldev
*dev
,
2932 enum b43_interference_mitigation mode
)
2934 struct b43_phy
*phy
= &dev
->phy
;
2935 struct b43_phy_g
*gphy
= phy
->g
;
2938 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
2939 if ((phy
->rev
== 0) || (!phy
->gmode
))
2942 gphy
->aci_wlan_automatic
= 0;
2944 case B43_INTERFMODE_AUTOWLAN
:
2945 gphy
->aci_wlan_automatic
= 1;
2946 if (gphy
->aci_enable
)
2947 mode
= B43_INTERFMODE_MANUALWLAN
;
2949 mode
= B43_INTERFMODE_NONE
;
2951 case B43_INTERFMODE_NONE
:
2952 case B43_INTERFMODE_NONWLAN
:
2953 case B43_INTERFMODE_MANUALWLAN
:
2959 currentmode
= gphy
->interfmode
;
2960 if (currentmode
== mode
)
2962 if (currentmode
!= B43_INTERFMODE_NONE
)
2963 b43_radio_interference_mitigation_disable(dev
, currentmode
);
2965 if (mode
== B43_INTERFMODE_NONE
) {
2966 gphy
->aci_enable
= 0;
2967 gphy
->aci_hw_rssi
= 0;
2969 b43_radio_interference_mitigation_enable(dev
, mode
);
2970 gphy
->interfmode
= mode
;
2975 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
2976 * This function converts a TSSI value to dBm in Q5.2
2978 static s8
b43_gphy_estimate_power_out(struct b43_wldev
*dev
, s8 tssi
)
2980 struct b43_phy_g
*gphy
= dev
->phy
.g
;
2984 tmp
= (gphy
->tgt_idle_tssi
- gphy
->cur_idle_tssi
+ tssi
);
2985 tmp
= clamp_val(tmp
, 0x00, 0x3F);
2986 dbm
= gphy
->tssi2dbm
[tmp
];
2991 static void b43_put_attenuation_into_ranges(struct b43_wldev
*dev
,
2992 int *_bbatt
, int *_rfatt
)
2994 int rfatt
= *_rfatt
;
2995 int bbatt
= *_bbatt
;
2996 struct b43_txpower_lo_control
*lo
= dev
->phy
.g
->lo_control
;
2998 /* Get baseband and radio attenuation values into their permitted ranges.
2999 * Radio attenuation affects power level 4 times as much as baseband. */
3001 /* Range constants */
3002 const int rf_min
= lo
->rfatt_list
.min_val
;
3003 const int rf_max
= lo
->rfatt_list
.max_val
;
3004 const int bb_min
= lo
->bbatt_list
.min_val
;
3005 const int bb_max
= lo
->bbatt_list
.max_val
;
3008 if (rfatt
> rf_max
&& bbatt
> bb_max
- 4)
3009 break; /* Can not get it into ranges */
3010 if (rfatt
< rf_min
&& bbatt
< bb_min
+ 4)
3011 break; /* Can not get it into ranges */
3012 if (bbatt
> bb_max
&& rfatt
> rf_max
- 1)
3013 break; /* Can not get it into ranges */
3014 if (bbatt
< bb_min
&& rfatt
< rf_min
+ 1)
3015 break; /* Can not get it into ranges */
3017 if (bbatt
> bb_max
) {
3022 if (bbatt
< bb_min
) {
3027 if (rfatt
> rf_max
) {
3032 if (rfatt
< rf_min
) {
3040 *_rfatt
= clamp_val(rfatt
, rf_min
, rf_max
);
3041 *_bbatt
= clamp_val(bbatt
, bb_min
, bb_max
);
3044 static void b43_gphy_op_adjust_txpower(struct b43_wldev
*dev
)
3046 struct b43_phy
*phy
= &dev
->phy
;
3047 struct b43_phy_g
*gphy
= phy
->g
;
3051 spin_lock_irq(&dev
->wl
->irq_lock
);
3053 /* Calculate the new attenuation values. */
3054 bbatt
= gphy
->bbatt
.att
;
3055 bbatt
+= gphy
->bbatt_delta
;
3056 rfatt
= gphy
->rfatt
.att
;
3057 rfatt
+= gphy
->rfatt_delta
;
3059 b43_put_attenuation_into_ranges(dev
, &bbatt
, &rfatt
);
3060 tx_control
= gphy
->tx_control
;
3061 if ((phy
->radio_ver
== 0x2050) && (phy
->radio_rev
== 2)) {
3063 if (tx_control
== 0) {
3069 } else if (dev
->dev
->bus
->sprom
.
3072 bbatt
+= 4 * (rfatt
- 2);
3075 } else if (rfatt
> 4 && tx_control
) {
3086 /* Save the control values */
3087 gphy
->tx_control
= tx_control
;
3088 b43_put_attenuation_into_ranges(dev
, &bbatt
, &rfatt
);
3089 gphy
->rfatt
.att
= rfatt
;
3090 gphy
->bbatt
.att
= bbatt
;
3092 /* We drop the lock early, so we can sleep during hardware
3093 * adjustment. Possible races with op_recalc_txpower are harmless,
3094 * as we will be called once again in case we raced. */
3095 spin_unlock_irq(&dev
->wl
->irq_lock
);
3097 if (b43_debug(dev
, B43_DBG_XMITPOWER
))
3098 b43dbg(dev
->wl
, "Adjusting TX power\n");
3100 /* Adjust the hardware */
3102 b43_radio_lock(dev
);
3103 b43_set_txpower_g(dev
, &gphy
->bbatt
, &gphy
->rfatt
,
3105 b43_radio_unlock(dev
);
3106 b43_phy_unlock(dev
);
3109 static enum b43_txpwr_result
b43_gphy_op_recalc_txpower(struct b43_wldev
*dev
,
3112 struct b43_phy
*phy
= &dev
->phy
;
3113 struct b43_phy_g
*gphy
= phy
->g
;
3114 unsigned int average_tssi
;
3115 int cck_result
, ofdm_result
;
3116 int estimated_pwr
, desired_pwr
, pwr_adjust
;
3117 int rfatt_delta
, bbatt_delta
;
3118 unsigned int max_pwr
;
3120 /* First get the average TSSI */
3121 cck_result
= b43_phy_shm_tssi_read(dev
, B43_SHM_SH_TSSI_CCK
);
3122 ofdm_result
= b43_phy_shm_tssi_read(dev
, B43_SHM_SH_TSSI_OFDM_G
);
3123 if ((cck_result
< 0) && (ofdm_result
< 0)) {
3124 /* No TSSI information available */
3126 goto no_adjustment_needed
;
3131 average_tssi
= ofdm_result
;
3132 else if (ofdm_result
< 0)
3133 average_tssi
= cck_result
;
3135 average_tssi
= (cck_result
+ ofdm_result
) / 2;
3136 /* Merge the average with the stored value. */
3137 if (likely(gphy
->average_tssi
!= 0xFF))
3138 average_tssi
= (average_tssi
+ gphy
->average_tssi
) / 2;
3139 gphy
->average_tssi
= average_tssi
;
3140 B43_WARN_ON(average_tssi
>= B43_TSSI_MAX
);
3142 /* Estimate the TX power emission based on the TSSI */
3143 estimated_pwr
= b43_gphy_estimate_power_out(dev
, average_tssi
);
3145 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
3146 max_pwr
= dev
->dev
->bus
->sprom
.maxpwr_bg
;
3147 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_PACTRL
)
3148 max_pwr
-= 3; /* minus 0.75 */
3149 if (unlikely(max_pwr
>= INT_TO_Q52(30/*dBm*/))) {
3151 "Invalid max-TX-power value in SPROM.\n");
3152 max_pwr
= INT_TO_Q52(20); /* fake it */
3153 dev
->dev
->bus
->sprom
.maxpwr_bg
= max_pwr
;
3156 /* Get desired power (in Q5.2) */
3157 if (phy
->desired_txpower
< 0)
3158 desired_pwr
= INT_TO_Q52(0);
3160 desired_pwr
= INT_TO_Q52(phy
->desired_txpower
);
3161 /* And limit it. max_pwr already is Q5.2 */
3162 desired_pwr
= clamp_val(desired_pwr
, 0, max_pwr
);
3163 if (b43_debug(dev
, B43_DBG_XMITPOWER
)) {
3165 "[TX power] current = " Q52_FMT
3166 " dBm, desired = " Q52_FMT
3167 " dBm, max = " Q52_FMT
"\n",
3168 Q52_ARG(estimated_pwr
),
3169 Q52_ARG(desired_pwr
),
3173 /* Calculate the adjustment delta. */
3174 pwr_adjust
= desired_pwr
- estimated_pwr
;
3175 if (pwr_adjust
== 0)
3176 goto no_adjustment_needed
;
3178 /* RF attenuation delta. */
3179 rfatt_delta
= ((pwr_adjust
+ 7) / 8);
3180 /* Lower attenuation => Bigger power output. Negate it. */
3181 rfatt_delta
= -rfatt_delta
;
3183 /* Baseband attenuation delta. */
3184 bbatt_delta
= pwr_adjust
/ 2;
3185 /* Lower attenuation => Bigger power output. Negate it. */
3186 bbatt_delta
= -bbatt_delta
;
3187 /* RF att affects power level 4 times as much as
3188 * Baseband attennuation. Subtract it. */
3189 bbatt_delta
-= 4 * rfatt_delta
;
3191 if (b43_debug(dev
, B43_DBG_XMITPOWER
)) {
3192 int dbm
= pwr_adjust
< 0 ? -pwr_adjust
: pwr_adjust
;
3194 "[TX power deltas] %s" Q52_FMT
" dBm => "
3195 "bbatt-delta = %d, rfatt-delta = %d\n",
3196 (pwr_adjust
< 0 ? "-" : ""), Q52_ARG(dbm
),
3197 bbatt_delta
, rfatt_delta
);
3199 /* So do we finally need to adjust something in hardware? */
3200 if ((rfatt_delta
== 0) && (bbatt_delta
== 0))
3201 goto no_adjustment_needed
;
3203 /* Save the deltas for later when we adjust the power. */
3204 gphy
->bbatt_delta
= bbatt_delta
;
3205 gphy
->rfatt_delta
= rfatt_delta
;
3207 /* We need to adjust the TX power on the device. */
3208 return B43_TXPWR_RES_NEED_ADJUST
;
3210 no_adjustment_needed
:
3211 return B43_TXPWR_RES_DONE
;
3214 static void b43_gphy_op_pwork_15sec(struct b43_wldev
*dev
)
3216 struct b43_phy
*phy
= &dev
->phy
;
3217 struct b43_phy_g
*gphy
= phy
->g
;
3219 //TODO: update_aci_moving_average
3220 if (gphy
->aci_enable
&& gphy
->aci_wlan_automatic
) {
3221 b43_mac_suspend(dev
);
3222 if (!gphy
->aci_enable
&& 1 /*TODO: not scanning? */ ) {
3223 if (0 /*TODO: bunch of conditions */ ) {
3224 phy
->ops
->interf_mitigation(dev
,
3225 B43_INTERFMODE_MANUALWLAN
);
3227 } else if (0 /*TODO*/) {
3228 if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev
))
3229 phy
->ops
->interf_mitigation(dev
, B43_INTERFMODE_NONE
);
3231 b43_mac_enable(dev
);
3232 } else if (gphy
->interfmode
== B43_INTERFMODE_NONWLAN
&&
3234 //TODO: implement rev1 workaround
3236 b43_lo_g_maintanance_work(dev
);
3239 static void b43_gphy_op_pwork_60sec(struct b43_wldev
*dev
)
3241 struct b43_phy
*phy
= &dev
->phy
;
3243 if (!(dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_RSSI
))
3246 b43_mac_suspend(dev
);
3247 b43_calc_nrssi_slope(dev
);
3248 if ((phy
->radio_ver
== 0x2050) && (phy
->radio_rev
== 8)) {
3249 u8 old_chan
= phy
->channel
;
3251 /* VCO Calibration */
3253 b43_switch_channel(dev
, 1);
3255 b43_switch_channel(dev
, 13);
3256 b43_switch_channel(dev
, old_chan
);
3258 b43_mac_enable(dev
);
3261 const struct b43_phy_operations b43_phyops_g
= {
3262 .allocate
= b43_gphy_op_allocate
,
3263 .free
= b43_gphy_op_free
,
3264 .prepare_structs
= b43_gphy_op_prepare_structs
,
3265 .prepare_hardware
= b43_gphy_op_prepare_hardware
,
3266 .init
= b43_gphy_op_init
,
3267 .exit
= b43_gphy_op_exit
,
3268 .phy_read
= b43_gphy_op_read
,
3269 .phy_write
= b43_gphy_op_write
,
3270 .radio_read
= b43_gphy_op_radio_read
,
3271 .radio_write
= b43_gphy_op_radio_write
,
3272 .supports_hwpctl
= b43_gphy_op_supports_hwpctl
,
3273 .software_rfkill
= b43_gphy_op_software_rfkill
,
3274 .switch_channel
= b43_gphy_op_switch_channel
,
3275 .get_default_chan
= b43_gphy_op_get_default_chan
,
3276 .set_rx_antenna
= b43_gphy_op_set_rx_antenna
,
3277 .interf_mitigation
= b43_gphy_op_interf_mitigation
,
3278 .recalc_txpower
= b43_gphy_op_recalc_txpower
,
3279 .adjust_txpower
= b43_gphy_op_adjust_txpower
,
3280 .pwork_15sec
= b43_gphy_op_pwork_15sec
,
3281 .pwork_60sec
= b43_gphy_op_pwork_60sec
,