projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
brcmfmac: Add support for the BCM4350 PCIE device.
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / chip.c
1 /*
2 * Copyright (c) 2014 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/list.h>
19 #include <linux/ssb/ssb_regs.h>
20 #include <linux/bcma/bcma.h>
21 #include <linux/bcma/bcma_regs.h>
22
23 #include <defs.h>
24 #include <soc.h>
25 #include <brcm_hw_ids.h>
26 #include <brcmu_utils.h>
27 #include <chipcommon.h>
28 #include "debug.h"
29 #include "chip.h"
30
31 /* SOC Interconnect types (aka chip types) */
32 #define SOCI_SB 0
33 #define SOCI_AI 1
34
35 /* PL-368 DMP definitions */
36 #define DMP_DESC_TYPE_MSK 0x0000000F
37 #define DMP_DESC_EMPTY 0x00000000
38 #define DMP_DESC_VALID 0x00000001
39 #define DMP_DESC_COMPONENT 0x00000001
40 #define DMP_DESC_MASTER_PORT 0x00000003
41 #define DMP_DESC_ADDRESS 0x00000005
42 #define DMP_DESC_ADDRSIZE_GT32 0x00000008
43 #define DMP_DESC_EOT 0x0000000F
44
45 #define DMP_COMP_DESIGNER 0xFFF00000
46 #define DMP_COMP_DESIGNER_S 20
47 #define DMP_COMP_PARTNUM 0x000FFF00
48 #define DMP_COMP_PARTNUM_S 8
49 #define DMP_COMP_CLASS 0x000000F0
50 #define DMP_COMP_CLASS_S 4
51 #define DMP_COMP_REVISION 0xFF000000
52 #define DMP_COMP_REVISION_S 24
53 #define DMP_COMP_NUM_SWRAP 0x00F80000
54 #define DMP_COMP_NUM_SWRAP_S 19
55 #define DMP_COMP_NUM_MWRAP 0x0007C000
56 #define DMP_COMP_NUM_MWRAP_S 14
57 #define DMP_COMP_NUM_SPORT 0x00003E00
58 #define DMP_COMP_NUM_SPORT_S 9
59 #define DMP_COMP_NUM_MPORT 0x000001F0
60 #define DMP_COMP_NUM_MPORT_S 4
61
62 #define DMP_MASTER_PORT_UID 0x0000FF00
63 #define DMP_MASTER_PORT_UID_S 8
64 #define DMP_MASTER_PORT_NUM 0x000000F0
65 #define DMP_MASTER_PORT_NUM_S 4
66
67 #define DMP_SLAVE_ADDR_BASE 0xFFFFF000
68 #define DMP_SLAVE_ADDR_BASE_S 12
69 #define DMP_SLAVE_PORT_NUM 0x00000F00
70 #define DMP_SLAVE_PORT_NUM_S 8
71 #define DMP_SLAVE_TYPE 0x000000C0
72 #define DMP_SLAVE_TYPE_S 6
73 #define DMP_SLAVE_TYPE_SLAVE 0
74 #define DMP_SLAVE_TYPE_BRIDGE 1
75 #define DMP_SLAVE_TYPE_SWRAP 2
76 #define DMP_SLAVE_TYPE_MWRAP 3
77 #define DMP_SLAVE_SIZE_TYPE 0x00000030
78 #define DMP_SLAVE_SIZE_TYPE_S 4
79 #define DMP_SLAVE_SIZE_4K 0
80 #define DMP_SLAVE_SIZE_8K 1
81 #define DMP_SLAVE_SIZE_16K 2
82 #define DMP_SLAVE_SIZE_DESC 3
83
84 /* EROM CompIdentB */
85 #define CIB_REV_MASK 0xff000000
86 #define CIB_REV_SHIFT 24
87
88 /* ARM CR4 core specific control flag bits */
89 #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
90
91 /* D11 core specific control flag bits */
92 #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
93 #define D11_BCMA_IOCTL_PHYRESET 0x0008
94
95 /* chip core base & ramsize */
96 /* bcm4329 */
97 /* SDIO device core, ID 0x829 */
98 #define BCM4329_CORE_BUS_BASE 0x18011000
99 /* internal memory core, ID 0x80e */
100 #define BCM4329_CORE_SOCRAM_BASE 0x18003000
101 /* ARM Cortex M3 core, ID 0x82a */
102 #define BCM4329_CORE_ARM_BASE 0x18002000
103
104 /* Max possibly supported memory size (limited by IO mapped memory) */
105 #define BRCMF_CHIP_MAX_MEMSIZE (4 * 1024 * 1024)
106
107 #define CORE_SB(base, field) \
108 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
109 #define SBCOREREV(sbidh) \
110 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
111 ((sbidh) & SSB_IDHIGH_RCLO))
112
113 struct sbconfig {
114 u32 PAD[2];
115 u32 sbipsflag; /* initiator port ocp slave flag */
116 u32 PAD[3];
117 u32 sbtpsflag; /* target port ocp slave flag */
118 u32 PAD[11];
119 u32 sbtmerrloga; /* (sonics >= 2.3) */
120 u32 PAD;
121 u32 sbtmerrlog; /* (sonics >= 2.3) */
122 u32 PAD[3];
123 u32 sbadmatch3; /* address match3 */
124 u32 PAD;
125 u32 sbadmatch2; /* address match2 */
126 u32 PAD;
127 u32 sbadmatch1; /* address match1 */
128 u32 PAD[7];
129 u32 sbimstate; /* initiator agent state */
130 u32 sbintvec; /* interrupt mask */
131 u32 sbtmstatelow; /* target state */
132 u32 sbtmstatehigh; /* target state */
133 u32 sbbwa0; /* bandwidth allocation table0 */
134 u32 PAD;
135 u32 sbimconfiglow; /* initiator configuration */
136 u32 sbimconfighigh; /* initiator configuration */
137 u32 sbadmatch0; /* address match0 */
138 u32 PAD;
139 u32 sbtmconfiglow; /* target configuration */
140 u32 sbtmconfighigh; /* target configuration */
141 u32 sbbconfig; /* broadcast configuration */
142 u32 PAD;
143 u32 sbbstate; /* broadcast state */
144 u32 PAD[3];
145 u32 sbactcnfg; /* activate configuration */
146 u32 PAD[3];
147 u32 sbflagst; /* current sbflags */
148 u32 PAD[3];
149 u32 sbidlow; /* identification */
150 u32 sbidhigh; /* identification */
151 };
152
153 /* bankidx and bankinfo reg defines corerev >= 8 */
154 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
155 #define SOCRAM_BANKINFO_SZMASK 0x0000007f
156 #define SOCRAM_BANKIDX_ROM_MASK 0x00000100
157
158 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
159 /* socram bankinfo memtype */
160 #define SOCRAM_MEMTYPE_RAM 0
161 #define SOCRAM_MEMTYPE_R0M 1
162 #define SOCRAM_MEMTYPE_DEVRAM 2
163
164 #define SOCRAM_BANKINFO_SZBASE 8192
165 #define SRCI_LSS_MASK 0x00f00000
166 #define SRCI_LSS_SHIFT 20
167 #define SRCI_SRNB_MASK 0xf0
168 #define SRCI_SRNB_SHIFT 4
169 #define SRCI_SRBSZ_MASK 0xf
170 #define SRCI_SRBSZ_SHIFT 0
171 #define SR_BSZ_BASE 14
172
173 struct sbsocramregs {
174 u32 coreinfo;
175 u32 bwalloc;
176 u32 extracoreinfo;
177 u32 biststat;
178 u32 bankidx;
179 u32 standbyctrl;
180
181 u32 errlogstatus; /* rev 6 */
182 u32 errlogaddr; /* rev 6 */
183 /* used for patching rev 3 & 5 */
184 u32 cambankidx;
185 u32 cambankstandbyctrl;
186 u32 cambankpatchctrl;
187 u32 cambankpatchtblbaseaddr;
188 u32 cambankcmdreg;
189 u32 cambankdatareg;
190 u32 cambankmaskreg;
191 u32 PAD[1];
192 u32 bankinfo; /* corev 8 */
193 u32 bankpda;
194 u32 PAD[14];
195 u32 extmemconfig;
196 u32 extmemparitycsr;
197 u32 extmemparityerrdata;
198 u32 extmemparityerrcnt;
199 u32 extmemwrctrlandsize;
200 u32 PAD[84];
201 u32 workaround;
202 u32 pwrctl; /* corerev >= 2 */
203 u32 PAD[133];
204 u32 sr_control; /* corerev >= 15 */
205 u32 sr_status; /* corerev >= 15 */
206 u32 sr_address; /* corerev >= 15 */
207 u32 sr_data; /* corerev >= 15 */
208 };
209
210 #define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
211
212 #define ARMCR4_CAP (0x04)
213 #define ARMCR4_BANKIDX (0x40)
214 #define ARMCR4_BANKINFO (0x44)
215 #define ARMCR4_BANKPDA (0x4C)
216
217 #define ARMCR4_TCBBNB_MASK 0xf0
218 #define ARMCR4_TCBBNB_SHIFT 4
219 #define ARMCR4_TCBANB_MASK 0xf
220 #define ARMCR4_TCBANB_SHIFT 0
221
222 #define ARMCR4_BSZ_MASK 0x3f
223 #define ARMCR4_BSZ_MULT 8192
224
225 struct brcmf_core_priv {
226 struct brcmf_core pub;
227 u32 wrapbase;
228 struct list_head list;
229 struct brcmf_chip_priv *chip;
230 };
231
232 struct brcmf_chip_priv {
233 struct brcmf_chip pub;
234 const struct brcmf_buscore_ops *ops;
235 void *ctx;
236 /* assured first core is chipcommon, second core is buscore */
237 struct list_head cores;
238 u16 num_cores;
239
240 bool (*iscoreup)(struct brcmf_core_priv *core);
241 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
242 u32 reset);
243 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
244 u32 postreset);
245 };
246
247 static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
248 struct brcmf_core *core)
249 {
250 u32 regdata;
251
252 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
253 core->rev = SBCOREREV(regdata);
254 }
255
256 static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
257 {
258 struct brcmf_chip_priv *ci;
259 u32 regdata;
260 u32 address;
261
262 ci = core->chip;
263 address = CORE_SB(core->pub.base, sbtmstatelow);
264 regdata = ci->ops->read32(ci->ctx, address);
265 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
266 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
267 return SSB_TMSLOW_CLOCK == regdata;
268 }
269
270 static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
271 {
272 struct brcmf_chip_priv *ci;
273 u32 regdata;
274 bool ret;
275
276 ci = core->chip;
277 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
278 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
279
280 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
281 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
282
283 return ret;
284 }
285
286 static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
287 u32 prereset, u32 reset)
288 {
289 struct brcmf_chip_priv *ci;
290 u32 val, base;
291
292 ci = core->chip;
293 base = core->pub.base;
294 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
295 if (val & SSB_TMSLOW_RESET)
296 return;
297
298 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
299 if ((val & SSB_TMSLOW_CLOCK) != 0) {
300 /*
301 * set target reject and spin until busy is clear
302 * (preserve core-specific bits)
303 */
304 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
305 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
306 val | SSB_TMSLOW_REJECT);
307
308 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
309 udelay(1);
310 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
311 & SSB_TMSHIGH_BUSY), 100000);
312
313 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
314 if (val & SSB_TMSHIGH_BUSY)
315 brcmf_err("core state still busy\n");
316
317 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
318 if (val & SSB_IDLOW_INITIATOR) {
319 val = ci->ops->read32(ci->ctx,
320 CORE_SB(base, sbimstate));
321 val |= SSB_IMSTATE_REJECT;
322 ci->ops->write32(ci->ctx,
323 CORE_SB(base, sbimstate), val);
324 val = ci->ops->read32(ci->ctx,
325 CORE_SB(base, sbimstate));
326 udelay(1);
327 SPINWAIT((ci->ops->read32(ci->ctx,
328 CORE_SB(base, sbimstate)) &
329 SSB_IMSTATE_BUSY), 100000);
330 }
331
332 /* set reset and reject while enabling the clocks */
333 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
334 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
335 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
336 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
337 udelay(10);
338
339 /* clear the initiator reject bit */
340 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
341 if (val & SSB_IDLOW_INITIATOR) {
342 val = ci->ops->read32(ci->ctx,
343 CORE_SB(base, sbimstate));
344 val &= ~SSB_IMSTATE_REJECT;
345 ci->ops->write32(ci->ctx,
346 CORE_SB(base, sbimstate), val);
347 }
348 }
349
350 /* leave reset and reject asserted */
351 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
352 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
353 udelay(1);
354 }
355
356 static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
357 u32 prereset, u32 reset)
358 {
359 struct brcmf_chip_priv *ci;
360 u32 regdata;
361
362 ci = core->chip;
363
364 /* if core is already in reset, skip reset */
365 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
366 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
367 goto in_reset_configure;
368
369 /* configure reset */
370 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
371 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
372 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
373
374 /* put in reset */
375 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
376 BCMA_RESET_CTL_RESET);
377 usleep_range(10, 20);
378
379 /* wait till reset is 1 */
380 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
381 BCMA_RESET_CTL_RESET, 300);
382
383 in_reset_configure:
384 /* in-reset configure */
385 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
386 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
387 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
388 }
389
390 static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
391 u32 reset, u32 postreset)
392 {
393 struct brcmf_chip_priv *ci;
394 u32 regdata;
395 u32 base;
396
397 ci = core->chip;
398 base = core->pub.base;
399 /*
400 * Must do the disable sequence first to work for
401 * arbitrary current core state.
402 */
403 brcmf_chip_sb_coredisable(core, 0, 0);
404
405 /*
406 * Now do the initialization sequence.
407 * set reset while enabling the clock and
408 * forcing them on throughout the core
409 */
410 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
411 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
412 SSB_TMSLOW_RESET);
413 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
414 udelay(1);
415
416 /* clear any serror */
417 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
418 if (regdata & SSB_TMSHIGH_SERR)
419 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
420
421 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
422 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
423 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
424 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
425 }
426
427 /* clear reset and allow it to propagate throughout the core */
428 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
429 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
430 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
431 udelay(1);
432
433 /* leave clock enabled */
434 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
435 SSB_TMSLOW_CLOCK);
436 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
437 udelay(1);
438 }
439
440 static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
441 u32 reset, u32 postreset)
442 {
443 struct brcmf_chip_priv *ci;
444 int count;
445
446 ci = core->chip;
447
448 /* must disable first to work for arbitrary current core state */
449 brcmf_chip_ai_coredisable(core, prereset, reset);
450
451 count = 0;
452 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
453 BCMA_RESET_CTL_RESET) {
454 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
455 count++;
456 if (count > 50)
457 break;
458 usleep_range(40, 60);
459 }
460
461 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
462 postreset | BCMA_IOCTL_CLK);
463 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
464 }
465
466 static char *brcmf_chip_name(uint chipid, char *buf, uint len)
467 {
468 const char *fmt;
469
470 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
471 snprintf(buf, len, fmt, chipid);
472 return buf;
473 }
474
475 static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
476 u16 coreid, u32 base,
477 u32 wrapbase)
478 {
479 struct brcmf_core_priv *core;
480
481 core = kzalloc(sizeof(*core), GFP_KERNEL);
482 if (!core)
483 return ERR_PTR(-ENOMEM);
484
485 core->pub.id = coreid;
486 core->pub.base = base;
487 core->chip = ci;
488 core->wrapbase = wrapbase;
489
490 list_add_tail(&core->list, &ci->cores);
491 return &core->pub;
492 }
493
494 /* safety check for chipinfo */
495 static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
496 {
497 struct brcmf_core_priv *core;
498 bool need_socram = false;
499 bool has_socram = false;
500 bool cpu_found = false;
501 int idx = 1;
502
503 list_for_each_entry(core, &ci->cores, list) {
504 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
505 idx++, core->pub.id, core->pub.rev, core->pub.base,
506 core->wrapbase);
507
508 switch (core->pub.id) {
509 case BCMA_CORE_ARM_CM3:
510 cpu_found = true;
511 need_socram = true;
512 break;
513 case BCMA_CORE_INTERNAL_MEM:
514 has_socram = true;
515 break;
516 case BCMA_CORE_ARM_CR4:
517 cpu_found = true;
518 break;
519 default:
520 break;
521 }
522 }
523
524 if (!cpu_found) {
525 brcmf_err("CPU core not detected\n");
526 return -ENXIO;
527 }
528 /* check RAM core presence for ARM CM3 core */
529 if (need_socram && !has_socram) {
530 brcmf_err("RAM core not provided with ARM CM3 core\n");
531 return -ENODEV;
532 }
533 return 0;
534 }
535
536 static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg)
537 {
538 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
539 }
540
541 static void brcmf_chip_core_write32(struct brcmf_core_priv *core,
542 u16 reg, u32 val)
543 {
544 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
545 }
546
547 static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx,
548 u32 *banksize)
549 {
550 u32 bankinfo;
551 u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
552
553 bankidx |= idx;
554 brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx);
555 bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo));
556 *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1;
557 *banksize *= SOCRAM_BANKINFO_SZBASE;
558 return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK);
559 }
560
561 static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
562 u32 *srsize)
563 {
564 u32 coreinfo;
565 uint nb, banksize, lss;
566 bool retent;
567 int i;
568
569 *ramsize = 0;
570 *srsize = 0;
571
572 if (WARN_ON(sr->pub.rev < 4))
573 return;
574
575 if (!brcmf_chip_iscoreup(&sr->pub))
576 brcmf_chip_resetcore(&sr->pub, 0, 0, 0);
577
578 /* Get info for determining size */
579 coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo));
580 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
581
582 if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) {
583 banksize = (coreinfo & SRCI_SRBSZ_MASK);
584 lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
585 if (lss != 0)
586 nb--;
587 *ramsize = nb * (1 << (banksize + SR_BSZ_BASE));
588 if (lss != 0)
589 *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
590 } else {
591 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
592 for (i = 0; i < nb; i++) {
593 retent = brcmf_chip_socram_banksize(sr, i, &banksize);
594 *ramsize += banksize;
595 if (retent)
596 *srsize += banksize;
597 }
598 }
599
600 /* hardcoded save&restore memory sizes */
601 switch (sr->chip->pub.chip) {
602 case BRCM_CC_4334_CHIP_ID:
603 if (sr->chip->pub.chiprev < 2)
604 *srsize = (32 * 1024);
605 break;
606 case BRCM_CC_43430_CHIP_ID:
607 /* assume sr for now as we can not check
608 * firmware sr capability at this point.
609 */
610 *srsize = (64 * 1024);
611 break;
612 default:
613 break;
614 }
615 }
616
617 /** Return the TCM-RAM size of the ARMCR4 core. */
618 static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
619 {
620 u32 corecap;
621 u32 memsize = 0;
622 u32 nab;
623 u32 nbb;
624 u32 totb;
625 u32 bxinfo;
626 u32 idx;
627
628 corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
629
630 nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
631 nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
632 totb = nab + nbb;
633
634 for (idx = 0; idx < totb; idx++) {
635 brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
636 bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
637 memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
638 }
639
640 return memsize;
641 }
642
643 static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
644 {
645 switch (ci->pub.chip) {
646 case BRCM_CC_4345_CHIP_ID:
647 return 0x198000;
648 case BRCM_CC_4335_CHIP_ID:
649 case BRCM_CC_4339_CHIP_ID:
650 case BRCM_CC_4350_CHIP_ID:
651 case BRCM_CC_4354_CHIP_ID:
652 case BRCM_CC_4356_CHIP_ID:
653 case BRCM_CC_43567_CHIP_ID:
654 case BRCM_CC_43569_CHIP_ID:
655 case BRCM_CC_43570_CHIP_ID:
656 case BRCM_CC_4358_CHIP_ID:
657 case BRCM_CC_43602_CHIP_ID:
658 return 0x180000;
659 default:
660 brcmf_err("unknown chip: %s\n", ci->pub.name);
661 break;
662 }
663 return 0;
664 }
665
666 static int brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
667 {
668 struct brcmf_core_priv *mem_core;
669 struct brcmf_core *mem;
670
671 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
672 if (mem) {
673 mem_core = container_of(mem, struct brcmf_core_priv, pub);
674 ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
675 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
676 if (!ci->pub.rambase) {
677 brcmf_err("RAM base not provided with ARM CR4 core\n");
678 return -EINVAL;
679 }
680 } else {
681 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_INTERNAL_MEM);
682 mem_core = container_of(mem, struct brcmf_core_priv, pub);
683 brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
684 &ci->pub.srsize);
685 }
686 brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n",
687 ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
688 ci->pub.srsize, ci->pub.srsize);
689
690 if (!ci->pub.ramsize) {
691 brcmf_err("RAM size is undetermined\n");
692 return -ENOMEM;
693 }
694
695 if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) {
696 brcmf_err("RAM size is incorrect\n");
697 return -ENOMEM;
698 }
699
700 return 0;
701 }
702
703 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
704 u8 *type)
705 {
706 u32 val;
707
708 /* read next descriptor */
709 val = ci->ops->read32(ci->ctx, *eromaddr);
710 *eromaddr += 4;
711
712 if (!type)
713 return val;
714
715 /* determine descriptor type */
716 *type = (val & DMP_DESC_TYPE_MSK);
717 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
718 *type = DMP_DESC_ADDRESS;
719
720 return val;
721 }
722
723 static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
724 u32 *regbase, u32 *wrapbase)
725 {
726 u8 desc;
727 u32 val;
728 u8 mpnum = 0;
729 u8 stype, sztype, wraptype;
730
731 *regbase = 0;
732 *wrapbase = 0;
733
734 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
735 if (desc == DMP_DESC_MASTER_PORT) {
736 mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
737 wraptype = DMP_SLAVE_TYPE_MWRAP;
738 } else if (desc == DMP_DESC_ADDRESS) {
739 /* revert erom address */
740 *eromaddr -= 4;
741 wraptype = DMP_SLAVE_TYPE_SWRAP;
742 } else {
743 *eromaddr -= 4;
744 return -EILSEQ;
745 }
746
747 do {
748 /* locate address descriptor */
749 do {
750 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
751 /* unexpected table end */
752 if (desc == DMP_DESC_EOT) {
753 *eromaddr -= 4;
754 return -EFAULT;
755 }
756 } while (desc != DMP_DESC_ADDRESS);
757
758 /* skip upper 32-bit address descriptor */
759 if (val & DMP_DESC_ADDRSIZE_GT32)
760 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
761
762 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
763
764 /* next size descriptor can be skipped */
765 if (sztype == DMP_SLAVE_SIZE_DESC) {
766 val = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
767 /* skip upper size descriptor if present */
768 if (val & DMP_DESC_ADDRSIZE_GT32)
769 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
770 }
771
772 /* only look for 4K register regions */
773 if (sztype != DMP_SLAVE_SIZE_4K)
774 continue;
775
776 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
777
778 /* only regular slave and wrapper */
779 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
780 *regbase = val & DMP_SLAVE_ADDR_BASE;
781 if (*wrapbase == 0 && stype == wraptype)
782 *wrapbase = val & DMP_SLAVE_ADDR_BASE;
783 } while (*regbase == 0 || *wrapbase == 0);
784
785 return 0;
786 }
787
788 static
789 int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
790 {
791 struct brcmf_core *core;
792 u32 eromaddr;
793 u8 desc_type = 0;
794 u32 val;
795 u16 id;
796 u8 nmp, nsp, nmw, nsw, rev;
797 u32 base, wrap;
798 int err;
799
800 eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
801
802 while (desc_type != DMP_DESC_EOT) {
803 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
804 if (!(val & DMP_DESC_VALID))
805 continue;
806
807 if (desc_type == DMP_DESC_EMPTY)
808 continue;
809
810 /* need a component descriptor */
811 if (desc_type != DMP_DESC_COMPONENT)
812 continue;
813
814 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
815
816 /* next descriptor must be component as well */
817 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
818 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
819 return -EFAULT;
820
821 /* only look at cores with master port(s) */
822 nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
823 nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
824 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
825 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
826 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
827
828 /* need core with ports */
829 if (nmw + nsw == 0)
830 continue;
831
832 /* try to obtain register address info */
833 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
834 if (err)
835 continue;
836
837 /* finally a core to be added */
838 core = brcmf_chip_add_core(ci, id, base, wrap);
839 if (IS_ERR(core))
840 return PTR_ERR(core);
841
842 core->rev = rev;
843 }
844
845 return 0;
846 }
847
848 static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
849 {
850 struct brcmf_core *core;
851 u32 regdata;
852 u32 socitype;
853 int ret;
854
855 /* Get CC core rev
856 * Chipid is assume to be at offset 0 from SI_ENUM_BASE
857 * For different chiptypes or old sdio hosts w/o chipcommon,
858 * other ways of recognition should be added here.
859 */
860 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
861 ci->pub.chip = regdata & CID_ID_MASK;
862 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
863 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
864
865 brcmf_chip_name(ci->pub.chip, ci->pub.name, sizeof(ci->pub.name));
866 brcmf_dbg(INFO, "found %s chip: BCM%s, rev=%d\n",
867 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name,
868 ci->pub.chiprev);
869
870 if (socitype == SOCI_SB) {
871 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
872 brcmf_err("SB chip is not supported\n");
873 return -ENODEV;
874 }
875 ci->iscoreup = brcmf_chip_sb_iscoreup;
876 ci->coredisable = brcmf_chip_sb_coredisable;
877 ci->resetcore = brcmf_chip_sb_resetcore;
878
879 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
880 SI_ENUM_BASE, 0);
881 brcmf_chip_sb_corerev(ci, core);
882 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
883 BCM4329_CORE_BUS_BASE, 0);
884 brcmf_chip_sb_corerev(ci, core);
885 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
886 BCM4329_CORE_SOCRAM_BASE, 0);
887 brcmf_chip_sb_corerev(ci, core);
888 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
889 BCM4329_CORE_ARM_BASE, 0);
890 brcmf_chip_sb_corerev(ci, core);
891
892 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
893 brcmf_chip_sb_corerev(ci, core);
894 } else if (socitype == SOCI_AI) {
895 ci->iscoreup = brcmf_chip_ai_iscoreup;
896 ci->coredisable = brcmf_chip_ai_coredisable;
897 ci->resetcore = brcmf_chip_ai_resetcore;
898
899 brcmf_chip_dmp_erom_scan(ci);
900 } else {
901 brcmf_err("chip backplane type %u is not supported\n",
902 socitype);
903 return -ENODEV;
904 }
905
906 ret = brcmf_chip_cores_check(ci);
907 if (ret)
908 return ret;
909
910 /* assure chip is passive for core access */
911 brcmf_chip_set_passive(&ci->pub);
912
913 /* Call bus specific reset function now. Cores have been determined
914 * but further access may require a chip specific reset at this point.
915 */
916 if (ci->ops->reset) {
917 ci->ops->reset(ci->ctx, &ci->pub);
918 brcmf_chip_set_passive(&ci->pub);
919 }
920
921 return brcmf_chip_get_raminfo(ci);
922 }
923
924 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
925 {
926 struct brcmf_core *core;
927 struct brcmf_core_priv *cr4;
928 u32 val;
929
930
931 core = brcmf_chip_get_core(&chip->pub, id);
932 if (!core)
933 return;
934
935 switch (id) {
936 case BCMA_CORE_ARM_CM3:
937 brcmf_chip_coredisable(core, 0, 0);
938 break;
939 case BCMA_CORE_ARM_CR4:
940 cr4 = container_of(core, struct brcmf_core_priv, pub);
941
942 /* clear all IOCTL bits except HALT bit */
943 val = chip->ops->read32(chip->ctx, cr4->wrapbase + BCMA_IOCTL);
944 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
945 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
946 ARMCR4_BCMA_IOCTL_CPUHALT);
947 break;
948 default:
949 brcmf_err("unknown id: %u\n", id);
950 break;
951 }
952 }
953
954 static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
955 {
956 struct brcmf_chip *pub;
957 struct brcmf_core_priv *cc;
958 u32 base;
959 u32 val;
960 int ret = 0;
961
962 pub = &chip->pub;
963 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
964 base = cc->pub.base;
965
966 /* get chipcommon capabilites */
967 pub->cc_caps = chip->ops->read32(chip->ctx,
968 CORE_CC_REG(base, capabilities));
969
970 /* get pmu caps & rev */
971 if (pub->cc_caps & CC_CAP_PMU) {
972 val = chip->ops->read32(chip->ctx,
973 CORE_CC_REG(base, pmucapabilities));
974 pub->pmurev = val & PCAP_REV_MASK;
975 pub->pmucaps = val;
976 }
977
978 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
979 cc->pub.rev, pub->pmurev, pub->pmucaps);
980
981 /* execute bus core specific setup */
982 if (chip->ops->setup)
983 ret = chip->ops->setup(chip->ctx, pub);
984
985 return ret;
986 }
987
988 struct brcmf_chip *brcmf_chip_attach(void *ctx,
989 const struct brcmf_buscore_ops *ops)
990 {
991 struct brcmf_chip_priv *chip;
992 int err = 0;
993
994 if (WARN_ON(!ops->read32))
995 err = -EINVAL;
996 if (WARN_ON(!ops->write32))
997 err = -EINVAL;
998 if (WARN_ON(!ops->prepare))
999 err = -EINVAL;
1000 if (WARN_ON(!ops->activate))
1001 err = -EINVAL;
1002 if (err < 0)
1003 return ERR_PTR(-EINVAL);
1004
1005 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1006 if (!chip)
1007 return ERR_PTR(-ENOMEM);
1008
1009 INIT_LIST_HEAD(&chip->cores);
1010 chip->num_cores = 0;
1011 chip->ops = ops;
1012 chip->ctx = ctx;
1013
1014 err = ops->prepare(ctx);
1015 if (err < 0)
1016 goto fail;
1017
1018 err = brcmf_chip_recognition(chip);
1019 if (err < 0)
1020 goto fail;
1021
1022 err = brcmf_chip_setup(chip);
1023 if (err < 0)
1024 goto fail;
1025
1026 return &chip->pub;
1027
1028 fail:
1029 brcmf_chip_detach(&chip->pub);
1030 return ERR_PTR(err);
1031 }
1032
1033 void brcmf_chip_detach(struct brcmf_chip *pub)
1034 {
1035 struct brcmf_chip_priv *chip;
1036 struct brcmf_core_priv *core;
1037 struct brcmf_core_priv *tmp;
1038
1039 chip = container_of(pub, struct brcmf_chip_priv, pub);
1040 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
1041 list_del(&core->list);
1042 kfree(core);
1043 }
1044 kfree(chip);
1045 }
1046
1047 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
1048 {
1049 struct brcmf_chip_priv *chip;
1050 struct brcmf_core_priv *core;
1051
1052 chip = container_of(pub, struct brcmf_chip_priv, pub);
1053 list_for_each_entry(core, &chip->cores, list)
1054 if (core->pub.id == coreid)
1055 return &core->pub;
1056
1057 return NULL;
1058 }
1059
1060 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
1061 {
1062 struct brcmf_chip_priv *chip;
1063 struct brcmf_core_priv *cc;
1064
1065 chip = container_of(pub, struct brcmf_chip_priv, pub);
1066 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1067 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
1068 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
1069 return &cc->pub;
1070 }
1071
1072 bool brcmf_chip_iscoreup(struct brcmf_core *pub)
1073 {
1074 struct brcmf_core_priv *core;
1075
1076 core = container_of(pub, struct brcmf_core_priv, pub);
1077 return core->chip->iscoreup(core);
1078 }
1079
1080 void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
1081 {
1082 struct brcmf_core_priv *core;
1083
1084 core = container_of(pub, struct brcmf_core_priv, pub);
1085 core->chip->coredisable(core, prereset, reset);
1086 }
1087
1088 void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
1089 u32 postreset)
1090 {
1091 struct brcmf_core_priv *core;
1092
1093 core = container_of(pub, struct brcmf_core_priv, pub);
1094 core->chip->resetcore(core, prereset, reset, postreset);
1095 }
1096
1097 static void
1098 brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip)
1099 {
1100 struct brcmf_core *core;
1101 struct brcmf_core_priv *sr;
1102
1103 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
1104 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1105 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1106 D11_BCMA_IOCTL_PHYCLOCKEN,
1107 D11_BCMA_IOCTL_PHYCLOCKEN,
1108 D11_BCMA_IOCTL_PHYCLOCKEN);
1109 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1110 brcmf_chip_resetcore(core, 0, 0, 0);
1111
1112 /* disable bank #3 remap for this device */
1113 if (chip->pub.chip == BRCM_CC_43430_CHIP_ID) {
1114 sr = container_of(core, struct brcmf_core_priv, pub);
1115 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankidx), 3);
1116 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0);
1117 }
1118 }
1119
1120 static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip)
1121 {
1122 struct brcmf_core *core;
1123
1124 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1125 if (!brcmf_chip_iscoreup(core)) {
1126 brcmf_err("SOCRAM core is down after reset?\n");
1127 return false;
1128 }
1129
1130 chip->ops->activate(chip->ctx, &chip->pub, 0);
1131
1132 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
1133 brcmf_chip_resetcore(core, 0, 0, 0);
1134
1135 return true;
1136 }
1137
1138 static inline void
1139 brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip)
1140 {
1141 struct brcmf_core *core;
1142
1143 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
1144
1145 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1146 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1147 D11_BCMA_IOCTL_PHYCLOCKEN,
1148 D11_BCMA_IOCTL_PHYCLOCKEN,
1149 D11_BCMA_IOCTL_PHYCLOCKEN);
1150 }
1151
1152 static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1153 {
1154 struct brcmf_core *core;
1155
1156 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1157
1158 /* restore ARM */
1159 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
1160 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1161
1162 return true;
1163 }
1164
1165 void brcmf_chip_set_passive(struct brcmf_chip *pub)
1166 {
1167 struct brcmf_chip_priv *chip;
1168 struct brcmf_core *arm;
1169
1170 brcmf_dbg(TRACE, "Enter\n");
1171
1172 chip = container_of(pub, struct brcmf_chip_priv, pub);
1173 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1174 if (arm) {
1175 brcmf_chip_cr4_set_passive(chip);
1176 return;
1177 }
1178
1179 brcmf_chip_cm3_set_passive(chip);
1180 }
1181
1182 bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec)
1183 {
1184 struct brcmf_chip_priv *chip;
1185 struct brcmf_core *arm;
1186
1187 brcmf_dbg(TRACE, "Enter\n");
1188
1189 chip = container_of(pub, struct brcmf_chip_priv, pub);
1190 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1191 if (arm)
1192 return brcmf_chip_cr4_set_active(chip, rstvec);
1193
1194 return brcmf_chip_cm3_set_active(chip);
1195 }
1196
1197 bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
1198 {
1199 u32 base, addr, reg, pmu_cc3_mask = ~0;
1200 struct brcmf_chip_priv *chip;
1201
1202 brcmf_dbg(TRACE, "Enter\n");
1203
1204 /* old chips with PMU version less than 17 don't support save restore */
1205 if (pub->pmurev < 17)
1206 return false;
1207
1208 base = brcmf_chip_get_chipcommon(pub)->base;
1209 chip = container_of(pub, struct brcmf_chip_priv, pub);
1210
1211 switch (pub->chip) {
1212 case BRCM_CC_4354_CHIP_ID:
1213 /* explicitly check SR engine enable bit */
1214 pmu_cc3_mask = BIT(2);
1215 /* fall-through */
1216 case BRCM_CC_43241_CHIP_ID:
1217 case BRCM_CC_4335_CHIP_ID:
1218 case BRCM_CC_4339_CHIP_ID:
1219 /* read PMU chipcontrol register 3 */
1220 addr = CORE_CC_REG(base, chipcontrol_addr);
1221 chip->ops->write32(chip->ctx, addr, 3);
1222 addr = CORE_CC_REG(base, chipcontrol_data);
1223 reg = chip->ops->read32(chip->ctx, addr);
1224 return (reg & pmu_cc3_mask) != 0;
1225 case BRCM_CC_43430_CHIP_ID:
1226 addr = CORE_CC_REG(base, sr_control1);
1227 reg = chip->ops->read32(chip->ctx, addr);
1228 return reg != 0;
1229 default:
1230 addr = CORE_CC_REG(base, pmucapabilities_ext);
1231 reg = chip->ops->read32(chip->ctx, addr);
1232 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1233 return false;
1234
1235 addr = CORE_CC_REG(base, retention_ctl);
1236 reg = chip->ops->read32(chip->ctx, addr);
1237 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1238 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1239 }
1240 }
Linux kernel - Deliverables
This page took 0.061674 seconds and 6 git commands to generate.