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brcmfmac: Add wowl support for PCIE devices.
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / pcie.c
1 /* Copyright (c) 2014 Broadcom Corporation
2 *
3 * Permission to use, copy, modify, and/or distribute this software for any
4 * purpose with or without fee is hereby granted, provided that the above
5 * copyright notice and this permission notice appear in all copies.
6 *
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/firmware.h>
19 #include <linux/pci.h>
20 #include <linux/vmalloc.h>
21 #include <linux/delay.h>
22 #include <linux/unaligned/access_ok.h>
23 #include <linux/interrupt.h>
24 #include <linux/bcma/bcma.h>
25 #include <linux/sched.h>
26
27 #include <soc.h>
28 #include <chipcommon.h>
29 #include <brcmu_utils.h>
30 #include <brcmu_wifi.h>
31 #include <brcm_hw_ids.h>
32
33 #include "dhd_dbg.h"
34 #include "dhd_bus.h"
35 #include "commonring.h"
36 #include "msgbuf.h"
37 #include "pcie.h"
38 #include "firmware.h"
39 #include "chip.h"
40
41
42 enum brcmf_pcie_state {
43 BRCMFMAC_PCIE_STATE_DOWN,
44 BRCMFMAC_PCIE_STATE_UP
45 };
46
47
48 #define BRCMF_PCIE_43602_FW_NAME "brcm/brcmfmac43602-pcie.bin"
49 #define BRCMF_PCIE_43602_NVRAM_NAME "brcm/brcmfmac43602-pcie.txt"
50 #define BRCMF_PCIE_4354_FW_NAME "brcm/brcmfmac4354-pcie.bin"
51 #define BRCMF_PCIE_4354_NVRAM_NAME "brcm/brcmfmac4354-pcie.txt"
52 #define BRCMF_PCIE_4356_FW_NAME "brcm/brcmfmac4356-pcie.bin"
53 #define BRCMF_PCIE_4356_NVRAM_NAME "brcm/brcmfmac4356-pcie.txt"
54 #define BRCMF_PCIE_43570_FW_NAME "brcm/brcmfmac43570-pcie.bin"
55 #define BRCMF_PCIE_43570_NVRAM_NAME "brcm/brcmfmac43570-pcie.txt"
56
57 #define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */
58
59 #define BRCMF_PCIE_TCM_MAP_SIZE (4096 * 1024)
60 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
61
62 /* backplane addres space accessed by BAR0 */
63 #define BRCMF_PCIE_BAR0_WINDOW 0x80
64 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
65 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
66
67 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
68 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
69
70 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
71 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
72
73 #define BRCMF_PCIE_REG_INTSTATUS 0x90
74 #define BRCMF_PCIE_REG_INTMASK 0x94
75 #define BRCMF_PCIE_REG_SBMBX 0x98
76
77 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
78 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
79 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
80 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
81 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
82 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140
83
84 #define BRCMF_PCIE_GENREV1 1
85 #define BRCMF_PCIE_GENREV2 2
86
87 #define BRCMF_PCIE2_INTA 0x01
88 #define BRCMF_PCIE2_INTB 0x02
89
90 #define BRCMF_PCIE_INT_0 0x01
91 #define BRCMF_PCIE_INT_1 0x02
92 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
93 BRCMF_PCIE_INT_1)
94
95 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100
96 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200
97 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
98 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
99 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
100 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
101 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
102 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
103 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
104 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
105
106 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
107 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
108 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
109 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
110 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
111 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
112 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
113 BRCMF_PCIE_MB_INT_D2H3_DB1)
114
115 #define BRCMF_PCIE_MIN_SHARED_VERSION 4
116 #define BRCMF_PCIE_MAX_SHARED_VERSION 5
117 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
118 #define BRCMF_PCIE_SHARED_TXPUSH_SUPPORT 0x4000
119
120 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
121 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
122
123 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
124 #define BRCMF_SHARED_RING_BASE_OFFSET 52
125 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
126 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
127 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
128 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
129 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
130 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
131 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
132 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
133 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
134
135 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
136 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
137 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4
138 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8
139
140 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
141 #define BRCMF_RING_MAX_ITEM_OFFSET 4
142 #define BRCMF_RING_LEN_ITEMS_OFFSET 6
143 #define BRCMF_RING_MEM_SZ 16
144 #define BRCMF_RING_STATE_SZ 8
145
146 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET 4
147 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8
148 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12
149 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16
150 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0
151 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52
152
153 #define BRCMF_DEF_MAX_RXBUFPOST 255
154
155 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8
156 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
157 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
158
159 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
160 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
161
162 #define BRCMF_D2H_DEV_D3_ACK 0x00000001
163 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
164 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
165
166 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001
167 #define BRCMF_H2D_HOST_DS_ACK 0x00000002
168 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008
169 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010
170
171 #define BRCMF_PCIE_MBDATA_TIMEOUT 2000
172
173 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4
174 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C
175 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58
176 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C
177 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60
178 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64
179 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC
180 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC
181 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228
182 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248
183 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0
184 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4
185 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3
186
187
188 MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
189 MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
190 MODULE_FIRMWARE(BRCMF_PCIE_4354_FW_NAME);
191 MODULE_FIRMWARE(BRCMF_PCIE_4354_NVRAM_NAME);
192 MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
193 MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
194
195
196 struct brcmf_pcie_console {
197 u32 base_addr;
198 u32 buf_addr;
199 u32 bufsize;
200 u32 read_idx;
201 u8 log_str[256];
202 u8 log_idx;
203 };
204
205 struct brcmf_pcie_shared_info {
206 u32 tcm_base_address;
207 u32 flags;
208 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
209 struct brcmf_pcie_ringbuf *flowrings;
210 u16 max_rxbufpost;
211 u32 nrof_flowrings;
212 u32 rx_dataoffset;
213 u32 htod_mb_data_addr;
214 u32 dtoh_mb_data_addr;
215 u32 ring_info_addr;
216 struct brcmf_pcie_console console;
217 void *scratch;
218 dma_addr_t scratch_dmahandle;
219 void *ringupd;
220 dma_addr_t ringupd_dmahandle;
221 };
222
223 struct brcmf_pcie_core_info {
224 u32 base;
225 u32 wrapbase;
226 };
227
228 struct brcmf_pciedev_info {
229 enum brcmf_pcie_state state;
230 bool in_irq;
231 bool irq_requested;
232 struct pci_dev *pdev;
233 char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
234 char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
235 void __iomem *regs;
236 void __iomem *tcm;
237 u32 tcm_size;
238 u32 ram_base;
239 u32 ram_size;
240 struct brcmf_chip *ci;
241 u32 coreid;
242 u32 generic_corerev;
243 struct brcmf_pcie_shared_info shared;
244 void (*ringbell)(struct brcmf_pciedev_info *devinfo);
245 wait_queue_head_t mbdata_resp_wait;
246 bool mbdata_completed;
247 bool irq_allocated;
248 bool wowl_enabled;
249 };
250
251 struct brcmf_pcie_ringbuf {
252 struct brcmf_commonring commonring;
253 dma_addr_t dma_handle;
254 u32 w_idx_addr;
255 u32 r_idx_addr;
256 struct brcmf_pciedev_info *devinfo;
257 u8 id;
258 };
259
260
261 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
262 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
263 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
264 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
265 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
266 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
267 };
268
269 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
270 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
271 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
272 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
273 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
274 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
275 };
276
277
278 /* dma flushing needs implementation for mips and arm platforms. Should
279 * be put in util. Note, this is not real flushing. It is virtual non
280 * cached memory. Only write buffers should have to be drained. Though
281 * this may be different depending on platform......
282 */
283 #define brcmf_dma_flush(addr, len)
284 #define brcmf_dma_invalidate_cache(addr, len)
285
286
287 static u32
288 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
289 {
290 void __iomem *address = devinfo->regs + reg_offset;
291
292 return (ioread32(address));
293 }
294
295
296 static void
297 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
298 u32 value)
299 {
300 void __iomem *address = devinfo->regs + reg_offset;
301
302 iowrite32(value, address);
303 }
304
305
306 static u8
307 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
308 {
309 void __iomem *address = devinfo->tcm + mem_offset;
310
311 return (ioread8(address));
312 }
313
314
315 static u16
316 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
317 {
318 void __iomem *address = devinfo->tcm + mem_offset;
319
320 return (ioread16(address));
321 }
322
323
324 static void
325 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
326 u16 value)
327 {
328 void __iomem *address = devinfo->tcm + mem_offset;
329
330 iowrite16(value, address);
331 }
332
333
334 static u32
335 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
336 {
337 void __iomem *address = devinfo->tcm + mem_offset;
338
339 return (ioread32(address));
340 }
341
342
343 static void
344 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
345 u32 value)
346 {
347 void __iomem *address = devinfo->tcm + mem_offset;
348
349 iowrite32(value, address);
350 }
351
352
353 static u32
354 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
355 {
356 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
357
358 return (ioread32(addr));
359 }
360
361
362 static void
363 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
364 u32 value)
365 {
366 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
367
368 iowrite32(value, addr);
369 }
370
371
372 static void
373 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
374 void *srcaddr, u32 len)
375 {
376 void __iomem *address = devinfo->tcm + mem_offset;
377 __le32 *src32;
378 __le16 *src16;
379 u8 *src8;
380
381 if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
382 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
383 src8 = (u8 *)srcaddr;
384 while (len) {
385 iowrite8(*src8, address);
386 address++;
387 src8++;
388 len--;
389 }
390 } else {
391 len = len / 2;
392 src16 = (__le16 *)srcaddr;
393 while (len) {
394 iowrite16(le16_to_cpu(*src16), address);
395 address += 2;
396 src16++;
397 len--;
398 }
399 }
400 } else {
401 len = len / 4;
402 src32 = (__le32 *)srcaddr;
403 while (len) {
404 iowrite32(le32_to_cpu(*src32), address);
405 address += 4;
406 src32++;
407 len--;
408 }
409 }
410 }
411
412
413 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
414 CHIPCREGOFFS(reg), value)
415
416
417 static void
418 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
419 {
420 const struct pci_dev *pdev = devinfo->pdev;
421 struct brcmf_core *core;
422 u32 bar0_win;
423
424 core = brcmf_chip_get_core(devinfo->ci, coreid);
425 if (core) {
426 bar0_win = core->base;
427 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
428 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
429 &bar0_win) == 0) {
430 if (bar0_win != core->base) {
431 bar0_win = core->base;
432 pci_write_config_dword(pdev,
433 BRCMF_PCIE_BAR0_WINDOW,
434 bar0_win);
435 }
436 }
437 } else {
438 brcmf_err("Unsupported core selected %x\n", coreid);
439 }
440 }
441
442
443 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
444 {
445 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
446 BRCMF_PCIE_CFGREG_PM_CSR,
447 BRCMF_PCIE_CFGREG_MSI_CAP,
448 BRCMF_PCIE_CFGREG_MSI_ADDR_L,
449 BRCMF_PCIE_CFGREG_MSI_ADDR_H,
450 BRCMF_PCIE_CFGREG_MSI_DATA,
451 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
452 BRCMF_PCIE_CFGREG_RBAR_CTRL,
453 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
454 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
455 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
456 u32 i;
457 u32 val;
458 u32 lsc;
459
460 if (!devinfo->ci)
461 return;
462
463 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
464 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
465 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
466 lsc = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
467 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
468 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, val);
469
470 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
471 WRITECC32(devinfo, watchdog, 4);
472 msleep(100);
473
474 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
475 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
476 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
477 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, lsc);
478
479 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
480 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
481 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
482 cfg_offset[i]);
483 val = brcmf_pcie_read_reg32(devinfo,
484 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
485 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
486 cfg_offset[i], val);
487 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA,
488 val);
489 }
490 }
491
492
493 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
494 {
495 u32 config;
496
497 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
498 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0)
499 brcmf_pcie_reset_device(devinfo);
500 /* BAR1 window may not be sized properly */
501 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
502 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
503 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
504 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
505
506 device_wakeup_enable(&devinfo->pdev->dev);
507 }
508
509
510 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
511 {
512 brcmf_chip_enter_download(devinfo->ci);
513
514 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
515 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
516 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
517 5);
518 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
519 0);
520 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
521 7);
522 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
523 0);
524 }
525 return 0;
526 }
527
528
529 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
530 u32 resetintr)
531 {
532 struct brcmf_core *core;
533
534 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
535 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
536 brcmf_chip_resetcore(core, 0, 0, 0);
537 }
538
539 return !brcmf_chip_exit_download(devinfo->ci, resetintr);
540 }
541
542
543 static int
544 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
545 {
546 struct brcmf_pcie_shared_info *shared;
547 u32 addr;
548 u32 cur_htod_mb_data;
549 u32 i;
550
551 shared = &devinfo->shared;
552 addr = shared->htod_mb_data_addr;
553 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
554
555 if (cur_htod_mb_data != 0)
556 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
557 cur_htod_mb_data);
558
559 i = 0;
560 while (cur_htod_mb_data != 0) {
561 msleep(10);
562 i++;
563 if (i > 100)
564 return -EIO;
565 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
566 }
567
568 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
569 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
570 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
571
572 return 0;
573 }
574
575
576 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
577 {
578 struct brcmf_pcie_shared_info *shared;
579 u32 addr;
580 u32 dtoh_mb_data;
581
582 shared = &devinfo->shared;
583 addr = shared->dtoh_mb_data_addr;
584 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
585
586 if (!dtoh_mb_data)
587 return;
588
589 brcmf_pcie_write_tcm32(devinfo, addr, 0);
590
591 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
592 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
593 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
594 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
595 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
596 }
597 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
598 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
599 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
600 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
601 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
602 devinfo->mbdata_completed = true;
603 wake_up(&devinfo->mbdata_resp_wait);
604 }
605 }
606 }
607
608
609 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
610 {
611 struct brcmf_pcie_shared_info *shared;
612 struct brcmf_pcie_console *console;
613 u32 addr;
614
615 shared = &devinfo->shared;
616 console = &shared->console;
617 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
618 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
619
620 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
621 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
622 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
623 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
624
625 brcmf_dbg(PCIE, "Console: base %x, buf %x, size %d\n",
626 console->base_addr, console->buf_addr, console->bufsize);
627 }
628
629
630 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
631 {
632 struct brcmf_pcie_console *console;
633 u32 addr;
634 u8 ch;
635 u32 newidx;
636
637 console = &devinfo->shared.console;
638 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
639 newidx = brcmf_pcie_read_tcm32(devinfo, addr);
640 while (newidx != console->read_idx) {
641 addr = console->buf_addr + console->read_idx;
642 ch = brcmf_pcie_read_tcm8(devinfo, addr);
643 console->read_idx++;
644 if (console->read_idx == console->bufsize)
645 console->read_idx = 0;
646 if (ch == '\r')
647 continue;
648 console->log_str[console->log_idx] = ch;
649 console->log_idx++;
650 if ((ch != '\n') &&
651 (console->log_idx == (sizeof(console->log_str) - 2))) {
652 ch = '\n';
653 console->log_str[console->log_idx] = ch;
654 console->log_idx++;
655 }
656
657 if (ch == '\n') {
658 console->log_str[console->log_idx] = 0;
659 brcmf_dbg(PCIE, "CONSOLE: %s\n", console->log_str);
660 console->log_idx = 0;
661 }
662 }
663 }
664
665
666 static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
667 {
668 u32 reg_value;
669
670 brcmf_dbg(PCIE, "RING !\n");
671 reg_value = brcmf_pcie_read_reg32(devinfo,
672 BRCMF_PCIE_PCIE2REG_MAILBOXINT);
673 reg_value |= BRCMF_PCIE2_INTB;
674 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
675 reg_value);
676 }
677
678
679 static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
680 {
681 brcmf_dbg(PCIE, "RING !\n");
682 /* Any arbitrary value will do, lets use 1 */
683 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
684 }
685
686
687 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
688 {
689 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
690 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
691 0);
692 else
693 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
694 0);
695 }
696
697
698 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
699 {
700 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
701 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
702 BRCMF_PCIE_INT_DEF);
703 else
704 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
705 BRCMF_PCIE_MB_INT_D2H_DB |
706 BRCMF_PCIE_MB_INT_FN0_0 |
707 BRCMF_PCIE_MB_INT_FN0_1);
708 }
709
710
711 static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
712 {
713 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
714 u32 status;
715
716 status = 0;
717 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
718 if (status) {
719 brcmf_pcie_intr_disable(devinfo);
720 brcmf_dbg(PCIE, "Enter\n");
721 return IRQ_WAKE_THREAD;
722 }
723 return IRQ_NONE;
724 }
725
726
727 static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
728 {
729 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
730
731 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
732 brcmf_pcie_intr_disable(devinfo);
733 brcmf_dbg(PCIE, "Enter\n");
734 return IRQ_WAKE_THREAD;
735 }
736 return IRQ_NONE;
737 }
738
739
740 static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
741 {
742 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
743 const struct pci_dev *pdev = devinfo->pdev;
744 u32 status;
745
746 devinfo->in_irq = true;
747 status = 0;
748 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
749 brcmf_dbg(PCIE, "Enter %x\n", status);
750 if (status) {
751 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
752 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
753 brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
754 }
755 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
756 brcmf_pcie_intr_enable(devinfo);
757 devinfo->in_irq = false;
758 return IRQ_HANDLED;
759 }
760
761
762 static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
763 {
764 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
765 u32 status;
766
767 devinfo->in_irq = true;
768 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
769 brcmf_dbg(PCIE, "Enter %x\n", status);
770 if (status) {
771 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
772 status);
773 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
774 BRCMF_PCIE_MB_INT_FN0_1))
775 brcmf_pcie_handle_mb_data(devinfo);
776 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
777 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
778 brcmf_proto_msgbuf_rx_trigger(
779 &devinfo->pdev->dev);
780 }
781 }
782 brcmf_pcie_bus_console_read(devinfo);
783 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
784 brcmf_pcie_intr_enable(devinfo);
785 devinfo->in_irq = false;
786 return IRQ_HANDLED;
787 }
788
789
790 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
791 {
792 struct pci_dev *pdev;
793
794 pdev = devinfo->pdev;
795
796 brcmf_pcie_intr_disable(devinfo);
797
798 brcmf_dbg(PCIE, "Enter\n");
799 /* is it a v1 or v2 implementation */
800 devinfo->irq_requested = false;
801 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
802 if (request_threaded_irq(pdev->irq,
803 brcmf_pcie_quick_check_isr_v1,
804 brcmf_pcie_isr_thread_v1,
805 IRQF_SHARED, "brcmf_pcie_intr",
806 devinfo)) {
807 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
808 return -EIO;
809 }
810 } else {
811 if (request_threaded_irq(pdev->irq,
812 brcmf_pcie_quick_check_isr_v2,
813 brcmf_pcie_isr_thread_v2,
814 IRQF_SHARED, "brcmf_pcie_intr",
815 devinfo)) {
816 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
817 return -EIO;
818 }
819 }
820 devinfo->irq_requested = true;
821 devinfo->irq_allocated = true;
822 return 0;
823 }
824
825
826 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
827 {
828 struct pci_dev *pdev;
829 u32 status;
830 u32 count;
831
832 if (!devinfo->irq_allocated)
833 return;
834
835 pdev = devinfo->pdev;
836
837 brcmf_pcie_intr_disable(devinfo);
838 if (!devinfo->irq_requested)
839 return;
840 devinfo->irq_requested = false;
841 free_irq(pdev->irq, devinfo);
842
843 msleep(50);
844 count = 0;
845 while ((devinfo->in_irq) && (count < 20)) {
846 msleep(50);
847 count++;
848 }
849 if (devinfo->in_irq)
850 brcmf_err("Still in IRQ (processing) !!!\n");
851
852 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
853 status = 0;
854 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
855 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
856 } else {
857 status = brcmf_pcie_read_reg32(devinfo,
858 BRCMF_PCIE_PCIE2REG_MAILBOXINT);
859 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
860 status);
861 }
862 devinfo->irq_allocated = false;
863 }
864
865
866 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
867 {
868 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
869 struct brcmf_pciedev_info *devinfo = ring->devinfo;
870 struct brcmf_commonring *commonring = &ring->commonring;
871
872 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
873 return -EIO;
874
875 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
876 commonring->w_ptr, ring->id);
877
878 brcmf_pcie_write_tcm16(devinfo, ring->r_idx_addr, commonring->r_ptr);
879
880 return 0;
881 }
882
883
884 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
885 {
886 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
887 struct brcmf_pciedev_info *devinfo = ring->devinfo;
888 struct brcmf_commonring *commonring = &ring->commonring;
889
890 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
891 return -EIO;
892
893 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
894 commonring->r_ptr, ring->id);
895
896 brcmf_pcie_write_tcm16(devinfo, ring->w_idx_addr, commonring->w_ptr);
897
898 return 0;
899 }
900
901
902 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
903 {
904 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
905 struct brcmf_pciedev_info *devinfo = ring->devinfo;
906
907 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
908 return -EIO;
909
910 devinfo->ringbell(devinfo);
911
912 return 0;
913 }
914
915
916 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
917 {
918 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
919 struct brcmf_pciedev_info *devinfo = ring->devinfo;
920 struct brcmf_commonring *commonring = &ring->commonring;
921
922 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
923 return -EIO;
924
925 commonring->r_ptr = brcmf_pcie_read_tcm16(devinfo, ring->r_idx_addr);
926
927 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
928 commonring->w_ptr, ring->id);
929
930 return 0;
931 }
932
933
934 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
935 {
936 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
937 struct brcmf_pciedev_info *devinfo = ring->devinfo;
938 struct brcmf_commonring *commonring = &ring->commonring;
939
940 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
941 return -EIO;
942
943 commonring->w_ptr = brcmf_pcie_read_tcm16(devinfo, ring->w_idx_addr);
944
945 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
946 commonring->r_ptr, ring->id);
947
948 return 0;
949 }
950
951
952 static void *
953 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
954 u32 size, u32 tcm_dma_phys_addr,
955 dma_addr_t *dma_handle)
956 {
957 void *ring;
958 long long address;
959
960 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
961 GFP_KERNEL);
962 if (!ring)
963 return NULL;
964
965 address = (long long)(long)*dma_handle;
966 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
967 address & 0xffffffff);
968 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
969
970 memset(ring, 0, size);
971
972 return (ring);
973 }
974
975
976 static struct brcmf_pcie_ringbuf *
977 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
978 u32 tcm_ring_phys_addr)
979 {
980 void *dma_buf;
981 dma_addr_t dma_handle;
982 struct brcmf_pcie_ringbuf *ring;
983 u32 size;
984 u32 addr;
985
986 size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
987 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
988 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
989 &dma_handle);
990 if (!dma_buf)
991 return NULL;
992
993 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
994 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
995 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
996 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
997
998 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
999 if (!ring) {
1000 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1001 dma_handle);
1002 return NULL;
1003 }
1004 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1005 brcmf_ring_itemsize[ring_id], dma_buf);
1006 ring->dma_handle = dma_handle;
1007 ring->devinfo = devinfo;
1008 brcmf_commonring_register_cb(&ring->commonring,
1009 brcmf_pcie_ring_mb_ring_bell,
1010 brcmf_pcie_ring_mb_update_rptr,
1011 brcmf_pcie_ring_mb_update_wptr,
1012 brcmf_pcie_ring_mb_write_rptr,
1013 brcmf_pcie_ring_mb_write_wptr, ring);
1014
1015 return (ring);
1016 }
1017
1018
1019 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1020 struct brcmf_pcie_ringbuf *ring)
1021 {
1022 void *dma_buf;
1023 u32 size;
1024
1025 if (!ring)
1026 return;
1027
1028 dma_buf = ring->commonring.buf_addr;
1029 if (dma_buf) {
1030 size = ring->commonring.depth * ring->commonring.item_len;
1031 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1032 }
1033 kfree(ring);
1034 }
1035
1036
1037 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1038 {
1039 u32 i;
1040
1041 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1042 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1043 devinfo->shared.commonrings[i]);
1044 devinfo->shared.commonrings[i] = NULL;
1045 }
1046 kfree(devinfo->shared.flowrings);
1047 devinfo->shared.flowrings = NULL;
1048 }
1049
1050
1051 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1052 {
1053 struct brcmf_pcie_ringbuf *ring;
1054 struct brcmf_pcie_ringbuf *rings;
1055 u32 ring_addr;
1056 u32 d2h_w_idx_ptr;
1057 u32 d2h_r_idx_ptr;
1058 u32 h2d_w_idx_ptr;
1059 u32 h2d_r_idx_ptr;
1060 u32 addr;
1061 u32 ring_mem_ptr;
1062 u32 i;
1063 u16 max_sub_queues;
1064
1065 ring_addr = devinfo->shared.ring_info_addr;
1066 brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1067
1068 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1069 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1070 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1071 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1072 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1073 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1074 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1075 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1076
1077 addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1078 ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1079
1080 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1081 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1082 if (!ring)
1083 goto fail;
1084 ring->w_idx_addr = h2d_w_idx_ptr;
1085 ring->r_idx_addr = h2d_r_idx_ptr;
1086 ring->id = i;
1087 devinfo->shared.commonrings[i] = ring;
1088
1089 h2d_w_idx_ptr += sizeof(u32);
1090 h2d_r_idx_ptr += sizeof(u32);
1091 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1092 }
1093
1094 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1095 i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1096 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1097 if (!ring)
1098 goto fail;
1099 ring->w_idx_addr = d2h_w_idx_ptr;
1100 ring->r_idx_addr = d2h_r_idx_ptr;
1101 ring->id = i;
1102 devinfo->shared.commonrings[i] = ring;
1103
1104 d2h_w_idx_ptr += sizeof(u32);
1105 d2h_r_idx_ptr += sizeof(u32);
1106 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1107 }
1108
1109 addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1110 max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1111 devinfo->shared.nrof_flowrings =
1112 max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1113 rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1114 GFP_KERNEL);
1115 if (!rings)
1116 goto fail;
1117
1118 brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1119 devinfo->shared.nrof_flowrings);
1120
1121 for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1122 ring = &rings[i];
1123 ring->devinfo = devinfo;
1124 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1125 brcmf_commonring_register_cb(&ring->commonring,
1126 brcmf_pcie_ring_mb_ring_bell,
1127 brcmf_pcie_ring_mb_update_rptr,
1128 brcmf_pcie_ring_mb_update_wptr,
1129 brcmf_pcie_ring_mb_write_rptr,
1130 brcmf_pcie_ring_mb_write_wptr,
1131 ring);
1132 ring->w_idx_addr = h2d_w_idx_ptr;
1133 ring->r_idx_addr = h2d_r_idx_ptr;
1134 h2d_w_idx_ptr += sizeof(u32);
1135 h2d_r_idx_ptr += sizeof(u32);
1136 }
1137 devinfo->shared.flowrings = rings;
1138
1139 return 0;
1140
1141 fail:
1142 brcmf_err("Allocating commonring buffers failed\n");
1143 brcmf_pcie_release_ringbuffers(devinfo);
1144 return -ENOMEM;
1145 }
1146
1147
1148 static void
1149 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1150 {
1151 if (devinfo->shared.scratch)
1152 dma_free_coherent(&devinfo->pdev->dev,
1153 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1154 devinfo->shared.scratch,
1155 devinfo->shared.scratch_dmahandle);
1156 if (devinfo->shared.ringupd)
1157 dma_free_coherent(&devinfo->pdev->dev,
1158 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1159 devinfo->shared.ringupd,
1160 devinfo->shared.ringupd_dmahandle);
1161 }
1162
1163 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1164 {
1165 long long address;
1166 u32 addr;
1167
1168 devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1169 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1170 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1171 if (!devinfo->shared.scratch)
1172 goto fail;
1173
1174 memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1175 brcmf_dma_flush(devinfo->shared.scratch, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1176
1177 addr = devinfo->shared.tcm_base_address +
1178 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1179 address = (long long)(long)devinfo->shared.scratch_dmahandle;
1180 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1181 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1182 addr = devinfo->shared.tcm_base_address +
1183 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1184 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1185
1186 devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1187 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1188 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1189 if (!devinfo->shared.ringupd)
1190 goto fail;
1191
1192 memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1193 brcmf_dma_flush(devinfo->shared.ringupd, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1194
1195 addr = devinfo->shared.tcm_base_address +
1196 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1197 address = (long long)(long)devinfo->shared.ringupd_dmahandle;
1198 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1199 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1200 addr = devinfo->shared.tcm_base_address +
1201 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1202 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1203 return 0;
1204
1205 fail:
1206 brcmf_err("Allocating scratch buffers failed\n");
1207 brcmf_pcie_release_scratchbuffers(devinfo);
1208 return -ENOMEM;
1209 }
1210
1211
1212 static void brcmf_pcie_down(struct device *dev)
1213 {
1214 }
1215
1216
1217 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1218 {
1219 return 0;
1220 }
1221
1222
1223 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1224 uint len)
1225 {
1226 return 0;
1227 }
1228
1229
1230 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1231 uint len)
1232 {
1233 return 0;
1234 }
1235
1236
1237 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1238 {
1239 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1240 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1241 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1242
1243 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1244 devinfo->wowl_enabled = enabled;
1245 if (enabled)
1246 device_set_wakeup_enable(&devinfo->pdev->dev, true);
1247 else
1248 device_set_wakeup_enable(&devinfo->pdev->dev, false);
1249 }
1250
1251
1252 static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1253 .txdata = brcmf_pcie_tx,
1254 .stop = brcmf_pcie_down,
1255 .txctl = brcmf_pcie_tx_ctlpkt,
1256 .rxctl = brcmf_pcie_rx_ctlpkt,
1257 .wowl_config = brcmf_pcie_wowl_config,
1258 };
1259
1260
1261 static int
1262 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1263 u32 sharedram_addr)
1264 {
1265 struct brcmf_pcie_shared_info *shared;
1266 u32 addr;
1267 u32 version;
1268
1269 shared = &devinfo->shared;
1270 shared->tcm_base_address = sharedram_addr;
1271
1272 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1273 version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1274 brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1275 if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1276 (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1277 brcmf_err("Unsupported PCIE version %d\n", version);
1278 return -EINVAL;
1279 }
1280 if (shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT) {
1281 brcmf_err("Unsupported legacy TX mode 0x%x\n",
1282 shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT);
1283 return -EINVAL;
1284 }
1285
1286 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1287 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1288 if (shared->max_rxbufpost == 0)
1289 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1290
1291 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1292 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1293
1294 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1295 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1296
1297 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1298 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1299
1300 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1301 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1302
1303 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1304 shared->max_rxbufpost, shared->rx_dataoffset);
1305
1306 brcmf_pcie_bus_console_init(devinfo);
1307
1308 return 0;
1309 }
1310
1311
1312 static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1313 {
1314 char *fw_name;
1315 char *nvram_name;
1316 uint fw_len, nv_len;
1317 char end;
1318
1319 brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1320 devinfo->ci->chiprev);
1321
1322 switch (devinfo->ci->chip) {
1323 case BRCM_CC_43602_CHIP_ID:
1324 fw_name = BRCMF_PCIE_43602_FW_NAME;
1325 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1326 break;
1327 case BRCM_CC_4354_CHIP_ID:
1328 fw_name = BRCMF_PCIE_4354_FW_NAME;
1329 nvram_name = BRCMF_PCIE_4354_NVRAM_NAME;
1330 break;
1331 case BRCM_CC_4356_CHIP_ID:
1332 fw_name = BRCMF_PCIE_4356_FW_NAME;
1333 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1334 break;
1335 case BRCM_CC_43567_CHIP_ID:
1336 case BRCM_CC_43569_CHIP_ID:
1337 case BRCM_CC_43570_CHIP_ID:
1338 fw_name = BRCMF_PCIE_43570_FW_NAME;
1339 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1340 break;
1341 default:
1342 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1343 return -ENODEV;
1344 }
1345
1346 fw_len = sizeof(devinfo->fw_name) - 1;
1347 nv_len = sizeof(devinfo->nvram_name) - 1;
1348 /* check if firmware path is provided by module parameter */
1349 if (brcmf_firmware_path[0] != '\0') {
1350 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1351 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1352 fw_len -= strlen(devinfo->fw_name);
1353 nv_len -= strlen(devinfo->nvram_name);
1354
1355 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1356 if (end != '/') {
1357 strncat(devinfo->fw_name, "/", fw_len);
1358 strncat(devinfo->nvram_name, "/", nv_len);
1359 fw_len--;
1360 nv_len--;
1361 }
1362 }
1363 strncat(devinfo->fw_name, fw_name, fw_len);
1364 strncat(devinfo->nvram_name, nvram_name, nv_len);
1365
1366 return 0;
1367 }
1368
1369
1370 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1371 const struct firmware *fw, void *nvram,
1372 u32 nvram_len)
1373 {
1374 u32 sharedram_addr;
1375 u32 sharedram_addr_written;
1376 u32 loop_counter;
1377 int err;
1378 u32 address;
1379 u32 resetintr;
1380
1381 devinfo->ringbell = brcmf_pcie_ringbell_v2;
1382 devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1383
1384 brcmf_dbg(PCIE, "Halt ARM.\n");
1385 err = brcmf_pcie_enter_download_state(devinfo);
1386 if (err)
1387 return err;
1388
1389 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1390 brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1391 (void *)fw->data, fw->size);
1392
1393 resetintr = get_unaligned_le32(fw->data);
1394 release_firmware(fw);
1395
1396 /* reset last 4 bytes of RAM address. to be used for shared
1397 * area. This identifies when FW is running
1398 */
1399 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1400
1401 if (nvram) {
1402 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1403 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1404 nvram_len;
1405 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1406 brcmf_fw_nvram_free(nvram);
1407 } else {
1408 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1409 devinfo->nvram_name);
1410 }
1411
1412 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1413 devinfo->ci->ramsize -
1414 4);
1415 brcmf_dbg(PCIE, "Bring ARM in running state\n");
1416 err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1417 if (err)
1418 return err;
1419
1420 brcmf_dbg(PCIE, "Wait for FW init\n");
1421 sharedram_addr = sharedram_addr_written;
1422 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1423 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1424 msleep(50);
1425 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1426 devinfo->ci->ramsize -
1427 4);
1428 loop_counter--;
1429 }
1430 if (sharedram_addr == sharedram_addr_written) {
1431 brcmf_err("FW failed to initialize\n");
1432 return -ENODEV;
1433 }
1434 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1435
1436 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1437 }
1438
1439
1440 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1441 {
1442 struct pci_dev *pdev;
1443 int err;
1444 phys_addr_t bar0_addr, bar1_addr;
1445 ulong bar1_size;
1446
1447 pdev = devinfo->pdev;
1448
1449 err = pci_enable_device(pdev);
1450 if (err) {
1451 brcmf_err("pci_enable_device failed err=%d\n", err);
1452 return err;
1453 }
1454
1455 pci_set_master(pdev);
1456
1457 /* Bar-0 mapped address */
1458 bar0_addr = pci_resource_start(pdev, 0);
1459 /* Bar-1 mapped address */
1460 bar1_addr = pci_resource_start(pdev, 2);
1461 /* read Bar-1 mapped memory range */
1462 bar1_size = pci_resource_len(pdev, 2);
1463 if ((bar1_size == 0) || (bar1_addr == 0)) {
1464 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1465 bar1_size, (unsigned long long)bar1_addr);
1466 return -EINVAL;
1467 }
1468
1469 devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1470 devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1471 devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1472
1473 if (!devinfo->regs || !devinfo->tcm) {
1474 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1475 devinfo->tcm);
1476 return -EINVAL;
1477 }
1478 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1479 devinfo->regs, (unsigned long long)bar0_addr);
1480 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1481 devinfo->tcm, (unsigned long long)bar1_addr);
1482
1483 return 0;
1484 }
1485
1486
1487 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1488 {
1489 if (devinfo->tcm)
1490 iounmap(devinfo->tcm);
1491 if (devinfo->regs)
1492 iounmap(devinfo->regs);
1493
1494 pci_disable_device(devinfo->pdev);
1495 }
1496
1497
1498 static int brcmf_pcie_attach_bus(struct device *dev)
1499 {
1500 int ret;
1501
1502 /* Attach to the common driver interface */
1503 ret = brcmf_attach(dev);
1504 if (ret) {
1505 brcmf_err("brcmf_attach failed\n");
1506 } else {
1507 ret = brcmf_bus_start(dev);
1508 if (ret)
1509 brcmf_err("dongle is not responding\n");
1510 }
1511
1512 return ret;
1513 }
1514
1515
1516 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1517 {
1518 u32 ret_addr;
1519
1520 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1521 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1522 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1523
1524 return ret_addr;
1525 }
1526
1527
1528 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1529 {
1530 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1531
1532 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1533 return brcmf_pcie_read_reg32(devinfo, addr);
1534 }
1535
1536
1537 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1538 {
1539 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1540
1541 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1542 brcmf_pcie_write_reg32(devinfo, addr, value);
1543 }
1544
1545
1546 static int brcmf_pcie_buscoreprep(void *ctx)
1547 {
1548 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1549 int err;
1550
1551 err = brcmf_pcie_get_resource(devinfo);
1552 if (err == 0) {
1553 /* Set CC watchdog to reset all the cores on the chip to bring
1554 * back dongle to a sane state.
1555 */
1556 brcmf_pcie_buscore_write32(ctx, CORE_CC_REG(SI_ENUM_BASE,
1557 watchdog), 4);
1558 msleep(100);
1559 }
1560
1561 return err;
1562 }
1563
1564
1565 static void brcmf_pcie_buscore_exitdl(void *ctx, struct brcmf_chip *chip,
1566 u32 rstvec)
1567 {
1568 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1569
1570 brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1571 }
1572
1573
1574 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1575 .prepare = brcmf_pcie_buscoreprep,
1576 .exit_dl = brcmf_pcie_buscore_exitdl,
1577 .read32 = brcmf_pcie_buscore_read32,
1578 .write32 = brcmf_pcie_buscore_write32,
1579 };
1580
1581 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1582 void *nvram, u32 nvram_len)
1583 {
1584 struct brcmf_bus *bus = dev_get_drvdata(dev);
1585 struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1586 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1587 struct brcmf_commonring **flowrings;
1588 int ret;
1589 u32 i;
1590
1591 brcmf_pcie_attach(devinfo);
1592
1593 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1594 if (ret)
1595 goto fail;
1596
1597 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1598
1599 ret = brcmf_pcie_init_ringbuffers(devinfo);
1600 if (ret)
1601 goto fail;
1602
1603 ret = brcmf_pcie_init_scratchbuffers(devinfo);
1604 if (ret)
1605 goto fail;
1606
1607 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1608 ret = brcmf_pcie_request_irq(devinfo);
1609 if (ret)
1610 goto fail;
1611
1612 /* hook the commonrings in the bus structure. */
1613 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1614 bus->msgbuf->commonrings[i] =
1615 &devinfo->shared.commonrings[i]->commonring;
1616
1617 flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(flowrings),
1618 GFP_KERNEL);
1619 if (!flowrings)
1620 goto fail;
1621
1622 for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1623 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1624 bus->msgbuf->flowrings = flowrings;
1625
1626 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1627 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1628 bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1629
1630 init_waitqueue_head(&devinfo->mbdata_resp_wait);
1631
1632 brcmf_pcie_intr_enable(devinfo);
1633 if (brcmf_pcie_attach_bus(bus->dev) == 0)
1634 return;
1635
1636 brcmf_pcie_bus_console_read(devinfo);
1637
1638 fail:
1639 device_release_driver(dev);
1640 }
1641
1642 static int
1643 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1644 {
1645 int ret;
1646 struct brcmf_pciedev_info *devinfo;
1647 struct brcmf_pciedev *pcie_bus_dev;
1648 struct brcmf_bus *bus;
1649
1650 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
1651
1652 ret = -ENOMEM;
1653 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1654 if (devinfo == NULL)
1655 return ret;
1656
1657 devinfo->pdev = pdev;
1658 pcie_bus_dev = NULL;
1659 devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1660 if (IS_ERR(devinfo->ci)) {
1661 ret = PTR_ERR(devinfo->ci);
1662 devinfo->ci = NULL;
1663 goto fail;
1664 }
1665
1666 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1667 if (pcie_bus_dev == NULL) {
1668 ret = -ENOMEM;
1669 goto fail;
1670 }
1671
1672 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1673 if (!bus) {
1674 ret = -ENOMEM;
1675 goto fail;
1676 }
1677 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1678 if (!bus->msgbuf) {
1679 ret = -ENOMEM;
1680 kfree(bus);
1681 goto fail;
1682 }
1683
1684 /* hook it all together. */
1685 pcie_bus_dev->devinfo = devinfo;
1686 pcie_bus_dev->bus = bus;
1687 bus->dev = &pdev->dev;
1688 bus->bus_priv.pcie = pcie_bus_dev;
1689 bus->ops = &brcmf_pcie_bus_ops;
1690 bus->proto_type = BRCMF_PROTO_MSGBUF;
1691 bus->chip = devinfo->coreid;
1692 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1693 dev_set_drvdata(&pdev->dev, bus);
1694
1695 ret = brcmf_pcie_get_fwnames(devinfo);
1696 if (ret)
1697 goto fail_bus;
1698
1699 ret = brcmf_fw_get_firmwares(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1700 BRCMF_FW_REQ_NV_OPTIONAL,
1701 devinfo->fw_name, devinfo->nvram_name,
1702 brcmf_pcie_setup);
1703 if (ret == 0)
1704 return 0;
1705 fail_bus:
1706 kfree(bus->msgbuf);
1707 kfree(bus);
1708 fail:
1709 brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1710 brcmf_pcie_release_resource(devinfo);
1711 if (devinfo->ci)
1712 brcmf_chip_detach(devinfo->ci);
1713 kfree(pcie_bus_dev);
1714 kfree(devinfo);
1715 return ret;
1716 }
1717
1718
1719 static void
1720 brcmf_pcie_remove(struct pci_dev *pdev)
1721 {
1722 struct brcmf_pciedev_info *devinfo;
1723 struct brcmf_bus *bus;
1724
1725 brcmf_dbg(PCIE, "Enter\n");
1726
1727 bus = dev_get_drvdata(&pdev->dev);
1728 if (bus == NULL)
1729 return;
1730
1731 devinfo = bus->bus_priv.pcie->devinfo;
1732
1733 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1734 if (devinfo->ci)
1735 brcmf_pcie_intr_disable(devinfo);
1736
1737 brcmf_detach(&pdev->dev);
1738
1739 kfree(bus->bus_priv.pcie);
1740 kfree(bus->msgbuf->flowrings);
1741 kfree(bus->msgbuf);
1742 kfree(bus);
1743
1744 brcmf_pcie_release_irq(devinfo);
1745 brcmf_pcie_release_scratchbuffers(devinfo);
1746 brcmf_pcie_release_ringbuffers(devinfo);
1747 brcmf_pcie_reset_device(devinfo);
1748 brcmf_pcie_release_resource(devinfo);
1749
1750 if (devinfo->ci)
1751 brcmf_chip_detach(devinfo->ci);
1752
1753 kfree(devinfo);
1754 dev_set_drvdata(&pdev->dev, NULL);
1755 }
1756
1757
1758 #ifdef CONFIG_PM
1759
1760
1761 static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1762 {
1763 struct brcmf_pciedev_info *devinfo;
1764 struct brcmf_bus *bus;
1765 int err;
1766
1767 brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1768
1769 bus = dev_get_drvdata(&pdev->dev);
1770 devinfo = bus->bus_priv.pcie->devinfo;
1771
1772 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1773
1774 devinfo->mbdata_completed = false;
1775 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1776
1777 wait_event_timeout(devinfo->mbdata_resp_wait,
1778 devinfo->mbdata_completed,
1779 msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1780 if (!devinfo->mbdata_completed) {
1781 brcmf_err("Timeout on response for entering D3 substate\n");
1782 return -EIO;
1783 }
1784 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
1785
1786 err = pci_save_state(pdev);
1787 if (err)
1788 brcmf_err("pci_save_state failed, err=%d\n", err);
1789 if ((err) || (!devinfo->wowl_enabled)) {
1790 brcmf_chip_detach(devinfo->ci);
1791 devinfo->ci = NULL;
1792 brcmf_pcie_remove(pdev);
1793 return 0;
1794 }
1795
1796 return pci_prepare_to_sleep(pdev);
1797 }
1798
1799 static int brcmf_pcie_resume(struct pci_dev *pdev)
1800 {
1801 struct brcmf_pciedev_info *devinfo;
1802 struct brcmf_bus *bus;
1803 int err;
1804
1805 bus = dev_get_drvdata(&pdev->dev);
1806 brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
1807
1808 err = pci_set_power_state(pdev, PCI_D0);
1809 if (err) {
1810 brcmf_err("pci_set_power_state failed, err=%d\n", err);
1811 goto cleanup;
1812 }
1813 pci_restore_state(pdev);
1814 pci_enable_wake(pdev, PCI_D3hot, false);
1815 pci_enable_wake(pdev, PCI_D3cold, false);
1816
1817 /* Check if device is still up and running, if so we are ready */
1818 if (bus) {
1819 devinfo = bus->bus_priv.pcie->devinfo;
1820 if (brcmf_pcie_read_reg32(devinfo,
1821 BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
1822 if (brcmf_pcie_send_mb_data(devinfo,
1823 BRCMF_H2D_HOST_D0_INFORM))
1824 goto cleanup;
1825 brcmf_dbg(PCIE, "Hot resume, continue....\n");
1826 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1827 brcmf_bus_change_state(bus, BRCMF_BUS_DATA);
1828 brcmf_pcie_intr_enable(devinfo);
1829 return 0;
1830 }
1831 }
1832
1833 cleanup:
1834 if (bus) {
1835 devinfo = bus->bus_priv.pcie->devinfo;
1836 brcmf_chip_detach(devinfo->ci);
1837 devinfo->ci = NULL;
1838 brcmf_pcie_remove(pdev);
1839 }
1840 err = brcmf_pcie_probe(pdev, NULL);
1841 if (err)
1842 brcmf_err("probe after resume failed, err=%d\n", err);
1843
1844 return err;
1845 }
1846
1847
1848 #endif /* CONFIG_PM */
1849
1850
1851 #define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1852 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1853
1854 static struct pci_device_id brcmf_pcie_devid_table[] = {
1855 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_DEVICE_ID),
1856 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1857 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1858 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1859 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1860 { /* end: all zeroes */ }
1861 };
1862
1863
1864 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
1865
1866
1867 static struct pci_driver brcmf_pciedrvr = {
1868 .node = {},
1869 .name = KBUILD_MODNAME,
1870 .id_table = brcmf_pcie_devid_table,
1871 .probe = brcmf_pcie_probe,
1872 .remove = brcmf_pcie_remove,
1873 #ifdef CONFIG_PM
1874 .suspend = brcmf_pcie_suspend,
1875 .resume = brcmf_pcie_resume
1876 #endif /* CONFIG_PM */
1877 };
1878
1879
1880 void brcmf_pcie_register(void)
1881 {
1882 int err;
1883
1884 brcmf_dbg(PCIE, "Enter\n");
1885 err = pci_register_driver(&brcmf_pciedrvr);
1886 if (err)
1887 brcmf_err("PCIE driver registration failed, err=%d\n", err);
1888 }
1889
1890
1891 void brcmf_pcie_exit(void)
1892 {
1893 brcmf_dbg(PCIE, "Enter\n");
1894 pci_unregister_driver(&brcmf_pciedrvr);
1895 }
Linux kernel - Deliverables
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