1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program;
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
27 * Contact Information:
28 * Intel Linux Wireless <linuxwifi@intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
34 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
35 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
36 * All rights reserved.
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *****************************************************************************/
65 #include <linux/devcoredump.h>
73 static ssize_t
iwl_mvm_read_coredump(char *buffer
, loff_t offset
, size_t count
,
74 void *data
, size_t datalen
)
76 const struct iwl_mvm_dump_ptrs
*dump_ptrs
= data
;
78 ssize_t bytes_read_trans
;
80 if (offset
< dump_ptrs
->op_mode_len
) {
81 bytes_read
= min_t(ssize_t
, count
,
82 dump_ptrs
->op_mode_len
- offset
);
83 memcpy(buffer
, (u8
*)dump_ptrs
->op_mode_ptr
+ offset
,
94 if (!dump_ptrs
->trans_ptr
)
97 offset
-= dump_ptrs
->op_mode_len
;
98 bytes_read_trans
= min_t(ssize_t
, count
,
99 dump_ptrs
->trans_ptr
->len
- offset
);
100 memcpy(buffer
+ bytes_read
,
101 (u8
*)dump_ptrs
->trans_ptr
->data
+ offset
,
104 return bytes_read
+ bytes_read_trans
;
107 static void iwl_mvm_free_coredump(void *data
)
109 const struct iwl_mvm_dump_ptrs
*fw_error_dump
= data
;
111 vfree(fw_error_dump
->op_mode_ptr
);
112 vfree(fw_error_dump
->trans_ptr
);
113 kfree(fw_error_dump
);
116 #define RADIO_REG_MAX_READ 0x2ad
117 static void iwl_mvm_read_radio_reg(struct iwl_mvm
*mvm
,
118 struct iwl_fw_error_dump_data
**dump_data
)
120 u8
*pos
= (void *)(*dump_data
)->data
;
124 if (!iwl_trans_grab_nic_access(mvm
->trans
, &flags
))
127 (*dump_data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG
);
128 (*dump_data
)->len
= cpu_to_le32(RADIO_REG_MAX_READ
);
130 for (i
= 0; i
< RADIO_REG_MAX_READ
; i
++) {
131 u32 rd_cmd
= RADIO_RSP_RD_CMD
;
133 rd_cmd
|= i
<< RADIO_RSP_ADDR_POS
;
134 iwl_write_prph_no_grab(mvm
->trans
, RSP_RADIO_CMD
, rd_cmd
);
135 *pos
= (u8
)iwl_read_prph_no_grab(mvm
->trans
, RSP_RADIO_RDDAT
);
140 *dump_data
= iwl_fw_error_next_data(*dump_data
);
142 iwl_trans_release_nic_access(mvm
->trans
, &flags
);
145 static void iwl_mvm_dump_fifos(struct iwl_mvm
*mvm
,
146 struct iwl_fw_error_dump_data
**dump_data
)
148 struct iwl_fw_error_dump_fifo
*fifo_hdr
;
154 if (!iwl_trans_grab_nic_access(mvm
->trans
, &flags
))
157 /* Pull RXF data from all RXFs */
158 for (i
= 0; i
< ARRAY_SIZE(mvm
->shared_mem_cfg
.rxfifo_size
); i
++) {
160 * Keep aside the additional offset that might be needed for
163 u32 offset_diff
= RXF_DIFF_FROM_PREV
* i
;
165 fifo_hdr
= (void *)(*dump_data
)->data
;
166 fifo_data
= (void *)fifo_hdr
->data
;
167 fifo_len
= mvm
->shared_mem_cfg
.rxfifo_size
[i
];
169 /* No need to try to read the data if the length is 0 */
173 /* Add a TLV for the RXF */
174 (*dump_data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_RXF
);
175 (*dump_data
)->len
= cpu_to_le32(fifo_len
+ sizeof(*fifo_hdr
));
177 fifo_hdr
->fifo_num
= cpu_to_le32(i
);
178 fifo_hdr
->available_bytes
=
179 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
183 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
187 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
190 fifo_hdr
->fence_ptr
=
191 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
194 fifo_hdr
->fence_mode
=
195 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
200 iwl_trans_write_prph(mvm
->trans
,
201 RXF_SET_FENCE_MODE
+ offset_diff
, 0x1);
202 /* Set fence pointer to the same place like WR pointer */
203 iwl_trans_write_prph(mvm
->trans
,
204 RXF_LD_WR2FENCE
+ offset_diff
, 0x1);
205 /* Set fence offset */
206 iwl_trans_write_prph(mvm
->trans
,
207 RXF_LD_FENCE_OFFSET_ADDR
+ offset_diff
,
211 fifo_len
/= sizeof(u32
); /* Size in DWORDS */
212 for (j
= 0; j
< fifo_len
; j
++)
213 fifo_data
[j
] = iwl_trans_read_prph(mvm
->trans
,
214 RXF_FIFO_RD_FENCE_INC
+
216 *dump_data
= iwl_fw_error_next_data(*dump_data
);
219 /* Pull TXF data from all TXFs */
220 for (i
= 0; i
< ARRAY_SIZE(mvm
->shared_mem_cfg
.txfifo_size
); i
++) {
221 /* Mark the number of TXF we're pulling now */
222 iwl_trans_write_prph(mvm
->trans
, TXF_LARC_NUM
, i
);
224 fifo_hdr
= (void *)(*dump_data
)->data
;
225 fifo_data
= (void *)fifo_hdr
->data
;
226 fifo_len
= mvm
->shared_mem_cfg
.txfifo_size
[i
];
228 /* No need to try to read the data if the length is 0 */
232 /* Add a TLV for the FIFO */
233 (*dump_data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_TXF
);
234 (*dump_data
)->len
= cpu_to_le32(fifo_len
+ sizeof(*fifo_hdr
));
236 fifo_hdr
->fifo_num
= cpu_to_le32(i
);
237 fifo_hdr
->available_bytes
=
238 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
241 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
244 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
246 fifo_hdr
->fence_ptr
=
247 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
249 fifo_hdr
->fence_mode
=
250 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
253 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
254 iwl_trans_write_prph(mvm
->trans
, TXF_READ_MODIFY_ADDR
,
257 /* Dummy-read to advance the read pointer to the head */
258 iwl_trans_read_prph(mvm
->trans
, TXF_READ_MODIFY_DATA
);
261 fifo_len
/= sizeof(u32
); /* Size in DWORDS */
262 for (j
= 0; j
< fifo_len
; j
++)
263 fifo_data
[j
] = iwl_trans_read_prph(mvm
->trans
,
264 TXF_READ_MODIFY_DATA
);
265 *dump_data
= iwl_fw_error_next_data(*dump_data
);
268 if (fw_has_capa(&mvm
->fw
->ucode_capa
,
269 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
)) {
270 /* Pull UMAC internal TXF data from all TXFs */
272 i
< ARRAY_SIZE(mvm
->shared_mem_cfg
.internal_txfifo_size
);
274 fifo_hdr
= (void *)(*dump_data
)->data
;
275 fifo_data
= (void *)fifo_hdr
->data
;
276 fifo_len
= mvm
->shared_mem_cfg
.internal_txfifo_size
[i
];
278 /* No need to try to read the data if the length is 0 */
282 /* Add a TLV for the internal FIFOs */
284 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF
);
286 cpu_to_le32(fifo_len
+ sizeof(*fifo_hdr
));
288 fifo_hdr
->fifo_num
= cpu_to_le32(i
);
290 /* Mark the number of TXF we're pulling now */
291 iwl_trans_write_prph(mvm
->trans
, TXF_CPU2_NUM
, i
+
292 ARRAY_SIZE(mvm
->shared_mem_cfg
.txfifo_size
));
294 fifo_hdr
->available_bytes
=
295 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
296 TXF_CPU2_FIFO_ITEM_CNT
));
298 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
301 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
303 fifo_hdr
->fence_ptr
=
304 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
305 TXF_CPU2_FENCE_PTR
));
306 fifo_hdr
->fence_mode
=
307 cpu_to_le32(iwl_trans_read_prph(mvm
->trans
,
308 TXF_CPU2_LOCK_FENCE
));
310 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
311 iwl_trans_write_prph(mvm
->trans
,
312 TXF_CPU2_READ_MODIFY_ADDR
,
315 /* Dummy-read to advance the read pointer to head */
316 iwl_trans_read_prph(mvm
->trans
,
317 TXF_CPU2_READ_MODIFY_DATA
);
320 fifo_len
/= sizeof(u32
); /* Size in DWORDS */
321 for (j
= 0; j
< fifo_len
; j
++)
323 iwl_trans_read_prph(mvm
->trans
,
324 TXF_CPU2_READ_MODIFY_DATA
);
325 *dump_data
= iwl_fw_error_next_data(*dump_data
);
329 iwl_trans_release_nic_access(mvm
->trans
, &flags
);
332 void iwl_mvm_free_fw_dump_desc(struct iwl_mvm
*mvm
)
334 if (mvm
->fw_dump_desc
== &iwl_mvm_dump_desc_assert
)
337 kfree(mvm
->fw_dump_desc
);
338 mvm
->fw_dump_desc
= NULL
;
341 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
342 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */
344 struct iwl_prph_range
{
348 static const struct iwl_prph_range iwl_prph_dump_addr_comm
[] = {
349 { .start
= 0x00a00000, .end
= 0x00a00000 },
350 { .start
= 0x00a0000c, .end
= 0x00a00024 },
351 { .start
= 0x00a0002c, .end
= 0x00a0003c },
352 { .start
= 0x00a00410, .end
= 0x00a00418 },
353 { .start
= 0x00a00420, .end
= 0x00a00420 },
354 { .start
= 0x00a00428, .end
= 0x00a00428 },
355 { .start
= 0x00a00430, .end
= 0x00a0043c },
356 { .start
= 0x00a00444, .end
= 0x00a00444 },
357 { .start
= 0x00a004c0, .end
= 0x00a004cc },
358 { .start
= 0x00a004d8, .end
= 0x00a004d8 },
359 { .start
= 0x00a004e0, .end
= 0x00a004f0 },
360 { .start
= 0x00a00840, .end
= 0x00a00840 },
361 { .start
= 0x00a00850, .end
= 0x00a00858 },
362 { .start
= 0x00a01004, .end
= 0x00a01008 },
363 { .start
= 0x00a01010, .end
= 0x00a01010 },
364 { .start
= 0x00a01018, .end
= 0x00a01018 },
365 { .start
= 0x00a01024, .end
= 0x00a01024 },
366 { .start
= 0x00a0102c, .end
= 0x00a01034 },
367 { .start
= 0x00a0103c, .end
= 0x00a01040 },
368 { .start
= 0x00a01048, .end
= 0x00a01094 },
369 { .start
= 0x00a01c00, .end
= 0x00a01c20 },
370 { .start
= 0x00a01c58, .end
= 0x00a01c58 },
371 { .start
= 0x00a01c7c, .end
= 0x00a01c7c },
372 { .start
= 0x00a01c28, .end
= 0x00a01c54 },
373 { .start
= 0x00a01c5c, .end
= 0x00a01c5c },
374 { .start
= 0x00a01c60, .end
= 0x00a01cdc },
375 { .start
= 0x00a01ce0, .end
= 0x00a01d0c },
376 { .start
= 0x00a01d18, .end
= 0x00a01d20 },
377 { .start
= 0x00a01d2c, .end
= 0x00a01d30 },
378 { .start
= 0x00a01d40, .end
= 0x00a01d5c },
379 { .start
= 0x00a01d80, .end
= 0x00a01d80 },
380 { .start
= 0x00a01d98, .end
= 0x00a01d9c },
381 { .start
= 0x00a01da8, .end
= 0x00a01da8 },
382 { .start
= 0x00a01db8, .end
= 0x00a01df4 },
383 { .start
= 0x00a01dc0, .end
= 0x00a01dfc },
384 { .start
= 0x00a01e00, .end
= 0x00a01e2c },
385 { .start
= 0x00a01e40, .end
= 0x00a01e60 },
386 { .start
= 0x00a01e68, .end
= 0x00a01e6c },
387 { .start
= 0x00a01e74, .end
= 0x00a01e74 },
388 { .start
= 0x00a01e84, .end
= 0x00a01e90 },
389 { .start
= 0x00a01e9c, .end
= 0x00a01ec4 },
390 { .start
= 0x00a01ed0, .end
= 0x00a01ee0 },
391 { .start
= 0x00a01f00, .end
= 0x00a01f1c },
392 { .start
= 0x00a01f44, .end
= 0x00a01ffc },
393 { .start
= 0x00a02000, .end
= 0x00a02048 },
394 { .start
= 0x00a02068, .end
= 0x00a020f0 },
395 { .start
= 0x00a02100, .end
= 0x00a02118 },
396 { .start
= 0x00a02140, .end
= 0x00a0214c },
397 { .start
= 0x00a02168, .end
= 0x00a0218c },
398 { .start
= 0x00a021c0, .end
= 0x00a021c0 },
399 { .start
= 0x00a02400, .end
= 0x00a02410 },
400 { .start
= 0x00a02418, .end
= 0x00a02420 },
401 { .start
= 0x00a02428, .end
= 0x00a0242c },
402 { .start
= 0x00a02434, .end
= 0x00a02434 },
403 { .start
= 0x00a02440, .end
= 0x00a02460 },
404 { .start
= 0x00a02468, .end
= 0x00a024b0 },
405 { .start
= 0x00a024c8, .end
= 0x00a024cc },
406 { .start
= 0x00a02500, .end
= 0x00a02504 },
407 { .start
= 0x00a0250c, .end
= 0x00a02510 },
408 { .start
= 0x00a02540, .end
= 0x00a02554 },
409 { .start
= 0x00a02580, .end
= 0x00a025f4 },
410 { .start
= 0x00a02600, .end
= 0x00a0260c },
411 { .start
= 0x00a02648, .end
= 0x00a02650 },
412 { .start
= 0x00a02680, .end
= 0x00a02680 },
413 { .start
= 0x00a026c0, .end
= 0x00a026d0 },
414 { .start
= 0x00a02700, .end
= 0x00a0270c },
415 { .start
= 0x00a02804, .end
= 0x00a02804 },
416 { .start
= 0x00a02818, .end
= 0x00a0281c },
417 { .start
= 0x00a02c00, .end
= 0x00a02db4 },
418 { .start
= 0x00a02df4, .end
= 0x00a02fb0 },
419 { .start
= 0x00a03000, .end
= 0x00a03014 },
420 { .start
= 0x00a0301c, .end
= 0x00a0302c },
421 { .start
= 0x00a03034, .end
= 0x00a03038 },
422 { .start
= 0x00a03040, .end
= 0x00a03048 },
423 { .start
= 0x00a03060, .end
= 0x00a03068 },
424 { .start
= 0x00a03070, .end
= 0x00a03074 },
425 { .start
= 0x00a0307c, .end
= 0x00a0307c },
426 { .start
= 0x00a03080, .end
= 0x00a03084 },
427 { .start
= 0x00a0308c, .end
= 0x00a03090 },
428 { .start
= 0x00a03098, .end
= 0x00a03098 },
429 { .start
= 0x00a030a0, .end
= 0x00a030a0 },
430 { .start
= 0x00a030a8, .end
= 0x00a030b4 },
431 { .start
= 0x00a030bc, .end
= 0x00a030bc },
432 { .start
= 0x00a030c0, .end
= 0x00a0312c },
433 { .start
= 0x00a03c00, .end
= 0x00a03c5c },
434 { .start
= 0x00a04400, .end
= 0x00a04454 },
435 { .start
= 0x00a04460, .end
= 0x00a04474 },
436 { .start
= 0x00a044c0, .end
= 0x00a044ec },
437 { .start
= 0x00a04500, .end
= 0x00a04504 },
438 { .start
= 0x00a04510, .end
= 0x00a04538 },
439 { .start
= 0x00a04540, .end
= 0x00a04548 },
440 { .start
= 0x00a04560, .end
= 0x00a0457c },
441 { .start
= 0x00a04590, .end
= 0x00a04598 },
442 { .start
= 0x00a045c0, .end
= 0x00a045f4 },
443 { .start
= 0x00a44000, .end
= 0x00a7bf80 },
446 static const struct iwl_prph_range iwl_prph_dump_addr_9000
[] = {
447 { .start
= 0x00a05c00, .end
= 0x00a05c18 },
448 { .start
= 0x00a05400, .end
= 0x00a056e8 },
449 { .start
= 0x00a08000, .end
= 0x00a098bc },
450 { .start
= 0x00adfc00, .end
= 0x00adfd1c },
451 { .start
= 0x00a02400, .end
= 0x00a02758 },
454 static u32
iwl_dump_prph(struct iwl_trans
*trans
,
455 struct iwl_fw_error_dump_data
**data
,
456 const struct iwl_prph_range
*iwl_prph_dump_addr
,
459 struct iwl_fw_error_dump_prph
*prph
;
463 if (!iwl_trans_grab_nic_access(trans
, &flags
))
466 for (i
= 0; i
< range_len
; i
++) {
467 /* The range includes both boundaries */
468 int num_bytes_in_chunk
= iwl_prph_dump_addr
[i
].end
-
469 iwl_prph_dump_addr
[i
].start
+ 4;
473 prph_len
+= sizeof(**data
) + sizeof(*prph
) + num_bytes_in_chunk
;
475 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH
);
476 (*data
)->len
= cpu_to_le32(sizeof(*prph
) +
478 prph
= (void *)(*data
)->data
;
479 prph
->prph_start
= cpu_to_le32(iwl_prph_dump_addr
[i
].start
);
480 val
= (void *)prph
->data
;
482 for (reg
= iwl_prph_dump_addr
[i
].start
;
483 reg
<= iwl_prph_dump_addr
[i
].end
;
485 *val
++ = cpu_to_le32(iwl_read_prph_no_grab(trans
,
488 *data
= iwl_fw_error_next_data(*data
);
491 iwl_trans_release_nic_access(trans
, &flags
);
496 void iwl_mvm_fw_error_dump(struct iwl_mvm
*mvm
)
498 struct iwl_fw_error_dump_file
*dump_file
;
499 struct iwl_fw_error_dump_data
*dump_data
;
500 struct iwl_fw_error_dump_info
*dump_info
;
501 struct iwl_fw_error_dump_mem
*dump_mem
;
502 struct iwl_fw_error_dump_trigger_desc
*dump_trig
;
503 struct iwl_mvm_dump_ptrs
*fw_error_dump
;
504 u32 sram_len
, sram_ofs
;
505 struct iwl_fw_dbg_mem_seg_tlv
* const *fw_dbg_mem
=
506 mvm
->fw
->dbg_mem_tlv
;
507 u32 file_len
, fifo_data_len
= 0, prph_len
= 0, radio_len
= 0;
508 u32 smem_len
= mvm
->fw
->dbg_dynamic_mem
? 0 : mvm
->cfg
->smem_len
;
509 u32 sram2_len
= mvm
->fw
->dbg_dynamic_mem
? 0 : mvm
->cfg
->dccm2_len
;
510 bool monitor_dump_only
= false;
513 if (!IWL_MVM_COLLECT_FW_ERR_DUMP
&&
514 !mvm
->trans
->dbg_dest_tlv
)
517 lockdep_assert_held(&mvm
->mutex
);
519 /* there's no point in fw dump if the bus is dead */
520 if (test_bit(STATUS_TRANS_DEAD
, &mvm
->trans
->status
)) {
521 IWL_ERR(mvm
, "Skip fw error dump since bus is dead\n");
525 if (mvm
->fw_dump_trig
&&
526 mvm
->fw_dump_trig
->mode
& IWL_FW_DBG_TRIGGER_MONITOR_ONLY
)
527 monitor_dump_only
= true;
529 fw_error_dump
= kzalloc(sizeof(*fw_error_dump
), GFP_KERNEL
);
533 /* SRAM - include stack CCM if driver knows the values for it */
534 if (!mvm
->cfg
->dccm_offset
|| !mvm
->cfg
->dccm_len
) {
535 const struct fw_img
*img
;
537 img
= &mvm
->fw
->img
[mvm
->cur_ucode
];
538 sram_ofs
= img
->sec
[IWL_UCODE_SECTION_DATA
].offset
;
539 sram_len
= img
->sec
[IWL_UCODE_SECTION_DATA
].len
;
541 sram_ofs
= mvm
->cfg
->dccm_offset
;
542 sram_len
= mvm
->cfg
->dccm_len
;
545 /* reading RXF/TXF sizes */
546 if (test_bit(STATUS_FW_ERROR
, &mvm
->trans
->status
)) {
547 struct iwl_mvm_shared_mem_cfg
*mem_cfg
= &mvm
->shared_mem_cfg
;
552 for (i
= 0; i
< ARRAY_SIZE(mem_cfg
->rxfifo_size
); i
++) {
553 if (!mem_cfg
->rxfifo_size
[i
])
556 /* Add header info */
557 fifo_data_len
+= mem_cfg
->rxfifo_size
[i
] +
559 sizeof(struct iwl_fw_error_dump_fifo
);
562 for (i
= 0; i
< ARRAY_SIZE(mem_cfg
->txfifo_size
); i
++) {
563 if (!mem_cfg
->txfifo_size
[i
])
566 /* Add header info */
567 fifo_data_len
+= mem_cfg
->txfifo_size
[i
] +
569 sizeof(struct iwl_fw_error_dump_fifo
);
572 if (fw_has_capa(&mvm
->fw
->ucode_capa
,
573 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
)) {
575 i
< ARRAY_SIZE(mem_cfg
->internal_txfifo_size
);
577 if (!mem_cfg
->internal_txfifo_size
[i
])
580 /* Add header info */
582 mem_cfg
->internal_txfifo_size
[i
] +
584 sizeof(struct iwl_fw_error_dump_fifo
);
588 /* Make room for PRPH registers */
589 for (i
= 0; i
< ARRAY_SIZE(iwl_prph_dump_addr_comm
); i
++) {
590 /* The range includes both boundaries */
591 int num_bytes_in_chunk
=
592 iwl_prph_dump_addr_comm
[i
].end
-
593 iwl_prph_dump_addr_comm
[i
].start
+ 4;
595 prph_len
+= sizeof(*dump_data
) +
596 sizeof(struct iwl_fw_error_dump_prph
) +
600 if (mvm
->cfg
->mq_rx_supported
) {
602 ARRAY_SIZE(iwl_prph_dump_addr_9000
); i
++) {
603 /* The range includes both boundaries */
604 int num_bytes_in_chunk
=
605 iwl_prph_dump_addr_9000
[i
].end
-
606 iwl_prph_dump_addr_9000
[i
].start
+ 4;
608 prph_len
+= sizeof(*dump_data
) +
609 sizeof(struct iwl_fw_error_dump_prph
) +
614 if (mvm
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
)
615 radio_len
= sizeof(*dump_data
) + RADIO_REG_MAX_READ
;
618 file_len
= sizeof(*dump_file
) +
619 sizeof(*dump_data
) * 2 +
625 /* Make room for the SMEM, if it exists */
627 file_len
+= sizeof(*dump_data
) + sizeof(*dump_mem
) + smem_len
;
629 /* Make room for the secondary SRAM, if it exists */
631 file_len
+= sizeof(*dump_data
) + sizeof(*dump_mem
) + sram2_len
;
633 /* Make room for MEM segments */
634 for (i
= 0; i
< ARRAY_SIZE(mvm
->fw
->dbg_mem_tlv
); i
++) {
636 file_len
+= sizeof(*dump_data
) + sizeof(*dump_mem
) +
637 le32_to_cpu(fw_dbg_mem
[i
]->len
);
640 /* Make room for fw's virtual image pages, if it exists */
641 if (mvm
->fw
->img
[mvm
->cur_ucode
].paging_mem_size
&&
642 mvm
->fw_paging_db
[0].fw_paging_block
)
643 file_len
+= mvm
->num_of_paging_blk
*
644 (sizeof(*dump_data
) +
645 sizeof(struct iwl_fw_error_dump_paging
) +
648 /* If we only want a monitor dump, reset the file length */
649 if (monitor_dump_only
) {
650 file_len
= sizeof(*dump_file
) + sizeof(*dump_data
) +
655 * In 8000 HW family B-step include the ICCM (which resides separately)
657 if (mvm
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
&&
658 CSR_HW_REV_STEP(mvm
->trans
->hw_rev
) == SILICON_B_STEP
)
659 file_len
+= sizeof(*dump_data
) + sizeof(*dump_mem
) +
662 if (mvm
->fw_dump_desc
)
663 file_len
+= sizeof(*dump_data
) + sizeof(*dump_trig
) +
664 mvm
->fw_dump_desc
->len
;
666 if (!mvm
->fw
->dbg_dynamic_mem
)
667 file_len
+= sram_len
+ sizeof(*dump_mem
);
669 dump_file
= vzalloc(file_len
);
671 kfree(fw_error_dump
);
675 fw_error_dump
->op_mode_ptr
= dump_file
;
677 dump_file
->barker
= cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER
);
678 dump_data
= (void *)dump_file
->data
;
680 dump_data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO
);
681 dump_data
->len
= cpu_to_le32(sizeof(*dump_info
));
682 dump_info
= (void *)dump_data
->data
;
683 dump_info
->device_family
=
684 mvm
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
?
685 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7
) :
686 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8
);
687 dump_info
->hw_step
= cpu_to_le32(CSR_HW_REV_STEP(mvm
->trans
->hw_rev
));
688 memcpy(dump_info
->fw_human_readable
, mvm
->fw
->human_readable
,
689 sizeof(dump_info
->fw_human_readable
));
690 strncpy(dump_info
->dev_human_readable
, mvm
->cfg
->name
,
691 sizeof(dump_info
->dev_human_readable
));
692 strncpy(dump_info
->bus_human_readable
, mvm
->dev
->bus
->name
,
693 sizeof(dump_info
->bus_human_readable
));
695 dump_data
= iwl_fw_error_next_data(dump_data
);
696 /* We only dump the FIFOs if the FW is in error state */
697 if (test_bit(STATUS_FW_ERROR
, &mvm
->trans
->status
)) {
698 iwl_mvm_dump_fifos(mvm
, &dump_data
);
700 iwl_mvm_read_radio_reg(mvm
, &dump_data
);
703 if (mvm
->fw_dump_desc
) {
704 dump_data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO
);
705 dump_data
->len
= cpu_to_le32(sizeof(*dump_trig
) +
706 mvm
->fw_dump_desc
->len
);
707 dump_trig
= (void *)dump_data
->data
;
708 memcpy(dump_trig
, &mvm
->fw_dump_desc
->trig_desc
,
709 sizeof(*dump_trig
) + mvm
->fw_dump_desc
->len
);
711 dump_data
= iwl_fw_error_next_data(dump_data
);
714 /* In case we only want monitor dump, skip to dump trasport data */
715 if (monitor_dump_only
)
716 goto dump_trans_data
;
718 if (!mvm
->fw
->dbg_dynamic_mem
) {
719 dump_data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_MEM
);
720 dump_data
->len
= cpu_to_le32(sram_len
+ sizeof(*dump_mem
));
721 dump_mem
= (void *)dump_data
->data
;
722 dump_mem
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM
);
723 dump_mem
->offset
= cpu_to_le32(sram_ofs
);
724 iwl_trans_read_mem_bytes(mvm
->trans
, sram_ofs
, dump_mem
->data
,
726 dump_data
= iwl_fw_error_next_data(dump_data
);
729 for (i
= 0; i
< ARRAY_SIZE(mvm
->fw
->dbg_mem_tlv
); i
++) {
731 u32 len
= le32_to_cpu(fw_dbg_mem
[i
]->len
);
732 u32 ofs
= le32_to_cpu(fw_dbg_mem
[i
]->ofs
);
734 dump_data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_MEM
);
735 dump_data
->len
= cpu_to_le32(len
+
737 dump_mem
= (void *)dump_data
->data
;
738 dump_mem
->type
= fw_dbg_mem
[i
]->data_type
;
739 dump_mem
->offset
= cpu_to_le32(ofs
);
740 iwl_trans_read_mem_bytes(mvm
->trans
, ofs
,
743 dump_data
= iwl_fw_error_next_data(dump_data
);
748 dump_data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_MEM
);
749 dump_data
->len
= cpu_to_le32(smem_len
+ sizeof(*dump_mem
));
750 dump_mem
= (void *)dump_data
->data
;
751 dump_mem
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SMEM
);
752 dump_mem
->offset
= cpu_to_le32(mvm
->cfg
->smem_offset
);
753 iwl_trans_read_mem_bytes(mvm
->trans
, mvm
->cfg
->smem_offset
,
754 dump_mem
->data
, smem_len
);
755 dump_data
= iwl_fw_error_next_data(dump_data
);
759 dump_data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_MEM
);
760 dump_data
->len
= cpu_to_le32(sram2_len
+ sizeof(*dump_mem
));
761 dump_mem
= (void *)dump_data
->data
;
762 dump_mem
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM
);
763 dump_mem
->offset
= cpu_to_le32(mvm
->cfg
->dccm2_offset
);
764 iwl_trans_read_mem_bytes(mvm
->trans
, mvm
->cfg
->dccm2_offset
,
765 dump_mem
->data
, sram2_len
);
766 dump_data
= iwl_fw_error_next_data(dump_data
);
769 if (mvm
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
&&
770 CSR_HW_REV_STEP(mvm
->trans
->hw_rev
) == SILICON_B_STEP
) {
771 dump_data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_MEM
);
772 dump_data
->len
= cpu_to_le32(IWL8260_ICCM_LEN
+
774 dump_mem
= (void *)dump_data
->data
;
775 dump_mem
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM
);
776 dump_mem
->offset
= cpu_to_le32(IWL8260_ICCM_OFFSET
);
777 iwl_trans_read_mem_bytes(mvm
->trans
, IWL8260_ICCM_OFFSET
,
778 dump_mem
->data
, IWL8260_ICCM_LEN
);
779 dump_data
= iwl_fw_error_next_data(dump_data
);
782 /* Dump fw's virtual image */
783 if (mvm
->fw
->img
[mvm
->cur_ucode
].paging_mem_size
&&
784 mvm
->fw_paging_db
[0].fw_paging_block
) {
785 for (i
= 1; i
< mvm
->num_of_paging_blk
+ 1; i
++) {
786 struct iwl_fw_error_dump_paging
*paging
;
788 mvm
->fw_paging_db
[i
].fw_paging_block
;
790 dump_data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING
);
791 dump_data
->len
= cpu_to_le32(sizeof(*paging
) +
793 paging
= (void *)dump_data
->data
;
794 paging
->index
= cpu_to_le32(i
);
795 memcpy(paging
->data
, page_address(pages
),
797 dump_data
= iwl_fw_error_next_data(dump_data
);
802 iwl_dump_prph(mvm
->trans
, &dump_data
,
803 iwl_prph_dump_addr_comm
,
804 ARRAY_SIZE(iwl_prph_dump_addr_comm
));
806 if (mvm
->cfg
->mq_rx_supported
)
807 iwl_dump_prph(mvm
->trans
, &dump_data
,
808 iwl_prph_dump_addr_9000
,
809 ARRAY_SIZE(iwl_prph_dump_addr_9000
));
813 fw_error_dump
->trans_ptr
= iwl_trans_dump_data(mvm
->trans
,
815 fw_error_dump
->op_mode_len
= file_len
;
816 if (fw_error_dump
->trans_ptr
)
817 file_len
+= fw_error_dump
->trans_ptr
->len
;
818 dump_file
->file_len
= cpu_to_le32(file_len
);
820 dev_coredumpm(mvm
->trans
->dev
, THIS_MODULE
, fw_error_dump
, 0,
821 GFP_KERNEL
, iwl_mvm_read_coredump
, iwl_mvm_free_coredump
);
824 iwl_mvm_free_fw_dump_desc(mvm
);
825 mvm
->fw_dump_trig
= NULL
;
826 clear_bit(IWL_MVM_STATUS_DUMPING_FW_LOG
, &mvm
->status
);
829 const struct iwl_mvm_dump_desc iwl_mvm_dump_desc_assert
= {
831 .type
= cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT
),
835 int iwl_mvm_fw_dbg_collect_desc(struct iwl_mvm
*mvm
,
836 const struct iwl_mvm_dump_desc
*desc
,
837 const struct iwl_fw_dbg_trigger_tlv
*trigger
)
839 unsigned int delay
= 0;
842 delay
= msecs_to_jiffies(le32_to_cpu(trigger
->stop_delay
));
844 if (test_and_set_bit(IWL_MVM_STATUS_DUMPING_FW_LOG
, &mvm
->status
))
847 if (WARN_ON(mvm
->fw_dump_desc
))
848 iwl_mvm_free_fw_dump_desc(mvm
);
850 IWL_WARN(mvm
, "Collecting data: trigger %d fired.\n",
851 le32_to_cpu(desc
->trig_desc
.type
));
853 mvm
->fw_dump_desc
= desc
;
854 mvm
->fw_dump_trig
= trigger
;
856 queue_delayed_work(system_wq
, &mvm
->fw_dump_wk
, delay
);
861 int iwl_mvm_fw_dbg_collect(struct iwl_mvm
*mvm
, enum iwl_fw_dbg_trigger trig
,
862 const char *str
, size_t len
,
863 const struct iwl_fw_dbg_trigger_tlv
*trigger
)
865 struct iwl_mvm_dump_desc
*desc
;
867 desc
= kzalloc(sizeof(*desc
) + len
, GFP_ATOMIC
);
872 desc
->trig_desc
.type
= cpu_to_le32(trig
);
873 memcpy(desc
->trig_desc
.data
, str
, len
);
875 return iwl_mvm_fw_dbg_collect_desc(mvm
, desc
, trigger
);
878 int iwl_mvm_fw_dbg_collect_trig(struct iwl_mvm
*mvm
,
879 struct iwl_fw_dbg_trigger_tlv
*trigger
,
880 const char *fmt
, ...)
882 u16 occurrences
= le16_to_cpu(trigger
->occurrences
);
892 buf
[sizeof(buf
) - 1] = '\0';
895 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
898 /* check for truncation */
899 if (WARN_ON_ONCE(buf
[sizeof(buf
) - 1]))
900 buf
[sizeof(buf
) - 1] = '\0';
902 len
= strlen(buf
) + 1;
905 ret
= iwl_mvm_fw_dbg_collect(mvm
, le32_to_cpu(trigger
->id
), buf
, len
,
911 trigger
->occurrences
= cpu_to_le16(occurrences
- 1);
915 static inline void iwl_mvm_restart_early_start(struct iwl_mvm
*mvm
)
917 if (mvm
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
)
918 iwl_clear_bits_prph(mvm
->trans
, MON_BUFF_SAMPLE_CTL
, 0x100);
920 iwl_write_prph(mvm
->trans
, DBGC_IN_SAMPLE
, 1);
923 int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm
*mvm
, u8 conf_id
)
929 if (WARN_ONCE(conf_id
>= ARRAY_SIZE(mvm
->fw
->dbg_conf_tlv
),
930 "Invalid configuration %d\n", conf_id
))
933 /* EARLY START - firmware's configuration is hard coded */
934 if ((!mvm
->fw
->dbg_conf_tlv
[conf_id
] ||
935 !mvm
->fw
->dbg_conf_tlv
[conf_id
]->num_of_hcmds
) &&
936 conf_id
== FW_DBG_START_FROM_ALIVE
) {
937 iwl_mvm_restart_early_start(mvm
);
941 if (!mvm
->fw
->dbg_conf_tlv
[conf_id
])
944 if (mvm
->fw_dbg_conf
!= FW_DBG_INVALID
)
945 IWL_WARN(mvm
, "FW already configured (%d) - re-configuring\n",
948 /* Send all HCMDs for configuring the FW debug */
949 ptr
= (void *)&mvm
->fw
->dbg_conf_tlv
[conf_id
]->hcmd
;
950 for (i
= 0; i
< mvm
->fw
->dbg_conf_tlv
[conf_id
]->num_of_hcmds
; i
++) {
951 struct iwl_fw_dbg_conf_hcmd
*cmd
= (void *)ptr
;
953 ret
= iwl_mvm_send_cmd_pdu(mvm
, cmd
->id
, 0,
954 le16_to_cpu(cmd
->len
), cmd
->data
);
959 ptr
+= le16_to_cpu(cmd
->len
);
962 mvm
->fw_dbg_conf
= conf_id
;