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iwlwifi: move iwl_sta_modify_enable_tid_tx to iwl-sta.c
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/version.h>
30 #include <linux/init.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <net/mac80211.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40
41 #include "iwl-eeprom.h"
42 #include "iwl-dev.h"
43 #include "iwl-core.h"
44 #include "iwl-io.h"
45 #include "iwl-helpers.h"
46 #include "iwl-calib.h"
47 #include "iwl-sta.h"
48
49 /* module parameters */
50 static struct iwl_mod_params iwl4965_mod_params = {
51 .num_of_queues = IWL49_NUM_QUEUES,
52 .enable_qos = 1,
53 .amsdu_size_8K = 1,
54 .restart_fw = 1,
55 /* the rest are 0 by default */
56 };
57
58 #ifdef CONFIG_IWL4965_HT
59
60 static const u16 default_tid_to_tx_fifo[] = {
61 IWL_TX_FIFO_AC1,
62 IWL_TX_FIFO_AC0,
63 IWL_TX_FIFO_AC0,
64 IWL_TX_FIFO_AC1,
65 IWL_TX_FIFO_AC2,
66 IWL_TX_FIFO_AC2,
67 IWL_TX_FIFO_AC3,
68 IWL_TX_FIFO_AC3,
69 IWL_TX_FIFO_NONE,
70 IWL_TX_FIFO_NONE,
71 IWL_TX_FIFO_NONE,
72 IWL_TX_FIFO_NONE,
73 IWL_TX_FIFO_NONE,
74 IWL_TX_FIFO_NONE,
75 IWL_TX_FIFO_NONE,
76 IWL_TX_FIFO_NONE,
77 IWL_TX_FIFO_AC3
78 };
79
80 #endif /*CONFIG_IWL4965_HT */
81
82 /* check contents of special bootstrap uCode SRAM */
83 static int iwl4965_verify_bsm(struct iwl_priv *priv)
84 {
85 __le32 *image = priv->ucode_boot.v_addr;
86 u32 len = priv->ucode_boot.len;
87 u32 reg;
88 u32 val;
89
90 IWL_DEBUG_INFO("Begin verify bsm\n");
91
92 /* verify BSM SRAM contents */
93 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
94 for (reg = BSM_SRAM_LOWER_BOUND;
95 reg < BSM_SRAM_LOWER_BOUND + len;
96 reg += sizeof(u32), image++) {
97 val = iwl_read_prph(priv, reg);
98 if (val != le32_to_cpu(*image)) {
99 IWL_ERROR("BSM uCode verification failed at "
100 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
101 BSM_SRAM_LOWER_BOUND,
102 reg - BSM_SRAM_LOWER_BOUND, len,
103 val, le32_to_cpu(*image));
104 return -EIO;
105 }
106 }
107
108 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
109
110 return 0;
111 }
112
113 /**
114 * iwl4965_load_bsm - Load bootstrap instructions
115 *
116 * BSM operation:
117 *
118 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
119 * in special SRAM that does not power down during RFKILL. When powering back
120 * up after power-saving sleeps (or during initial uCode load), the BSM loads
121 * the bootstrap program into the on-board processor, and starts it.
122 *
123 * The bootstrap program loads (via DMA) instructions and data for a new
124 * program from host DRAM locations indicated by the host driver in the
125 * BSM_DRAM_* registers. Once the new program is loaded, it starts
126 * automatically.
127 *
128 * When initializing the NIC, the host driver points the BSM to the
129 * "initialize" uCode image. This uCode sets up some internal data, then
130 * notifies host via "initialize alive" that it is complete.
131 *
132 * The host then replaces the BSM_DRAM_* pointer values to point to the
133 * normal runtime uCode instructions and a backup uCode data cache buffer
134 * (filled initially with starting data values for the on-board processor),
135 * then triggers the "initialize" uCode to load and launch the runtime uCode,
136 * which begins normal operation.
137 *
138 * When doing a power-save shutdown, runtime uCode saves data SRAM into
139 * the backup data cache in DRAM before SRAM is powered down.
140 *
141 * When powering back up, the BSM loads the bootstrap program. This reloads
142 * the runtime uCode instructions and the backup data cache into SRAM,
143 * and re-launches the runtime uCode from where it left off.
144 */
145 static int iwl4965_load_bsm(struct iwl_priv *priv)
146 {
147 __le32 *image = priv->ucode_boot.v_addr;
148 u32 len = priv->ucode_boot.len;
149 dma_addr_t pinst;
150 dma_addr_t pdata;
151 u32 inst_len;
152 u32 data_len;
153 int i;
154 u32 done;
155 u32 reg_offset;
156 int ret;
157
158 IWL_DEBUG_INFO("Begin load bsm\n");
159
160 priv->ucode_type = UCODE_RT;
161
162 /* make sure bootstrap program is no larger than BSM's SRAM size */
163 if (len > IWL_MAX_BSM_SIZE)
164 return -EINVAL;
165
166 /* Tell bootstrap uCode where to find the "Initialize" uCode
167 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
168 * NOTE: iwl_init_alive_start() will replace these values,
169 * after the "initialize" uCode has run, to point to
170 * runtime/protocol instructions and backup data cache.
171 */
172 pinst = priv->ucode_init.p_addr >> 4;
173 pdata = priv->ucode_init_data.p_addr >> 4;
174 inst_len = priv->ucode_init.len;
175 data_len = priv->ucode_init_data.len;
176
177 ret = iwl_grab_nic_access(priv);
178 if (ret)
179 return ret;
180
181 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
182 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
183 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
184 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
185
186 /* Fill BSM memory with bootstrap instructions */
187 for (reg_offset = BSM_SRAM_LOWER_BOUND;
188 reg_offset < BSM_SRAM_LOWER_BOUND + len;
189 reg_offset += sizeof(u32), image++)
190 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
191
192 ret = iwl4965_verify_bsm(priv);
193 if (ret) {
194 iwl_release_nic_access(priv);
195 return ret;
196 }
197
198 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
199 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
200 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
201 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
202
203 /* Load bootstrap code into instruction SRAM now,
204 * to prepare to load "initialize" uCode */
205 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
206
207 /* Wait for load of bootstrap uCode to finish */
208 for (i = 0; i < 100; i++) {
209 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
210 if (!(done & BSM_WR_CTRL_REG_BIT_START))
211 break;
212 udelay(10);
213 }
214 if (i < 100)
215 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
216 else {
217 IWL_ERROR("BSM write did not complete!\n");
218 return -EIO;
219 }
220
221 /* Enable future boot loads whenever power management unit triggers it
222 * (e.g. when powering back up after power-save shutdown) */
223 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
224
225 iwl_release_nic_access(priv);
226
227 return 0;
228 }
229
230 /**
231 * iwl4965_set_ucode_ptrs - Set uCode address location
232 *
233 * Tell initialization uCode where to find runtime uCode.
234 *
235 * BSM registers initially contain pointers to initialization uCode.
236 * We need to replace them to load runtime uCode inst and data,
237 * and to save runtime data when powering down.
238 */
239 static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
240 {
241 dma_addr_t pinst;
242 dma_addr_t pdata;
243 unsigned long flags;
244 int ret = 0;
245
246 /* bits 35:4 for 4965 */
247 pinst = priv->ucode_code.p_addr >> 4;
248 pdata = priv->ucode_data_backup.p_addr >> 4;
249
250 spin_lock_irqsave(&priv->lock, flags);
251 ret = iwl_grab_nic_access(priv);
252 if (ret) {
253 spin_unlock_irqrestore(&priv->lock, flags);
254 return ret;
255 }
256
257 /* Tell bootstrap uCode where to find image to load */
258 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
259 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
260 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
261 priv->ucode_data.len);
262
263 /* Inst bytecount must be last to set up, bit 31 signals uCode
264 * that all new ptr/size info is in place */
265 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
266 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
267 iwl_release_nic_access(priv);
268
269 spin_unlock_irqrestore(&priv->lock, flags);
270
271 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
272
273 return ret;
274 }
275
276 /**
277 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
278 *
279 * Called after REPLY_ALIVE notification received from "initialize" uCode.
280 *
281 * The 4965 "initialize" ALIVE reply contains calibration data for:
282 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
283 * (3945 does not contain this data).
284 *
285 * Tell "initialize" uCode to go ahead and load the runtime uCode.
286 */
287 static void iwl4965_init_alive_start(struct iwl_priv *priv)
288 {
289 /* Check alive response for "valid" sign from uCode */
290 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
291 /* We had an error bringing up the hardware, so take it
292 * all the way back down so we can try again */
293 IWL_DEBUG_INFO("Initialize Alive failed.\n");
294 goto restart;
295 }
296
297 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
298 * This is a paranoid check, because we would not have gotten the
299 * "initialize" alive if code weren't properly loaded. */
300 if (iwl_verify_ucode(priv)) {
301 /* Runtime instruction load was bad;
302 * take it all the way back down so we can try again */
303 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
304 goto restart;
305 }
306
307 /* Calculate temperature */
308 priv->temperature = iwl4965_get_temperature(priv);
309
310 /* Send pointers to protocol/runtime uCode image ... init code will
311 * load and launch runtime uCode, which will send us another "Alive"
312 * notification. */
313 IWL_DEBUG_INFO("Initialization Alive received.\n");
314 if (iwl4965_set_ucode_ptrs(priv)) {
315 /* Runtime instruction load won't happen;
316 * take it all the way back down so we can try again */
317 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
318 goto restart;
319 }
320 return;
321
322 restart:
323 queue_work(priv->workqueue, &priv->restart);
324 }
325
326 static int is_fat_channel(__le32 rxon_flags)
327 {
328 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
329 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
330 }
331
332 int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
333 {
334 int idx = 0;
335
336 /* 4965 HT rate format */
337 if (rate_n_flags & RATE_MCS_HT_MSK) {
338 idx = (rate_n_flags & 0xff);
339
340 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
341 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
342
343 idx += IWL_FIRST_OFDM_RATE;
344 /* skip 9M not supported in ht*/
345 if (idx >= IWL_RATE_9M_INDEX)
346 idx += 1;
347 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
348 return idx;
349
350 /* 4965 legacy rate format, search for match in table */
351 } else {
352 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
353 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
354 return idx;
355 }
356
357 return -1;
358 }
359
360 /**
361 * translate ucode response to mac80211 tx status control values
362 */
363 void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
364 struct ieee80211_tx_info *control)
365 {
366 int rate_index;
367
368 control->antenna_sel_tx =
369 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
370 if (rate_n_flags & RATE_MCS_HT_MSK)
371 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
372 if (rate_n_flags & RATE_MCS_GF_MSK)
373 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
374 if (rate_n_flags & RATE_MCS_FAT_MSK)
375 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
376 if (rate_n_flags & RATE_MCS_DUP_MSK)
377 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
378 if (rate_n_flags & RATE_MCS_SGI_MSK)
379 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
380 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
381 if (control->band == IEEE80211_BAND_5GHZ)
382 rate_index -= IWL_FIRST_OFDM_RATE;
383 control->tx_rate_idx = rate_index;
384 }
385
386 /*
387 * EEPROM handlers
388 */
389
390 static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
391 {
392 u16 eeprom_ver;
393 u16 calib_ver;
394
395 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
396
397 calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
398
399 if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
400 calib_ver < EEPROM_4965_TX_POWER_VERSION)
401 goto err;
402
403 return 0;
404 err:
405 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
406 eeprom_ver, EEPROM_4965_EEPROM_VERSION,
407 calib_ver, EEPROM_4965_TX_POWER_VERSION);
408 return -EINVAL;
409
410 }
411 int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
412 {
413 int ret;
414 unsigned long flags;
415
416 spin_lock_irqsave(&priv->lock, flags);
417 ret = iwl_grab_nic_access(priv);
418 if (ret) {
419 spin_unlock_irqrestore(&priv->lock, flags);
420 return ret;
421 }
422
423 if (src == IWL_PWR_SRC_VAUX) {
424 u32 val;
425 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
426 &val);
427
428 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
429 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
430 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
431 ~APMG_PS_CTRL_MSK_PWR_SRC);
432 }
433 } else {
434 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
435 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
436 ~APMG_PS_CTRL_MSK_PWR_SRC);
437 }
438
439 iwl_release_nic_access(priv);
440 spin_unlock_irqrestore(&priv->lock, flags);
441
442 return ret;
443 }
444
445 /*
446 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
447 * must be called under priv->lock and mac access
448 */
449 static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
450 {
451 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
452 }
453
454 static int iwl4965_apm_init(struct iwl_priv *priv)
455 {
456 int ret = 0;
457
458 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
459 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
460
461 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
462 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
463 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
464
465 /* set "initialization complete" bit to move adapter
466 * D0U* --> D0A* state */
467 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
468
469 /* wait for clock stabilization */
470 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
471 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
472 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
473 if (ret < 0) {
474 IWL_DEBUG_INFO("Failed to init the card\n");
475 goto out;
476 }
477
478 ret = iwl_grab_nic_access(priv);
479 if (ret)
480 goto out;
481
482 /* enable DMA */
483 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
484 APMG_CLK_VAL_BSM_CLK_RQT);
485
486 udelay(20);
487
488 /* disable L1-Active */
489 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
490 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
491
492 iwl_release_nic_access(priv);
493 out:
494 return ret;
495 }
496
497
498 static void iwl4965_nic_config(struct iwl_priv *priv)
499 {
500 unsigned long flags;
501 u32 val;
502 u16 radio_cfg;
503 u8 val_link;
504
505 spin_lock_irqsave(&priv->lock, flags);
506
507 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
508 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
509 /* Enable No Snoop field */
510 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
511 val & ~(1 << 11));
512 }
513
514 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
515
516 /* L1 is enabled by BIOS */
517 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
518 /* diable L0S disabled L1A enabled */
519 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
520 else
521 /* L0S enabled L1A disabled */
522 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
523
524 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
525
526 /* write radio config values to register */
527 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
528 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
529 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
530 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
531 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
532
533 /* set CSR_HW_CONFIG_REG for uCode use */
534 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
535 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
536 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
537
538 priv->calib_info = (struct iwl_eeprom_calib_info *)
539 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
540
541 spin_unlock_irqrestore(&priv->lock, flags);
542 }
543
544 static int iwl4965_apm_stop_master(struct iwl_priv *priv)
545 {
546 int ret = 0;
547 unsigned long flags;
548
549 spin_lock_irqsave(&priv->lock, flags);
550
551 /* set stop master bit */
552 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
553
554 ret = iwl_poll_bit(priv, CSR_RESET,
555 CSR_RESET_REG_FLAG_MASTER_DISABLED,
556 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
557 if (ret < 0)
558 goto out;
559
560 out:
561 spin_unlock_irqrestore(&priv->lock, flags);
562 IWL_DEBUG_INFO("stop master\n");
563
564 return ret;
565 }
566
567 static void iwl4965_apm_stop(struct iwl_priv *priv)
568 {
569 unsigned long flags;
570
571 iwl4965_apm_stop_master(priv);
572
573 spin_lock_irqsave(&priv->lock, flags);
574
575 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
576
577 udelay(10);
578
579 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
580 spin_unlock_irqrestore(&priv->lock, flags);
581 }
582
583 static int iwl4965_apm_reset(struct iwl_priv *priv)
584 {
585 int ret = 0;
586 unsigned long flags;
587
588 iwl4965_apm_stop_master(priv);
589
590 spin_lock_irqsave(&priv->lock, flags);
591
592 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
593
594 udelay(10);
595
596 /* FIXME: put here L1A -L0S w/a */
597
598 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
599
600 ret = iwl_poll_bit(priv, CSR_RESET,
601 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
602 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
603
604 if (ret)
605 goto out;
606
607 udelay(10);
608
609 ret = iwl_grab_nic_access(priv);
610 if (ret)
611 goto out;
612 /* Enable DMA and BSM Clock */
613 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
614 APMG_CLK_VAL_BSM_CLK_RQT);
615
616 udelay(10);
617
618 /* disable L1A */
619 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
620 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
621
622 iwl_release_nic_access(priv);
623
624 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
625 wake_up_interruptible(&priv->wait_command_queue);
626
627 out:
628 spin_unlock_irqrestore(&priv->lock, flags);
629
630 return ret;
631 }
632
633 #define REG_RECALIB_PERIOD (60)
634
635 /**
636 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
637 *
638 * This callback is provided in order to send a statistics request.
639 *
640 * This timer function is continually reset to execute within
641 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
642 * was received. We need to ensure we receive the statistics in order
643 * to update the temperature used for calibrating the TXPOWER.
644 */
645 static void iwl4965_bg_statistics_periodic(unsigned long data)
646 {
647 struct iwl_priv *priv = (struct iwl_priv *)data;
648
649 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
650 return;
651
652 iwl_send_statistics_request(priv, CMD_ASYNC);
653 }
654
655 void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
656 {
657 struct iwl4965_ct_kill_config cmd;
658 unsigned long flags;
659 int ret = 0;
660
661 spin_lock_irqsave(&priv->lock, flags);
662 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
663 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
664 spin_unlock_irqrestore(&priv->lock, flags);
665
666 cmd.critical_temperature_R =
667 cpu_to_le32(priv->hw_params.ct_kill_threshold);
668
669 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
670 sizeof(cmd), &cmd);
671 if (ret)
672 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
673 else
674 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
675 "critical temperature is %d\n",
676 cmd.critical_temperature_R);
677 }
678
679 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
680
681 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
682 * Called after every association, but this runs only once!
683 * ... once chain noise is calibrated the first time, it's good forever. */
684 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
685 {
686 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
687
688 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
689 struct iwl4965_calibration_cmd cmd;
690
691 memset(&cmd, 0, sizeof(cmd));
692 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
693 cmd.diff_gain_a = 0;
694 cmd.diff_gain_b = 0;
695 cmd.diff_gain_c = 0;
696 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
697 sizeof(cmd), &cmd))
698 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
699 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
700 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
701 }
702 }
703
704 static void iwl4965_gain_computation(struct iwl_priv *priv,
705 u32 *average_noise,
706 u16 min_average_noise_antenna_i,
707 u32 min_average_noise)
708 {
709 int i, ret;
710 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
711
712 data->delta_gain_code[min_average_noise_antenna_i] = 0;
713
714 for (i = 0; i < NUM_RX_CHAINS; i++) {
715 s32 delta_g = 0;
716
717 if (!(data->disconn_array[i]) &&
718 (data->delta_gain_code[i] ==
719 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
720 delta_g = average_noise[i] - min_average_noise;
721 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
722 data->delta_gain_code[i] =
723 min(data->delta_gain_code[i],
724 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
725
726 data->delta_gain_code[i] =
727 (data->delta_gain_code[i] | (1 << 2));
728 } else {
729 data->delta_gain_code[i] = 0;
730 }
731 }
732 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
733 data->delta_gain_code[0],
734 data->delta_gain_code[1],
735 data->delta_gain_code[2]);
736
737 /* Differential gain gets sent to uCode only once */
738 if (!data->radio_write) {
739 struct iwl4965_calibration_cmd cmd;
740 data->radio_write = 1;
741
742 memset(&cmd, 0, sizeof(cmd));
743 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
744 cmd.diff_gain_a = data->delta_gain_code[0];
745 cmd.diff_gain_b = data->delta_gain_code[1];
746 cmd.diff_gain_c = data->delta_gain_code[2];
747 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
748 sizeof(cmd), &cmd);
749 if (ret)
750 IWL_DEBUG_CALIB("fail sending cmd "
751 "REPLY_PHY_CALIBRATION_CMD \n");
752
753 /* TODO we might want recalculate
754 * rx_chain in rxon cmd */
755
756 /* Mark so we run this algo only once! */
757 data->state = IWL_CHAIN_NOISE_CALIBRATED;
758 }
759 data->chain_noise_a = 0;
760 data->chain_noise_b = 0;
761 data->chain_noise_c = 0;
762 data->chain_signal_a = 0;
763 data->chain_signal_b = 0;
764 data->chain_signal_c = 0;
765 data->beacon_count = 0;
766 }
767
768 static void iwl4965_bg_sensitivity_work(struct work_struct *work)
769 {
770 struct iwl_priv *priv = container_of(work, struct iwl_priv,
771 sensitivity_work);
772
773 mutex_lock(&priv->mutex);
774
775 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
776 test_bit(STATUS_SCANNING, &priv->status)) {
777 mutex_unlock(&priv->mutex);
778 return;
779 }
780
781 if (priv->start_calib) {
782 iwl_chain_noise_calibration(priv, &priv->statistics);
783
784 iwl_sensitivity_calibration(priv, &priv->statistics);
785 }
786
787 mutex_unlock(&priv->mutex);
788 return;
789 }
790 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
791
792 static void iwl4965_bg_txpower_work(struct work_struct *work)
793 {
794 struct iwl_priv *priv = container_of(work, struct iwl_priv,
795 txpower_work);
796
797 /* If a scan happened to start before we got here
798 * then just return; the statistics notification will
799 * kick off another scheduled work to compensate for
800 * any temperature delta we missed here. */
801 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
802 test_bit(STATUS_SCANNING, &priv->status))
803 return;
804
805 mutex_lock(&priv->mutex);
806
807 /* Regardless of if we are assocaited, we must reconfigure the
808 * TX power since frames can be sent on non-radar channels while
809 * not associated */
810 iwl4965_hw_reg_send_txpower(priv);
811
812 /* Update last_temperature to keep is_calib_needed from running
813 * when it isn't needed... */
814 priv->last_temperature = priv->temperature;
815
816 mutex_unlock(&priv->mutex);
817 }
818
819 /*
820 * Acquire priv->lock before calling this function !
821 */
822 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
823 {
824 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
825 (index & 0xff) | (txq_id << 8));
826 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
827 }
828
829 /**
830 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
831 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
832 * @scd_retry: (1) Indicates queue will be used in aggregation mode
833 *
834 * NOTE: Acquire priv->lock before calling this function !
835 */
836 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
837 struct iwl_tx_queue *txq,
838 int tx_fifo_id, int scd_retry)
839 {
840 int txq_id = txq->q.id;
841
842 /* Find out whether to activate Tx queue */
843 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
844
845 /* Set up and activate */
846 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
847 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
848 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
849 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
850 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
851 IWL49_SCD_QUEUE_STTS_REG_MSK);
852
853 txq->sched_retry = scd_retry;
854
855 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
856 active ? "Activate" : "Deactivate",
857 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
858 }
859
860 static const u16 default_queue_to_tx_fifo[] = {
861 IWL_TX_FIFO_AC3,
862 IWL_TX_FIFO_AC2,
863 IWL_TX_FIFO_AC1,
864 IWL_TX_FIFO_AC0,
865 IWL49_CMD_FIFO_NUM,
866 IWL_TX_FIFO_HCCA_1,
867 IWL_TX_FIFO_HCCA_2
868 };
869
870 int iwl4965_alive_notify(struct iwl_priv *priv)
871 {
872 u32 a;
873 int i = 0;
874 unsigned long flags;
875 int ret;
876
877 spin_lock_irqsave(&priv->lock, flags);
878
879 ret = iwl_grab_nic_access(priv);
880 if (ret) {
881 spin_unlock_irqrestore(&priv->lock, flags);
882 return ret;
883 }
884
885 /* Clear 4965's internal Tx Scheduler data base */
886 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
887 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
888 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
889 iwl_write_targ_mem(priv, a, 0);
890 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
891 iwl_write_targ_mem(priv, a, 0);
892 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
893 iwl_write_targ_mem(priv, a, 0);
894
895 /* Tel 4965 where to find Tx byte count tables */
896 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
897 (priv->shared_phys +
898 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
899
900 /* Disable chain mode for all queues */
901 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
902
903 /* Initialize each Tx queue (including the command queue) */
904 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
905
906 /* TFD circular buffer read/write indexes */
907 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
908 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
909
910 /* Max Tx Window size for Scheduler-ACK mode */
911 iwl_write_targ_mem(priv, priv->scd_base_addr +
912 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
913 (SCD_WIN_SIZE <<
914 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
915 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
916
917 /* Frame limit */
918 iwl_write_targ_mem(priv, priv->scd_base_addr +
919 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
920 sizeof(u32),
921 (SCD_FRAME_LIMIT <<
922 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
923 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
924
925 }
926 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
927 (1 << priv->hw_params.max_txq_num) - 1);
928
929 /* Activate all Tx DMA/FIFO channels */
930 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
931
932 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
933
934 /* Map each Tx/cmd queue to its corresponding fifo */
935 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
936 int ac = default_queue_to_tx_fifo[i];
937 iwl_txq_ctx_activate(priv, i);
938 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
939 }
940
941 iwl_release_nic_access(priv);
942 spin_unlock_irqrestore(&priv->lock, flags);
943
944 return ret;
945 }
946
947 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
948 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
949 .min_nrg_cck = 97,
950 .max_nrg_cck = 0,
951
952 .auto_corr_min_ofdm = 85,
953 .auto_corr_min_ofdm_mrc = 170,
954 .auto_corr_min_ofdm_x1 = 105,
955 .auto_corr_min_ofdm_mrc_x1 = 220,
956
957 .auto_corr_max_ofdm = 120,
958 .auto_corr_max_ofdm_mrc = 210,
959 .auto_corr_max_ofdm_x1 = 140,
960 .auto_corr_max_ofdm_mrc_x1 = 270,
961
962 .auto_corr_min_cck = 125,
963 .auto_corr_max_cck = 200,
964 .auto_corr_min_cck_mrc = 200,
965 .auto_corr_max_cck_mrc = 400,
966
967 .nrg_th_cck = 100,
968 .nrg_th_ofdm = 100,
969 };
970 #endif
971
972 /**
973 * iwl4965_hw_set_hw_params
974 *
975 * Called when initializing driver
976 */
977 int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
978 {
979
980 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
981 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
982 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
983 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
984 return -EINVAL;
985 }
986
987 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
988 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
989 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
990 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
991 if (priv->cfg->mod_params->amsdu_size_8K)
992 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
993 else
994 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
995 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
996 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
997 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
998
999 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
1000 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
1001 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
1002 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
1003
1004 priv->hw_params.tx_chains_num = 2;
1005 priv->hw_params.rx_chains_num = 2;
1006 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
1007 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
1008 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
1009
1010 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1011 priv->hw_params.sens = &iwl4965_sensitivity;
1012 #endif
1013
1014 return 0;
1015 }
1016
1017 /* set card power command */
1018 static int iwl4965_set_power(struct iwl_priv *priv,
1019 void *cmd)
1020 {
1021 int ret = 0;
1022
1023 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
1024 sizeof(struct iwl4965_powertable_cmd),
1025 cmd, NULL);
1026 return ret;
1027 }
1028 int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1029 {
1030 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
1031 return -EINVAL;
1032 }
1033
1034 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1035 {
1036 s32 sign = 1;
1037
1038 if (num < 0) {
1039 sign = -sign;
1040 num = -num;
1041 }
1042 if (denom < 0) {
1043 sign = -sign;
1044 denom = -denom;
1045 }
1046 *res = 1;
1047 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1048
1049 return 1;
1050 }
1051
1052 /**
1053 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1054 *
1055 * Determines power supply voltage compensation for txpower calculations.
1056 * Returns number of 1/2-dB steps to subtract from gain table index,
1057 * to compensate for difference between power supply voltage during
1058 * factory measurements, vs. current power supply voltage.
1059 *
1060 * Voltage indication is higher for lower voltage.
1061 * Lower voltage requires more gain (lower gain table index).
1062 */
1063 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1064 s32 current_voltage)
1065 {
1066 s32 comp = 0;
1067
1068 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1069 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1070 return 0;
1071
1072 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1073 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1074
1075 if (current_voltage > eeprom_voltage)
1076 comp *= 2;
1077 if ((comp < -2) || (comp > 2))
1078 comp = 0;
1079
1080 return comp;
1081 }
1082
1083 static const struct iwl_channel_info *
1084 iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
1085 enum ieee80211_band band, u16 channel)
1086 {
1087 const struct iwl_channel_info *ch_info;
1088
1089 ch_info = iwl_get_channel_info(priv, band, channel);
1090
1091 if (!is_channel_valid(ch_info))
1092 return NULL;
1093
1094 return ch_info;
1095 }
1096
1097 static s32 iwl4965_get_tx_atten_grp(u16 channel)
1098 {
1099 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1100 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1101 return CALIB_CH_GROUP_5;
1102
1103 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1104 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1105 return CALIB_CH_GROUP_1;
1106
1107 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1108 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1109 return CALIB_CH_GROUP_2;
1110
1111 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1112 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1113 return CALIB_CH_GROUP_3;
1114
1115 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1116 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1117 return CALIB_CH_GROUP_4;
1118
1119 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1120 return -1;
1121 }
1122
1123 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
1124 {
1125 s32 b = -1;
1126
1127 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
1128 if (priv->calib_info->band_info[b].ch_from == 0)
1129 continue;
1130
1131 if ((channel >= priv->calib_info->band_info[b].ch_from)
1132 && (channel <= priv->calib_info->band_info[b].ch_to))
1133 break;
1134 }
1135
1136 return b;
1137 }
1138
1139 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1140 {
1141 s32 val;
1142
1143 if (x2 == x1)
1144 return y1;
1145 else {
1146 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1147 return val + y2;
1148 }
1149 }
1150
1151 /**
1152 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1153 *
1154 * Interpolates factory measurements from the two sample channels within a
1155 * sub-band, to apply to channel of interest. Interpolation is proportional to
1156 * differences in channel frequencies, which is proportional to differences
1157 * in channel number.
1158 */
1159 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
1160 struct iwl_eeprom_calib_ch_info *chan_info)
1161 {
1162 s32 s = -1;
1163 u32 c;
1164 u32 m;
1165 const struct iwl_eeprom_calib_measure *m1;
1166 const struct iwl_eeprom_calib_measure *m2;
1167 struct iwl_eeprom_calib_measure *omeas;
1168 u32 ch_i1;
1169 u32 ch_i2;
1170
1171 s = iwl4965_get_sub_band(priv, channel);
1172 if (s >= EEPROM_TX_POWER_BANDS) {
1173 IWL_ERROR("Tx Power can not find channel %d ", channel);
1174 return -1;
1175 }
1176
1177 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1178 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
1179 chan_info->ch_num = (u8) channel;
1180
1181 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1182 channel, s, ch_i1, ch_i2);
1183
1184 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1185 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
1186 m1 = &(priv->calib_info->band_info[s].ch1.
1187 measurements[c][m]);
1188 m2 = &(priv->calib_info->band_info[s].ch2.
1189 measurements[c][m]);
1190 omeas = &(chan_info->measurements[c][m]);
1191
1192 omeas->actual_pow =
1193 (u8) iwl4965_interpolate_value(channel, ch_i1,
1194 m1->actual_pow,
1195 ch_i2,
1196 m2->actual_pow);
1197 omeas->gain_idx =
1198 (u8) iwl4965_interpolate_value(channel, ch_i1,
1199 m1->gain_idx, ch_i2,
1200 m2->gain_idx);
1201 omeas->temperature =
1202 (u8) iwl4965_interpolate_value(channel, ch_i1,
1203 m1->temperature,
1204 ch_i2,
1205 m2->temperature);
1206 omeas->pa_det =
1207 (s8) iwl4965_interpolate_value(channel, ch_i1,
1208 m1->pa_det, ch_i2,
1209 m2->pa_det);
1210
1211 IWL_DEBUG_TXPOWER
1212 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1213 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1214 IWL_DEBUG_TXPOWER
1215 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1216 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1217 IWL_DEBUG_TXPOWER
1218 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1219 m1->pa_det, m2->pa_det, omeas->pa_det);
1220 IWL_DEBUG_TXPOWER
1221 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1222 m1->temperature, m2->temperature,
1223 omeas->temperature);
1224 }
1225 }
1226
1227 return 0;
1228 }
1229
1230 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1231 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1232 static s32 back_off_table[] = {
1233 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1234 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1235 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1236 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1237 10 /* CCK */
1238 };
1239
1240 /* Thermal compensation values for txpower for various frequency ranges ...
1241 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
1242 static struct iwl4965_txpower_comp_entry {
1243 s32 degrees_per_05db_a;
1244 s32 degrees_per_05db_a_denom;
1245 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1246 {9, 2}, /* group 0 5.2, ch 34-43 */
1247 {4, 1}, /* group 1 5.2, ch 44-70 */
1248 {4, 1}, /* group 2 5.2, ch 71-124 */
1249 {4, 1}, /* group 3 5.2, ch 125-200 */
1250 {3, 1} /* group 4 2.4, ch all */
1251 };
1252
1253 static s32 get_min_power_index(s32 rate_power_index, u32 band)
1254 {
1255 if (!band) {
1256 if ((rate_power_index & 7) <= 4)
1257 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1258 }
1259 return MIN_TX_GAIN_INDEX;
1260 }
1261
1262 struct gain_entry {
1263 u8 dsp;
1264 u8 radio;
1265 };
1266
1267 static const struct gain_entry gain_table[2][108] = {
1268 /* 5.2GHz power gain index table */
1269 {
1270 {123, 0x3F}, /* highest txpower */
1271 {117, 0x3F},
1272 {110, 0x3F},
1273 {104, 0x3F},
1274 {98, 0x3F},
1275 {110, 0x3E},
1276 {104, 0x3E},
1277 {98, 0x3E},
1278 {110, 0x3D},
1279 {104, 0x3D},
1280 {98, 0x3D},
1281 {110, 0x3C},
1282 {104, 0x3C},
1283 {98, 0x3C},
1284 {110, 0x3B},
1285 {104, 0x3B},
1286 {98, 0x3B},
1287 {110, 0x3A},
1288 {104, 0x3A},
1289 {98, 0x3A},
1290 {110, 0x39},
1291 {104, 0x39},
1292 {98, 0x39},
1293 {110, 0x38},
1294 {104, 0x38},
1295 {98, 0x38},
1296 {110, 0x37},
1297 {104, 0x37},
1298 {98, 0x37},
1299 {110, 0x36},
1300 {104, 0x36},
1301 {98, 0x36},
1302 {110, 0x35},
1303 {104, 0x35},
1304 {98, 0x35},
1305 {110, 0x34},
1306 {104, 0x34},
1307 {98, 0x34},
1308 {110, 0x33},
1309 {104, 0x33},
1310 {98, 0x33},
1311 {110, 0x32},
1312 {104, 0x32},
1313 {98, 0x32},
1314 {110, 0x31},
1315 {104, 0x31},
1316 {98, 0x31},
1317 {110, 0x30},
1318 {104, 0x30},
1319 {98, 0x30},
1320 {110, 0x25},
1321 {104, 0x25},
1322 {98, 0x25},
1323 {110, 0x24},
1324 {104, 0x24},
1325 {98, 0x24},
1326 {110, 0x23},
1327 {104, 0x23},
1328 {98, 0x23},
1329 {110, 0x22},
1330 {104, 0x18},
1331 {98, 0x18},
1332 {110, 0x17},
1333 {104, 0x17},
1334 {98, 0x17},
1335 {110, 0x16},
1336 {104, 0x16},
1337 {98, 0x16},
1338 {110, 0x15},
1339 {104, 0x15},
1340 {98, 0x15},
1341 {110, 0x14},
1342 {104, 0x14},
1343 {98, 0x14},
1344 {110, 0x13},
1345 {104, 0x13},
1346 {98, 0x13},
1347 {110, 0x12},
1348 {104, 0x08},
1349 {98, 0x08},
1350 {110, 0x07},
1351 {104, 0x07},
1352 {98, 0x07},
1353 {110, 0x06},
1354 {104, 0x06},
1355 {98, 0x06},
1356 {110, 0x05},
1357 {104, 0x05},
1358 {98, 0x05},
1359 {110, 0x04},
1360 {104, 0x04},
1361 {98, 0x04},
1362 {110, 0x03},
1363 {104, 0x03},
1364 {98, 0x03},
1365 {110, 0x02},
1366 {104, 0x02},
1367 {98, 0x02},
1368 {110, 0x01},
1369 {104, 0x01},
1370 {98, 0x01},
1371 {110, 0x00},
1372 {104, 0x00},
1373 {98, 0x00},
1374 {93, 0x00},
1375 {88, 0x00},
1376 {83, 0x00},
1377 {78, 0x00},
1378 },
1379 /* 2.4GHz power gain index table */
1380 {
1381 {110, 0x3f}, /* highest txpower */
1382 {104, 0x3f},
1383 {98, 0x3f},
1384 {110, 0x3e},
1385 {104, 0x3e},
1386 {98, 0x3e},
1387 {110, 0x3d},
1388 {104, 0x3d},
1389 {98, 0x3d},
1390 {110, 0x3c},
1391 {104, 0x3c},
1392 {98, 0x3c},
1393 {110, 0x3b},
1394 {104, 0x3b},
1395 {98, 0x3b},
1396 {110, 0x3a},
1397 {104, 0x3a},
1398 {98, 0x3a},
1399 {110, 0x39},
1400 {104, 0x39},
1401 {98, 0x39},
1402 {110, 0x38},
1403 {104, 0x38},
1404 {98, 0x38},
1405 {110, 0x37},
1406 {104, 0x37},
1407 {98, 0x37},
1408 {110, 0x36},
1409 {104, 0x36},
1410 {98, 0x36},
1411 {110, 0x35},
1412 {104, 0x35},
1413 {98, 0x35},
1414 {110, 0x34},
1415 {104, 0x34},
1416 {98, 0x34},
1417 {110, 0x33},
1418 {104, 0x33},
1419 {98, 0x33},
1420 {110, 0x32},
1421 {104, 0x32},
1422 {98, 0x32},
1423 {110, 0x31},
1424 {104, 0x31},
1425 {98, 0x31},
1426 {110, 0x30},
1427 {104, 0x30},
1428 {98, 0x30},
1429 {110, 0x6},
1430 {104, 0x6},
1431 {98, 0x6},
1432 {110, 0x5},
1433 {104, 0x5},
1434 {98, 0x5},
1435 {110, 0x4},
1436 {104, 0x4},
1437 {98, 0x4},
1438 {110, 0x3},
1439 {104, 0x3},
1440 {98, 0x3},
1441 {110, 0x2},
1442 {104, 0x2},
1443 {98, 0x2},
1444 {110, 0x1},
1445 {104, 0x1},
1446 {98, 0x1},
1447 {110, 0x0},
1448 {104, 0x0},
1449 {98, 0x0},
1450 {97, 0},
1451 {96, 0},
1452 {95, 0},
1453 {94, 0},
1454 {93, 0},
1455 {92, 0},
1456 {91, 0},
1457 {90, 0},
1458 {89, 0},
1459 {88, 0},
1460 {87, 0},
1461 {86, 0},
1462 {85, 0},
1463 {84, 0},
1464 {83, 0},
1465 {82, 0},
1466 {81, 0},
1467 {80, 0},
1468 {79, 0},
1469 {78, 0},
1470 {77, 0},
1471 {76, 0},
1472 {75, 0},
1473 {74, 0},
1474 {73, 0},
1475 {72, 0},
1476 {71, 0},
1477 {70, 0},
1478 {69, 0},
1479 {68, 0},
1480 {67, 0},
1481 {66, 0},
1482 {65, 0},
1483 {64, 0},
1484 {63, 0},
1485 {62, 0},
1486 {61, 0},
1487 {60, 0},
1488 {59, 0},
1489 }
1490 };
1491
1492 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1493 u8 is_fat, u8 ctrl_chan_high,
1494 struct iwl4965_tx_power_db *tx_power_tbl)
1495 {
1496 u8 saturation_power;
1497 s32 target_power;
1498 s32 user_target_power;
1499 s32 power_limit;
1500 s32 current_temp;
1501 s32 reg_limit;
1502 s32 current_regulatory;
1503 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1504 int i;
1505 int c;
1506 const struct iwl_channel_info *ch_info = NULL;
1507 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1508 const struct iwl_eeprom_calib_measure *measurement;
1509 s16 voltage;
1510 s32 init_voltage;
1511 s32 voltage_compensation;
1512 s32 degrees_per_05db_num;
1513 s32 degrees_per_05db_denom;
1514 s32 factory_temp;
1515 s32 temperature_comp[2];
1516 s32 factory_gain_index[2];
1517 s32 factory_actual_pwr[2];
1518 s32 power_index;
1519
1520 /* Sanity check requested level (dBm) */
1521 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1522 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1523 priv->user_txpower_limit);
1524 return -EINVAL;
1525 }
1526 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1527 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1528 priv->user_txpower_limit);
1529 return -EINVAL;
1530 }
1531
1532 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1533 * are used for indexing into txpower table) */
1534 user_target_power = 2 * priv->user_txpower_limit;
1535
1536 /* Get current (RXON) channel, band, width */
1537 ch_info =
1538 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
1539
1540 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1541 is_fat);
1542
1543 if (!ch_info)
1544 return -EINVAL;
1545
1546 /* get txatten group, used to select 1) thermal txpower adjustment
1547 * and 2) mimo txpower balance between Tx chains. */
1548 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1549 if (txatten_grp < 0)
1550 return -EINVAL;
1551
1552 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1553 channel, txatten_grp);
1554
1555 if (is_fat) {
1556 if (ctrl_chan_high)
1557 channel -= 2;
1558 else
1559 channel += 2;
1560 }
1561
1562 /* hardware txpower limits ...
1563 * saturation (clipping distortion) txpowers are in half-dBm */
1564 if (band)
1565 saturation_power = priv->calib_info->saturation_power24;
1566 else
1567 saturation_power = priv->calib_info->saturation_power52;
1568
1569 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1570 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1571 if (band)
1572 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1573 else
1574 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1575 }
1576
1577 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1578 * max_power_avg values are in dBm, convert * 2 */
1579 if (is_fat)
1580 reg_limit = ch_info->fat_max_power_avg * 2;
1581 else
1582 reg_limit = ch_info->max_power_avg * 2;
1583
1584 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1585 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1586 if (band)
1587 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1588 else
1589 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1590 }
1591
1592 /* Interpolate txpower calibration values for this channel,
1593 * based on factory calibration tests on spaced channels. */
1594 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1595
1596 /* calculate tx gain adjustment based on power supply voltage */
1597 voltage = priv->calib_info->voltage;
1598 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1599 voltage_compensation =
1600 iwl4965_get_voltage_compensation(voltage, init_voltage);
1601
1602 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
1603 init_voltage,
1604 voltage, voltage_compensation);
1605
1606 /* get current temperature (Celsius) */
1607 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1608 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1609 current_temp = KELVIN_TO_CELSIUS(current_temp);
1610
1611 /* select thermal txpower adjustment params, based on channel group
1612 * (same frequency group used for mimo txatten adjustment) */
1613 degrees_per_05db_num =
1614 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1615 degrees_per_05db_denom =
1616 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1617
1618 /* get per-chain txpower values from factory measurements */
1619 for (c = 0; c < 2; c++) {
1620 measurement = &ch_eeprom_info.measurements[c][1];
1621
1622 /* txgain adjustment (in half-dB steps) based on difference
1623 * between factory and current temperature */
1624 factory_temp = measurement->temperature;
1625 iwl4965_math_div_round((current_temp - factory_temp) *
1626 degrees_per_05db_denom,
1627 degrees_per_05db_num,
1628 &temperature_comp[c]);
1629
1630 factory_gain_index[c] = measurement->gain_idx;
1631 factory_actual_pwr[c] = measurement->actual_pow;
1632
1633 IWL_DEBUG_TXPOWER("chain = %d\n", c);
1634 IWL_DEBUG_TXPOWER("fctry tmp %d, "
1635 "curr tmp %d, comp %d steps\n",
1636 factory_temp, current_temp,
1637 temperature_comp[c]);
1638
1639 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
1640 factory_gain_index[c],
1641 factory_actual_pwr[c]);
1642 }
1643
1644 /* for each of 33 bit-rates (including 1 for CCK) */
1645 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1646 u8 is_mimo_rate;
1647 union iwl4965_tx_power_dual_stream tx_power;
1648
1649 /* for mimo, reduce each chain's txpower by half
1650 * (3dB, 6 steps), so total output power is regulatory
1651 * compliant. */
1652 if (i & 0x8) {
1653 current_regulatory = reg_limit -
1654 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1655 is_mimo_rate = 1;
1656 } else {
1657 current_regulatory = reg_limit;
1658 is_mimo_rate = 0;
1659 }
1660
1661 /* find txpower limit, either hardware or regulatory */
1662 power_limit = saturation_power - back_off_table[i];
1663 if (power_limit > current_regulatory)
1664 power_limit = current_regulatory;
1665
1666 /* reduce user's txpower request if necessary
1667 * for this rate on this channel */
1668 target_power = user_target_power;
1669 if (target_power > power_limit)
1670 target_power = power_limit;
1671
1672 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
1673 i, saturation_power - back_off_table[i],
1674 current_regulatory, user_target_power,
1675 target_power);
1676
1677 /* for each of 2 Tx chains (radio transmitters) */
1678 for (c = 0; c < 2; c++) {
1679 s32 atten_value;
1680
1681 if (is_mimo_rate)
1682 atten_value =
1683 (s32)le32_to_cpu(priv->card_alive_init.
1684 tx_atten[txatten_grp][c]);
1685 else
1686 atten_value = 0;
1687
1688 /* calculate index; higher index means lower txpower */
1689 power_index = (u8) (factory_gain_index[c] -
1690 (target_power -
1691 factory_actual_pwr[c]) -
1692 temperature_comp[c] -
1693 voltage_compensation +
1694 atten_value);
1695
1696 /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
1697 power_index); */
1698
1699 if (power_index < get_min_power_index(i, band))
1700 power_index = get_min_power_index(i, band);
1701
1702 /* adjust 5 GHz index to support negative indexes */
1703 if (!band)
1704 power_index += 9;
1705
1706 /* CCK, rate 32, reduce txpower for CCK */
1707 if (i == POWER_TABLE_CCK_ENTRY)
1708 power_index +=
1709 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1710
1711 /* stay within the table! */
1712 if (power_index > 107) {
1713 IWL_WARNING("txpower index %d > 107\n",
1714 power_index);
1715 power_index = 107;
1716 }
1717 if (power_index < 0) {
1718 IWL_WARNING("txpower index %d < 0\n",
1719 power_index);
1720 power_index = 0;
1721 }
1722
1723 /* fill txpower command for this rate/chain */
1724 tx_power.s.radio_tx_gain[c] =
1725 gain_table[band][power_index].radio;
1726 tx_power.s.dsp_predis_atten[c] =
1727 gain_table[band][power_index].dsp;
1728
1729 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
1730 "gain 0x%02x dsp %d\n",
1731 c, atten_value, power_index,
1732 tx_power.s.radio_tx_gain[c],
1733 tx_power.s.dsp_predis_atten[c]);
1734 }/* for each chain */
1735
1736 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1737
1738 }/* for each rate */
1739
1740 return 0;
1741 }
1742
1743 /**
1744 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
1745 *
1746 * Uses the active RXON for channel, band, and characteristics (fat, high)
1747 * The power limit is taken from priv->user_txpower_limit.
1748 */
1749 int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
1750 {
1751 struct iwl4965_txpowertable_cmd cmd = { 0 };
1752 int ret;
1753 u8 band = 0;
1754 u8 is_fat = 0;
1755 u8 ctrl_chan_high = 0;
1756
1757 if (test_bit(STATUS_SCANNING, &priv->status)) {
1758 /* If this gets hit a lot, switch it to a BUG() and catch
1759 * the stack trace to find out who is calling this during
1760 * a scan. */
1761 IWL_WARNING("TX Power requested while scanning!\n");
1762 return -EAGAIN;
1763 }
1764
1765 band = priv->band == IEEE80211_BAND_2GHZ;
1766
1767 is_fat = is_fat_channel(priv->active_rxon.flags);
1768
1769 if (is_fat &&
1770 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1771 ctrl_chan_high = 1;
1772
1773 cmd.band = band;
1774 cmd.channel = priv->active_rxon.channel;
1775
1776 ret = iwl4965_fill_txpower_tbl(priv, band,
1777 le16_to_cpu(priv->active_rxon.channel),
1778 is_fat, ctrl_chan_high, &cmd.tx_power);
1779 if (ret)
1780 goto out;
1781
1782 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1783
1784 out:
1785 return ret;
1786 }
1787
1788 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1789 {
1790 int ret = 0;
1791 struct iwl4965_rxon_assoc_cmd rxon_assoc;
1792 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1793 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1794
1795 if ((rxon1->flags == rxon2->flags) &&
1796 (rxon1->filter_flags == rxon2->filter_flags) &&
1797 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1798 (rxon1->ofdm_ht_single_stream_basic_rates ==
1799 rxon2->ofdm_ht_single_stream_basic_rates) &&
1800 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1801 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1802 (rxon1->rx_chain == rxon2->rx_chain) &&
1803 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1804 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1805 return 0;
1806 }
1807
1808 rxon_assoc.flags = priv->staging_rxon.flags;
1809 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1810 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1811 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1812 rxon_assoc.reserved = 0;
1813 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1814 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1815 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1816 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1817 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1818
1819 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1820 sizeof(rxon_assoc), &rxon_assoc, NULL);
1821 if (ret)
1822 return ret;
1823
1824 return ret;
1825 }
1826
1827
1828 int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1829 {
1830 int rc;
1831 u8 band = 0;
1832 u8 is_fat = 0;
1833 u8 ctrl_chan_high = 0;
1834 struct iwl4965_channel_switch_cmd cmd = { 0 };
1835 const struct iwl_channel_info *ch_info;
1836
1837 band = priv->band == IEEE80211_BAND_2GHZ;
1838
1839 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1840
1841 is_fat = is_fat_channel(priv->staging_rxon.flags);
1842
1843 if (is_fat &&
1844 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1845 ctrl_chan_high = 1;
1846
1847 cmd.band = band;
1848 cmd.expect_beacon = 0;
1849 cmd.channel = cpu_to_le16(channel);
1850 cmd.rxon_flags = priv->active_rxon.flags;
1851 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1852 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1853 if (ch_info)
1854 cmd.expect_beacon = is_channel_radar(ch_info);
1855 else
1856 cmd.expect_beacon = 1;
1857
1858 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
1859 ctrl_chan_high, &cmd.tx_power);
1860 if (rc) {
1861 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
1862 return rc;
1863 }
1864
1865 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
1866 return rc;
1867 }
1868
1869 static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
1870 {
1871 struct iwl4965_shared *s = priv->shared_virt;
1872 return le32_to_cpu(s->rb_closed) & 0xFFF;
1873 }
1874
1875 int iwl4965_hw_get_temperature(struct iwl_priv *priv)
1876 {
1877 return priv->temperature;
1878 }
1879
1880 unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
1881 struct iwl_frame *frame, u8 rate)
1882 {
1883 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
1884 unsigned int frame_size;
1885
1886 tx_beacon_cmd = &frame->u.beacon;
1887 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
1888
1889 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
1890 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1891
1892 frame_size = iwl4965_fill_beacon_frame(priv,
1893 tx_beacon_cmd->frame,
1894 iwl_bcast_addr,
1895 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
1896
1897 BUG_ON(frame_size > MAX_MPDU_SIZE);
1898 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
1899
1900 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
1901 tx_beacon_cmd->tx.rate_n_flags =
1902 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
1903 else
1904 tx_beacon_cmd->tx.rate_n_flags =
1905 iwl4965_hw_set_rate_n_flags(rate, 0);
1906
1907 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
1908 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
1909 return (sizeof(*tx_beacon_cmd) + frame_size);
1910 }
1911
1912 static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
1913 {
1914 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
1915 sizeof(struct iwl4965_shared),
1916 &priv->shared_phys);
1917 if (!priv->shared_virt)
1918 return -ENOMEM;
1919
1920 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
1921
1922 priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
1923
1924 return 0;
1925 }
1926
1927 static void iwl4965_free_shared_mem(struct iwl_priv *priv)
1928 {
1929 if (priv->shared_virt)
1930 pci_free_consistent(priv->pci_dev,
1931 sizeof(struct iwl4965_shared),
1932 priv->shared_virt,
1933 priv->shared_phys);
1934 }
1935
1936 /**
1937 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
1938 */
1939 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
1940 struct iwl_tx_queue *txq,
1941 u16 byte_cnt)
1942 {
1943 int len;
1944 int txq_id = txq->q.id;
1945 struct iwl4965_shared *shared_data = priv->shared_virt;
1946
1947 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1948
1949 /* Set up byte count within first 256 entries */
1950 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
1951 tfd_offset[txq->q.write_ptr], byte_cnt, len);
1952
1953 /* If within first 64 entries, duplicate at end */
1954 if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
1955 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
1956 tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
1957 byte_cnt, len);
1958 }
1959
1960 /**
1961 * sign_extend - Sign extend a value using specified bit as sign-bit
1962 *
1963 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1964 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1965 *
1966 * @param oper value to sign extend
1967 * @param index 0 based bit index (0<=index<32) to sign bit
1968 */
1969 static s32 sign_extend(u32 oper, int index)
1970 {
1971 u8 shift = 31 - index;
1972
1973 return (s32)(oper << shift) >> shift;
1974 }
1975
1976 /**
1977 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
1978 * @statistics: Provides the temperature reading from the uCode
1979 *
1980 * A return of <0 indicates bogus data in the statistics
1981 */
1982 int iwl4965_get_temperature(const struct iwl_priv *priv)
1983 {
1984 s32 temperature;
1985 s32 vt;
1986 s32 R1, R2, R3;
1987 u32 R4;
1988
1989 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1990 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
1991 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
1992 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1993 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1994 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1995 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1996 } else {
1997 IWL_DEBUG_TEMP("Running temperature calibration\n");
1998 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1999 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2000 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2001 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2002 }
2003
2004 /*
2005 * Temperature is only 23 bits, so sign extend out to 32.
2006 *
2007 * NOTE If we haven't received a statistics notification yet
2008 * with an updated temperature, use R4 provided to us in the
2009 * "initialize" ALIVE response.
2010 */
2011 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2012 vt = sign_extend(R4, 23);
2013 else
2014 vt = sign_extend(
2015 le32_to_cpu(priv->statistics.general.temperature), 23);
2016
2017 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2018 R1, R2, R3, vt);
2019
2020 if (R3 == R1) {
2021 IWL_ERROR("Calibration conflict R1 == R3\n");
2022 return -1;
2023 }
2024
2025 /* Calculate temperature in degrees Kelvin, adjust by 97%.
2026 * Add offset to center the adjustment around 0 degrees Centigrade. */
2027 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2028 temperature /= (R3 - R1);
2029 temperature = (temperature * 97) / 100 +
2030 TEMPERATURE_CALIB_KELVIN_OFFSET;
2031
2032 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2033 KELVIN_TO_CELSIUS(temperature));
2034
2035 return temperature;
2036 }
2037
2038 /* Adjust Txpower only if temperature variance is greater than threshold. */
2039 #define IWL_TEMPERATURE_THRESHOLD 3
2040
2041 /**
2042 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2043 *
2044 * If the temperature changed has changed sufficiently, then a recalibration
2045 * is needed.
2046 *
2047 * Assumes caller will replace priv->last_temperature once calibration
2048 * executed.
2049 */
2050 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
2051 {
2052 int temp_diff;
2053
2054 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2055 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2056 return 0;
2057 }
2058
2059 temp_diff = priv->temperature - priv->last_temperature;
2060
2061 /* get absolute value */
2062 if (temp_diff < 0) {
2063 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2064 temp_diff = -temp_diff;
2065 } else if (temp_diff == 0)
2066 IWL_DEBUG_POWER("Same temp, \n");
2067 else
2068 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2069
2070 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2071 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2072 return 0;
2073 }
2074
2075 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2076
2077 return 1;
2078 }
2079
2080 /* Calculate noise level, based on measurements during network silence just
2081 * before arriving beacon. This measurement can be done only if we know
2082 * exactly when to expect beacons, therefore only when we're associated. */
2083 static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
2084 {
2085 struct statistics_rx_non_phy *rx_info
2086 = &(priv->statistics.rx.general);
2087 int num_active_rx = 0;
2088 int total_silence = 0;
2089 int bcn_silence_a =
2090 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2091 int bcn_silence_b =
2092 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2093 int bcn_silence_c =
2094 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2095
2096 if (bcn_silence_a) {
2097 total_silence += bcn_silence_a;
2098 num_active_rx++;
2099 }
2100 if (bcn_silence_b) {
2101 total_silence += bcn_silence_b;
2102 num_active_rx++;
2103 }
2104 if (bcn_silence_c) {
2105 total_silence += bcn_silence_c;
2106 num_active_rx++;
2107 }
2108
2109 /* Average among active antennas */
2110 if (num_active_rx)
2111 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2112 else
2113 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2114
2115 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2116 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2117 priv->last_rx_noise);
2118 }
2119
2120 void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
2121 struct iwl_rx_mem_buffer *rxb)
2122 {
2123 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2124 int change;
2125 s32 temp;
2126
2127 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2128 (int)sizeof(priv->statistics), pkt->len);
2129
2130 change = ((priv->statistics.general.temperature !=
2131 pkt->u.stats.general.temperature) ||
2132 ((priv->statistics.flag &
2133 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2134 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2135
2136 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2137
2138 set_bit(STATUS_STATISTICS, &priv->status);
2139
2140 /* Reschedule the statistics timer to occur in
2141 * REG_RECALIB_PERIOD seconds to ensure we get a
2142 * thermal update even if the uCode doesn't give
2143 * us one */
2144 mod_timer(&priv->statistics_periodic, jiffies +
2145 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2146
2147 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2148 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2149 iwl4965_rx_calc_noise(priv);
2150 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
2151 queue_work(priv->workqueue, &priv->sensitivity_work);
2152 #endif
2153 }
2154
2155 iwl_leds_background(priv);
2156
2157 /* If the hardware hasn't reported a change in
2158 * temperature then don't bother computing a
2159 * calibrated temperature value */
2160 if (!change)
2161 return;
2162
2163 temp = iwl4965_get_temperature(priv);
2164 if (temp < 0)
2165 return;
2166
2167 if (priv->temperature != temp) {
2168 if (priv->temperature)
2169 IWL_DEBUG_TEMP("Temperature changed "
2170 "from %dC to %dC\n",
2171 KELVIN_TO_CELSIUS(priv->temperature),
2172 KELVIN_TO_CELSIUS(temp));
2173 else
2174 IWL_DEBUG_TEMP("Temperature "
2175 "initialized to %dC\n",
2176 KELVIN_TO_CELSIUS(temp));
2177 }
2178
2179 priv->temperature = temp;
2180 set_bit(STATUS_TEMPERATURE, &priv->status);
2181
2182 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2183 iwl4965_is_temp_calib_needed(priv))
2184 queue_work(priv->workqueue, &priv->txpower_work);
2185 }
2186
2187 static void iwl4965_add_radiotap(struct iwl_priv *priv,
2188 struct sk_buff *skb,
2189 struct iwl4965_rx_phy_res *rx_start,
2190 struct ieee80211_rx_status *stats,
2191 u32 ampdu_status)
2192 {
2193 s8 signal = stats->signal;
2194 s8 noise = 0;
2195 int rate = stats->rate_idx;
2196 u64 tsf = stats->mactime;
2197 __le16 antenna;
2198 __le16 phy_flags_hw = rx_start->phy_flags;
2199 struct iwl4965_rt_rx_hdr {
2200 struct ieee80211_radiotap_header rt_hdr;
2201 __le64 rt_tsf; /* TSF */
2202 u8 rt_flags; /* radiotap packet flags */
2203 u8 rt_rate; /* rate in 500kb/s */
2204 __le16 rt_channelMHz; /* channel in MHz */
2205 __le16 rt_chbitmask; /* channel bitfield */
2206 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2207 s8 rt_dbmnoise;
2208 u8 rt_antenna; /* antenna number */
2209 } __attribute__ ((packed)) *iwl4965_rt;
2210
2211 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2212 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2213 if (net_ratelimit())
2214 printk(KERN_ERR "not enough headroom [%d] for "
2215 "radiotap head [%zd]\n",
2216 skb_headroom(skb), sizeof(*iwl4965_rt));
2217 return;
2218 }
2219
2220 /* put radiotap header in front of 802.11 header and data */
2221 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2222
2223 /* initialise radiotap header */
2224 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2225 iwl4965_rt->rt_hdr.it_pad = 0;
2226
2227 /* total header + data */
2228 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2229 &iwl4965_rt->rt_hdr.it_len);
2230
2231 /* Indicate all the fields we add to the radiotap header */
2232 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2233 (1 << IEEE80211_RADIOTAP_FLAGS) |
2234 (1 << IEEE80211_RADIOTAP_RATE) |
2235 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2236 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2237 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2238 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2239 &iwl4965_rt->rt_hdr.it_present);
2240
2241 /* Zero the flags, we'll add to them as we go */
2242 iwl4965_rt->rt_flags = 0;
2243
2244 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2245
2246 iwl4965_rt->rt_dbmsignal = signal;
2247 iwl4965_rt->rt_dbmnoise = noise;
2248
2249 /* Convert the channel frequency and set the flags */
2250 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2251 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2252 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2253 IEEE80211_CHAN_5GHZ),
2254 &iwl4965_rt->rt_chbitmask);
2255 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2256 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2257 IEEE80211_CHAN_2GHZ),
2258 &iwl4965_rt->rt_chbitmask);
2259 else /* 802.11g */
2260 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2261 IEEE80211_CHAN_2GHZ),
2262 &iwl4965_rt->rt_chbitmask);
2263
2264 if (rate == -1)
2265 iwl4965_rt->rt_rate = 0;
2266 else
2267 iwl4965_rt->rt_rate = iwl_rates[rate].ieee;
2268
2269 /*
2270 * "antenna number"
2271 *
2272 * It seems that the antenna field in the phy flags value
2273 * is actually a bitfield. This is undefined by radiotap,
2274 * it wants an actual antenna number but I always get "7"
2275 * for most legacy frames I receive indicating that the
2276 * same frame was received on all three RX chains.
2277 *
2278 * I think this field should be removed in favour of a
2279 * new 802.11n radiotap field "RX chains" that is defined
2280 * as a bitmask.
2281 */
2282 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2283 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
2284
2285 /* set the preamble flag if appropriate */
2286 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2287 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2288
2289 stats->flag |= RX_FLAG_RADIOTAP;
2290 }
2291
2292 static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2293 {
2294 /* 0 - mgmt, 1 - cnt, 2 - data */
2295 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2296 priv->rx_stats[idx].cnt++;
2297 priv->rx_stats[idx].bytes += len;
2298 }
2299
2300 /*
2301 * returns non-zero if packet should be dropped
2302 */
2303 static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2304 struct ieee80211_hdr *hdr,
2305 u32 decrypt_res,
2306 struct ieee80211_rx_status *stats)
2307 {
2308 u16 fc = le16_to_cpu(hdr->frame_control);
2309
2310 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2311 return 0;
2312
2313 if (!(fc & IEEE80211_FCTL_PROTECTED))
2314 return 0;
2315
2316 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2317 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2318 case RX_RES_STATUS_SEC_TYPE_TKIP:
2319 /* The uCode has got a bad phase 1 Key, pushes the packet.
2320 * Decryption will be done in SW. */
2321 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2322 RX_RES_STATUS_BAD_KEY_TTAK)
2323 break;
2324
2325 case RX_RES_STATUS_SEC_TYPE_WEP:
2326 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2327 RX_RES_STATUS_BAD_ICV_MIC) {
2328 /* bad ICV, the packet is destroyed since the
2329 * decryption is inplace, drop it */
2330 IWL_DEBUG_RX("Packet destroyed\n");
2331 return -1;
2332 }
2333 case RX_RES_STATUS_SEC_TYPE_CCMP:
2334 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2335 RX_RES_STATUS_DECRYPT_OK) {
2336 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2337 stats->flag |= RX_FLAG_DECRYPTED;
2338 }
2339 break;
2340
2341 default:
2342 break;
2343 }
2344 return 0;
2345 }
2346
2347 static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
2348 {
2349 u32 decrypt_out = 0;
2350
2351 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2352 RX_RES_STATUS_STATION_FOUND)
2353 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2354 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2355
2356 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2357
2358 /* packet was not encrypted */
2359 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2360 RX_RES_STATUS_SEC_TYPE_NONE)
2361 return decrypt_out;
2362
2363 /* packet was encrypted with unknown alg */
2364 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2365 RX_RES_STATUS_SEC_TYPE_ERR)
2366 return decrypt_out;
2367
2368 /* decryption was not done in HW */
2369 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2370 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2371 return decrypt_out;
2372
2373 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2374
2375 case RX_RES_STATUS_SEC_TYPE_CCMP:
2376 /* alg is CCM: check MIC only */
2377 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2378 /* Bad MIC */
2379 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2380 else
2381 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2382
2383 break;
2384
2385 case RX_RES_STATUS_SEC_TYPE_TKIP:
2386 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2387 /* Bad TTAK */
2388 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2389 break;
2390 }
2391 /* fall through if TTAK OK */
2392 default:
2393 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2394 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2395 else
2396 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2397 break;
2398 };
2399
2400 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
2401 decrypt_in, decrypt_out);
2402
2403 return decrypt_out;
2404 }
2405
2406 static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
2407 int include_phy,
2408 struct iwl_rx_mem_buffer *rxb,
2409 struct ieee80211_rx_status *stats)
2410 {
2411 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2412 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2413 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
2414 struct ieee80211_hdr *hdr;
2415 u16 len;
2416 __le32 *rx_end;
2417 unsigned int skblen;
2418 u32 ampdu_status;
2419 u32 ampdu_status_legacy;
2420
2421 if (!include_phy && priv->last_phy_res[0])
2422 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2423
2424 if (!rx_start) {
2425 IWL_ERROR("MPDU frame without a PHY data\n");
2426 return;
2427 }
2428 if (include_phy) {
2429 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
2430 rx_start->cfg_phy_cnt);
2431
2432 len = le16_to_cpu(rx_start->byte_count);
2433
2434 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
2435 sizeof(struct iwl4965_rx_phy_res) +
2436 rx_start->cfg_phy_cnt + len);
2437
2438 } else {
2439 struct iwl4965_rx_mpdu_res_start *amsdu =
2440 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2441
2442 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
2443 sizeof(struct iwl4965_rx_mpdu_res_start));
2444 len = le16_to_cpu(amsdu->byte_count);
2445 rx_start->byte_count = amsdu->byte_count;
2446 rx_end = (__le32 *) (((u8 *) hdr) + len);
2447 }
2448 /* In monitor mode allow 802.11 ACk frames (10 bytes) */
2449 if (len > priv->hw_params.max_pkt_size ||
2450 len < ((priv->iw_mode == IEEE80211_IF_TYPE_MNTR) ? 10 : 16)) {
2451 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
2452 return;
2453 }
2454
2455 ampdu_status = le32_to_cpu(*rx_end);
2456 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
2457
2458 if (!include_phy) {
2459 /* New status scheme, need to translate */
2460 ampdu_status_legacy = ampdu_status;
2461 ampdu_status = iwl4965_translate_rx_status(priv, ampdu_status);
2462 }
2463
2464 /* start from MAC */
2465 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
2466 skb_put(rxb->skb, len); /* end where data ends */
2467
2468 /* We only process data packets if the interface is open */
2469 if (unlikely(!priv->is_open)) {
2470 IWL_DEBUG_DROP_LIMIT
2471 ("Dropping packet while interface is not open.\n");
2472 return;
2473 }
2474
2475 stats->flag = 0;
2476 hdr = (struct ieee80211_hdr *)rxb->skb->data;
2477
2478 /* in case of HW accelerated crypto and bad decryption, drop */
2479 if (!priv->hw_params.sw_crypto &&
2480 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
2481 return;
2482
2483 if (priv->add_radiotap)
2484 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
2485
2486 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
2487 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
2488 priv->alloc_rxb_skb--;
2489 rxb->skb = NULL;
2490 }
2491
2492 /* Calc max signal level (dBm) among 3 possible receivers */
2493 static int iwl4965_calc_rssi(struct iwl_priv *priv,
2494 struct iwl4965_rx_phy_res *rx_resp)
2495 {
2496 /* data from PHY/DSP regarding signal strength, etc.,
2497 * contents are always there, not configurable by host. */
2498 struct iwl4965_rx_non_cfg_phy *ncphy =
2499 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
2500 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
2501 >> IWL_AGC_DB_POS;
2502
2503 u32 valid_antennae =
2504 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
2505 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
2506 u8 max_rssi = 0;
2507 u32 i;
2508
2509 /* Find max rssi among 3 possible receivers.
2510 * These values are measured by the digital signal processor (DSP).
2511 * They should stay fairly constant even as the signal strength varies,
2512 * if the radio's automatic gain control (AGC) is working right.
2513 * AGC value (see below) will provide the "interesting" info. */
2514 for (i = 0; i < 3; i++)
2515 if (valid_antennae & (1 << i))
2516 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2517
2518 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2519 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2520 max_rssi, agc);
2521
2522 /* dBm = max_rssi dB - agc dB - constant.
2523 * Higher AGC (higher radio gain) means lower signal. */
2524 return (max_rssi - agc - IWL_RSSI_OFFSET);
2525 }
2526
2527 static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
2528 {
2529 unsigned long flags;
2530
2531 spin_lock_irqsave(&priv->sta_lock, flags);
2532 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
2533 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
2534 priv->stations[sta_id].sta.sta.modify_mask = 0;
2535 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2536 spin_unlock_irqrestore(&priv->sta_lock, flags);
2537
2538 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
2539 }
2540
2541 static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
2542 {
2543 /* FIXME: need locking over ps_status ??? */
2544 u8 sta_id = iwl_find_station(priv, addr);
2545
2546 if (sta_id != IWL_INVALID_STATION) {
2547 u8 sta_awake = priv->stations[sta_id].
2548 ps_status == STA_PS_STATUS_WAKE;
2549
2550 if (sta_awake && ps_bit)
2551 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
2552 else if (!sta_awake && !ps_bit) {
2553 iwl4965_sta_modify_ps_wake(priv, sta_id);
2554 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
2555 }
2556 }
2557 }
2558 #ifdef CONFIG_IWLWIFI_DEBUG
2559
2560 /**
2561 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
2562 *
2563 * You may hack this function to show different aspects of received frames,
2564 * including selective frame dumps.
2565 * group100 parameter selects whether to show 1 out of 100 good frames.
2566 *
2567 * TODO: This was originally written for 3945, need to audit for
2568 * proper operation with 4965.
2569 */
2570 static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
2571 struct iwl_rx_packet *pkt,
2572 struct ieee80211_hdr *header, int group100)
2573 {
2574 u32 to_us;
2575 u32 print_summary = 0;
2576 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
2577 u32 hundred = 0;
2578 u32 dataframe = 0;
2579 u16 fc;
2580 u16 seq_ctl;
2581 u16 channel;
2582 u16 phy_flags;
2583 int rate_sym;
2584 u16 length;
2585 u16 status;
2586 u16 bcn_tmr;
2587 u32 tsf_low;
2588 u64 tsf;
2589 u8 rssi;
2590 u8 agc;
2591 u16 sig_avg;
2592 u16 noise_diff;
2593 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
2594 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
2595 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
2596 u8 *data = IWL_RX_DATA(pkt);
2597
2598 if (likely(!(priv->debug_level & IWL_DL_RX)))
2599 return;
2600
2601 /* MAC header */
2602 fc = le16_to_cpu(header->frame_control);
2603 seq_ctl = le16_to_cpu(header->seq_ctrl);
2604
2605 /* metadata */
2606 channel = le16_to_cpu(rx_hdr->channel);
2607 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
2608 rate_sym = rx_hdr->rate;
2609 length = le16_to_cpu(rx_hdr->len);
2610
2611 /* end-of-frame status and timestamp */
2612 status = le32_to_cpu(rx_end->status);
2613 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
2614 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
2615 tsf = le64_to_cpu(rx_end->timestamp);
2616
2617 /* signal statistics */
2618 rssi = rx_stats->rssi;
2619 agc = rx_stats->agc;
2620 sig_avg = le16_to_cpu(rx_stats->sig_avg);
2621 noise_diff = le16_to_cpu(rx_stats->noise_diff);
2622
2623 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
2624
2625 /* if data frame is to us and all is good,
2626 * (optionally) print summary for only 1 out of every 100 */
2627 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
2628 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
2629 dataframe = 1;
2630 if (!group100)
2631 print_summary = 1; /* print each frame */
2632 else if (priv->framecnt_to_us < 100) {
2633 priv->framecnt_to_us++;
2634 print_summary = 0;
2635 } else {
2636 priv->framecnt_to_us = 0;
2637 print_summary = 1;
2638 hundred = 1;
2639 }
2640 } else {
2641 /* print summary for all other frames */
2642 print_summary = 1;
2643 }
2644
2645 if (print_summary) {
2646 char *title;
2647 int rate_idx;
2648 u32 bitrate;
2649
2650 if (hundred)
2651 title = "100Frames";
2652 else if (fc & IEEE80211_FCTL_RETRY)
2653 title = "Retry";
2654 else if (ieee80211_is_assoc_response(fc))
2655 title = "AscRsp";
2656 else if (ieee80211_is_reassoc_response(fc))
2657 title = "RasRsp";
2658 else if (ieee80211_is_probe_response(fc)) {
2659 title = "PrbRsp";
2660 print_dump = 1; /* dump frame contents */
2661 } else if (ieee80211_is_beacon(fc)) {
2662 title = "Beacon";
2663 print_dump = 1; /* dump frame contents */
2664 } else if (ieee80211_is_atim(fc))
2665 title = "ATIM";
2666 else if (ieee80211_is_auth(fc))
2667 title = "Auth";
2668 else if (ieee80211_is_deauth(fc))
2669 title = "DeAuth";
2670 else if (ieee80211_is_disassoc(fc))
2671 title = "DisAssoc";
2672 else
2673 title = "Frame";
2674
2675 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
2676 if (unlikely(rate_idx == -1))
2677 bitrate = 0;
2678 else
2679 bitrate = iwl_rates[rate_idx].ieee / 2;
2680
2681 /* print frame summary.
2682 * MAC addresses show just the last byte (for brevity),
2683 * but you can hack it to show more, if you'd like to. */
2684 if (dataframe)
2685 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
2686 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
2687 title, fc, header->addr1[5],
2688 length, rssi, channel, bitrate);
2689 else {
2690 /* src/dst addresses assume managed mode */
2691 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
2692 "src=0x%02x, rssi=%u, tim=%lu usec, "
2693 "phy=0x%02x, chnl=%d\n",
2694 title, fc, header->addr1[5],
2695 header->addr3[5], rssi,
2696 tsf_low - priv->scan_start_tsf,
2697 phy_flags, channel);
2698 }
2699 }
2700 if (print_dump)
2701 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
2702 }
2703 #else
2704 static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
2705 struct iwl_rx_packet *pkt,
2706 struct ieee80211_hdr *header,
2707 int group100)
2708 {
2709 }
2710 #endif
2711
2712
2713
2714 /* Called for REPLY_RX (legacy ABG frames), or
2715 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
2716 static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
2717 struct iwl_rx_mem_buffer *rxb)
2718 {
2719 struct ieee80211_hdr *header;
2720 struct ieee80211_rx_status rx_status;
2721 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2722 /* Use phy data (Rx signal strength, etc.) contained within
2723 * this rx packet for legacy frames,
2724 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
2725 int include_phy = (pkt->hdr.cmd == REPLY_RX);
2726 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2727 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
2728 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2729 __le32 *rx_end;
2730 unsigned int len = 0;
2731 u16 fc;
2732 u8 network_packet;
2733
2734 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
2735 rx_status.freq =
2736 ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
2737 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
2738 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
2739 rx_status.rate_idx =
2740 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
2741 if (rx_status.band == IEEE80211_BAND_5GHZ)
2742 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
2743
2744 rx_status.antenna = 0;
2745 rx_status.flag = 0;
2746
2747 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
2748 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
2749 rx_start->cfg_phy_cnt);
2750 return;
2751 }
2752
2753 if (!include_phy) {
2754 if (priv->last_phy_res[0])
2755 rx_start = (struct iwl4965_rx_phy_res *)
2756 &priv->last_phy_res[1];
2757 else
2758 rx_start = NULL;
2759 }
2760
2761 if (!rx_start) {
2762 IWL_ERROR("MPDU frame without a PHY data\n");
2763 return;
2764 }
2765
2766 if (include_phy) {
2767 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
2768 + rx_start->cfg_phy_cnt);
2769
2770 len = le16_to_cpu(rx_start->byte_count);
2771 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
2772 sizeof(struct iwl4965_rx_phy_res) + len);
2773 } else {
2774 struct iwl4965_rx_mpdu_res_start *amsdu =
2775 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2776
2777 header = (void *)(pkt->u.raw +
2778 sizeof(struct iwl4965_rx_mpdu_res_start));
2779 len = le16_to_cpu(amsdu->byte_count);
2780 rx_end = (__le32 *) (pkt->u.raw +
2781 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
2782 }
2783
2784 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
2785 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
2786 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
2787 le32_to_cpu(*rx_end));
2788 return;
2789 }
2790
2791 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
2792
2793 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
2794 rx_status.signal = iwl4965_calc_rssi(priv, rx_start);
2795
2796 /* Meaningful noise values are available only from beacon statistics,
2797 * which are gathered only when associated, and indicate noise
2798 * only for the associated network channel ...
2799 * Ignore these noise values while scanning (other channels) */
2800 if (iwl_is_associated(priv) &&
2801 !test_bit(STATUS_SCANNING, &priv->status)) {
2802 rx_status.noise = priv->last_rx_noise;
2803 rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal,
2804 rx_status.noise);
2805 } else {
2806 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2807 rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal, 0);
2808 }
2809
2810 /* Reset beacon noise level if not associated. */
2811 if (!iwl_is_associated(priv))
2812 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2813
2814 /* Set "1" to report good data frames in groups of 100 */
2815 /* FIXME: need to optimze the call: */
2816 iwl4965_dbg_report_frame(priv, pkt, header, 1);
2817
2818 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
2819 rx_status.signal, rx_status.noise, rx_status.signal,
2820 (unsigned long long)rx_status.mactime);
2821
2822
2823 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
2824 iwl4965_handle_data_packet(priv, 1, include_phy,
2825 rxb, &rx_status);
2826 return;
2827 }
2828
2829 network_packet = iwl4965_is_network_packet(priv, header);
2830 if (network_packet) {
2831 priv->last_rx_rssi = rx_status.signal;
2832 priv->last_beacon_time = priv->ucode_beacon_time;
2833 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
2834 }
2835
2836 fc = le16_to_cpu(header->frame_control);
2837 switch (fc & IEEE80211_FCTL_FTYPE) {
2838 case IEEE80211_FTYPE_MGMT:
2839 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
2840 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
2841 header->addr2);
2842 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
2843 break;
2844
2845 case IEEE80211_FTYPE_CTL:
2846 #ifdef CONFIG_IWL4965_HT
2847 switch (fc & IEEE80211_FCTL_STYPE) {
2848 case IEEE80211_STYPE_BACK_REQ:
2849 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
2850 iwl4965_handle_data_packet(priv, 0, include_phy,
2851 rxb, &rx_status);
2852 break;
2853 default:
2854 break;
2855 }
2856 #endif
2857 break;
2858
2859 case IEEE80211_FTYPE_DATA: {
2860 DECLARE_MAC_BUF(mac1);
2861 DECLARE_MAC_BUF(mac2);
2862 DECLARE_MAC_BUF(mac3);
2863
2864 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
2865 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
2866 header->addr2);
2867
2868 if (unlikely(!network_packet))
2869 IWL_DEBUG_DROP("Dropping (non network): "
2870 "%s, %s, %s\n",
2871 print_mac(mac1, header->addr1),
2872 print_mac(mac2, header->addr2),
2873 print_mac(mac3, header->addr3));
2874 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
2875 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
2876 print_mac(mac1, header->addr1),
2877 print_mac(mac2, header->addr2),
2878 print_mac(mac3, header->addr3));
2879 else
2880 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
2881 &rx_status);
2882 break;
2883 }
2884 default:
2885 break;
2886
2887 }
2888 }
2889
2890 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
2891 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
2892 static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
2893 struct iwl_rx_mem_buffer *rxb)
2894 {
2895 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2896 priv->last_phy_res[0] = 1;
2897 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
2898 sizeof(struct iwl4965_rx_phy_res));
2899 }
2900
2901 #ifdef CONFIG_IWL4965_HT
2902
2903 /**
2904 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2905 *
2906 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2907 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2908 */
2909 static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
2910 struct iwl_ht_agg *agg,
2911 struct iwl4965_compressed_ba_resp*
2912 ba_resp)
2913
2914 {
2915 int i, sh, ack;
2916 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2917 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2918 u64 bitmap;
2919 int successes = 0;
2920 struct ieee80211_tx_info *info;
2921
2922 if (unlikely(!agg->wait_for_ba)) {
2923 IWL_ERROR("Received BA when not expected\n");
2924 return -EINVAL;
2925 }
2926
2927 /* Mark that the expected block-ack response arrived */
2928 agg->wait_for_ba = 0;
2929 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
2930
2931 /* Calculate shift to align block-ack bits with our Tx window bits */
2932 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
2933 if (sh < 0) /* tbw something is wrong with indices */
2934 sh += 0x100;
2935
2936 /* don't use 64-bit values for now */
2937 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2938
2939 if (agg->frame_count > (64 - sh)) {
2940 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
2941 return -1;
2942 }
2943
2944 /* check for success or failure according to the
2945 * transmitted bitmap and block-ack bitmap */
2946 bitmap &= agg->bitmap;
2947
2948 /* For each frame attempted in aggregation,
2949 * update driver's record of tx frame's status. */
2950 for (i = 0; i < agg->frame_count ; i++) {
2951 ack = bitmap & (1 << i);
2952 successes += !!ack;
2953 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
2954 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
2955 agg->start_idx + i);
2956 }
2957
2958 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
2959 memset(&info->status, 0, sizeof(info->status));
2960 info->flags = IEEE80211_TX_STAT_ACK;
2961 info->flags |= IEEE80211_TX_STAT_AMPDU;
2962 info->status.ampdu_ack_map = successes;
2963 info->status.ampdu_ack_len = agg->frame_count;
2964 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
2965
2966 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
2967
2968 return 0;
2969 }
2970
2971 /**
2972 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2973 */
2974 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
2975 u16 txq_id)
2976 {
2977 /* Simply stop the queue, but don't change any configuration;
2978 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
2979 iwl_write_prph(priv,
2980 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
2981 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
2982 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
2983 }
2984
2985 /**
2986 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
2987 * priv->lock must be held by the caller
2988 */
2989 static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
2990 u16 ssn_idx, u8 tx_fifo)
2991 {
2992 int ret = 0;
2993
2994 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
2995 IWL_WARNING("queue number too small: %d, must be > %d\n",
2996 txq_id, IWL_BACK_QUEUE_FIRST_ID);
2997 return -EINVAL;
2998 }
2999
3000 ret = iwl_grab_nic_access(priv);
3001 if (ret)
3002 return ret;
3003
3004 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3005
3006 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3007
3008 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3009 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3010 /* supposes that ssn_idx is valid (!= 0xFFF) */
3011 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3012
3013 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3014 iwl_txq_ctx_deactivate(priv, txq_id);
3015 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3016
3017 iwl_release_nic_access(priv);
3018
3019 return 0;
3020 }
3021
3022 int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
3023 u8 tid, int txq_id)
3024 {
3025 struct iwl_queue *q = &priv->txq[txq_id].q;
3026 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3027 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3028
3029 switch (priv->stations[sta_id].tid[tid].agg.state) {
3030 case IWL_EMPTYING_HW_QUEUE_DELBA:
3031 /* We are reclaiming the last packet of the */
3032 /* aggregated HW queue */
3033 if (txq_id == tid_data->agg.txq_id &&
3034 q->read_ptr == q->write_ptr) {
3035 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3036 int tx_fifo = default_tid_to_tx_fifo[tid];
3037 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3038 iwl4965_tx_queue_agg_disable(priv, txq_id,
3039 ssn, tx_fifo);
3040 tid_data->agg.state = IWL_AGG_OFF;
3041 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3042 }
3043 break;
3044 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3045 /* We are reclaiming the last packet of the queue */
3046 if (tid_data->tfds_in_queue == 0) {
3047 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3048 tid_data->agg.state = IWL_AGG_ON;
3049 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3050 }
3051 break;
3052 }
3053 return 0;
3054 }
3055
3056 /**
3057 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3058 *
3059 * Handles block-acknowledge notification from device, which reports success
3060 * of frames sent via aggregation.
3061 */
3062 static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
3063 struct iwl_rx_mem_buffer *rxb)
3064 {
3065 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3066 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
3067 int index;
3068 struct iwl_tx_queue *txq = NULL;
3069 struct iwl_ht_agg *agg;
3070 DECLARE_MAC_BUF(mac);
3071
3072 /* "flow" corresponds to Tx queue */
3073 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3074
3075 /* "ssn" is start of block-ack Tx window, corresponds to index
3076 * (in Tx queue's circular buffer) of first TFD/frame in window */
3077 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3078
3079 if (scd_flow >= priv->hw_params.max_txq_num) {
3080 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3081 return;
3082 }
3083
3084 txq = &priv->txq[scd_flow];
3085 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
3086
3087 /* Find index just before block-ack window */
3088 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
3089
3090 /* TODO: Need to get this copy more safely - now good for debug */
3091
3092 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3093 "sta_id = %d\n",
3094 agg->wait_for_ba,
3095 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
3096 ba_resp->sta_id);
3097 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
3098 "%d, scd_ssn = %d\n",
3099 ba_resp->tid,
3100 ba_resp->seq_ctl,
3101 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
3102 ba_resp->scd_flow,
3103 ba_resp->scd_ssn);
3104 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
3105 agg->start_idx,
3106 (unsigned long long)agg->bitmap);
3107
3108 /* Update driver's record of ACK vs. not for each frame in window */
3109 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
3110
3111 /* Release all TFDs before the SSN, i.e. all TFDs in front of
3112 * block-ack window (we assume that they've been successfully
3113 * transmitted ... if not, it's too late anyway). */
3114 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3115 /* calculate mac80211 ampdu sw queue to wake */
3116 int ampdu_q =
3117 scd_flow - IWL_BACK_QUEUE_FIRST_ID + priv->hw->queues;
3118 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
3119 priv->stations[ba_resp->sta_id].
3120 tid[ba_resp->tid].tfds_in_queue -= freed;
3121 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
3122 priv->mac80211_registered &&
3123 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3124 ieee80211_wake_queue(priv->hw, ampdu_q);
3125 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3126 ba_resp->tid, scd_flow);
3127 }
3128 }
3129
3130 /**
3131 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3132 */
3133 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
3134 u16 txq_id)
3135 {
3136 u32 tbl_dw_addr;
3137 u32 tbl_dw;
3138 u16 scd_q2ratid;
3139
3140 scd_q2ratid = ra_tid & IWL49_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3141
3142 tbl_dw_addr = priv->scd_base_addr +
3143 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3144
3145 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
3146
3147 if (txq_id & 0x1)
3148 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3149 else
3150 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3151
3152 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
3153
3154 return 0;
3155 }
3156
3157
3158 /**
3159 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3160 *
3161 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3162 * i.e. it must be one of the higher queues used for aggregation
3163 */
3164 static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
3165 int tx_fifo, int sta_id, int tid,
3166 u16 ssn_idx)
3167 {
3168 unsigned long flags;
3169 int rc;
3170 u16 ra_tid;
3171
3172 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3173 IWL_WARNING("queue number too small: %d, must be > %d\n",
3174 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3175
3176 ra_tid = BUILD_RAxTID(sta_id, tid);
3177
3178 /* Modify device's station table to Tx this TID */
3179 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
3180
3181 spin_lock_irqsave(&priv->lock, flags);
3182 rc = iwl_grab_nic_access(priv);
3183 if (rc) {
3184 spin_unlock_irqrestore(&priv->lock, flags);
3185 return rc;
3186 }
3187
3188 /* Stop this Tx queue before configuring it */
3189 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3190
3191 /* Map receiver-address / traffic-ID to this queue */
3192 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3193
3194 /* Set this queue as a chain-building queue */
3195 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3196
3197 /* Place first TFD at index corresponding to start sequence number.
3198 * Assumes that ssn_idx is valid (!= 0xFFF) */
3199 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3200 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3201 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3202
3203 /* Set up Tx window size and frame limit for this queue */
3204 iwl_write_targ_mem(priv,
3205 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3206 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3207 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3208
3209 iwl_write_targ_mem(priv, priv->scd_base_addr +
3210 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3211 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3212 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3213
3214 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3215
3216 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
3217 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3218
3219 iwl_release_nic_access(priv);
3220 spin_unlock_irqrestore(&priv->lock, flags);
3221
3222 return 0;
3223 }
3224
3225 #endif /* CONFIG_IWL4965_HT */
3226
3227
3228 #ifdef CONFIG_IWL4965_HT
3229 static int iwl4965_rx_agg_start(struct iwl_priv *priv,
3230 const u8 *addr, int tid, u16 ssn)
3231 {
3232 unsigned long flags;
3233 int sta_id;
3234
3235 sta_id = iwl_find_station(priv, addr);
3236 if (sta_id == IWL_INVALID_STATION)
3237 return -ENXIO;
3238
3239 spin_lock_irqsave(&priv->sta_lock, flags);
3240 priv->stations[sta_id].sta.station_flags_msk = 0;
3241 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3242 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
3243 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3244 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3245 spin_unlock_irqrestore(&priv->sta_lock, flags);
3246
3247 return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
3248 CMD_ASYNC);
3249 }
3250
3251 static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
3252 const u8 *addr, int tid)
3253 {
3254 unsigned long flags;
3255 int sta_id;
3256
3257 sta_id = iwl_find_station(priv, addr);
3258 if (sta_id == IWL_INVALID_STATION)
3259 return -ENXIO;
3260
3261 spin_lock_irqsave(&priv->sta_lock, flags);
3262 priv->stations[sta_id].sta.station_flags_msk = 0;
3263 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3264 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
3265 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3266 spin_unlock_irqrestore(&priv->sta_lock, flags);
3267
3268 return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
3269 CMD_ASYNC);
3270 }
3271
3272 /*
3273 * Find first available (lowest unused) Tx Queue, mark it "active".
3274 * Called only when finding queue for aggregation.
3275 * Should never return anything < 7, because they should already
3276 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
3277 */
3278 static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
3279 {
3280 int txq_id;
3281
3282 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
3283 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
3284 return txq_id;
3285 return -1;
3286 }
3287
3288 static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
3289 u16 tid, u16 *start_seq_num)
3290 {
3291 struct iwl_priv *priv = hw->priv;
3292 int sta_id;
3293 int tx_fifo;
3294 int txq_id;
3295 int ssn = -1;
3296 int ret = 0;
3297 unsigned long flags;
3298 struct iwl_tid_data *tid_data;
3299 DECLARE_MAC_BUF(mac);
3300
3301 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
3302 tx_fifo = default_tid_to_tx_fifo[tid];
3303 else
3304 return -EINVAL;
3305
3306 IWL_WARNING("%s on ra = %s tid = %d\n",
3307 __func__, print_mac(mac, ra), tid);
3308
3309 sta_id = iwl_find_station(priv, ra);
3310 if (sta_id == IWL_INVALID_STATION)
3311 return -ENXIO;
3312
3313 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
3314 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
3315 return -ENXIO;
3316 }
3317
3318 txq_id = iwl4965_txq_ctx_activate_free(priv);
3319 if (txq_id == -1)
3320 return -ENXIO;
3321
3322 spin_lock_irqsave(&priv->sta_lock, flags);
3323 tid_data = &priv->stations[sta_id].tid[tid];
3324 ssn = SEQ_TO_SN(tid_data->seq_number);
3325 tid_data->agg.txq_id = txq_id;
3326 spin_unlock_irqrestore(&priv->sta_lock, flags);
3327
3328 *start_seq_num = ssn;
3329 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
3330 sta_id, tid, ssn);
3331 if (ret)
3332 return ret;
3333
3334 ret = 0;
3335 if (tid_data->tfds_in_queue == 0) {
3336 printk(KERN_ERR "HW queue is empty\n");
3337 tid_data->agg.state = IWL_AGG_ON;
3338 ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
3339 } else {
3340 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
3341 tid_data->tfds_in_queue);
3342 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
3343 }
3344 return ret;
3345 }
3346
3347 static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
3348 {
3349 struct iwl_priv *priv = hw->priv;
3350 int tx_fifo_id, txq_id, sta_id, ssn = -1;
3351 struct iwl_tid_data *tid_data;
3352 int ret, write_ptr, read_ptr;
3353 unsigned long flags;
3354 DECLARE_MAC_BUF(mac);
3355
3356 if (!ra) {
3357 IWL_ERROR("ra = NULL\n");
3358 return -EINVAL;
3359 }
3360
3361 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
3362 tx_fifo_id = default_tid_to_tx_fifo[tid];
3363 else
3364 return -EINVAL;
3365
3366 sta_id = iwl_find_station(priv, ra);
3367
3368 if (sta_id == IWL_INVALID_STATION)
3369 return -ENXIO;
3370
3371 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
3372 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
3373
3374 tid_data = &priv->stations[sta_id].tid[tid];
3375 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
3376 txq_id = tid_data->agg.txq_id;
3377 write_ptr = priv->txq[txq_id].q.write_ptr;
3378 read_ptr = priv->txq[txq_id].q.read_ptr;
3379
3380 /* The queue is not empty */
3381 if (write_ptr != read_ptr) {
3382 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
3383 priv->stations[sta_id].tid[tid].agg.state =
3384 IWL_EMPTYING_HW_QUEUE_DELBA;
3385 return 0;
3386 }
3387
3388 IWL_DEBUG_HT("HW queue is empty\n");
3389 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
3390
3391 spin_lock_irqsave(&priv->lock, flags);
3392 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
3393 spin_unlock_irqrestore(&priv->lock, flags);
3394
3395 if (ret)
3396 return ret;
3397
3398 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
3399
3400 return 0;
3401 }
3402
3403 int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
3404 enum ieee80211_ampdu_mlme_action action,
3405 const u8 *addr, u16 tid, u16 *ssn)
3406 {
3407 struct iwl_priv *priv = hw->priv;
3408 DECLARE_MAC_BUF(mac);
3409
3410 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
3411 print_mac(mac, addr), tid);
3412
3413 switch (action) {
3414 case IEEE80211_AMPDU_RX_START:
3415 IWL_DEBUG_HT("start Rx\n");
3416 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
3417 case IEEE80211_AMPDU_RX_STOP:
3418 IWL_DEBUG_HT("stop Rx\n");
3419 return iwl4965_rx_agg_stop(priv, addr, tid);
3420 case IEEE80211_AMPDU_TX_START:
3421 IWL_DEBUG_HT("start Tx\n");
3422 return iwl4965_tx_agg_start(hw, addr, tid, ssn);
3423 case IEEE80211_AMPDU_TX_STOP:
3424 IWL_DEBUG_HT("stop Tx\n");
3425 return iwl4965_tx_agg_stop(hw, addr, tid);
3426 default:
3427 IWL_DEBUG_HT("unknown\n");
3428 return -EINVAL;
3429 break;
3430 }
3431 return 0;
3432 }
3433 #endif /* CONFIG_IWL4965_HT */
3434
3435
3436 static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
3437 {
3438 switch (cmd_id) {
3439 case REPLY_RXON:
3440 return (u16) sizeof(struct iwl4965_rxon_cmd);
3441 default:
3442 return len;
3443 }
3444 }
3445
3446 static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
3447 {
3448 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
3449 addsta->mode = cmd->mode;
3450 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
3451 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
3452 addsta->station_flags = cmd->station_flags;
3453 addsta->station_flags_msk = cmd->station_flags_msk;
3454 addsta->tid_disable_tx = cmd->tid_disable_tx;
3455 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
3456 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
3457 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
3458 addsta->reserved1 = __constant_cpu_to_le16(0);
3459 addsta->reserved2 = __constant_cpu_to_le32(0);
3460
3461 return (u16)sizeof(struct iwl4965_addsta_cmd);
3462 }
3463
3464 #ifdef CONFIG_IWL4965_HT
3465 static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
3466 {
3467 __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status +
3468 tx_resp->frame_count);
3469 return le32_to_cpu(*scd_ssn) & MAX_SN;
3470
3471 }
3472
3473 /**
3474 * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
3475 */
3476 static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
3477 struct iwl_ht_agg *agg,
3478 struct iwl4965_tx_resp_agg *tx_resp,
3479 u16 start_idx)
3480 {
3481 u16 status;
3482 struct agg_tx_status *frame_status = &tx_resp->status;
3483 struct ieee80211_tx_info *info = NULL;
3484 struct ieee80211_hdr *hdr = NULL;
3485 int i, sh;
3486 int txq_id, idx;
3487 u16 seq;
3488
3489 if (agg->wait_for_ba)
3490 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
3491
3492 agg->frame_count = tx_resp->frame_count;
3493 agg->start_idx = start_idx;
3494 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
3495 agg->bitmap = 0;
3496
3497 /* # frames attempted by Tx command */
3498 if (agg->frame_count == 1) {
3499 /* Only one frame was attempted; no block-ack will arrive */
3500 status = le16_to_cpu(frame_status[0].status);
3501 seq = le16_to_cpu(frame_status[0].sequence);
3502 idx = SEQ_TO_INDEX(seq);
3503 txq_id = SEQ_TO_QUEUE(seq);
3504
3505 /* FIXME: code repetition */
3506 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
3507 agg->frame_count, agg->start_idx, idx);
3508
3509 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
3510 info->status.retry_count = tx_resp->failure_frame;
3511 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
3512 info->flags |= iwl_is_tx_success(status)?
3513 IEEE80211_TX_STAT_ACK : 0;
3514 iwl4965_hwrate_to_tx_control(priv,
3515 le32_to_cpu(tx_resp->rate_n_flags),
3516 info);
3517 /* FIXME: code repetition end */
3518
3519 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
3520 status & 0xff, tx_resp->failure_frame);
3521 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
3522 iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
3523
3524 agg->wait_for_ba = 0;
3525 } else {
3526 /* Two or more frames were attempted; expect block-ack */
3527 u64 bitmap = 0;
3528 int start = agg->start_idx;
3529
3530 /* Construct bit-map of pending frames within Tx window */
3531 for (i = 0; i < agg->frame_count; i++) {
3532 u16 sc;
3533 status = le16_to_cpu(frame_status[i].status);
3534 seq = le16_to_cpu(frame_status[i].sequence);
3535 idx = SEQ_TO_INDEX(seq);
3536 txq_id = SEQ_TO_QUEUE(seq);
3537
3538 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
3539 AGG_TX_STATE_ABORT_MSK))
3540 continue;
3541
3542 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
3543 agg->frame_count, txq_id, idx);
3544
3545 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
3546
3547 sc = le16_to_cpu(hdr->seq_ctrl);
3548 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
3549 IWL_ERROR("BUG_ON idx doesn't match seq control"
3550 " idx=%d, seq_idx=%d, seq=%d\n",
3551 idx, SEQ_TO_SN(sc),
3552 hdr->seq_ctrl);
3553 return -1;
3554 }
3555
3556 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
3557 i, idx, SEQ_TO_SN(sc));
3558
3559 sh = idx - start;
3560 if (sh > 64) {
3561 sh = (start - idx) + 0xff;
3562 bitmap = bitmap << sh;
3563 sh = 0;
3564 start = idx;
3565 } else if (sh < -64)
3566 sh = 0xff - (start - idx);
3567 else if (sh < 0) {
3568 sh = start - idx;
3569 start = idx;
3570 bitmap = bitmap << sh;
3571 sh = 0;
3572 }
3573 bitmap |= (1 << sh);
3574 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
3575 start, (u32)(bitmap & 0xFFFFFFFF));
3576 }
3577
3578 agg->bitmap = bitmap;
3579 agg->start_idx = start;
3580 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
3581 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
3582 agg->frame_count, agg->start_idx,
3583 (unsigned long long)agg->bitmap);
3584
3585 if (bitmap)
3586 agg->wait_for_ba = 1;
3587 }
3588 return 0;
3589 }
3590 #endif
3591
3592 /**
3593 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
3594 */
3595 static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
3596 struct iwl_rx_mem_buffer *rxb)
3597 {
3598 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3599 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3600 int txq_id = SEQ_TO_QUEUE(sequence);
3601 int index = SEQ_TO_INDEX(sequence);
3602 struct iwl_tx_queue *txq = &priv->txq[txq_id];
3603 struct ieee80211_tx_info *info;
3604 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
3605 u32 status = le32_to_cpu(tx_resp->status);
3606 #ifdef CONFIG_IWL4965_HT
3607 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
3608 u16 fc;
3609 struct ieee80211_hdr *hdr;
3610 u8 *qc = NULL;
3611 #endif
3612
3613 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
3614 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
3615 "is out of range [0-%d] %d %d\n", txq_id,
3616 index, txq->q.n_bd, txq->q.write_ptr,
3617 txq->q.read_ptr);
3618 return;
3619 }
3620
3621 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
3622 memset(&info->status, 0, sizeof(info->status));
3623
3624 #ifdef CONFIG_IWL4965_HT
3625 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
3626 fc = le16_to_cpu(hdr->frame_control);
3627 if (ieee80211_is_qos_data(fc)) {
3628 qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
3629 tid = qc[0] & 0xf;
3630 }
3631
3632 sta_id = iwl_get_ra_sta_id(priv, hdr);
3633 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
3634 IWL_ERROR("Station not known\n");
3635 return;
3636 }
3637
3638 if (txq->sched_retry) {
3639 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
3640 struct iwl_ht_agg *agg = NULL;
3641
3642 if (!qc)
3643 return;
3644
3645 agg = &priv->stations[sta_id].tid[tid].agg;
3646
3647 iwl4965_tx_status_reply_tx(priv, agg,
3648 (struct iwl4965_tx_resp_agg *)tx_resp, index);
3649
3650 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) {
3651 /* TODO: send BAR */
3652 }
3653
3654 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
3655 int freed, ampdu_q;
3656 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
3657 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
3658 "%d index %d\n", scd_ssn , index);
3659 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
3660 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3661
3662 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
3663 txq_id >= 0 && priv->mac80211_registered &&
3664 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
3665 /* calculate mac80211 ampdu sw queue to wake */
3666 ampdu_q = txq_id - IWL_BACK_QUEUE_FIRST_ID +
3667 priv->hw->queues;
3668 if (agg->state == IWL_AGG_OFF)
3669 ieee80211_wake_queue(priv->hw, txq_id);
3670 else
3671 ieee80211_wake_queue(priv->hw, ampdu_q);
3672 }
3673 iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id);
3674 }
3675 } else {
3676 #endif /* CONFIG_IWL4965_HT */
3677
3678 info->status.retry_count = tx_resp->failure_frame;
3679 info->flags |= iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
3680 iwl4965_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
3681 info);
3682
3683 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x "
3684 "retries %d\n", txq_id, iwl_get_tx_fail_reason(status),
3685 status, le32_to_cpu(tx_resp->rate_n_flags),
3686 tx_resp->failure_frame);
3687
3688 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
3689 #ifdef CONFIG_IWL4965_HT
3690 if (index != -1) {
3691 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
3692 if (tid != MAX_TID_COUNT)
3693 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3694 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
3695 (txq_id >= 0) && priv->mac80211_registered)
3696 ieee80211_wake_queue(priv->hw, txq_id);
3697 if (tid != MAX_TID_COUNT)
3698 iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id);
3699 }
3700 }
3701 #endif /* CONFIG_IWL4965_HT */
3702
3703 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3704 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3705 }
3706
3707
3708 /* Set up 4965-specific Rx frame reply handlers */
3709 static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
3710 {
3711 /* Legacy Rx frames */
3712 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
3713
3714 /* High-throughput (HT) Rx frames */
3715 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
3716 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
3717
3718 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
3719
3720 #ifdef CONFIG_IWL4965_HT
3721 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
3722 #endif /* CONFIG_IWL4965_HT */
3723 }
3724
3725 void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
3726 {
3727 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
3728 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
3729 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
3730 #endif
3731 init_timer(&priv->statistics_periodic);
3732 priv->statistics_periodic.data = (unsigned long)priv;
3733 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
3734 }
3735
3736 void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
3737 {
3738 del_timer_sync(&priv->statistics_periodic);
3739
3740 cancel_delayed_work(&priv->init_alive_start);
3741 }
3742
3743
3744 static struct iwl_hcmd_ops iwl4965_hcmd = {
3745 .rxon_assoc = iwl4965_send_rxon_assoc,
3746 };
3747
3748 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
3749 .get_hcmd_size = iwl4965_get_hcmd_size,
3750 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
3751 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
3752 .chain_noise_reset = iwl4965_chain_noise_reset,
3753 .gain_computation = iwl4965_gain_computation,
3754 #endif
3755 };
3756
3757 static struct iwl_lib_ops iwl4965_lib = {
3758 .set_hw_params = iwl4965_hw_set_hw_params,
3759 .alloc_shared_mem = iwl4965_alloc_shared_mem,
3760 .free_shared_mem = iwl4965_free_shared_mem,
3761 .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
3762 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
3763 .txq_set_sched = iwl4965_txq_set_sched,
3764 .rx_handler_setup = iwl4965_rx_handler_setup,
3765 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
3766 .alive_notify = iwl4965_alive_notify,
3767 .init_alive_start = iwl4965_init_alive_start,
3768 .load_ucode = iwl4965_load_bsm,
3769 .apm_ops = {
3770 .init = iwl4965_apm_init,
3771 .reset = iwl4965_apm_reset,
3772 .stop = iwl4965_apm_stop,
3773 .config = iwl4965_nic_config,
3774 .set_pwr_src = iwl4965_set_pwr_src,
3775 },
3776 .eeprom_ops = {
3777 .regulatory_bands = {
3778 EEPROM_REGULATORY_BAND_1_CHANNELS,
3779 EEPROM_REGULATORY_BAND_2_CHANNELS,
3780 EEPROM_REGULATORY_BAND_3_CHANNELS,
3781 EEPROM_REGULATORY_BAND_4_CHANNELS,
3782 EEPROM_REGULATORY_BAND_5_CHANNELS,
3783 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
3784 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
3785 },
3786 .verify_signature = iwlcore_eeprom_verify_signature,
3787 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
3788 .release_semaphore = iwlcore_eeprom_release_semaphore,
3789 .check_version = iwl4965_eeprom_check_version,
3790 .query_addr = iwlcore_eeprom_query_addr,
3791 },
3792 .radio_kill_sw = iwl4965_radio_kill_sw,
3793 .set_power = iwl4965_set_power,
3794 .update_chain_flags = iwl4965_update_chain_flags,
3795 };
3796
3797 static struct iwl_ops iwl4965_ops = {
3798 .lib = &iwl4965_lib,
3799 .hcmd = &iwl4965_hcmd,
3800 .utils = &iwl4965_hcmd_utils,
3801 };
3802
3803 struct iwl_cfg iwl4965_agn_cfg = {
3804 .name = "4965AGN",
3805 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
3806 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
3807 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
3808 .ops = &iwl4965_ops,
3809 .mod_params = &iwl4965_mod_params,
3810 };
3811
3812 module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
3813 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
3814 module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
3815 MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
3816 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
3817 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
3818 module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
3819 MODULE_PARM_DESC(debug, "debug output mask");
3820 module_param_named(
3821 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
3822 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
3823
3824 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
3825 MODULE_PARM_DESC(queues_num, "number of hw queues.");
3826
3827 /* QoS */
3828 module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
3829 MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
3830 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
3831 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
3832 module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
3833 MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
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