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iwlwifi: TX setup fix confusion between TX queue and TX DMA channel
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
38
39 #include "iwl-eeprom.h"
40 #include "iwl-dev.h"
41 #include "iwl-core.h"
42 #include "iwl-io.h"
43 #include "iwl-sta.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
46
47 #define IWL5000_UCODE_API "-1"
48
49 #define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode"
50
51 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
52 IWL_TX_FIFO_AC3,
53 IWL_TX_FIFO_AC2,
54 IWL_TX_FIFO_AC1,
55 IWL_TX_FIFO_AC0,
56 IWL50_CMD_FIFO_NUM,
57 IWL_TX_FIFO_HCCA_1,
58 IWL_TX_FIFO_HCCA_2
59 };
60
61 /* FIXME: same implementation as 4965 */
62 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
63 {
64 int ret = 0;
65 unsigned long flags;
66
67 spin_lock_irqsave(&priv->lock, flags);
68
69 /* set stop master bit */
70 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
71
72 ret = iwl_poll_bit(priv, CSR_RESET,
73 CSR_RESET_REG_FLAG_MASTER_DISABLED,
74 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
75 if (ret < 0)
76 goto out;
77
78 out:
79 spin_unlock_irqrestore(&priv->lock, flags);
80 IWL_DEBUG_INFO("stop master\n");
81
82 return ret;
83 }
84
85
86 static int iwl5000_apm_init(struct iwl_priv *priv)
87 {
88 int ret = 0;
89
90 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
92
93 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
94 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
95 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
96
97 /* Set FH wait threshold to maximum (HW error during stress W/A) */
98 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
99
100 /* enable HAP INTA to move device L1a -> L0s */
101 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
102 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
103
104 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
105
106 /* set "initialization complete" bit to move adapter
107 * D0U* --> D0A* state */
108 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
109
110 /* wait for clock stabilization */
111 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
113 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
114 if (ret < 0) {
115 IWL_DEBUG_INFO("Failed to init the card\n");
116 return ret;
117 }
118
119 ret = iwl_grab_nic_access(priv);
120 if (ret)
121 return ret;
122
123 /* enable DMA */
124 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
125
126 udelay(20);
127
128 /* disable L1-Active */
129 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
130 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
131
132 iwl_release_nic_access(priv);
133
134 return ret;
135 }
136
137 /* FIXME: this is identical to 4965 */
138 static void iwl5000_apm_stop(struct iwl_priv *priv)
139 {
140 unsigned long flags;
141
142 iwl5000_apm_stop_master(priv);
143
144 spin_lock_irqsave(&priv->lock, flags);
145
146 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
147
148 udelay(10);
149
150 /* clear "init complete" move adapter D0A* --> D0U state */
151 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
152
153 spin_unlock_irqrestore(&priv->lock, flags);
154 }
155
156
157 static int iwl5000_apm_reset(struct iwl_priv *priv)
158 {
159 int ret = 0;
160 unsigned long flags;
161
162 iwl5000_apm_stop_master(priv);
163
164 spin_lock_irqsave(&priv->lock, flags);
165
166 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
167
168 udelay(10);
169
170
171 /* FIXME: put here L1A -L0S w/a */
172
173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
174
175 /* set "initialization complete" bit to move adapter
176 * D0U* --> D0A* state */
177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
178
179 /* wait for clock stabilization */
180 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
182 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
183 if (ret < 0) {
184 IWL_DEBUG_INFO("Failed to init the card\n");
185 goto out;
186 }
187
188 ret = iwl_grab_nic_access(priv);
189 if (ret)
190 goto out;
191
192 /* enable DMA */
193 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
194
195 udelay(20);
196
197 /* disable L1-Active */
198 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
199 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
200
201 iwl_release_nic_access(priv);
202
203 out:
204 spin_unlock_irqrestore(&priv->lock, flags);
205
206 return ret;
207 }
208
209
210 static void iwl5000_nic_config(struct iwl_priv *priv)
211 {
212 unsigned long flags;
213 u16 radio_cfg;
214 u16 link;
215
216 spin_lock_irqsave(&priv->lock, flags);
217
218 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
219
220 /* L1 is enabled by BIOS */
221 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
222 /* disable L0S disabled L1A enabled */
223 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
224 else
225 /* L0S enabled L1A disabled */
226 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
227
228 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
229
230 /* write radio config values to register */
231 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
232 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
233 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
234 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
235 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
236
237 /* set CSR_HW_CONFIG_REG for uCode use */
238 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
239 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
240 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
241
242 /* W/A : NIC is stuck in a reset state after Early PCIe power off
243 * (PCIe power is lost before PERST# is asserted),
244 * causing ME FW to lose ownership and not being able to obtain it back.
245 */
246 iwl_grab_nic_access(priv);
247 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
248 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
249 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
250 iwl_release_nic_access(priv);
251
252 spin_unlock_irqrestore(&priv->lock, flags);
253 }
254
255
256
257 /*
258 * EEPROM
259 */
260 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
261 {
262 u16 offset = 0;
263
264 if ((address & INDIRECT_ADDRESS) == 0)
265 return address;
266
267 switch (address & INDIRECT_TYPE_MSK) {
268 case INDIRECT_HOST:
269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
270 break;
271 case INDIRECT_GENERAL:
272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
273 break;
274 case INDIRECT_REGULATORY:
275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
276 break;
277 case INDIRECT_CALIBRATION:
278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
279 break;
280 case INDIRECT_PROCESS_ADJST:
281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
282 break;
283 case INDIRECT_OTHERS:
284 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
285 break;
286 default:
287 IWL_ERROR("illegal indirect type: 0x%X\n",
288 address & INDIRECT_TYPE_MSK);
289 break;
290 }
291
292 /* translate the offset from words to byte */
293 return (address & ADDRESS_MSK) + (offset << 1);
294 }
295
296 static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
297 {
298 struct iwl_eeprom_calib_hdr {
299 u8 version;
300 u8 pa_type;
301 u16 voltage;
302 } *hdr;
303
304 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
305 EEPROM_5000_CALIB_ALL);
306 return hdr->version;
307
308 }
309
310 static void iwl5000_gain_computation(struct iwl_priv *priv,
311 u32 average_noise[NUM_RX_CHAINS],
312 u16 min_average_noise_antenna_i,
313 u32 min_average_noise)
314 {
315 int i;
316 s32 delta_g;
317 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
318
319 /* Find Gain Code for the antennas B and C */
320 for (i = 1; i < NUM_RX_CHAINS; i++) {
321 if ((data->disconn_array[i])) {
322 data->delta_gain_code[i] = 0;
323 continue;
324 }
325 delta_g = (1000 * ((s32)average_noise[0] -
326 (s32)average_noise[i])) / 1500;
327 /* bound gain by 2 bits value max, 3rd bit is sign */
328 data->delta_gain_code[i] =
329 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
330
331 if (delta_g < 0)
332 /* set negative sign */
333 data->delta_gain_code[i] |= (1 << 2);
334 }
335
336 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
337 data->delta_gain_code[1], data->delta_gain_code[2]);
338
339 if (!data->radio_write) {
340 struct iwl_calib_chain_noise_gain_cmd cmd;
341 memset(&cmd, 0, sizeof(cmd));
342
343 cmd.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
344 cmd.delta_gain_1 = data->delta_gain_code[1];
345 cmd.delta_gain_2 = data->delta_gain_code[2];
346 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
347 sizeof(cmd), &cmd, NULL);
348
349 data->radio_write = 1;
350 data->state = IWL_CHAIN_NOISE_CALIBRATED;
351 }
352
353 data->chain_noise_a = 0;
354 data->chain_noise_b = 0;
355 data->chain_noise_c = 0;
356 data->chain_signal_a = 0;
357 data->chain_signal_b = 0;
358 data->chain_signal_c = 0;
359 data->beacon_count = 0;
360 }
361
362 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
363 {
364 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
365
366 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
367 struct iwl_calib_chain_noise_reset_cmd cmd;
368
369 memset(&cmd, 0, sizeof(cmd));
370 cmd.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
371 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
372 sizeof(cmd), &cmd))
373 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
374 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
375 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
376 }
377 }
378
379 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
380 __le32 *tx_flags)
381 {
382 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
383 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
384 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
385 else
386 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
387 }
388
389 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
390 .min_nrg_cck = 95,
391 .max_nrg_cck = 0,
392 .auto_corr_min_ofdm = 90,
393 .auto_corr_min_ofdm_mrc = 170,
394 .auto_corr_min_ofdm_x1 = 120,
395 .auto_corr_min_ofdm_mrc_x1 = 240,
396
397 .auto_corr_max_ofdm = 120,
398 .auto_corr_max_ofdm_mrc = 210,
399 .auto_corr_max_ofdm_x1 = 155,
400 .auto_corr_max_ofdm_mrc_x1 = 290,
401
402 .auto_corr_min_cck = 125,
403 .auto_corr_max_cck = 200,
404 .auto_corr_min_cck_mrc = 170,
405 .auto_corr_max_cck_mrc = 400,
406 .nrg_th_cck = 95,
407 .nrg_th_ofdm = 95,
408 };
409
410 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
411 size_t offset)
412 {
413 u32 address = eeprom_indirect_address(priv, offset);
414 BUG_ON(address >= priv->cfg->eeprom_size);
415 return &priv->eeprom[address];
416 }
417
418 /*
419 * Calibration
420 */
421 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
422 {
423 u8 data[sizeof(struct iwl_calib_hdr) +
424 sizeof(struct iwl_cal_xtal_freq)];
425 struct iwl_calib_cmd *cmd = (struct iwl_calib_cmd *)data;
426 struct iwl_cal_xtal_freq *xtal = (struct iwl_cal_xtal_freq *)cmd->data;
427 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
428
429 cmd->hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
430 xtal->cap_pin1 = (u8)xtal_calib[0];
431 xtal->cap_pin2 = (u8)xtal_calib[1];
432 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
433 data, sizeof(data));
434 }
435
436 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
437 {
438 struct iwl_calib_cfg_cmd calib_cfg_cmd;
439 struct iwl_host_cmd cmd = {
440 .id = CALIBRATION_CFG_CMD,
441 .len = sizeof(struct iwl_calib_cfg_cmd),
442 .data = &calib_cfg_cmd,
443 };
444
445 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
446 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
447 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
448 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
449 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
450
451 return iwl_send_cmd(priv, &cmd);
452 }
453
454 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
455 struct iwl_rx_mem_buffer *rxb)
456 {
457 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
458 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
459 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
460 int index;
461
462 /* reduce the size of the length field itself */
463 len -= 4;
464
465 /* Define the order in which the results will be sent to the runtime
466 * uCode. iwl_send_calib_results sends them in a row according to their
467 * index. We sort them here */
468 switch (hdr->op_code) {
469 case IWL_PHY_CALIBRATE_LO_CMD:
470 index = IWL_CALIB_LO;
471 break;
472 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
473 index = IWL_CALIB_TX_IQ;
474 break;
475 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
476 index = IWL_CALIB_TX_IQ_PERD;
477 break;
478 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
479 index = IWL_CALIB_BASE_BAND;
480 break;
481 default:
482 IWL_ERROR("Unknown calibration notification %d\n",
483 hdr->op_code);
484 return;
485 }
486 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
487 }
488
489 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
490 struct iwl_rx_mem_buffer *rxb)
491 {
492 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
493 queue_work(priv->workqueue, &priv->restart);
494 }
495
496 /*
497 * ucode
498 */
499 static int iwl5000_load_section(struct iwl_priv *priv,
500 struct fw_desc *image,
501 u32 dst_addr)
502 {
503 int ret = 0;
504 unsigned long flags;
505
506 dma_addr_t phy_addr = image->p_addr;
507 u32 byte_cnt = image->len;
508
509 spin_lock_irqsave(&priv->lock, flags);
510 ret = iwl_grab_nic_access(priv);
511 if (ret) {
512 spin_unlock_irqrestore(&priv->lock, flags);
513 return ret;
514 }
515
516 iwl_write_direct32(priv,
517 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
518 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
519
520 iwl_write_direct32(priv,
521 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
522
523 iwl_write_direct32(priv,
524 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
525 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
526
527 iwl_write_direct32(priv,
528 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
529 (iwl_get_dma_hi_addr(phy_addr)
530 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
531
532 iwl_write_direct32(priv,
533 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
534 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
535 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
536 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
537
538 iwl_write_direct32(priv,
539 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
540 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
541 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
542 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
543
544 iwl_release_nic_access(priv);
545 spin_unlock_irqrestore(&priv->lock, flags);
546 return 0;
547 }
548
549 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
550 struct fw_desc *inst_image,
551 struct fw_desc *data_image)
552 {
553 int ret = 0;
554
555 ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND);
556 if (ret)
557 return ret;
558
559 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
560 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
561 priv->ucode_write_complete, 5 * HZ);
562 if (ret == -ERESTARTSYS) {
563 IWL_ERROR("Could not load the INST uCode section due "
564 "to interrupt\n");
565 return ret;
566 }
567 if (!ret) {
568 IWL_ERROR("Could not load the INST uCode section\n");
569 return -ETIMEDOUT;
570 }
571
572 priv->ucode_write_complete = 0;
573
574 ret = iwl5000_load_section(
575 priv, data_image, RTC_DATA_LOWER_BOUND);
576 if (ret)
577 return ret;
578
579 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
580
581 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
582 priv->ucode_write_complete, 5 * HZ);
583 if (ret == -ERESTARTSYS) {
584 IWL_ERROR("Could not load the INST uCode section due "
585 "to interrupt\n");
586 return ret;
587 } else if (!ret) {
588 IWL_ERROR("Could not load the DATA uCode section\n");
589 return -ETIMEDOUT;
590 } else
591 ret = 0;
592
593 priv->ucode_write_complete = 0;
594
595 return ret;
596 }
597
598 static int iwl5000_load_ucode(struct iwl_priv *priv)
599 {
600 int ret = 0;
601
602 /* check whether init ucode should be loaded, or rather runtime ucode */
603 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
604 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
605 ret = iwl5000_load_given_ucode(priv,
606 &priv->ucode_init, &priv->ucode_init_data);
607 if (!ret) {
608 IWL_DEBUG_INFO("Init ucode load complete.\n");
609 priv->ucode_type = UCODE_INIT;
610 }
611 } else {
612 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
613 "Loading runtime ucode...\n");
614 ret = iwl5000_load_given_ucode(priv,
615 &priv->ucode_code, &priv->ucode_data);
616 if (!ret) {
617 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
618 priv->ucode_type = UCODE_RT;
619 }
620 }
621
622 return ret;
623 }
624
625 static void iwl5000_init_alive_start(struct iwl_priv *priv)
626 {
627 int ret = 0;
628
629 /* Check alive response for "valid" sign from uCode */
630 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
631 /* We had an error bringing up the hardware, so take it
632 * all the way back down so we can try again */
633 IWL_DEBUG_INFO("Initialize Alive failed.\n");
634 goto restart;
635 }
636
637 /* initialize uCode was loaded... verify inst image.
638 * This is a paranoid check, because we would not have gotten the
639 * "initialize" alive if code weren't properly loaded. */
640 if (iwl_verify_ucode(priv)) {
641 /* Runtime instruction load was bad;
642 * take it all the way back down so we can try again */
643 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
644 goto restart;
645 }
646
647 iwl_clear_stations_table(priv);
648 ret = priv->cfg->ops->lib->alive_notify(priv);
649 if (ret) {
650 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
651 goto restart;
652 }
653
654 iwl5000_send_calib_cfg(priv);
655 return;
656
657 restart:
658 /* real restart (first load init_ucode) */
659 queue_work(priv->workqueue, &priv->restart);
660 }
661
662 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
663 int txq_id, u32 index)
664 {
665 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
666 (index & 0xff) | (txq_id << 8));
667 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
668 }
669
670 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
671 struct iwl_tx_queue *txq,
672 int tx_fifo_id, int scd_retry)
673 {
674 int txq_id = txq->q.id;
675 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
676
677 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
678 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
679 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
680 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
681 IWL50_SCD_QUEUE_STTS_REG_MSK);
682
683 txq->sched_retry = scd_retry;
684
685 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
686 active ? "Activate" : "Deactivate",
687 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
688 }
689
690 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
691 {
692 struct iwl_wimax_coex_cmd coex_cmd;
693
694 memset(&coex_cmd, 0, sizeof(coex_cmd));
695
696 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
697 sizeof(coex_cmd), &coex_cmd);
698 }
699
700 static int iwl5000_alive_notify(struct iwl_priv *priv)
701 {
702 u32 a;
703 unsigned long flags;
704 int ret;
705 int i, chan;
706
707 spin_lock_irqsave(&priv->lock, flags);
708
709 ret = iwl_grab_nic_access(priv);
710 if (ret) {
711 spin_unlock_irqrestore(&priv->lock, flags);
712 return ret;
713 }
714
715 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
716 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
717 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
718 a += 4)
719 iwl_write_targ_mem(priv, a, 0);
720 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
721 a += 4)
722 iwl_write_targ_mem(priv, a, 0);
723 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
724 iwl_write_targ_mem(priv, a, 0);
725
726 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
727 priv->scd_bc_tbls.dma >> 10);
728
729 /* Enable DMA channel */
730 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
731 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
732 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
733 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
734
735 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
736 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
737 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
738
739 /* initiate the queues */
740 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
741 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
742 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
743 iwl_write_targ_mem(priv, priv->scd_base_addr +
744 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
745 iwl_write_targ_mem(priv, priv->scd_base_addr +
746 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
747 sizeof(u32),
748 ((SCD_WIN_SIZE <<
749 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
750 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
751 ((SCD_FRAME_LIMIT <<
752 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
753 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
754 }
755
756 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
757 IWL_MASK(0, priv->hw_params.max_txq_num));
758
759 /* Activate all Tx DMA/FIFO channels */
760 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
761
762 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
763
764 /* map qos queues to fifos one-to-one */
765 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
766 int ac = iwl5000_default_queue_to_tx_fifo[i];
767 iwl_txq_ctx_activate(priv, i);
768 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
769 }
770 /* TODO - need to initialize those FIFOs inside the loop above,
771 * not only mark them as active */
772 iwl_txq_ctx_activate(priv, 4);
773 iwl_txq_ctx_activate(priv, 7);
774 iwl_txq_ctx_activate(priv, 8);
775 iwl_txq_ctx_activate(priv, 9);
776
777 iwl_release_nic_access(priv);
778 spin_unlock_irqrestore(&priv->lock, flags);
779
780
781 iwl5000_send_wimax_coex(priv);
782
783 iwl5000_set_Xtal_calib(priv);
784 iwl_send_calib_results(priv);
785
786 return 0;
787 }
788
789 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
790 {
791 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
792 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
793 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
794 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
795 return -EINVAL;
796 }
797
798 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
799 priv->hw_params.scd_bc_tbls_size =
800 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
801 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
802 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
803 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
804 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
805 priv->hw_params.max_bsm_size = 0;
806 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
807 BIT(IEEE80211_BAND_5GHZ);
808 priv->hw_params.sens = &iwl5000_sensitivity;
809
810 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
811 case CSR_HW_REV_TYPE_5100:
812 priv->hw_params.tx_chains_num = 1;
813 priv->hw_params.rx_chains_num = 2;
814 priv->hw_params.valid_tx_ant = ANT_B;
815 priv->hw_params.valid_rx_ant = ANT_AB;
816 break;
817 case CSR_HW_REV_TYPE_5150:
818 priv->hw_params.tx_chains_num = 1;
819 priv->hw_params.rx_chains_num = 2;
820 priv->hw_params.valid_tx_ant = ANT_A;
821 priv->hw_params.valid_rx_ant = ANT_AB;
822 break;
823 case CSR_HW_REV_TYPE_5300:
824 case CSR_HW_REV_TYPE_5350:
825 priv->hw_params.tx_chains_num = 3;
826 priv->hw_params.rx_chains_num = 3;
827 priv->hw_params.valid_tx_ant = ANT_ABC;
828 priv->hw_params.valid_rx_ant = ANT_ABC;
829 break;
830 }
831
832 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
833 case CSR_HW_REV_TYPE_5100:
834 case CSR_HW_REV_TYPE_5300:
835 case CSR_HW_REV_TYPE_5350:
836 /* 5X00 and 5350 wants in Celsius */
837 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
838 break;
839 case CSR_HW_REV_TYPE_5150:
840 /* 5150 wants in Kelvin */
841 priv->hw_params.ct_kill_threshold =
842 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
843 break;
844 }
845
846 /* Set initial calibration set */
847 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
848 case CSR_HW_REV_TYPE_5100:
849 case CSR_HW_REV_TYPE_5300:
850 case CSR_HW_REV_TYPE_5350:
851 priv->hw_params.calib_init_cfg =
852 BIT(IWL_CALIB_XTAL) |
853 BIT(IWL_CALIB_LO) |
854 BIT(IWL_CALIB_TX_IQ) |
855 BIT(IWL_CALIB_TX_IQ_PERD) |
856 BIT(IWL_CALIB_BASE_BAND);
857 break;
858 case CSR_HW_REV_TYPE_5150:
859 priv->hw_params.calib_init_cfg = 0;
860 break;
861 }
862
863
864 return 0;
865 }
866
867 /**
868 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
869 */
870 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
871 struct iwl_tx_queue *txq,
872 u16 byte_cnt)
873 {
874 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
875 int write_ptr = txq->q.write_ptr;
876 int txq_id = txq->q.id;
877 u8 sec_ctl = 0;
878 u8 sta_id = 0;
879 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
880 __le16 bc_ent;
881
882 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
883
884 if (txq_id != IWL_CMD_QUEUE_NUM) {
885 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
886 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
887
888 switch (sec_ctl & TX_CMD_SEC_MSK) {
889 case TX_CMD_SEC_CCM:
890 len += CCMP_MIC_LEN;
891 break;
892 case TX_CMD_SEC_TKIP:
893 len += TKIP_ICV_LEN;
894 break;
895 case TX_CMD_SEC_WEP:
896 len += WEP_IV_LEN + WEP_ICV_LEN;
897 break;
898 }
899 }
900
901 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
902
903 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
904
905 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
906 scd_bc_tbl[txq_id].
907 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
908 }
909
910 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
911 struct iwl_tx_queue *txq)
912 {
913 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
914 int txq_id = txq->q.id;
915 int read_ptr = txq->q.read_ptr;
916 u8 sta_id = 0;
917 __le16 bc_ent;
918
919 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
920
921 if (txq_id != IWL_CMD_QUEUE_NUM)
922 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
923
924 bc_ent = cpu_to_le16(1 | (sta_id << 12));
925 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
926
927 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
928 scd_bc_tbl[txq_id].
929 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
930 }
931
932 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
933 u16 txq_id)
934 {
935 u32 tbl_dw_addr;
936 u32 tbl_dw;
937 u16 scd_q2ratid;
938
939 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
940
941 tbl_dw_addr = priv->scd_base_addr +
942 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
943
944 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
945
946 if (txq_id & 0x1)
947 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
948 else
949 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
950
951 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
952
953 return 0;
954 }
955 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
956 {
957 /* Simply stop the queue, but don't change any configuration;
958 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
959 iwl_write_prph(priv,
960 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
961 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
962 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
963 }
964
965 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
966 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
967 {
968 unsigned long flags;
969 int ret;
970 u16 ra_tid;
971
972 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
973 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
974 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
975 txq_id, IWL50_FIRST_AMPDU_QUEUE,
976 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
977 return -EINVAL;
978 }
979
980 ra_tid = BUILD_RAxTID(sta_id, tid);
981
982 /* Modify device's station table to Tx this TID */
983 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
984
985 spin_lock_irqsave(&priv->lock, flags);
986 ret = iwl_grab_nic_access(priv);
987 if (ret) {
988 spin_unlock_irqrestore(&priv->lock, flags);
989 return ret;
990 }
991
992 /* Stop this Tx queue before configuring it */
993 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
994
995 /* Map receiver-address / traffic-ID to this queue */
996 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
997
998 /* Set this queue as a chain-building queue */
999 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1000
1001 /* enable aggregations for the queue */
1002 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1003
1004 /* Place first TFD at index corresponding to start sequence number.
1005 * Assumes that ssn_idx is valid (!= 0xFFF) */
1006 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1007 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1008 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1009
1010 /* Set up Tx window size and frame limit for this queue */
1011 iwl_write_targ_mem(priv, priv->scd_base_addr +
1012 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1013 sizeof(u32),
1014 ((SCD_WIN_SIZE <<
1015 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1016 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1017 ((SCD_FRAME_LIMIT <<
1018 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1019 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1020
1021 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1022
1023 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1024 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1025
1026 iwl_release_nic_access(priv);
1027 spin_unlock_irqrestore(&priv->lock, flags);
1028
1029 return 0;
1030 }
1031
1032 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1033 u16 ssn_idx, u8 tx_fifo)
1034 {
1035 int ret;
1036
1037 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1038 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1039 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1040 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1041 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1042 return -EINVAL;
1043 }
1044
1045 ret = iwl_grab_nic_access(priv);
1046 if (ret)
1047 return ret;
1048
1049 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1050
1051 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1052
1053 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1054 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1055 /* supposes that ssn_idx is valid (!= 0xFFF) */
1056 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1057
1058 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1059 iwl_txq_ctx_deactivate(priv, txq_id);
1060 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1061
1062 iwl_release_nic_access(priv);
1063
1064 return 0;
1065 }
1066
1067 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1068 {
1069 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1070 memcpy(data, cmd, size);
1071 return size;
1072 }
1073
1074
1075 /*
1076 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1077 * must be called under priv->lock and mac access
1078 */
1079 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1080 {
1081 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1082 }
1083
1084
1085 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1086 {
1087 return le32_to_cpup((__le32 *)&tx_resp->status +
1088 tx_resp->frame_count) & MAX_SN;
1089 }
1090
1091 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1092 struct iwl_ht_agg *agg,
1093 struct iwl5000_tx_resp *tx_resp,
1094 int txq_id, u16 start_idx)
1095 {
1096 u16 status;
1097 struct agg_tx_status *frame_status = &tx_resp->status;
1098 struct ieee80211_tx_info *info = NULL;
1099 struct ieee80211_hdr *hdr = NULL;
1100 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1101 int i, sh, idx;
1102 u16 seq;
1103
1104 if (agg->wait_for_ba)
1105 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1106
1107 agg->frame_count = tx_resp->frame_count;
1108 agg->start_idx = start_idx;
1109 agg->rate_n_flags = rate_n_flags;
1110 agg->bitmap = 0;
1111
1112 /* # frames attempted by Tx command */
1113 if (agg->frame_count == 1) {
1114 /* Only one frame was attempted; no block-ack will arrive */
1115 status = le16_to_cpu(frame_status[0].status);
1116 idx = start_idx;
1117
1118 /* FIXME: code repetition */
1119 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1120 agg->frame_count, agg->start_idx, idx);
1121
1122 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1123 info->status.rates[0].count = tx_resp->failure_frame + 1;
1124 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1125 info->flags |= iwl_is_tx_success(status) ?
1126 IEEE80211_TX_STAT_ACK : 0;
1127 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1128
1129 /* FIXME: code repetition end */
1130
1131 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1132 status & 0xff, tx_resp->failure_frame);
1133 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
1134
1135 agg->wait_for_ba = 0;
1136 } else {
1137 /* Two or more frames were attempted; expect block-ack */
1138 u64 bitmap = 0;
1139 int start = agg->start_idx;
1140
1141 /* Construct bit-map of pending frames within Tx window */
1142 for (i = 0; i < agg->frame_count; i++) {
1143 u16 sc;
1144 status = le16_to_cpu(frame_status[i].status);
1145 seq = le16_to_cpu(frame_status[i].sequence);
1146 idx = SEQ_TO_INDEX(seq);
1147 txq_id = SEQ_TO_QUEUE(seq);
1148
1149 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1150 AGG_TX_STATE_ABORT_MSK))
1151 continue;
1152
1153 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1154 agg->frame_count, txq_id, idx);
1155
1156 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1157
1158 sc = le16_to_cpu(hdr->seq_ctrl);
1159 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1160 IWL_ERROR("BUG_ON idx doesn't match seq control"
1161 " idx=%d, seq_idx=%d, seq=%d\n",
1162 idx, SEQ_TO_SN(sc),
1163 hdr->seq_ctrl);
1164 return -1;
1165 }
1166
1167 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1168 i, idx, SEQ_TO_SN(sc));
1169
1170 sh = idx - start;
1171 if (sh > 64) {
1172 sh = (start - idx) + 0xff;
1173 bitmap = bitmap << sh;
1174 sh = 0;
1175 start = idx;
1176 } else if (sh < -64)
1177 sh = 0xff - (start - idx);
1178 else if (sh < 0) {
1179 sh = start - idx;
1180 start = idx;
1181 bitmap = bitmap << sh;
1182 sh = 0;
1183 }
1184 bitmap |= 1ULL << sh;
1185 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1186 start, (unsigned long long)bitmap);
1187 }
1188
1189 agg->bitmap = bitmap;
1190 agg->start_idx = start;
1191 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1192 agg->frame_count, agg->start_idx,
1193 (unsigned long long)agg->bitmap);
1194
1195 if (bitmap)
1196 agg->wait_for_ba = 1;
1197 }
1198 return 0;
1199 }
1200
1201 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1202 struct iwl_rx_mem_buffer *rxb)
1203 {
1204 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1205 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1206 int txq_id = SEQ_TO_QUEUE(sequence);
1207 int index = SEQ_TO_INDEX(sequence);
1208 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1209 struct ieee80211_tx_info *info;
1210 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1211 u32 status = le16_to_cpu(tx_resp->status.status);
1212 int tid;
1213 int sta_id;
1214 int freed;
1215
1216 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1217 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1218 "is out of range [0-%d] %d %d\n", txq_id,
1219 index, txq->q.n_bd, txq->q.write_ptr,
1220 txq->q.read_ptr);
1221 return;
1222 }
1223
1224 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1225 memset(&info->status, 0, sizeof(info->status));
1226
1227 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1228 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1229
1230 if (txq->sched_retry) {
1231 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1232 struct iwl_ht_agg *agg = NULL;
1233
1234 agg = &priv->stations[sta_id].tid[tid].agg;
1235
1236 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1237
1238 /* check if BAR is needed */
1239 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1240 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1241
1242 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1243 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1244 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim "
1245 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1246 scd_ssn , index, txq_id, txq->swq_id);
1247
1248 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1249 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1250
1251 if (priv->mac80211_registered &&
1252 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1253 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1254 if (agg->state == IWL_AGG_OFF)
1255 ieee80211_wake_queue(priv->hw, txq_id);
1256 else
1257 ieee80211_wake_queue(priv->hw,
1258 txq->swq_id);
1259 }
1260 }
1261 } else {
1262 BUG_ON(txq_id != txq->swq_id);
1263
1264 info->status.rates[0].count = tx_resp->failure_frame + 1;
1265 info->flags |= iwl_is_tx_success(status) ?
1266 IEEE80211_TX_STAT_ACK : 0;
1267 iwl_hwrate_to_tx_control(priv,
1268 le32_to_cpu(tx_resp->rate_n_flags),
1269 info);
1270
1271 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags "
1272 "0x%x retries %d\n",
1273 txq_id,
1274 iwl_get_tx_fail_reason(status), status,
1275 le32_to_cpu(tx_resp->rate_n_flags),
1276 tx_resp->failure_frame);
1277
1278 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1279 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1280 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1281
1282 if (priv->mac80211_registered &&
1283 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1284 ieee80211_wake_queue(priv->hw, txq_id);
1285 }
1286
1287 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1288 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1289
1290 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1291 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1292 }
1293
1294 /* Currently 5000 is the superset of everything */
1295 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1296 {
1297 return len;
1298 }
1299
1300 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1301 {
1302 /* in 5000 the tx power calibration is done in uCode */
1303 priv->disable_tx_power_cal = 1;
1304 }
1305
1306 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1307 {
1308 /* init calibration handlers */
1309 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1310 iwl5000_rx_calib_result;
1311 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1312 iwl5000_rx_calib_complete;
1313 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1314 }
1315
1316
1317 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1318 {
1319 return (addr >= RTC_DATA_LOWER_BOUND) &&
1320 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1321 }
1322
1323 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1324 {
1325 int ret = 0;
1326 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1327 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1328 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1329
1330 if ((rxon1->flags == rxon2->flags) &&
1331 (rxon1->filter_flags == rxon2->filter_flags) &&
1332 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1333 (rxon1->ofdm_ht_single_stream_basic_rates ==
1334 rxon2->ofdm_ht_single_stream_basic_rates) &&
1335 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1336 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1337 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1338 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1339 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1340 (rxon1->rx_chain == rxon2->rx_chain) &&
1341 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1342 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1343 return 0;
1344 }
1345
1346 rxon_assoc.flags = priv->staging_rxon.flags;
1347 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1348 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1349 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1350 rxon_assoc.reserved1 = 0;
1351 rxon_assoc.reserved2 = 0;
1352 rxon_assoc.reserved3 = 0;
1353 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1354 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1355 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1356 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1357 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1358 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1359 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1360 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1361
1362 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1363 sizeof(rxon_assoc), &rxon_assoc, NULL);
1364 if (ret)
1365 return ret;
1366
1367 return ret;
1368 }
1369 static int iwl5000_send_tx_power(struct iwl_priv *priv)
1370 {
1371 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1372
1373 /* half dBm need to multiply */
1374 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1375 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1376 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1377 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1378 sizeof(tx_power_cmd), &tx_power_cmd,
1379 NULL);
1380 }
1381
1382 static void iwl5000_temperature(struct iwl_priv *priv)
1383 {
1384 /* store temperature from statistics (in Celsius) */
1385 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1386 }
1387
1388 /* Calc max signal level (dBm) among 3 possible receivers */
1389 static int iwl5000_calc_rssi(struct iwl_priv *priv,
1390 struct iwl_rx_phy_res *rx_resp)
1391 {
1392 /* data from PHY/DSP regarding signal strength, etc.,
1393 * contents are always there, not configurable by host
1394 */
1395 struct iwl5000_non_cfg_phy *ncphy =
1396 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1397 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1398 u8 agc;
1399
1400 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1401 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1402
1403 /* Find max rssi among 3 possible receivers.
1404 * These values are measured by the digital signal processor (DSP).
1405 * They should stay fairly constant even as the signal strength varies,
1406 * if the radio's automatic gain control (AGC) is working right.
1407 * AGC value (see below) will provide the "interesting" info.
1408 */
1409 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1410 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1411 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1412 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1413 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1414
1415 max_rssi = max_t(u32, rssi_a, rssi_b);
1416 max_rssi = max_t(u32, max_rssi, rssi_c);
1417
1418 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1419 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1420
1421 /* dBm = max_rssi dB - agc dB - constant.
1422 * Higher AGC (higher radio gain) means lower signal. */
1423 return max_rssi - agc - IWL_RSSI_OFFSET;
1424 }
1425
1426 static struct iwl_hcmd_ops iwl5000_hcmd = {
1427 .rxon_assoc = iwl5000_send_rxon_assoc,
1428 };
1429
1430 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1431 .get_hcmd_size = iwl5000_get_hcmd_size,
1432 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1433 .gain_computation = iwl5000_gain_computation,
1434 .chain_noise_reset = iwl5000_chain_noise_reset,
1435 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1436 .calc_rssi = iwl5000_calc_rssi,
1437 };
1438
1439 static struct iwl_lib_ops iwl5000_lib = {
1440 .set_hw_params = iwl5000_hw_set_hw_params,
1441 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1442 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1443 .txq_set_sched = iwl5000_txq_set_sched,
1444 .txq_agg_enable = iwl5000_txq_agg_enable,
1445 .txq_agg_disable = iwl5000_txq_agg_disable,
1446 .rx_handler_setup = iwl5000_rx_handler_setup,
1447 .setup_deferred_work = iwl5000_setup_deferred_work,
1448 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1449 .load_ucode = iwl5000_load_ucode,
1450 .init_alive_start = iwl5000_init_alive_start,
1451 .alive_notify = iwl5000_alive_notify,
1452 .send_tx_power = iwl5000_send_tx_power,
1453 .temperature = iwl5000_temperature,
1454 .update_chain_flags = iwl_update_chain_flags,
1455 .apm_ops = {
1456 .init = iwl5000_apm_init,
1457 .reset = iwl5000_apm_reset,
1458 .stop = iwl5000_apm_stop,
1459 .config = iwl5000_nic_config,
1460 .set_pwr_src = iwl_set_pwr_src,
1461 },
1462 .eeprom_ops = {
1463 .regulatory_bands = {
1464 EEPROM_5000_REG_BAND_1_CHANNELS,
1465 EEPROM_5000_REG_BAND_2_CHANNELS,
1466 EEPROM_5000_REG_BAND_3_CHANNELS,
1467 EEPROM_5000_REG_BAND_4_CHANNELS,
1468 EEPROM_5000_REG_BAND_5_CHANNELS,
1469 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1470 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1471 },
1472 .verify_signature = iwlcore_eeprom_verify_signature,
1473 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1474 .release_semaphore = iwlcore_eeprom_release_semaphore,
1475 .calib_version = iwl5000_eeprom_calib_version,
1476 .query_addr = iwl5000_eeprom_query_addr,
1477 },
1478 };
1479
1480 static struct iwl_ops iwl5000_ops = {
1481 .lib = &iwl5000_lib,
1482 .hcmd = &iwl5000_hcmd,
1483 .utils = &iwl5000_hcmd_utils,
1484 };
1485
1486 static struct iwl_mod_params iwl50_mod_params = {
1487 .num_of_queues = IWL50_NUM_QUEUES,
1488 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1489 .enable_qos = 1,
1490 .amsdu_size_8K = 1,
1491 .restart_fw = 1,
1492 /* the rest are 0 by default */
1493 };
1494
1495
1496 struct iwl_cfg iwl5300_agn_cfg = {
1497 .name = "5300AGN",
1498 .fw_name = IWL5000_MODULE_FIRMWARE,
1499 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1500 .ops = &iwl5000_ops,
1501 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1502 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1503 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1504 .mod_params = &iwl50_mod_params,
1505 };
1506
1507 struct iwl_cfg iwl5100_bg_cfg = {
1508 .name = "5100BG",
1509 .fw_name = IWL5000_MODULE_FIRMWARE,
1510 .sku = IWL_SKU_G,
1511 .ops = &iwl5000_ops,
1512 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1513 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1514 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1515 .mod_params = &iwl50_mod_params,
1516 };
1517
1518 struct iwl_cfg iwl5100_abg_cfg = {
1519 .name = "5100ABG",
1520 .fw_name = IWL5000_MODULE_FIRMWARE,
1521 .sku = IWL_SKU_A|IWL_SKU_G,
1522 .ops = &iwl5000_ops,
1523 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1524 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1525 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1526 .mod_params = &iwl50_mod_params,
1527 };
1528
1529 struct iwl_cfg iwl5100_agn_cfg = {
1530 .name = "5100AGN",
1531 .fw_name = IWL5000_MODULE_FIRMWARE,
1532 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1533 .ops = &iwl5000_ops,
1534 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1535 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1536 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1537 .mod_params = &iwl50_mod_params,
1538 };
1539
1540 struct iwl_cfg iwl5350_agn_cfg = {
1541 .name = "5350AGN",
1542 .fw_name = IWL5000_MODULE_FIRMWARE,
1543 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1544 .ops = &iwl5000_ops,
1545 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1546 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1547 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1548 .mod_params = &iwl50_mod_params,
1549 };
1550
1551 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE);
1552
1553 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1554 MODULE_PARM_DESC(disable50,
1555 "manually disable the 50XX radio (default 0 [radio on])");
1556 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1557 MODULE_PARM_DESC(swcrypto50,
1558 "using software crypto engine (default 0 [hardware])\n");
1559 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1560 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1561 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1562 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1563 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1564 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
1565 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1566 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1567 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1568 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1569 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1570 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
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