1 /******************************************************************************
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *****************************************************************************/
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/version.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
40 #include "iwl-eeprom.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
47 #define IWL5000_UCODE_API "-1"
49 static int iwl5000_apm_init(struct iwl_priv
*priv
)
53 iwl_set_bit(priv
, CSR_GIO_CHICKEN_BITS
,
54 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
56 iwl_set_bit(priv
, CSR_ANA_PLL_CFG
, CSR50_ANA_PLL_CFG_VAL
);
58 /* set "initialization complete" bit to move adapter
59 * D0U* --> D0A* state */
60 iwl_set_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
62 /* wait for clock stabilization */
63 ret
= iwl_poll_bit(priv
, CSR_GP_CNTRL
,
64 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
65 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
67 IWL_DEBUG_INFO("Failed to init the card\n");
71 ret
= iwl_grab_nic_access(priv
);
76 iwl_write_prph(priv
, APMG_CLK_EN_REG
,
77 APMG_CLK_VAL_DMA_CLK_RQT
);
81 iwl_set_bits_prph(priv
, APMG_PCIDEV_STT_REG
,
82 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
84 iwl_release_nic_access(priv
);
89 static void iwl5000_nic_config(struct iwl_priv
*priv
)
95 spin_lock_irqsave(&priv
->lock
, flags
);
97 pci_read_config_byte(priv
->pci_dev
, PCI_LINK_CTRL
, &val_link
);
99 /* disable L1 entry -- workaround for pre-B1 */
100 pci_write_config_byte(priv
->pci_dev
, PCI_LINK_CTRL
, val_link
& ~0x02);
102 radio_cfg
= iwl_eeprom_query16(priv
, EEPROM_RADIO_CONFIG
);
104 /* write radio config values to register */
105 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) < EEPROM_5000_RF_CFG_TYPE_MAX
)
106 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
107 EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) |
108 EEPROM_RF_CFG_STEP_MSK(radio_cfg
) |
109 EEPROM_RF_CFG_DASH_MSK(radio_cfg
));
111 /* set CSR_HW_CONFIG_REG for uCode use */
112 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
113 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI
|
114 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI
);
116 spin_unlock_irqrestore(&priv
->lock
, flags
);
124 static u32
eeprom_indirect_address(const struct iwl_priv
*priv
, u32 address
)
128 if ((address
& INDIRECT_ADDRESS
) == 0)
131 switch (address
& INDIRECT_TYPE_MSK
) {
133 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_HOST
);
135 case INDIRECT_GENERAL
:
136 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_GENERAL
);
138 case INDIRECT_REGULATORY
:
139 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_REGULATORY
);
141 case INDIRECT_CALIBRATION
:
142 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_CALIBRATION
);
144 case INDIRECT_PROCESS_ADJST
:
145 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_PROCESS_ADJST
);
147 case INDIRECT_OTHERS
:
148 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_OTHERS
);
151 IWL_ERROR("illegal indirect type: 0x%X\n",
152 address
& INDIRECT_TYPE_MSK
);
156 /* translate the offset from words to byte */
157 return (address
& ADDRESS_MSK
) + (offset
<< 1);
160 static int iwl5000_eeprom_check_version(struct iwl_priv
*priv
)
163 struct iwl_eeprom_calib_hdr
{
169 eeprom_ver
= iwl_eeprom_query16(priv
, EEPROM_VERSION
);
171 hdr
= (struct iwl_eeprom_calib_hdr
*)iwl_eeprom_query_addr(priv
,
172 EEPROM_5000_CALIB_ALL
);
174 if (eeprom_ver
< EEPROM_5000_EEPROM_VERSION
||
175 hdr
->version
< EEPROM_5000_TX_POWER_VERSION
)
180 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
181 eeprom_ver
, EEPROM_5000_EEPROM_VERSION
,
182 hdr
->version
, EEPROM_5000_TX_POWER_VERSION
);
187 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
189 static void iwl5000_gain_computation(struct iwl_priv
*priv
,
190 u32 average_noise
[NUM_RX_CHAINS
],
191 u16 min_average_noise_antenna_i
,
192 u32 min_average_noise
)
196 struct iwl_chain_noise_data
*data
= &priv
->chain_noise_data
;
198 /* Find Gain Code for the antennas B and C */
199 for (i
= 1; i
< NUM_RX_CHAINS
; i
++) {
200 if ((data
->disconn_array
[i
])) {
201 data
->delta_gain_code
[i
] = 0;
204 delta_g
= (1000 * ((s32
)average_noise
[0] -
205 (s32
)average_noise
[i
])) / 1500;
206 /* bound gain by 2 bits value max, 3rd bit is sign */
207 data
->delta_gain_code
[i
] =
208 min(abs(delta_g
), CHAIN_NOISE_MAX_DELTA_GAIN_CODE
);
211 /* set negative sign */
212 data
->delta_gain_code
[i
] |= (1 << 2);
215 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
216 data
->delta_gain_code
[1], data
->delta_gain_code
[2]);
218 if (!data
->radio_write
) {
219 struct iwl5000_calibration_chain_noise_gain_cmd cmd
;
220 memset(&cmd
, 0, sizeof(cmd
));
222 cmd
.op_code
= IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD
;
223 cmd
.delta_gain_1
= data
->delta_gain_code
[1];
224 cmd
.delta_gain_2
= data
->delta_gain_code
[2];
225 iwl_send_cmd_pdu_async(priv
, REPLY_PHY_CALIBRATION_CMD
,
226 sizeof(cmd
), &cmd
, NULL
);
228 data
->radio_write
= 1;
229 data
->state
= IWL_CHAIN_NOISE_CALIBRATED
;
232 data
->chain_noise_a
= 0;
233 data
->chain_noise_b
= 0;
234 data
->chain_noise_c
= 0;
235 data
->chain_signal_a
= 0;
236 data
->chain_signal_b
= 0;
237 data
->chain_signal_c
= 0;
238 data
->beacon_count
= 0;
242 static void iwl5000_chain_noise_reset(struct iwl_priv
*priv
)
244 struct iwl_chain_noise_data
*data
= &priv
->chain_noise_data
;
246 if ((data
->state
== IWL_CHAIN_NOISE_ALIVE
) && iwl_is_associated(priv
)) {
247 struct iwl5000_calibration_chain_noise_reset_cmd cmd
;
249 memset(&cmd
, 0, sizeof(cmd
));
250 cmd
.op_code
= IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD
;
251 if (iwl_send_cmd_pdu(priv
, REPLY_PHY_CALIBRATION_CMD
,
253 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
254 data
->state
= IWL_CHAIN_NOISE_ACCUMULATE
;
255 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
259 static struct iwl_sensitivity_ranges iwl5000_sensitivity
= {
262 .auto_corr_min_ofdm
= 90,
263 .auto_corr_min_ofdm_mrc
= 170,
264 .auto_corr_min_ofdm_x1
= 120,
265 .auto_corr_min_ofdm_mrc_x1
= 240,
267 .auto_corr_max_ofdm
= 120,
268 .auto_corr_max_ofdm_mrc
= 210,
269 .auto_corr_max_ofdm_x1
= 155,
270 .auto_corr_max_ofdm_mrc_x1
= 290,
272 .auto_corr_min_cck
= 125,
273 .auto_corr_max_cck
= 200,
274 .auto_corr_min_cck_mrc
= 170,
275 .auto_corr_max_cck_mrc
= 400,
280 #endif /* CONFIG_IWL5000_RUN_TIME_CALIB */
282 static const u8
*iwl5000_eeprom_query_addr(const struct iwl_priv
*priv
,
285 u32 address
= eeprom_indirect_address(priv
, offset
);
286 BUG_ON(address
>= priv
->cfg
->eeprom_size
);
287 return &priv
->eeprom
[address
];
290 static int iwl5000_hw_set_hw_params(struct iwl_priv
*priv
)
292 if ((priv
->cfg
->mod_params
->num_of_queues
> IWL50_NUM_QUEUES
) ||
293 (priv
->cfg
->mod_params
->num_of_queues
< IWL_MIN_NUM_QUEUES
)) {
294 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
295 IWL_MIN_NUM_QUEUES
, IWL50_NUM_QUEUES
);
299 priv
->hw_params
.max_txq_num
= priv
->cfg
->mod_params
->num_of_queues
;
300 priv
->hw_params
.sw_crypto
= priv
->cfg
->mod_params
->sw_crypto
;
301 priv
->hw_params
.tx_cmd_len
= sizeof(struct iwl4965_tx_cmd
);
302 priv
->hw_params
.max_rxq_size
= RX_QUEUE_SIZE
;
303 priv
->hw_params
.max_rxq_log
= RX_QUEUE_SIZE_LOG
;
304 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
305 priv
->hw_params
.rx_buf_size
= IWL_RX_BUF_SIZE_8K
;
307 priv
->hw_params
.rx_buf_size
= IWL_RX_BUF_SIZE_4K
;
308 priv
->hw_params
.max_pkt_size
= priv
->hw_params
.rx_buf_size
- 256;
309 priv
->hw_params
.max_stations
= IWL5000_STATION_COUNT
;
310 priv
->hw_params
.bcast_sta_id
= IWL5000_BROADCAST_ID
;
311 priv
->hw_params
.max_data_size
= IWL50_RTC_DATA_SIZE
;
312 priv
->hw_params
.max_inst_size
= IWL50_RTC_INST_SIZE
;
313 priv
->hw_params
.max_bsm_size
= BSM_SRAM_SIZE
;
314 priv
->hw_params
.fat_channel
= BIT(IEEE80211_BAND_2GHZ
) |
315 BIT(IEEE80211_BAND_5GHZ
);
316 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
317 priv
->hw_params
.sens
= &iwl5000_sensitivity
;
320 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
321 case CSR_HW_REV_TYPE_5100
:
322 case CSR_HW_REV_TYPE_5150
:
323 priv
->hw_params
.tx_chains_num
= 1;
324 priv
->hw_params
.rx_chains_num
= 2;
325 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
326 priv
->hw_params
.valid_tx_ant
= ANT_A
;
327 priv
->hw_params
.valid_rx_ant
= ANT_AB
;
329 case CSR_HW_REV_TYPE_5300
:
330 case CSR_HW_REV_TYPE_5350
:
331 priv
->hw_params
.tx_chains_num
= 3;
332 priv
->hw_params
.rx_chains_num
= 3;
333 priv
->hw_params
.valid_tx_ant
= ANT_ABC
;
334 priv
->hw_params
.valid_rx_ant
= ANT_ABC
;
338 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
339 case CSR_HW_REV_TYPE_5100
:
340 case CSR_HW_REV_TYPE_5300
:
341 /* 5X00 wants in Celsius */
342 priv
->hw_params
.ct_kill_threshold
= CT_KILL_THRESHOLD
;
344 case CSR_HW_REV_TYPE_5150
:
345 case CSR_HW_REV_TYPE_5350
:
346 /* 5X50 wants in Kelvin */
347 priv
->hw_params
.ct_kill_threshold
=
348 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD
);
355 static int iwl5000_alloc_shared_mem(struct iwl_priv
*priv
)
357 priv
->shared_virt
= pci_alloc_consistent(priv
->pci_dev
,
358 sizeof(struct iwl5000_shared
),
360 if (!priv
->shared_virt
)
363 memset(priv
->shared_virt
, 0, sizeof(struct iwl5000_shared
));
368 static void iwl5000_free_shared_mem(struct iwl_priv
*priv
)
370 if (priv
->shared_virt
)
371 pci_free_consistent(priv
->pci_dev
,
372 sizeof(struct iwl5000_shared
),
378 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
380 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv
*priv
,
381 struct iwl4965_tx_queue
*txq
,
384 struct iwl5000_shared
*shared_data
= priv
->shared_virt
;
385 int txq_id
= txq
->q
.id
;
390 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
392 if (txq_id
!= IWL_CMD_QUEUE_NUM
) {
393 sta
= txq
->cmd
[txq
->q
.write_ptr
].cmd
.tx
.sta_id
;
394 sec_ctl
= txq
->cmd
[txq
->q
.write_ptr
].cmd
.tx
.sec_ctl
;
396 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
400 case TX_CMD_SEC_TKIP
:
404 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
409 IWL_SET_BITS16(shared_data
->queues_byte_cnt_tbls
[txq_id
].
410 tfd_offset
[txq
->q
.write_ptr
], byte_cnt
, len
);
412 IWL_SET_BITS16(shared_data
->queues_byte_cnt_tbls
[txq_id
].
413 tfd_offset
[txq
->q
.write_ptr
], sta_id
, sta
);
415 if (txq
->q
.write_ptr
< IWL50_MAX_WIN_SIZE
) {
416 IWL_SET_BITS16(shared_data
->queues_byte_cnt_tbls
[txq_id
].
417 tfd_offset
[IWL50_QUEUE_SIZE
+ txq
->q
.write_ptr
],
419 IWL_SET_BITS16(shared_data
->queues_byte_cnt_tbls
[txq_id
].
420 tfd_offset
[IWL50_QUEUE_SIZE
+ txq
->q
.write_ptr
],
425 static u16
iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd
*cmd
, u8
*data
)
427 u16 size
= (u16
)sizeof(struct iwl_addsta_cmd
);
428 memcpy(data
, cmd
, size
);
433 static struct iwl_hcmd_ops iwl5000_hcmd
= {
436 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils
= {
437 .build_addsta_hcmd
= iwl5000_build_addsta_hcmd
,
438 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
439 .gain_computation
= iwl5000_gain_computation
,
440 .chain_noise_reset
= iwl5000_chain_noise_reset
,
444 static struct iwl_lib_ops iwl5000_lib
= {
445 .set_hw_params
= iwl5000_hw_set_hw_params
,
446 .alloc_shared_mem
= iwl5000_alloc_shared_mem
,
447 .free_shared_mem
= iwl5000_free_shared_mem
,
448 .txq_update_byte_cnt_tbl
= iwl5000_txq_update_byte_cnt_tbl
,
450 .init
= iwl5000_apm_init
,
451 .config
= iwl5000_nic_config
,
452 .set_pwr_src
= iwl4965_set_pwr_src
,
455 .regulatory_bands
= {
456 EEPROM_5000_REG_BAND_1_CHANNELS
,
457 EEPROM_5000_REG_BAND_2_CHANNELS
,
458 EEPROM_5000_REG_BAND_3_CHANNELS
,
459 EEPROM_5000_REG_BAND_4_CHANNELS
,
460 EEPROM_5000_REG_BAND_5_CHANNELS
,
461 EEPROM_5000_REG_BAND_24_FAT_CHANNELS
,
462 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
464 .verify_signature
= iwlcore_eeprom_verify_signature
,
465 .acquire_semaphore
= iwlcore_eeprom_acquire_semaphore
,
466 .release_semaphore
= iwlcore_eeprom_release_semaphore
,
467 .check_version
= iwl5000_eeprom_check_version
,
468 .query_addr
= iwl5000_eeprom_query_addr
,
472 static struct iwl_ops iwl5000_ops
= {
474 .hcmd
= &iwl5000_hcmd
,
475 .utils
= &iwl5000_hcmd_utils
,
478 static struct iwl_mod_params iwl50_mod_params
= {
479 .num_of_queues
= IWL50_NUM_QUEUES
,
482 /* the rest are 0 by default */
486 struct iwl_cfg iwl5300_agn_cfg
= {
488 .fw_name
= "iwlwifi-5000" IWL5000_UCODE_API
".ucode",
489 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
491 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
492 .mod_params
= &iwl50_mod_params
,
495 struct iwl_cfg iwl5100_agn_cfg
= {
497 .fw_name
= "iwlwifi-5000" IWL5000_UCODE_API
".ucode",
498 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
500 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
501 .mod_params
= &iwl50_mod_params
,
504 struct iwl_cfg iwl5350_agn_cfg
= {
506 .fw_name
= "iwlwifi-5000" IWL5000_UCODE_API
".ucode",
507 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
509 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
510 .mod_params
= &iwl50_mod_params
,
513 module_param_named(disable50
, iwl50_mod_params
.disable
, int, 0444);
514 MODULE_PARM_DESC(disable50
,
515 "manually disable the 50XX radio (default 0 [radio on])");
516 module_param_named(swcrypto50
, iwl50_mod_params
.sw_crypto
, bool, 0444);
517 MODULE_PARM_DESC(swcrypto50
,
518 "using software crypto engine (default 0 [hardware])\n");
519 module_param_named(debug50
, iwl50_mod_params
.debug
, int, 0444);
520 MODULE_PARM_DESC(debug50
, "50XX debug output mask");
521 module_param_named(queues_num50
, iwl50_mod_params
.num_of_queues
, int, 0444);
522 MODULE_PARM_DESC(queues_num50
, "number of hw queues in 50xx series");
523 module_param_named(qos_enable50
, iwl50_mod_params
.enable_qos
, int, 0444);
524 MODULE_PARM_DESC(qos_enable50
, "enable all 50XX QoS functionality");
525 module_param_named(amsdu_size_8K50
, iwl50_mod_params
.amsdu_size_8K
, int, 0444);
526 MODULE_PARM_DESC(amsdu_size_8K50
, "enable 8K amsdu size in 50XX series");