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Merge branch 'for-airlied' of git://git.freedesktop.org/git/nouveau/linux-2.6 into...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/sched.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39
40 #include "iwl-eeprom.h"
41 #include "iwl-dev.h"
42 #include "iwl-core.h"
43 #include "iwl-io.h"
44 #include "iwl-sta.h"
45 #include "iwl-helpers.h"
46 #include "iwl-agn-led.h"
47 #include "iwl-5000-hw.h"
48 #include "iwl-6000-hw.h"
49
50 /* Highest firmware API version supported */
51 #define IWL5000_UCODE_API_MAX 2
52 #define IWL5150_UCODE_API_MAX 2
53
54 /* Lowest firmware API version supported */
55 #define IWL5000_UCODE_API_MIN 1
56 #define IWL5150_UCODE_API_MIN 1
57
58 #define IWL5000_FW_PRE "iwlwifi-5000-"
59 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
60 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
61
62 #define IWL5150_FW_PRE "iwlwifi-5150-"
63 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
64 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
65
66 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
67 IWL_TX_FIFO_AC3,
68 IWL_TX_FIFO_AC2,
69 IWL_TX_FIFO_AC1,
70 IWL_TX_FIFO_AC0,
71 IWL50_CMD_FIFO_NUM,
72 IWL_TX_FIFO_HCCA_1,
73 IWL_TX_FIFO_HCCA_2
74 };
75
76 /* NIC configuration for 5000 series */
77 void iwl5000_nic_config(struct iwl_priv *priv)
78 {
79 unsigned long flags;
80 u16 radio_cfg;
81
82 spin_lock_irqsave(&priv->lock, flags);
83
84 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
85
86 /* write radio config values to register */
87 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
88 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
89 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
90 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
91 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
92
93 /* set CSR_HW_CONFIG_REG for uCode use */
94 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
95 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
96 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
97
98 /* W/A : NIC is stuck in a reset state after Early PCIe power off
99 * (PCIe power is lost before PERST# is asserted),
100 * causing ME FW to lose ownership and not being able to obtain it back.
101 */
102 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
103 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
104 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
105
106
107 spin_unlock_irqrestore(&priv->lock, flags);
108 }
109
110
111 /*
112 * EEPROM
113 */
114 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
115 {
116 u16 offset = 0;
117
118 if ((address & INDIRECT_ADDRESS) == 0)
119 return address;
120
121 switch (address & INDIRECT_TYPE_MSK) {
122 case INDIRECT_HOST:
123 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
124 break;
125 case INDIRECT_GENERAL:
126 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
127 break;
128 case INDIRECT_REGULATORY:
129 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
130 break;
131 case INDIRECT_CALIBRATION:
132 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
133 break;
134 case INDIRECT_PROCESS_ADJST:
135 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
136 break;
137 case INDIRECT_OTHERS:
138 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
139 break;
140 default:
141 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
142 address & INDIRECT_TYPE_MSK);
143 break;
144 }
145
146 /* translate the offset from words to byte */
147 return (address & ADDRESS_MSK) + (offset << 1);
148 }
149
150 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
151 {
152 struct iwl_eeprom_calib_hdr {
153 u8 version;
154 u8 pa_type;
155 u16 voltage;
156 } *hdr;
157
158 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
159 EEPROM_5000_CALIB_ALL);
160 return hdr->version;
161
162 }
163
164 static void iwl5000_gain_computation(struct iwl_priv *priv,
165 u32 average_noise[NUM_RX_CHAINS],
166 u16 min_average_noise_antenna_i,
167 u32 min_average_noise,
168 u8 default_chain)
169 {
170 int i;
171 s32 delta_g;
172 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
173
174 /*
175 * Find Gain Code for the chains based on "default chain"
176 */
177 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
178 if ((data->disconn_array[i])) {
179 data->delta_gain_code[i] = 0;
180 continue;
181 }
182 delta_g = (1000 * ((s32)average_noise[default_chain] -
183 (s32)average_noise[i])) / 1500;
184 /* bound gain by 2 bits value max, 3rd bit is sign */
185 data->delta_gain_code[i] =
186 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
187
188 if (delta_g < 0)
189 /* set negative sign */
190 data->delta_gain_code[i] |= (1 << 2);
191 }
192
193 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
194 data->delta_gain_code[1], data->delta_gain_code[2]);
195
196 if (!data->radio_write) {
197 struct iwl_calib_chain_noise_gain_cmd cmd;
198
199 memset(&cmd, 0, sizeof(cmd));
200
201 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
202 cmd.hdr.first_group = 0;
203 cmd.hdr.groups_num = 1;
204 cmd.hdr.data_valid = 1;
205 cmd.delta_gain_1 = data->delta_gain_code[1];
206 cmd.delta_gain_2 = data->delta_gain_code[2];
207 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
208 sizeof(cmd), &cmd, NULL);
209
210 data->radio_write = 1;
211 data->state = IWL_CHAIN_NOISE_CALIBRATED;
212 }
213
214 data->chain_noise_a = 0;
215 data->chain_noise_b = 0;
216 data->chain_noise_c = 0;
217 data->chain_signal_a = 0;
218 data->chain_signal_b = 0;
219 data->chain_signal_c = 0;
220 data->beacon_count = 0;
221 }
222
223 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
224 {
225 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
226 int ret;
227
228 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
229 struct iwl_calib_chain_noise_reset_cmd cmd;
230 memset(&cmd, 0, sizeof(cmd));
231
232 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
233 cmd.hdr.first_group = 0;
234 cmd.hdr.groups_num = 1;
235 cmd.hdr.data_valid = 1;
236 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
237 sizeof(cmd), &cmd);
238 if (ret)
239 IWL_ERR(priv,
240 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
241 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
242 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
243 }
244 }
245
246 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
247 __le32 *tx_flags)
248 {
249 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
250 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
251 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
252 else
253 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
254 }
255
256 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
257 .min_nrg_cck = 95,
258 .max_nrg_cck = 0, /* not used, set to 0 */
259 .auto_corr_min_ofdm = 90,
260 .auto_corr_min_ofdm_mrc = 170,
261 .auto_corr_min_ofdm_x1 = 120,
262 .auto_corr_min_ofdm_mrc_x1 = 240,
263
264 .auto_corr_max_ofdm = 120,
265 .auto_corr_max_ofdm_mrc = 210,
266 .auto_corr_max_ofdm_x1 = 155,
267 .auto_corr_max_ofdm_mrc_x1 = 290,
268
269 .auto_corr_min_cck = 125,
270 .auto_corr_max_cck = 200,
271 .auto_corr_min_cck_mrc = 170,
272 .auto_corr_max_cck_mrc = 400,
273 .nrg_th_cck = 95,
274 .nrg_th_ofdm = 95,
275
276 .barker_corr_th_min = 190,
277 .barker_corr_th_min_mrc = 390,
278 .nrg_th_cca = 62,
279 };
280
281 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
282 .min_nrg_cck = 95,
283 .max_nrg_cck = 0, /* not used, set to 0 */
284 .auto_corr_min_ofdm = 90,
285 .auto_corr_min_ofdm_mrc = 170,
286 .auto_corr_min_ofdm_x1 = 105,
287 .auto_corr_min_ofdm_mrc_x1 = 220,
288
289 .auto_corr_max_ofdm = 120,
290 .auto_corr_max_ofdm_mrc = 210,
291 /* max = min for performance bug in 5150 DSP */
292 .auto_corr_max_ofdm_x1 = 105,
293 .auto_corr_max_ofdm_mrc_x1 = 220,
294
295 .auto_corr_min_cck = 125,
296 .auto_corr_max_cck = 200,
297 .auto_corr_min_cck_mrc = 170,
298 .auto_corr_max_cck_mrc = 400,
299 .nrg_th_cck = 95,
300 .nrg_th_ofdm = 95,
301
302 .barker_corr_th_min = 190,
303 .barker_corr_th_min_mrc = 390,
304 .nrg_th_cca = 62,
305 };
306
307 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
308 size_t offset)
309 {
310 u32 address = eeprom_indirect_address(priv, offset);
311 BUG_ON(address >= priv->cfg->eeprom_size);
312 return &priv->eeprom[address];
313 }
314
315 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
316 {
317 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
318 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
319 iwl_temp_calib_to_offset(priv);
320
321 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
322 }
323
324 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
325 {
326 /* want Celsius */
327 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
328 }
329
330 /*
331 * Calibration
332 */
333 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
334 {
335 struct iwl_calib_xtal_freq_cmd cmd;
336 __le16 *xtal_calib =
337 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
338
339 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
340 cmd.hdr.first_group = 0;
341 cmd.hdr.groups_num = 1;
342 cmd.hdr.data_valid = 1;
343 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
344 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
345 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
346 (u8 *)&cmd, sizeof(cmd));
347 }
348
349 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
350 {
351 struct iwl_calib_cfg_cmd calib_cfg_cmd;
352 struct iwl_host_cmd cmd = {
353 .id = CALIBRATION_CFG_CMD,
354 .len = sizeof(struct iwl_calib_cfg_cmd),
355 .data = &calib_cfg_cmd,
356 };
357
358 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
359 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
360 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
361 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
362 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
363
364 return iwl_send_cmd(priv, &cmd);
365 }
366
367 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
368 struct iwl_rx_mem_buffer *rxb)
369 {
370 struct iwl_rx_packet *pkt = rxb_addr(rxb);
371 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
372 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
373 int index;
374
375 /* reduce the size of the length field itself */
376 len -= 4;
377
378 /* Define the order in which the results will be sent to the runtime
379 * uCode. iwl_send_calib_results sends them in a row according to their
380 * index. We sort them here */
381 switch (hdr->op_code) {
382 case IWL_PHY_CALIBRATE_DC_CMD:
383 index = IWL_CALIB_DC;
384 break;
385 case IWL_PHY_CALIBRATE_LO_CMD:
386 index = IWL_CALIB_LO;
387 break;
388 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
389 index = IWL_CALIB_TX_IQ;
390 break;
391 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
392 index = IWL_CALIB_TX_IQ_PERD;
393 break;
394 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
395 index = IWL_CALIB_BASE_BAND;
396 break;
397 default:
398 IWL_ERR(priv, "Unknown calibration notification %d\n",
399 hdr->op_code);
400 return;
401 }
402 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
403 }
404
405 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
406 struct iwl_rx_mem_buffer *rxb)
407 {
408 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
409 queue_work(priv->workqueue, &priv->restart);
410 }
411
412 /*
413 * ucode
414 */
415 static int iwl5000_load_section(struct iwl_priv *priv,
416 struct fw_desc *image,
417 u32 dst_addr)
418 {
419 dma_addr_t phy_addr = image->p_addr;
420 u32 byte_cnt = image->len;
421
422 iwl_write_direct32(priv,
423 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
424 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
425
426 iwl_write_direct32(priv,
427 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
428
429 iwl_write_direct32(priv,
430 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
431 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
432
433 iwl_write_direct32(priv,
434 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
435 (iwl_get_dma_hi_addr(phy_addr)
436 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
437
438 iwl_write_direct32(priv,
439 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
440 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
441 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
442 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
443
444 iwl_write_direct32(priv,
445 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
446 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
447 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
448 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
449
450 return 0;
451 }
452
453 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
454 struct fw_desc *inst_image,
455 struct fw_desc *data_image)
456 {
457 int ret = 0;
458
459 ret = iwl5000_load_section(priv, inst_image,
460 IWL50_RTC_INST_LOWER_BOUND);
461 if (ret)
462 return ret;
463
464 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
465 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
466 priv->ucode_write_complete, 5 * HZ);
467 if (ret == -ERESTARTSYS) {
468 IWL_ERR(priv, "Could not load the INST uCode section due "
469 "to interrupt\n");
470 return ret;
471 }
472 if (!ret) {
473 IWL_ERR(priv, "Could not load the INST uCode section\n");
474 return -ETIMEDOUT;
475 }
476
477 priv->ucode_write_complete = 0;
478
479 ret = iwl5000_load_section(
480 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
481 if (ret)
482 return ret;
483
484 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
485
486 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
487 priv->ucode_write_complete, 5 * HZ);
488 if (ret == -ERESTARTSYS) {
489 IWL_ERR(priv, "Could not load the INST uCode section due "
490 "to interrupt\n");
491 return ret;
492 } else if (!ret) {
493 IWL_ERR(priv, "Could not load the DATA uCode section\n");
494 return -ETIMEDOUT;
495 } else
496 ret = 0;
497
498 priv->ucode_write_complete = 0;
499
500 return ret;
501 }
502
503 int iwl5000_load_ucode(struct iwl_priv *priv)
504 {
505 int ret = 0;
506
507 /* check whether init ucode should be loaded, or rather runtime ucode */
508 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
509 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
510 ret = iwl5000_load_given_ucode(priv,
511 &priv->ucode_init, &priv->ucode_init_data);
512 if (!ret) {
513 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
514 priv->ucode_type = UCODE_INIT;
515 }
516 } else {
517 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
518 "Loading runtime ucode...\n");
519 ret = iwl5000_load_given_ucode(priv,
520 &priv->ucode_code, &priv->ucode_data);
521 if (!ret) {
522 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
523 priv->ucode_type = UCODE_RT;
524 }
525 }
526
527 return ret;
528 }
529
530 void iwl5000_init_alive_start(struct iwl_priv *priv)
531 {
532 int ret = 0;
533
534 /* Check alive response for "valid" sign from uCode */
535 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
536 /* We had an error bringing up the hardware, so take it
537 * all the way back down so we can try again */
538 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
539 goto restart;
540 }
541
542 /* initialize uCode was loaded... verify inst image.
543 * This is a paranoid check, because we would not have gotten the
544 * "initialize" alive if code weren't properly loaded. */
545 if (iwl_verify_ucode(priv)) {
546 /* Runtime instruction load was bad;
547 * take it all the way back down so we can try again */
548 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
549 goto restart;
550 }
551
552 iwl_clear_stations_table(priv);
553 ret = priv->cfg->ops->lib->alive_notify(priv);
554 if (ret) {
555 IWL_WARN(priv,
556 "Could not complete ALIVE transition: %d\n", ret);
557 goto restart;
558 }
559
560 iwl5000_send_calib_cfg(priv);
561 return;
562
563 restart:
564 /* real restart (first load init_ucode) */
565 queue_work(priv->workqueue, &priv->restart);
566 }
567
568 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
569 int txq_id, u32 index)
570 {
571 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
572 (index & 0xff) | (txq_id << 8));
573 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
574 }
575
576 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
577 struct iwl_tx_queue *txq,
578 int tx_fifo_id, int scd_retry)
579 {
580 int txq_id = txq->q.id;
581 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
582
583 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
584 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
585 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
586 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
587 IWL50_SCD_QUEUE_STTS_REG_MSK);
588
589 txq->sched_retry = scd_retry;
590
591 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
592 active ? "Activate" : "Deactivate",
593 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
594 }
595
596 int iwl5000_alive_notify(struct iwl_priv *priv)
597 {
598 u32 a;
599 unsigned long flags;
600 int i, chan;
601 u32 reg_val;
602
603 spin_lock_irqsave(&priv->lock, flags);
604
605 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
606 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
607 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
608 a += 4)
609 iwl_write_targ_mem(priv, a, 0);
610 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
611 a += 4)
612 iwl_write_targ_mem(priv, a, 0);
613 for (; a < priv->scd_base_addr +
614 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
615 iwl_write_targ_mem(priv, a, 0);
616
617 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
618 priv->scd_bc_tbls.dma >> 10);
619
620 /* Enable DMA channel */
621 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
622 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
623 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
624 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
625
626 /* Update FH chicken bits */
627 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
628 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
629 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
630
631 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
632 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
633 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
634
635 /* initiate the queues */
636 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
637 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
638 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
639 iwl_write_targ_mem(priv, priv->scd_base_addr +
640 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
641 iwl_write_targ_mem(priv, priv->scd_base_addr +
642 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
643 sizeof(u32),
644 ((SCD_WIN_SIZE <<
645 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
646 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
647 ((SCD_FRAME_LIMIT <<
648 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
649 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
650 }
651
652 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
653 IWL_MASK(0, priv->hw_params.max_txq_num));
654
655 /* Activate all Tx DMA/FIFO channels */
656 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
657
658 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
659
660 /* map qos queues to fifos one-to-one */
661 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
662 int ac = iwl5000_default_queue_to_tx_fifo[i];
663 iwl_txq_ctx_activate(priv, i);
664 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
665 }
666
667 /*
668 * TODO - need to initialize these queues and map them to FIFOs
669 * in the loop above, not only mark them as active. We do this
670 * because we want the first aggregation queue to be queue #10,
671 * but do not use 8 or 9 otherwise yet.
672 */
673 iwl_txq_ctx_activate(priv, 7);
674 iwl_txq_ctx_activate(priv, 8);
675 iwl_txq_ctx_activate(priv, 9);
676
677 spin_unlock_irqrestore(&priv->lock, flags);
678
679
680 iwl_send_wimax_coex(priv);
681
682 iwl5000_set_Xtal_calib(priv);
683 iwl_send_calib_results(priv);
684
685 return 0;
686 }
687
688 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
689 {
690 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
691 priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
692 priv->cfg->num_of_queues =
693 priv->cfg->mod_params->num_of_queues;
694
695 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
696 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
697 priv->hw_params.scd_bc_tbls_size =
698 priv->cfg->num_of_queues *
699 sizeof(struct iwl5000_scd_bc_tbl);
700 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
701 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
702 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
703
704 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
705 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
706
707 priv->hw_params.max_bsm_size = 0;
708 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
709 BIT(IEEE80211_BAND_5GHZ);
710 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
711
712 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
713 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
714 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
715 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
716
717 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
718 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
719
720 /* Set initial sensitivity parameters */
721 /* Set initial calibration set */
722 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
723 case CSR_HW_REV_TYPE_5150:
724 priv->hw_params.sens = &iwl5150_sensitivity;
725 priv->hw_params.calib_init_cfg =
726 BIT(IWL_CALIB_DC) |
727 BIT(IWL_CALIB_LO) |
728 BIT(IWL_CALIB_TX_IQ) |
729 BIT(IWL_CALIB_BASE_BAND);
730
731 break;
732 default:
733 priv->hw_params.sens = &iwl5000_sensitivity;
734 priv->hw_params.calib_init_cfg =
735 BIT(IWL_CALIB_XTAL) |
736 BIT(IWL_CALIB_LO) |
737 BIT(IWL_CALIB_TX_IQ) |
738 BIT(IWL_CALIB_TX_IQ_PERD) |
739 BIT(IWL_CALIB_BASE_BAND);
740 break;
741 }
742
743 return 0;
744 }
745
746 /**
747 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
748 */
749 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
750 struct iwl_tx_queue *txq,
751 u16 byte_cnt)
752 {
753 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
754 int write_ptr = txq->q.write_ptr;
755 int txq_id = txq->q.id;
756 u8 sec_ctl = 0;
757 u8 sta_id = 0;
758 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
759 __le16 bc_ent;
760
761 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
762
763 if (txq_id != IWL_CMD_QUEUE_NUM) {
764 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
765 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
766
767 switch (sec_ctl & TX_CMD_SEC_MSK) {
768 case TX_CMD_SEC_CCM:
769 len += CCMP_MIC_LEN;
770 break;
771 case TX_CMD_SEC_TKIP:
772 len += TKIP_ICV_LEN;
773 break;
774 case TX_CMD_SEC_WEP:
775 len += WEP_IV_LEN + WEP_ICV_LEN;
776 break;
777 }
778 }
779
780 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
781
782 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
783
784 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
785 scd_bc_tbl[txq_id].
786 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
787 }
788
789 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
790 struct iwl_tx_queue *txq)
791 {
792 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
793 int txq_id = txq->q.id;
794 int read_ptr = txq->q.read_ptr;
795 u8 sta_id = 0;
796 __le16 bc_ent;
797
798 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
799
800 if (txq_id != IWL_CMD_QUEUE_NUM)
801 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
802
803 bc_ent = cpu_to_le16(1 | (sta_id << 12));
804 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
805
806 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
807 scd_bc_tbl[txq_id].
808 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
809 }
810
811 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
812 u16 txq_id)
813 {
814 u32 tbl_dw_addr;
815 u32 tbl_dw;
816 u16 scd_q2ratid;
817
818 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
819
820 tbl_dw_addr = priv->scd_base_addr +
821 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
822
823 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
824
825 if (txq_id & 0x1)
826 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
827 else
828 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
829
830 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
831
832 return 0;
833 }
834 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
835 {
836 /* Simply stop the queue, but don't change any configuration;
837 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
838 iwl_write_prph(priv,
839 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
840 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
841 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
842 }
843
844 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
845 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
846 {
847 unsigned long flags;
848 u16 ra_tid;
849
850 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
851 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
852 <= txq_id)) {
853 IWL_WARN(priv,
854 "queue number out of range: %d, must be %d to %d\n",
855 txq_id, IWL50_FIRST_AMPDU_QUEUE,
856 IWL50_FIRST_AMPDU_QUEUE +
857 priv->cfg->num_of_ampdu_queues - 1);
858 return -EINVAL;
859 }
860
861 ra_tid = BUILD_RAxTID(sta_id, tid);
862
863 /* Modify device's station table to Tx this TID */
864 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
865
866 spin_lock_irqsave(&priv->lock, flags);
867
868 /* Stop this Tx queue before configuring it */
869 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
870
871 /* Map receiver-address / traffic-ID to this queue */
872 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
873
874 /* Set this queue as a chain-building queue */
875 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
876
877 /* enable aggregations for the queue */
878 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
879
880 /* Place first TFD at index corresponding to start sequence number.
881 * Assumes that ssn_idx is valid (!= 0xFFF) */
882 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
883 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
884 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
885
886 /* Set up Tx window size and frame limit for this queue */
887 iwl_write_targ_mem(priv, priv->scd_base_addr +
888 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
889 sizeof(u32),
890 ((SCD_WIN_SIZE <<
891 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
892 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
893 ((SCD_FRAME_LIMIT <<
894 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
895 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
896
897 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
898
899 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
900 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
901
902 spin_unlock_irqrestore(&priv->lock, flags);
903
904 return 0;
905 }
906
907 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
908 u16 ssn_idx, u8 tx_fifo)
909 {
910 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
911 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
912 <= txq_id)) {
913 IWL_ERR(priv,
914 "queue number out of range: %d, must be %d to %d\n",
915 txq_id, IWL50_FIRST_AMPDU_QUEUE,
916 IWL50_FIRST_AMPDU_QUEUE +
917 priv->cfg->num_of_ampdu_queues - 1);
918 return -EINVAL;
919 }
920
921 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
922
923 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
924
925 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
926 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
927 /* supposes that ssn_idx is valid (!= 0xFFF) */
928 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
929
930 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
931 iwl_txq_ctx_deactivate(priv, txq_id);
932 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
933
934 return 0;
935 }
936
937 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
938 {
939 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
940 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
941 memcpy(addsta, cmd, size);
942 /* resrved in 5000 */
943 addsta->rate_n_flags = cpu_to_le16(0);
944 return size;
945 }
946
947
948 /*
949 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
950 * must be called under priv->lock and mac access
951 */
952 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
953 {
954 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
955 }
956
957
958 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
959 {
960 return le32_to_cpup((__le32 *)&tx_resp->status +
961 tx_resp->frame_count) & MAX_SN;
962 }
963
964 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
965 struct iwl_ht_agg *agg,
966 struct iwl5000_tx_resp *tx_resp,
967 int txq_id, u16 start_idx)
968 {
969 u16 status;
970 struct agg_tx_status *frame_status = &tx_resp->status;
971 struct ieee80211_tx_info *info = NULL;
972 struct ieee80211_hdr *hdr = NULL;
973 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
974 int i, sh, idx;
975 u16 seq;
976
977 if (agg->wait_for_ba)
978 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
979
980 agg->frame_count = tx_resp->frame_count;
981 agg->start_idx = start_idx;
982 agg->rate_n_flags = rate_n_flags;
983 agg->bitmap = 0;
984
985 /* # frames attempted by Tx command */
986 if (agg->frame_count == 1) {
987 /* Only one frame was attempted; no block-ack will arrive */
988 status = le16_to_cpu(frame_status[0].status);
989 idx = start_idx;
990
991 /* FIXME: code repetition */
992 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
993 agg->frame_count, agg->start_idx, idx);
994
995 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
996 info->status.rates[0].count = tx_resp->failure_frame + 1;
997 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
998 info->flags |= iwl_tx_status_to_mac80211(status);
999 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1000
1001 /* FIXME: code repetition end */
1002
1003 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1004 status & 0xff, tx_resp->failure_frame);
1005 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1006
1007 agg->wait_for_ba = 0;
1008 } else {
1009 /* Two or more frames were attempted; expect block-ack */
1010 u64 bitmap = 0;
1011 int start = agg->start_idx;
1012
1013 /* Construct bit-map of pending frames within Tx window */
1014 for (i = 0; i < agg->frame_count; i++) {
1015 u16 sc;
1016 status = le16_to_cpu(frame_status[i].status);
1017 seq = le16_to_cpu(frame_status[i].sequence);
1018 idx = SEQ_TO_INDEX(seq);
1019 txq_id = SEQ_TO_QUEUE(seq);
1020
1021 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1022 AGG_TX_STATE_ABORT_MSK))
1023 continue;
1024
1025 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1026 agg->frame_count, txq_id, idx);
1027
1028 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1029 if (!hdr) {
1030 IWL_ERR(priv,
1031 "BUG_ON idx doesn't point to valid skb"
1032 " idx=%d, txq_id=%d\n", idx, txq_id);
1033 return -1;
1034 }
1035
1036 sc = le16_to_cpu(hdr->seq_ctrl);
1037 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1038 IWL_ERR(priv,
1039 "BUG_ON idx doesn't match seq control"
1040 " idx=%d, seq_idx=%d, seq=%d\n",
1041 idx, SEQ_TO_SN(sc),
1042 hdr->seq_ctrl);
1043 return -1;
1044 }
1045
1046 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1047 i, idx, SEQ_TO_SN(sc));
1048
1049 sh = idx - start;
1050 if (sh > 64) {
1051 sh = (start - idx) + 0xff;
1052 bitmap = bitmap << sh;
1053 sh = 0;
1054 start = idx;
1055 } else if (sh < -64)
1056 sh = 0xff - (start - idx);
1057 else if (sh < 0) {
1058 sh = start - idx;
1059 start = idx;
1060 bitmap = bitmap << sh;
1061 sh = 0;
1062 }
1063 bitmap |= 1ULL << sh;
1064 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1065 start, (unsigned long long)bitmap);
1066 }
1067
1068 agg->bitmap = bitmap;
1069 agg->start_idx = start;
1070 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1071 agg->frame_count, agg->start_idx,
1072 (unsigned long long)agg->bitmap);
1073
1074 if (bitmap)
1075 agg->wait_for_ba = 1;
1076 }
1077 return 0;
1078 }
1079
1080 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1081 struct iwl_rx_mem_buffer *rxb)
1082 {
1083 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1084 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1085 int txq_id = SEQ_TO_QUEUE(sequence);
1086 int index = SEQ_TO_INDEX(sequence);
1087 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1088 struct ieee80211_tx_info *info;
1089 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1090 u32 status = le16_to_cpu(tx_resp->status.status);
1091 int tid;
1092 int sta_id;
1093 int freed;
1094
1095 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1096 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1097 "is out of range [0-%d] %d %d\n", txq_id,
1098 index, txq->q.n_bd, txq->q.write_ptr,
1099 txq->q.read_ptr);
1100 return;
1101 }
1102
1103 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1104 memset(&info->status, 0, sizeof(info->status));
1105
1106 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1107 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1108
1109 if (txq->sched_retry) {
1110 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1111 struct iwl_ht_agg *agg = NULL;
1112
1113 agg = &priv->stations[sta_id].tid[tid].agg;
1114
1115 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1116
1117 /* check if BAR is needed */
1118 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1119 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1120
1121 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1122 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1123 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1124 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1125 scd_ssn , index, txq_id, txq->swq_id);
1126
1127 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1128 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1129
1130 if (priv->mac80211_registered &&
1131 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1132 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1133 if (agg->state == IWL_AGG_OFF)
1134 iwl_wake_queue(priv, txq_id);
1135 else
1136 iwl_wake_queue(priv, txq->swq_id);
1137 }
1138 }
1139 } else {
1140 BUG_ON(txq_id != txq->swq_id);
1141
1142 info->status.rates[0].count = tx_resp->failure_frame + 1;
1143 info->flags |= iwl_tx_status_to_mac80211(status);
1144 iwl_hwrate_to_tx_control(priv,
1145 le32_to_cpu(tx_resp->rate_n_flags),
1146 info);
1147
1148 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1149 "0x%x retries %d\n",
1150 txq_id,
1151 iwl_get_tx_fail_reason(status), status,
1152 le32_to_cpu(tx_resp->rate_n_flags),
1153 tx_resp->failure_frame);
1154
1155 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1156 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1157 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1158
1159 if (priv->mac80211_registered &&
1160 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1161 iwl_wake_queue(priv, txq_id);
1162 }
1163
1164 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1165 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1166
1167 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1168 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1169 }
1170
1171 /* Currently 5000 is the superset of everything */
1172 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1173 {
1174 return len;
1175 }
1176
1177 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1178 {
1179 /* in 5000 the tx power calibration is done in uCode */
1180 priv->disable_tx_power_cal = 1;
1181 }
1182
1183 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1184 {
1185 /* init calibration handlers */
1186 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1187 iwl5000_rx_calib_result;
1188 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1189 iwl5000_rx_calib_complete;
1190 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1191 }
1192
1193
1194 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1195 {
1196 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1197 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1198 }
1199
1200 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1201 {
1202 int ret = 0;
1203 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1204 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1205 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1206
1207 if ((rxon1->flags == rxon2->flags) &&
1208 (rxon1->filter_flags == rxon2->filter_flags) &&
1209 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1210 (rxon1->ofdm_ht_single_stream_basic_rates ==
1211 rxon2->ofdm_ht_single_stream_basic_rates) &&
1212 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1213 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1214 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1215 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1216 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1217 (rxon1->rx_chain == rxon2->rx_chain) &&
1218 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1219 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1220 return 0;
1221 }
1222
1223 rxon_assoc.flags = priv->staging_rxon.flags;
1224 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1225 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1226 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1227 rxon_assoc.reserved1 = 0;
1228 rxon_assoc.reserved2 = 0;
1229 rxon_assoc.reserved3 = 0;
1230 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1231 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1232 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1233 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1234 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1235 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1236 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1237 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1238
1239 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1240 sizeof(rxon_assoc), &rxon_assoc, NULL);
1241 if (ret)
1242 return ret;
1243
1244 return ret;
1245 }
1246 int iwl5000_send_tx_power(struct iwl_priv *priv)
1247 {
1248 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1249 u8 tx_ant_cfg_cmd;
1250
1251 /* half dBm need to multiply */
1252 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1253
1254 if (priv->tx_power_lmt_in_half_dbm &&
1255 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
1256 /*
1257 * For the newer devices which using enhanced/extend tx power
1258 * table in EEPROM, the format is in half dBm. driver need to
1259 * convert to dBm format before report to mac80211.
1260 * By doing so, there is a possibility of 1/2 dBm resolution
1261 * lost. driver will perform "round-up" operation before
1262 * reporting, but it will cause 1/2 dBm tx power over the
1263 * regulatory limit. Perform the checking here, if the
1264 * "tx_power_user_lmt" is higher than EEPROM value (in
1265 * half-dBm format), lower the tx power based on EEPROM
1266 */
1267 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
1268 }
1269 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1270 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1271
1272 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1273 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1274 else
1275 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1276
1277 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1278 sizeof(tx_power_cmd), &tx_power_cmd,
1279 NULL);
1280 }
1281
1282 void iwl5000_temperature(struct iwl_priv *priv)
1283 {
1284 /* store temperature from statistics (in Celsius) */
1285 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1286 iwl_tt_handler(priv);
1287 }
1288
1289 static void iwl5150_temperature(struct iwl_priv *priv)
1290 {
1291 u32 vt = 0;
1292 s32 offset = iwl_temp_calib_to_offset(priv);
1293
1294 vt = le32_to_cpu(priv->statistics.general.temperature);
1295 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1296 /* now vt hold the temperature in Kelvin */
1297 priv->temperature = KELVIN_TO_CELSIUS(vt);
1298 iwl_tt_handler(priv);
1299 }
1300
1301 /* Calc max signal level (dBm) among 3 possible receivers */
1302 int iwl5000_calc_rssi(struct iwl_priv *priv,
1303 struct iwl_rx_phy_res *rx_resp)
1304 {
1305 /* data from PHY/DSP regarding signal strength, etc.,
1306 * contents are always there, not configurable by host
1307 */
1308 struct iwl5000_non_cfg_phy *ncphy =
1309 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1310 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1311 u8 agc;
1312
1313 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1314 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1315
1316 /* Find max rssi among 3 possible receivers.
1317 * These values are measured by the digital signal processor (DSP).
1318 * They should stay fairly constant even as the signal strength varies,
1319 * if the radio's automatic gain control (AGC) is working right.
1320 * AGC value (see below) will provide the "interesting" info.
1321 */
1322 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1323 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1324 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1325 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1326 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1327
1328 max_rssi = max_t(u32, rssi_a, rssi_b);
1329 max_rssi = max_t(u32, max_rssi, rssi_c);
1330
1331 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1332 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1333
1334 /* dBm = max_rssi dB - agc dB - constant.
1335 * Higher AGC (higher radio gain) means lower signal. */
1336 return max_rssi - agc - IWL49_RSSI_OFFSET;
1337 }
1338
1339 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1340 {
1341 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1342 .valid = cpu_to_le32(valid_tx_ant),
1343 };
1344
1345 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1346 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1347 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1348 sizeof(struct iwl_tx_ant_config_cmd),
1349 &tx_ant_cmd);
1350 } else {
1351 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1352 return -EOPNOTSUPP;
1353 }
1354 }
1355
1356
1357 #define IWL5000_UCODE_GET(item) \
1358 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1359 u32 api_ver) \
1360 { \
1361 if (api_ver <= 2) \
1362 return le32_to_cpu(ucode->u.v1.item); \
1363 return le32_to_cpu(ucode->u.v2.item); \
1364 }
1365
1366 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1367 {
1368 if (api_ver <= 2)
1369 return UCODE_HEADER_SIZE(1);
1370 return UCODE_HEADER_SIZE(2);
1371 }
1372
1373 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1374 u32 api_ver)
1375 {
1376 if (api_ver <= 2)
1377 return 0;
1378 return le32_to_cpu(ucode->u.v2.build);
1379 }
1380
1381 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1382 u32 api_ver)
1383 {
1384 if (api_ver <= 2)
1385 return (u8 *) ucode->u.v1.data;
1386 return (u8 *) ucode->u.v2.data;
1387 }
1388
1389 IWL5000_UCODE_GET(inst_size);
1390 IWL5000_UCODE_GET(data_size);
1391 IWL5000_UCODE_GET(init_size);
1392 IWL5000_UCODE_GET(init_data_size);
1393 IWL5000_UCODE_GET(boot_size);
1394
1395 static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1396 {
1397 struct iwl5000_channel_switch_cmd cmd;
1398 const struct iwl_channel_info *ch_info;
1399 struct iwl_host_cmd hcmd = {
1400 .id = REPLY_CHANNEL_SWITCH,
1401 .len = sizeof(cmd),
1402 .flags = CMD_SIZE_HUGE,
1403 .data = &cmd,
1404 };
1405
1406 IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1407 priv->active_rxon.channel, channel);
1408 cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1409 cmd.channel = cpu_to_le16(channel);
1410 cmd.rxon_flags = priv->staging_rxon.flags;
1411 cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1412 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1413 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1414 if (ch_info)
1415 cmd.expect_beacon = is_channel_radar(ch_info);
1416 else {
1417 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1418 priv->active_rxon.channel, channel);
1419 return -EFAULT;
1420 }
1421 priv->switch_rxon.channel = cpu_to_le16(channel);
1422 priv->switch_rxon.switch_in_progress = true;
1423
1424 return iwl_send_cmd_sync(priv, &hcmd);
1425 }
1426
1427 struct iwl_hcmd_ops iwl5000_hcmd = {
1428 .rxon_assoc = iwl5000_send_rxon_assoc,
1429 .commit_rxon = iwl_commit_rxon,
1430 .set_rxon_chain = iwl_set_rxon_chain,
1431 .set_tx_ant = iwl5000_send_tx_ant_config,
1432 };
1433
1434 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1435 .get_hcmd_size = iwl5000_get_hcmd_size,
1436 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1437 .gain_computation = iwl5000_gain_computation,
1438 .chain_noise_reset = iwl5000_chain_noise_reset,
1439 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1440 .calc_rssi = iwl5000_calc_rssi,
1441 };
1442
1443 struct iwl_ucode_ops iwl5000_ucode = {
1444 .get_header_size = iwl5000_ucode_get_header_size,
1445 .get_build = iwl5000_ucode_get_build,
1446 .get_inst_size = iwl5000_ucode_get_inst_size,
1447 .get_data_size = iwl5000_ucode_get_data_size,
1448 .get_init_size = iwl5000_ucode_get_init_size,
1449 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1450 .get_boot_size = iwl5000_ucode_get_boot_size,
1451 .get_data = iwl5000_ucode_get_data,
1452 };
1453
1454 struct iwl_lib_ops iwl5000_lib = {
1455 .set_hw_params = iwl5000_hw_set_hw_params,
1456 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1457 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1458 .txq_set_sched = iwl5000_txq_set_sched,
1459 .txq_agg_enable = iwl5000_txq_agg_enable,
1460 .txq_agg_disable = iwl5000_txq_agg_disable,
1461 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1462 .txq_free_tfd = iwl_hw_txq_free_tfd,
1463 .txq_init = iwl_hw_tx_queue_init,
1464 .rx_handler_setup = iwl5000_rx_handler_setup,
1465 .setup_deferred_work = iwl5000_setup_deferred_work,
1466 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1467 .dump_nic_event_log = iwl_dump_nic_event_log,
1468 .dump_nic_error_log = iwl_dump_nic_error_log,
1469 .load_ucode = iwl5000_load_ucode,
1470 .init_alive_start = iwl5000_init_alive_start,
1471 .alive_notify = iwl5000_alive_notify,
1472 .send_tx_power = iwl5000_send_tx_power,
1473 .update_chain_flags = iwl_update_chain_flags,
1474 .set_channel_switch = iwl5000_hw_channel_switch,
1475 .apm_ops = {
1476 .init = iwl_apm_init,
1477 .stop = iwl_apm_stop,
1478 .config = iwl5000_nic_config,
1479 .set_pwr_src = iwl_set_pwr_src,
1480 },
1481 .eeprom_ops = {
1482 .regulatory_bands = {
1483 EEPROM_5000_REG_BAND_1_CHANNELS,
1484 EEPROM_5000_REG_BAND_2_CHANNELS,
1485 EEPROM_5000_REG_BAND_3_CHANNELS,
1486 EEPROM_5000_REG_BAND_4_CHANNELS,
1487 EEPROM_5000_REG_BAND_5_CHANNELS,
1488 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1489 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1490 },
1491 .verify_signature = iwlcore_eeprom_verify_signature,
1492 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1493 .release_semaphore = iwlcore_eeprom_release_semaphore,
1494 .calib_version = iwl5000_eeprom_calib_version,
1495 .query_addr = iwl5000_eeprom_query_addr,
1496 },
1497 .post_associate = iwl_post_associate,
1498 .isr = iwl_isr_ict,
1499 .config_ap = iwl_config_ap,
1500 .temp_ops = {
1501 .temperature = iwl5000_temperature,
1502 .set_ct_kill = iwl5000_set_ct_threshold,
1503 },
1504 };
1505
1506 static struct iwl_lib_ops iwl5150_lib = {
1507 .set_hw_params = iwl5000_hw_set_hw_params,
1508 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1509 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1510 .txq_set_sched = iwl5000_txq_set_sched,
1511 .txq_agg_enable = iwl5000_txq_agg_enable,
1512 .txq_agg_disable = iwl5000_txq_agg_disable,
1513 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1514 .txq_free_tfd = iwl_hw_txq_free_tfd,
1515 .txq_init = iwl_hw_tx_queue_init,
1516 .rx_handler_setup = iwl5000_rx_handler_setup,
1517 .setup_deferred_work = iwl5000_setup_deferred_work,
1518 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1519 .dump_nic_event_log = iwl_dump_nic_event_log,
1520 .dump_nic_error_log = iwl_dump_nic_error_log,
1521 .load_ucode = iwl5000_load_ucode,
1522 .init_alive_start = iwl5000_init_alive_start,
1523 .alive_notify = iwl5000_alive_notify,
1524 .send_tx_power = iwl5000_send_tx_power,
1525 .update_chain_flags = iwl_update_chain_flags,
1526 .set_channel_switch = iwl5000_hw_channel_switch,
1527 .apm_ops = {
1528 .init = iwl_apm_init,
1529 .stop = iwl_apm_stop,
1530 .config = iwl5000_nic_config,
1531 .set_pwr_src = iwl_set_pwr_src,
1532 },
1533 .eeprom_ops = {
1534 .regulatory_bands = {
1535 EEPROM_5000_REG_BAND_1_CHANNELS,
1536 EEPROM_5000_REG_BAND_2_CHANNELS,
1537 EEPROM_5000_REG_BAND_3_CHANNELS,
1538 EEPROM_5000_REG_BAND_4_CHANNELS,
1539 EEPROM_5000_REG_BAND_5_CHANNELS,
1540 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1541 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1542 },
1543 .verify_signature = iwlcore_eeprom_verify_signature,
1544 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1545 .release_semaphore = iwlcore_eeprom_release_semaphore,
1546 .calib_version = iwl5000_eeprom_calib_version,
1547 .query_addr = iwl5000_eeprom_query_addr,
1548 },
1549 .post_associate = iwl_post_associate,
1550 .isr = iwl_isr_ict,
1551 .config_ap = iwl_config_ap,
1552 .temp_ops = {
1553 .temperature = iwl5150_temperature,
1554 .set_ct_kill = iwl5150_set_ct_threshold,
1555 },
1556 };
1557
1558 static struct iwl_ops iwl5000_ops = {
1559 .ucode = &iwl5000_ucode,
1560 .lib = &iwl5000_lib,
1561 .hcmd = &iwl5000_hcmd,
1562 .utils = &iwl5000_hcmd_utils,
1563 .led = &iwlagn_led_ops,
1564 };
1565
1566 static struct iwl_ops iwl5150_ops = {
1567 .ucode = &iwl5000_ucode,
1568 .lib = &iwl5150_lib,
1569 .hcmd = &iwl5000_hcmd,
1570 .utils = &iwl5000_hcmd_utils,
1571 .led = &iwlagn_led_ops,
1572 };
1573
1574 struct iwl_mod_params iwl50_mod_params = {
1575 .amsdu_size_8K = 1,
1576 .restart_fw = 1,
1577 /* the rest are 0 by default */
1578 };
1579
1580
1581 struct iwl_cfg iwl5300_agn_cfg = {
1582 .name = "5300AGN",
1583 .fw_name_pre = IWL5000_FW_PRE,
1584 .ucode_api_max = IWL5000_UCODE_API_MAX,
1585 .ucode_api_min = IWL5000_UCODE_API_MIN,
1586 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1587 .ops = &iwl5000_ops,
1588 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1589 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1590 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1591 .num_of_queues = IWL50_NUM_QUEUES,
1592 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1593 .mod_params = &iwl50_mod_params,
1594 .valid_tx_ant = ANT_ABC,
1595 .valid_rx_ant = ANT_ABC,
1596 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1597 .set_l0s = true,
1598 .use_bsm = false,
1599 .ht_greenfield_support = true,
1600 .led_compensation = 51,
1601 .use_rts_for_ht = true, /* use rts/cts protection */
1602 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1603 .sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1604 };
1605
1606 struct iwl_cfg iwl5100_bgn_cfg = {
1607 .name = "5100BGN",
1608 .fw_name_pre = IWL5000_FW_PRE,
1609 .ucode_api_max = IWL5000_UCODE_API_MAX,
1610 .ucode_api_min = IWL5000_UCODE_API_MIN,
1611 .sku = IWL_SKU_G|IWL_SKU_N,
1612 .ops = &iwl5000_ops,
1613 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1614 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1615 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1616 .num_of_queues = IWL50_NUM_QUEUES,
1617 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1618 .mod_params = &iwl50_mod_params,
1619 .valid_tx_ant = ANT_B,
1620 .valid_rx_ant = ANT_AB,
1621 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1622 .set_l0s = true,
1623 .use_bsm = false,
1624 .ht_greenfield_support = true,
1625 .led_compensation = 51,
1626 .use_rts_for_ht = true, /* use rts/cts protection */
1627 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1628 };
1629
1630 struct iwl_cfg iwl5100_abg_cfg = {
1631 .name = "5100ABG",
1632 .fw_name_pre = IWL5000_FW_PRE,
1633 .ucode_api_max = IWL5000_UCODE_API_MAX,
1634 .ucode_api_min = IWL5000_UCODE_API_MIN,
1635 .sku = IWL_SKU_A|IWL_SKU_G,
1636 .ops = &iwl5000_ops,
1637 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1638 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1639 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1640 .num_of_queues = IWL50_NUM_QUEUES,
1641 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1642 .mod_params = &iwl50_mod_params,
1643 .valid_tx_ant = ANT_B,
1644 .valid_rx_ant = ANT_AB,
1645 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1646 .set_l0s = true,
1647 .use_bsm = false,
1648 .led_compensation = 51,
1649 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1650 };
1651
1652 struct iwl_cfg iwl5100_agn_cfg = {
1653 .name = "5100AGN",
1654 .fw_name_pre = IWL5000_FW_PRE,
1655 .ucode_api_max = IWL5000_UCODE_API_MAX,
1656 .ucode_api_min = IWL5000_UCODE_API_MIN,
1657 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1658 .ops = &iwl5000_ops,
1659 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1660 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1661 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1662 .num_of_queues = IWL50_NUM_QUEUES,
1663 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1664 .mod_params = &iwl50_mod_params,
1665 .valid_tx_ant = ANT_B,
1666 .valid_rx_ant = ANT_AB,
1667 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1668 .set_l0s = true,
1669 .use_bsm = false,
1670 .ht_greenfield_support = true,
1671 .led_compensation = 51,
1672 .use_rts_for_ht = true, /* use rts/cts protection */
1673 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1674 .sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1675 };
1676
1677 struct iwl_cfg iwl5350_agn_cfg = {
1678 .name = "5350AGN",
1679 .fw_name_pre = IWL5000_FW_PRE,
1680 .ucode_api_max = IWL5000_UCODE_API_MAX,
1681 .ucode_api_min = IWL5000_UCODE_API_MIN,
1682 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1683 .ops = &iwl5000_ops,
1684 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1685 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1686 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1687 .num_of_queues = IWL50_NUM_QUEUES,
1688 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1689 .mod_params = &iwl50_mod_params,
1690 .valid_tx_ant = ANT_ABC,
1691 .valid_rx_ant = ANT_ABC,
1692 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1693 .set_l0s = true,
1694 .use_bsm = false,
1695 .ht_greenfield_support = true,
1696 .led_compensation = 51,
1697 .use_rts_for_ht = true, /* use rts/cts protection */
1698 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1699 .sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1700 };
1701
1702 struct iwl_cfg iwl5150_agn_cfg = {
1703 .name = "5150AGN",
1704 .fw_name_pre = IWL5150_FW_PRE,
1705 .ucode_api_max = IWL5150_UCODE_API_MAX,
1706 .ucode_api_min = IWL5150_UCODE_API_MIN,
1707 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1708 .ops = &iwl5150_ops,
1709 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1710 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1711 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1712 .num_of_queues = IWL50_NUM_QUEUES,
1713 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1714 .mod_params = &iwl50_mod_params,
1715 .valid_tx_ant = ANT_A,
1716 .valid_rx_ant = ANT_AB,
1717 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1718 .set_l0s = true,
1719 .use_bsm = false,
1720 .ht_greenfield_support = true,
1721 .led_compensation = 51,
1722 .use_rts_for_ht = true, /* use rts/cts protection */
1723 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1724 .sm_ps_mode = WLAN_HT_CAP_SM_PS_DISABLED,
1725 };
1726
1727 struct iwl_cfg iwl5150_abg_cfg = {
1728 .name = "5150ABG",
1729 .fw_name_pre = IWL5150_FW_PRE,
1730 .ucode_api_max = IWL5150_UCODE_API_MAX,
1731 .ucode_api_min = IWL5150_UCODE_API_MIN,
1732 .sku = IWL_SKU_A|IWL_SKU_G,
1733 .ops = &iwl5150_ops,
1734 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1735 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1736 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1737 .num_of_queues = IWL50_NUM_QUEUES,
1738 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1739 .mod_params = &iwl50_mod_params,
1740 .valid_tx_ant = ANT_A,
1741 .valid_rx_ant = ANT_AB,
1742 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1743 .set_l0s = true,
1744 .use_bsm = false,
1745 .led_compensation = 51,
1746 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1747 };
1748
1749 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1750 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1751
1752 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1753 MODULE_PARM_DESC(swcrypto50,
1754 "using software crypto engine (default 0 [hardware])\n");
1755 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1756 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1757 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1758 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1759 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1760 int, S_IRUGO);
1761 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1762 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1763 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
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