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1710815691d54ee2cae1ca4b051397af5e2c3b60
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/delay.h>
36 #include <linux/skbuff.h>
37 #include <linux/netdevice.h>
38 #include <linux/wireless.h>
39 #include <linux/firmware.h>
40 #include <linux/etherdevice.h>
41 #include <linux/if_arp.h>
42
43 #include <net/mac80211.h>
44
45 #include <asm/div64.h>
46
47 #define DRV_NAME "iwlagn"
48
49 #include "iwl-eeprom.h"
50 #include "iwl-dev.h"
51 #include "iwl-core.h"
52 #include "iwl-io.h"
53 #include "iwl-helpers.h"
54 #include "iwl-sta.h"
55 #include "iwl-calib.h"
56
57
58 /******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
64 /*
65 * module name, copyright, version, etc.
66 */
67 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
68
69 #ifdef CONFIG_IWLWIFI_DEBUG
70 #define VD "d"
71 #else
72 #define VD
73 #endif
74
75 #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
76 #define VS "s"
77 #else
78 #define VS
79 #endif
80
81 #define DRV_VERSION IWLWIFI_VERSION VD VS
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88 MODULE_ALIAS("iwl4965");
89
90 /*************** STATION TABLE MANAGEMENT ****
91 * mac80211 should be examined to determine if sta_info is duplicating
92 * the functionality provided here
93 */
94
95 /**************************************************************/
96
97 /**
98 * iwl_commit_rxon - commit staging_rxon to hardware
99 *
100 * The RXON command in staging_rxon is committed to the hardware and
101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
105 int iwl_commit_rxon(struct iwl_priv *priv)
106 {
107 /* cast away the const for active_rxon in this function */
108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
112
113 if (!iwl_is_alive(priv))
114 return -EBUSY;
115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
118
119 ret = iwl_check_rxon_cmd(priv);
120 if (ret) {
121 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
122 return -EINVAL;
123 }
124
125 /* If we don't need to send a full RXON, we can use
126 * iwl_rxon_assoc_cmd which is used to reconfigure filter
127 * and other flags for the current radio configuration. */
128 if (!iwl_full_rxon_required(priv)) {
129 ret = iwl_send_rxon_assoc(priv);
130 if (ret) {
131 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
132 return ret;
133 }
134
135 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
136 iwl_print_rx_config_cmd(priv);
137 return 0;
138 }
139
140 /* station table will be cleared */
141 priv->assoc_station_added = 0;
142
143 /* If we are currently associated and the new config requires
144 * an RXON_ASSOC and the new config wants the associated mask enabled,
145 * we must clear the associated from the active configuration
146 * before we apply the new config */
147 if (iwl_is_associated(priv) && new_assoc) {
148 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
149 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
150
151 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
152 sizeof(struct iwl_rxon_cmd),
153 &priv->active_rxon);
154
155 /* If the mask clearing failed then we set
156 * active_rxon back to what it was previously */
157 if (ret) {
158 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
159 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
160 return ret;
161 }
162 }
163
164 IWL_DEBUG_INFO(priv, "Sending RXON\n"
165 "* with%s RXON_FILTER_ASSOC_MSK\n"
166 "* channel = %d\n"
167 "* bssid = %pM\n",
168 (new_assoc ? "" : "out"),
169 le16_to_cpu(priv->staging_rxon.channel),
170 priv->staging_rxon.bssid_addr);
171
172 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
173
174 /* Apply the new configuration
175 * RXON unassoc clears the station table in uCode, send it before
176 * we add the bcast station. If assoc bit is set, we will send RXON
177 * after having added the bcast and bssid station.
178 */
179 if (!new_assoc) {
180 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
181 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
182 if (ret) {
183 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
184 return ret;
185 }
186 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
187 }
188
189 iwl_clear_stations_table(priv);
190
191 priv->start_calib = 0;
192
193 /* Add the broadcast address so we can send broadcast frames */
194 iwl_add_bcast_station(priv);
195
196 /* If we have set the ASSOC_MSK and we are in BSS mode then
197 * add the IWL_AP_ID to the station rate table */
198 if (new_assoc) {
199 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
200 ret = iwl_rxon_add_station(priv,
201 priv->active_rxon.bssid_addr, 1);
202 if (ret == IWL_INVALID_STATION) {
203 IWL_ERR(priv,
204 "Error adding AP address for TX.\n");
205 return -EIO;
206 }
207 priv->assoc_station_added = 1;
208 if (priv->default_wep_key &&
209 iwl_send_static_wepkey_cmd(priv, 0))
210 IWL_ERR(priv,
211 "Could not send WEP static key.\n");
212 }
213
214 /*
215 * allow CTS-to-self if possible for new association.
216 * this is relevant only for 5000 series and up,
217 * but will not damage 4965
218 */
219 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
220
221 /* Apply the new configuration
222 * RXON assoc doesn't clear the station table in uCode,
223 */
224 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
225 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
226 if (ret) {
227 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
228 return ret;
229 }
230 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
231 }
232 iwl_print_rx_config_cmd(priv);
233
234 iwl_init_sensitivity(priv);
235
236 /* If we issue a new RXON command which required a tune then we must
237 * send a new TXPOWER command or we won't be able to Tx any frames */
238 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
239 if (ret) {
240 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
241 return ret;
242 }
243
244 return 0;
245 }
246
247 void iwl_update_chain_flags(struct iwl_priv *priv)
248 {
249
250 if (priv->cfg->ops->hcmd->set_rxon_chain)
251 priv->cfg->ops->hcmd->set_rxon_chain(priv);
252 iwlcore_commit_rxon(priv);
253 }
254
255 static void iwl_clear_free_frames(struct iwl_priv *priv)
256 {
257 struct list_head *element;
258
259 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
260 priv->frames_count);
261
262 while (!list_empty(&priv->free_frames)) {
263 element = priv->free_frames.next;
264 list_del(element);
265 kfree(list_entry(element, struct iwl_frame, list));
266 priv->frames_count--;
267 }
268
269 if (priv->frames_count) {
270 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
271 priv->frames_count);
272 priv->frames_count = 0;
273 }
274 }
275
276 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
277 {
278 struct iwl_frame *frame;
279 struct list_head *element;
280 if (list_empty(&priv->free_frames)) {
281 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
282 if (!frame) {
283 IWL_ERR(priv, "Could not allocate frame!\n");
284 return NULL;
285 }
286
287 priv->frames_count++;
288 return frame;
289 }
290
291 element = priv->free_frames.next;
292 list_del(element);
293 return list_entry(element, struct iwl_frame, list);
294 }
295
296 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
297 {
298 memset(frame, 0, sizeof(*frame));
299 list_add(&frame->list, &priv->free_frames);
300 }
301
302 static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
303 struct ieee80211_hdr *hdr,
304 int left)
305 {
306 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
307 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
308 (priv->iw_mode != NL80211_IFTYPE_AP)))
309 return 0;
310
311 if (priv->ibss_beacon->len > left)
312 return 0;
313
314 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
315
316 return priv->ibss_beacon->len;
317 }
318
319 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
320 struct iwl_frame *frame, u8 rate)
321 {
322 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
323 unsigned int frame_size;
324
325 tx_beacon_cmd = &frame->u.beacon;
326 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
327
328 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
329 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
330
331 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
332 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
333
334 BUG_ON(frame_size > MAX_MPDU_SIZE);
335 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
336
337 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
338 tx_beacon_cmd->tx.rate_n_flags =
339 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
340 else
341 tx_beacon_cmd->tx.rate_n_flags =
342 iwl_hw_set_rate_n_flags(rate, 0);
343
344 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
345 TX_CMD_FLG_TSF_MSK |
346 TX_CMD_FLG_STA_RATE_MSK;
347
348 return sizeof(*tx_beacon_cmd) + frame_size;
349 }
350 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
351 {
352 struct iwl_frame *frame;
353 unsigned int frame_size;
354 int rc;
355 u8 rate;
356
357 frame = iwl_get_free_frame(priv);
358
359 if (!frame) {
360 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
361 "command.\n");
362 return -ENOMEM;
363 }
364
365 rate = iwl_rate_get_lowest_plcp(priv);
366
367 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
368
369 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
370 &frame->u.cmd[0]);
371
372 iwl_free_frame(priv, frame);
373
374 return rc;
375 }
376
377 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
378 {
379 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
380
381 dma_addr_t addr = get_unaligned_le32(&tb->lo);
382 if (sizeof(dma_addr_t) > sizeof(u32))
383 addr |=
384 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
385
386 return addr;
387 }
388
389 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
390 {
391 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
392
393 return le16_to_cpu(tb->hi_n_len) >> 4;
394 }
395
396 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
397 dma_addr_t addr, u16 len)
398 {
399 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
400 u16 hi_n_len = len << 4;
401
402 put_unaligned_le32(addr, &tb->lo);
403 if (sizeof(dma_addr_t) > sizeof(u32))
404 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
405
406 tb->hi_n_len = cpu_to_le16(hi_n_len);
407
408 tfd->num_tbs = idx + 1;
409 }
410
411 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
412 {
413 return tfd->num_tbs & 0x1f;
414 }
415
416 /**
417 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
418 * @priv - driver private data
419 * @txq - tx queue
420 *
421 * Does NOT advance any TFD circular buffer read/write indexes
422 * Does NOT free the TFD itself (which is within circular buffer)
423 */
424 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
425 {
426 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
427 struct iwl_tfd *tfd;
428 struct pci_dev *dev = priv->pci_dev;
429 int index = txq->q.read_ptr;
430 int i;
431 int num_tbs;
432
433 tfd = &tfd_tmp[index];
434
435 /* Sanity check on number of chunks */
436 num_tbs = iwl_tfd_get_num_tbs(tfd);
437
438 if (num_tbs >= IWL_NUM_OF_TBS) {
439 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
440 /* @todo issue fatal error, it is quite serious situation */
441 return;
442 }
443
444 /* Unmap tx_cmd */
445 if (num_tbs)
446 pci_unmap_single(dev,
447 pci_unmap_addr(&txq->meta[index], mapping),
448 pci_unmap_len(&txq->meta[index], len),
449 PCI_DMA_BIDIRECTIONAL);
450
451 /* Unmap chunks, if any. */
452 for (i = 1; i < num_tbs; i++) {
453 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
454 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
455
456 if (txq->txb) {
457 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
458 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
459 }
460 }
461 }
462
463 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
464 struct iwl_tx_queue *txq,
465 dma_addr_t addr, u16 len,
466 u8 reset, u8 pad)
467 {
468 struct iwl_queue *q;
469 struct iwl_tfd *tfd, *tfd_tmp;
470 u32 num_tbs;
471
472 q = &txq->q;
473 tfd_tmp = (struct iwl_tfd *)txq->tfds;
474 tfd = &tfd_tmp[q->write_ptr];
475
476 if (reset)
477 memset(tfd, 0, sizeof(*tfd));
478
479 num_tbs = iwl_tfd_get_num_tbs(tfd);
480
481 /* Each TFD can point to a maximum 20 Tx buffers */
482 if (num_tbs >= IWL_NUM_OF_TBS) {
483 IWL_ERR(priv, "Error can not send more than %d chunks\n",
484 IWL_NUM_OF_TBS);
485 return -EINVAL;
486 }
487
488 BUG_ON(addr & ~DMA_BIT_MASK(36));
489 if (unlikely(addr & ~IWL_TX_DMA_MASK))
490 IWL_ERR(priv, "Unaligned address = %llx\n",
491 (unsigned long long)addr);
492
493 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
494
495 return 0;
496 }
497
498 /*
499 * Tell nic where to find circular buffer of Tx Frame Descriptors for
500 * given Tx queue, and enable the DMA channel used for that queue.
501 *
502 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
503 * channels supported in hardware.
504 */
505 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
506 struct iwl_tx_queue *txq)
507 {
508 int txq_id = txq->q.id;
509
510 /* Circular buffer (TFD queue in DRAM) physical base address */
511 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
512 txq->q.dma_addr >> 8);
513
514 return 0;
515 }
516
517 /******************************************************************************
518 *
519 * Generic RX handler implementations
520 *
521 ******************************************************************************/
522 static void iwl_rx_reply_alive(struct iwl_priv *priv,
523 struct iwl_rx_mem_buffer *rxb)
524 {
525 struct iwl_rx_packet *pkt = rxb_addr(rxb);
526 struct iwl_alive_resp *palive;
527 struct delayed_work *pwork;
528
529 palive = &pkt->u.alive_frame;
530
531 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
532 "0x%01X 0x%01X\n",
533 palive->is_valid, palive->ver_type,
534 palive->ver_subtype);
535
536 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
537 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
538 memcpy(&priv->card_alive_init,
539 &pkt->u.alive_frame,
540 sizeof(struct iwl_init_alive_resp));
541 pwork = &priv->init_alive_start;
542 } else {
543 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
544 memcpy(&priv->card_alive, &pkt->u.alive_frame,
545 sizeof(struct iwl_alive_resp));
546 pwork = &priv->alive_start;
547 }
548
549 /* We delay the ALIVE response by 5ms to
550 * give the HW RF Kill time to activate... */
551 if (palive->is_valid == UCODE_VALID_OK)
552 queue_delayed_work(priv->workqueue, pwork,
553 msecs_to_jiffies(5));
554 else
555 IWL_WARN(priv, "uCode did not respond OK.\n");
556 }
557
558 static void iwl_bg_beacon_update(struct work_struct *work)
559 {
560 struct iwl_priv *priv =
561 container_of(work, struct iwl_priv, beacon_update);
562 struct sk_buff *beacon;
563
564 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
565 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
566
567 if (!beacon) {
568 IWL_ERR(priv, "update beacon failed\n");
569 return;
570 }
571
572 mutex_lock(&priv->mutex);
573 /* new beacon skb is allocated every time; dispose previous.*/
574 if (priv->ibss_beacon)
575 dev_kfree_skb(priv->ibss_beacon);
576
577 priv->ibss_beacon = beacon;
578 mutex_unlock(&priv->mutex);
579
580 iwl_send_beacon_cmd(priv);
581 }
582
583 /**
584 * iwl_bg_statistics_periodic - Timer callback to queue statistics
585 *
586 * This callback is provided in order to send a statistics request.
587 *
588 * This timer function is continually reset to execute within
589 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
590 * was received. We need to ensure we receive the statistics in order
591 * to update the temperature used for calibrating the TXPOWER.
592 */
593 static void iwl_bg_statistics_periodic(unsigned long data)
594 {
595 struct iwl_priv *priv = (struct iwl_priv *)data;
596
597 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
598 return;
599
600 /* dont send host command if rf-kill is on */
601 if (!iwl_is_ready_rf(priv))
602 return;
603
604 iwl_send_statistics_request(priv, CMD_ASYNC);
605 }
606
607 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
608 struct iwl_rx_mem_buffer *rxb)
609 {
610 #ifdef CONFIG_IWLWIFI_DEBUG
611 struct iwl_rx_packet *pkt = rxb_addr(rxb);
612 struct iwl4965_beacon_notif *beacon =
613 (struct iwl4965_beacon_notif *)pkt->u.raw;
614 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
615
616 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
617 "tsf %d %d rate %d\n",
618 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
619 beacon->beacon_notify_hdr.failure_frame,
620 le32_to_cpu(beacon->ibss_mgr_status),
621 le32_to_cpu(beacon->high_tsf),
622 le32_to_cpu(beacon->low_tsf), rate);
623 #endif
624
625 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
626 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
627 queue_work(priv->workqueue, &priv->beacon_update);
628 }
629
630 /* Handle notification from uCode that card's power state is changing
631 * due to software, hardware, or critical temperature RFKILL */
632 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
633 struct iwl_rx_mem_buffer *rxb)
634 {
635 struct iwl_rx_packet *pkt = rxb_addr(rxb);
636 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
637 unsigned long status = priv->status;
638
639 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
640 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
641 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
642
643 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
644 RF_CARD_DISABLED)) {
645
646 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
647 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
648
649 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
650 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
651
652 if (!(flags & RXON_CARD_DISABLED)) {
653 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
654 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
655 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
656 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
657 }
658 if (flags & RF_CARD_DISABLED)
659 iwl_tt_enter_ct_kill(priv);
660 }
661 if (!(flags & RF_CARD_DISABLED))
662 iwl_tt_exit_ct_kill(priv);
663
664 if (flags & HW_CARD_DISABLED)
665 set_bit(STATUS_RF_KILL_HW, &priv->status);
666 else
667 clear_bit(STATUS_RF_KILL_HW, &priv->status);
668
669
670 if (!(flags & RXON_CARD_DISABLED))
671 iwl_scan_cancel(priv);
672
673 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
674 test_bit(STATUS_RF_KILL_HW, &priv->status)))
675 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
676 test_bit(STATUS_RF_KILL_HW, &priv->status));
677 else
678 wake_up_interruptible(&priv->wait_command_queue);
679 }
680
681 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
682 {
683 if (src == IWL_PWR_SRC_VAUX) {
684 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
685 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
686 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
687 ~APMG_PS_CTRL_MSK_PWR_SRC);
688 } else {
689 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
690 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
691 ~APMG_PS_CTRL_MSK_PWR_SRC);
692 }
693
694 return 0;
695 }
696
697 /**
698 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
699 *
700 * Setup the RX handlers for each of the reply types sent from the uCode
701 * to the host.
702 *
703 * This function chains into the hardware specific files for them to setup
704 * any hardware specific handlers as well.
705 */
706 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
707 {
708 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
709 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
710 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
711 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
712 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
713 iwl_rx_pm_debug_statistics_notif;
714 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
715
716 /*
717 * The same handler is used for both the REPLY to a discrete
718 * statistics request from the host as well as for the periodic
719 * statistics notifications (after received beacons) from the uCode.
720 */
721 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
722 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
723
724 iwl_setup_spectrum_handlers(priv);
725 iwl_setup_rx_scan_handlers(priv);
726
727 /* status change handler */
728 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
729
730 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
731 iwl_rx_missed_beacon_notif;
732 /* Rx handlers */
733 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
734 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
735 /* block ack */
736 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
737 /* Set up hardware specific Rx handlers */
738 priv->cfg->ops->lib->rx_handler_setup(priv);
739 }
740
741 /**
742 * iwl_rx_handle - Main entry function for receiving responses from uCode
743 *
744 * Uses the priv->rx_handlers callback function array to invoke
745 * the appropriate handlers, including command responses,
746 * frame-received notifications, and other notifications.
747 */
748 void iwl_rx_handle(struct iwl_priv *priv)
749 {
750 struct iwl_rx_mem_buffer *rxb;
751 struct iwl_rx_packet *pkt;
752 struct iwl_rx_queue *rxq = &priv->rxq;
753 u32 r, i;
754 int reclaim;
755 unsigned long flags;
756 u8 fill_rx = 0;
757 u32 count = 8;
758 int total_empty;
759
760 /* uCode's read index (stored in shared DRAM) indicates the last Rx
761 * buffer that the driver may process (last buffer filled by ucode). */
762 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
763 i = rxq->read;
764
765 /* Rx interrupt, but nothing sent from uCode */
766 if (i == r)
767 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
768
769 /* calculate total frames need to be restock after handling RX */
770 total_empty = r - rxq->write_actual;
771 if (total_empty < 0)
772 total_empty += RX_QUEUE_SIZE;
773
774 if (total_empty > (RX_QUEUE_SIZE / 2))
775 fill_rx = 1;
776
777 while (i != r) {
778 rxb = rxq->queue[i];
779
780 /* If an RXB doesn't have a Rx queue slot associated with it,
781 * then a bug has been introduced in the queue refilling
782 * routines -- catch it here */
783 BUG_ON(rxb == NULL);
784
785 rxq->queue[i] = NULL;
786
787 pci_unmap_page(priv->pci_dev, rxb->page_dma,
788 PAGE_SIZE << priv->hw_params.rx_page_order,
789 PCI_DMA_FROMDEVICE);
790 pkt = rxb_addr(rxb);
791
792 trace_iwlwifi_dev_rx(priv, pkt,
793 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
794
795 /* Reclaim a command buffer only if this packet is a response
796 * to a (driver-originated) command.
797 * If the packet (e.g. Rx frame) originated from uCode,
798 * there is no command buffer to reclaim.
799 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
800 * but apparently a few don't get set; catch them here. */
801 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
802 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
803 (pkt->hdr.cmd != REPLY_RX) &&
804 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
805 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
806 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
807 (pkt->hdr.cmd != REPLY_TX);
808
809 /* Based on type of command response or notification,
810 * handle those that need handling via function in
811 * rx_handlers table. See iwl_setup_rx_handlers() */
812 if (priv->rx_handlers[pkt->hdr.cmd]) {
813 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
814 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
815 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
816 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
817 } else {
818 /* No handling needed */
819 IWL_DEBUG_RX(priv,
820 "r %d i %d No handler needed for %s, 0x%02x\n",
821 r, i, get_cmd_string(pkt->hdr.cmd),
822 pkt->hdr.cmd);
823 }
824
825 /*
826 * XXX: After here, we should always check rxb->page
827 * against NULL before touching it or its virtual
828 * memory (pkt). Because some rx_handler might have
829 * already taken or freed the pages.
830 */
831
832 if (reclaim) {
833 /* Invoke any callbacks, transfer the buffer to caller,
834 * and fire off the (possibly) blocking iwl_send_cmd()
835 * as we reclaim the driver command queue */
836 if (rxb->page)
837 iwl_tx_cmd_complete(priv, rxb);
838 else
839 IWL_WARN(priv, "Claim null rxb?\n");
840 }
841
842 /* Reuse the page if possible. For notification packets and
843 * SKBs that fail to Rx correctly, add them back into the
844 * rx_free list for reuse later. */
845 spin_lock_irqsave(&rxq->lock, flags);
846 if (rxb->page != NULL) {
847 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
848 0, PAGE_SIZE << priv->hw_params.rx_page_order,
849 PCI_DMA_FROMDEVICE);
850 list_add_tail(&rxb->list, &rxq->rx_free);
851 rxq->free_count++;
852 } else
853 list_add_tail(&rxb->list, &rxq->rx_used);
854
855 spin_unlock_irqrestore(&rxq->lock, flags);
856
857 i = (i + 1) & RX_QUEUE_MASK;
858 /* If there are a lot of unused frames,
859 * restock the Rx queue so ucode wont assert. */
860 if (fill_rx) {
861 count++;
862 if (count >= 8) {
863 rxq->read = i;
864 iwl_rx_replenish_now(priv);
865 count = 0;
866 }
867 }
868 }
869
870 /* Backtrack one entry */
871 rxq->read = i;
872 if (fill_rx)
873 iwl_rx_replenish_now(priv);
874 else
875 iwl_rx_queue_restock(priv);
876 }
877
878 /* call this function to flush any scheduled tasklet */
879 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
880 {
881 /* wait to make sure we flush pending tasklet*/
882 synchronize_irq(priv->pci_dev->irq);
883 tasklet_kill(&priv->irq_tasklet);
884 }
885
886 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
887 {
888 u32 inta, handled = 0;
889 u32 inta_fh;
890 unsigned long flags;
891 u32 i;
892 #ifdef CONFIG_IWLWIFI_DEBUG
893 u32 inta_mask;
894 #endif
895
896 spin_lock_irqsave(&priv->lock, flags);
897
898 /* Ack/clear/reset pending uCode interrupts.
899 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
900 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
901 inta = iwl_read32(priv, CSR_INT);
902 iwl_write32(priv, CSR_INT, inta);
903
904 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
905 * Any new interrupts that happen after this, either while we're
906 * in this tasklet, or later, will show up in next ISR/tasklet. */
907 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
908 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
909
910 #ifdef CONFIG_IWLWIFI_DEBUG
911 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
912 /* just for debug */
913 inta_mask = iwl_read32(priv, CSR_INT_MASK);
914 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
915 inta, inta_mask, inta_fh);
916 }
917 #endif
918
919 spin_unlock_irqrestore(&priv->lock, flags);
920
921 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
922 * atomic, make sure that inta covers all the interrupts that
923 * we've discovered, even if FH interrupt came in just after
924 * reading CSR_INT. */
925 if (inta_fh & CSR49_FH_INT_RX_MASK)
926 inta |= CSR_INT_BIT_FH_RX;
927 if (inta_fh & CSR49_FH_INT_TX_MASK)
928 inta |= CSR_INT_BIT_FH_TX;
929
930 /* Now service all interrupt bits discovered above. */
931 if (inta & CSR_INT_BIT_HW_ERR) {
932 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
933
934 /* Tell the device to stop sending interrupts */
935 iwl_disable_interrupts(priv);
936
937 priv->isr_stats.hw++;
938 iwl_irq_handle_error(priv);
939
940 handled |= CSR_INT_BIT_HW_ERR;
941
942 return;
943 }
944
945 #ifdef CONFIG_IWLWIFI_DEBUG
946 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
947 /* NIC fires this, but we don't use it, redundant with WAKEUP */
948 if (inta & CSR_INT_BIT_SCD) {
949 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
950 "the frame/frames.\n");
951 priv->isr_stats.sch++;
952 }
953
954 /* Alive notification via Rx interrupt will do the real work */
955 if (inta & CSR_INT_BIT_ALIVE) {
956 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
957 priv->isr_stats.alive++;
958 }
959 }
960 #endif
961 /* Safely ignore these bits for debug checks below */
962 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
963
964 /* HW RF KILL switch toggled */
965 if (inta & CSR_INT_BIT_RF_KILL) {
966 int hw_rf_kill = 0;
967 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
968 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
969 hw_rf_kill = 1;
970
971 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
972 hw_rf_kill ? "disable radio" : "enable radio");
973
974 priv->isr_stats.rfkill++;
975
976 /* driver only loads ucode once setting the interface up.
977 * the driver allows loading the ucode even if the radio
978 * is killed. Hence update the killswitch state here. The
979 * rfkill handler will care about restarting if needed.
980 */
981 if (!test_bit(STATUS_ALIVE, &priv->status)) {
982 if (hw_rf_kill)
983 set_bit(STATUS_RF_KILL_HW, &priv->status);
984 else
985 clear_bit(STATUS_RF_KILL_HW, &priv->status);
986 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
987 }
988
989 handled |= CSR_INT_BIT_RF_KILL;
990 }
991
992 /* Chip got too hot and stopped itself */
993 if (inta & CSR_INT_BIT_CT_KILL) {
994 IWL_ERR(priv, "Microcode CT kill error detected.\n");
995 priv->isr_stats.ctkill++;
996 handled |= CSR_INT_BIT_CT_KILL;
997 }
998
999 /* Error detected by uCode */
1000 if (inta & CSR_INT_BIT_SW_ERR) {
1001 IWL_ERR(priv, "Microcode SW error detected. "
1002 " Restarting 0x%X.\n", inta);
1003 priv->isr_stats.sw++;
1004 priv->isr_stats.sw_err = inta;
1005 iwl_irq_handle_error(priv);
1006 handled |= CSR_INT_BIT_SW_ERR;
1007 }
1008
1009 /*
1010 * uCode wakes up after power-down sleep.
1011 * Tell device about any new tx or host commands enqueued,
1012 * and about any Rx buffers made available while asleep.
1013 */
1014 if (inta & CSR_INT_BIT_WAKEUP) {
1015 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1016 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1017 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1018 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1019 priv->isr_stats.wakeup++;
1020 handled |= CSR_INT_BIT_WAKEUP;
1021 }
1022
1023 /* All uCode command responses, including Tx command responses,
1024 * Rx "responses" (frame-received notification), and other
1025 * notifications from uCode come through here*/
1026 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1027 iwl_rx_handle(priv);
1028 priv->isr_stats.rx++;
1029 iwl_leds_background(priv);
1030 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1031 }
1032
1033 /* This "Tx" DMA channel is used only for loading uCode */
1034 if (inta & CSR_INT_BIT_FH_TX) {
1035 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1036 priv->isr_stats.tx++;
1037 handled |= CSR_INT_BIT_FH_TX;
1038 /* Wake up uCode load routine, now that load is complete */
1039 priv->ucode_write_complete = 1;
1040 wake_up_interruptible(&priv->wait_command_queue);
1041 }
1042
1043 if (inta & ~handled) {
1044 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1045 priv->isr_stats.unhandled++;
1046 }
1047
1048 if (inta & ~(priv->inta_mask)) {
1049 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1050 inta & ~priv->inta_mask);
1051 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1052 }
1053
1054 /* Re-enable all interrupts */
1055 /* only Re-enable if diabled by irq */
1056 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1057 iwl_enable_interrupts(priv);
1058
1059 #ifdef CONFIG_IWLWIFI_DEBUG
1060 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1061 inta = iwl_read32(priv, CSR_INT);
1062 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1063 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1064 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1065 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1066 }
1067 #endif
1068 }
1069
1070 /* tasklet for iwlagn interrupt */
1071 static void iwl_irq_tasklet(struct iwl_priv *priv)
1072 {
1073 u32 inta = 0;
1074 u32 handled = 0;
1075 unsigned long flags;
1076 #ifdef CONFIG_IWLWIFI_DEBUG
1077 u32 inta_mask;
1078 #endif
1079
1080 spin_lock_irqsave(&priv->lock, flags);
1081
1082 /* Ack/clear/reset pending uCode interrupts.
1083 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1084 */
1085 iwl_write32(priv, CSR_INT, priv->inta);
1086
1087 inta = priv->inta;
1088
1089 #ifdef CONFIG_IWLWIFI_DEBUG
1090 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1091 /* just for debug */
1092 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1093 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1094 inta, inta_mask);
1095 }
1096 #endif
1097
1098 spin_unlock_irqrestore(&priv->lock, flags);
1099
1100 /* saved interrupt in inta variable now we can reset priv->inta */
1101 priv->inta = 0;
1102
1103 /* Now service all interrupt bits discovered above. */
1104 if (inta & CSR_INT_BIT_HW_ERR) {
1105 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1106
1107 /* Tell the device to stop sending interrupts */
1108 iwl_disable_interrupts(priv);
1109
1110 priv->isr_stats.hw++;
1111 iwl_irq_handle_error(priv);
1112
1113 handled |= CSR_INT_BIT_HW_ERR;
1114
1115 return;
1116 }
1117
1118 #ifdef CONFIG_IWLWIFI_DEBUG
1119 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1120 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1121 if (inta & CSR_INT_BIT_SCD) {
1122 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1123 "the frame/frames.\n");
1124 priv->isr_stats.sch++;
1125 }
1126
1127 /* Alive notification via Rx interrupt will do the real work */
1128 if (inta & CSR_INT_BIT_ALIVE) {
1129 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1130 priv->isr_stats.alive++;
1131 }
1132 }
1133 #endif
1134 /* Safely ignore these bits for debug checks below */
1135 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1136
1137 /* HW RF KILL switch toggled */
1138 if (inta & CSR_INT_BIT_RF_KILL) {
1139 int hw_rf_kill = 0;
1140 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1141 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1142 hw_rf_kill = 1;
1143
1144 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1145 hw_rf_kill ? "disable radio" : "enable radio");
1146
1147 priv->isr_stats.rfkill++;
1148
1149 /* driver only loads ucode once setting the interface up.
1150 * the driver allows loading the ucode even if the radio
1151 * is killed. Hence update the killswitch state here. The
1152 * rfkill handler will care about restarting if needed.
1153 */
1154 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1155 if (hw_rf_kill)
1156 set_bit(STATUS_RF_KILL_HW, &priv->status);
1157 else
1158 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1159 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1160 }
1161
1162 handled |= CSR_INT_BIT_RF_KILL;
1163 }
1164
1165 /* Chip got too hot and stopped itself */
1166 if (inta & CSR_INT_BIT_CT_KILL) {
1167 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1168 priv->isr_stats.ctkill++;
1169 handled |= CSR_INT_BIT_CT_KILL;
1170 }
1171
1172 /* Error detected by uCode */
1173 if (inta & CSR_INT_BIT_SW_ERR) {
1174 IWL_ERR(priv, "Microcode SW error detected. "
1175 " Restarting 0x%X.\n", inta);
1176 priv->isr_stats.sw++;
1177 priv->isr_stats.sw_err = inta;
1178 iwl_irq_handle_error(priv);
1179 handled |= CSR_INT_BIT_SW_ERR;
1180 }
1181
1182 /* uCode wakes up after power-down sleep */
1183 if (inta & CSR_INT_BIT_WAKEUP) {
1184 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1185 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1186 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1187 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1188 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1189 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1190 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1191 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1192
1193 priv->isr_stats.wakeup++;
1194
1195 handled |= CSR_INT_BIT_WAKEUP;
1196 }
1197
1198 /* All uCode command responses, including Tx command responses,
1199 * Rx "responses" (frame-received notification), and other
1200 * notifications from uCode come through here*/
1201 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1202 CSR_INT_BIT_RX_PERIODIC)) {
1203 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1204 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1205 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1206 iwl_write32(priv, CSR_FH_INT_STATUS,
1207 CSR49_FH_INT_RX_MASK);
1208 }
1209 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1210 handled |= CSR_INT_BIT_RX_PERIODIC;
1211 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1212 }
1213 /* Sending RX interrupt require many steps to be done in the
1214 * the device:
1215 * 1- write interrupt to current index in ICT table.
1216 * 2- dma RX frame.
1217 * 3- update RX shared data to indicate last write index.
1218 * 4- send interrupt.
1219 * This could lead to RX race, driver could receive RX interrupt
1220 * but the shared data changes does not reflect this.
1221 * this could lead to RX race, RX periodic will solve this race
1222 */
1223 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1224 CSR_INT_PERIODIC_DIS);
1225 iwl_rx_handle(priv);
1226 /* Only set RX periodic if real RX is received. */
1227 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1228 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1229 CSR_INT_PERIODIC_ENA);
1230
1231 priv->isr_stats.rx++;
1232 iwl_leds_background(priv);
1233 }
1234
1235 /* This "Tx" DMA channel is used only for loading uCode */
1236 if (inta & CSR_INT_BIT_FH_TX) {
1237 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1238 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1239 priv->isr_stats.tx++;
1240 handled |= CSR_INT_BIT_FH_TX;
1241 /* Wake up uCode load routine, now that load is complete */
1242 priv->ucode_write_complete = 1;
1243 wake_up_interruptible(&priv->wait_command_queue);
1244 }
1245
1246 if (inta & ~handled) {
1247 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1248 priv->isr_stats.unhandled++;
1249 }
1250
1251 if (inta & ~(priv->inta_mask)) {
1252 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1253 inta & ~priv->inta_mask);
1254 }
1255
1256 /* Re-enable all interrupts */
1257 /* only Re-enable if diabled by irq */
1258 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1259 iwl_enable_interrupts(priv);
1260 }
1261
1262
1263 /******************************************************************************
1264 *
1265 * uCode download functions
1266 *
1267 ******************************************************************************/
1268
1269 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1270 {
1271 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1272 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1273 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1274 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1275 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1276 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1277 }
1278
1279 static void iwl_nic_start(struct iwl_priv *priv)
1280 {
1281 /* Remove all resets to allow NIC to operate */
1282 iwl_write32(priv, CSR_RESET, 0);
1283 }
1284
1285
1286 /**
1287 * iwl_read_ucode - Read uCode images from disk file.
1288 *
1289 * Copy into buffers for card to fetch via bus-mastering
1290 */
1291 static int iwl_read_ucode(struct iwl_priv *priv)
1292 {
1293 struct iwl_ucode_header *ucode;
1294 int ret = -EINVAL, index;
1295 const struct firmware *ucode_raw;
1296 const char *name_pre = priv->cfg->fw_name_pre;
1297 const unsigned int api_max = priv->cfg->ucode_api_max;
1298 const unsigned int api_min = priv->cfg->ucode_api_min;
1299 char buf[25];
1300 u8 *src;
1301 size_t len;
1302 u32 api_ver, build;
1303 u32 inst_size, data_size, init_size, init_data_size, boot_size;
1304 u16 eeprom_ver;
1305
1306 /* Ask kernel firmware_class module to get the boot firmware off disk.
1307 * request_firmware() is synchronous, file is in memory on return. */
1308 for (index = api_max; index >= api_min; index--) {
1309 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1310 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1311 if (ret < 0) {
1312 IWL_ERR(priv, "%s firmware file req failed: %d\n",
1313 buf, ret);
1314 if (ret == -ENOENT)
1315 continue;
1316 else
1317 goto error;
1318 } else {
1319 if (index < api_max)
1320 IWL_ERR(priv, "Loaded firmware %s, "
1321 "which is deprecated. "
1322 "Please use API v%u instead.\n",
1323 buf, api_max);
1324
1325 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
1326 buf, ucode_raw->size);
1327 break;
1328 }
1329 }
1330
1331 if (ret < 0)
1332 goto error;
1333
1334 /* Make sure that we got at least the v1 header! */
1335 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
1336 IWL_ERR(priv, "File size way too small!\n");
1337 ret = -EINVAL;
1338 goto err_release;
1339 }
1340
1341 /* Data from ucode file: header followed by uCode images */
1342 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1343
1344 priv->ucode_ver = le32_to_cpu(ucode->ver);
1345 api_ver = IWL_UCODE_API(priv->ucode_ver);
1346 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1347 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1348 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1349 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1350 init_data_size =
1351 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1352 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1353 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
1354
1355 /* api_ver should match the api version forming part of the
1356 * firmware filename ... but we don't check for that and only rely
1357 * on the API version read from firmware header from here on forward */
1358
1359 if (api_ver < api_min || api_ver > api_max) {
1360 IWL_ERR(priv, "Driver unable to support your firmware API. "
1361 "Driver supports v%u, firmware is v%u.\n",
1362 api_max, api_ver);
1363 priv->ucode_ver = 0;
1364 ret = -EINVAL;
1365 goto err_release;
1366 }
1367 if (api_ver != api_max)
1368 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
1369 "got v%u. New firmware can be obtained "
1370 "from http://www.intellinuxwireless.org.\n",
1371 api_max, api_ver);
1372
1373 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1374 IWL_UCODE_MAJOR(priv->ucode_ver),
1375 IWL_UCODE_MINOR(priv->ucode_ver),
1376 IWL_UCODE_API(priv->ucode_ver),
1377 IWL_UCODE_SERIAL(priv->ucode_ver));
1378
1379 snprintf(priv->hw->wiphy->fw_version,
1380 sizeof(priv->hw->wiphy->fw_version),
1381 "%u.%u.%u.%u",
1382 IWL_UCODE_MAJOR(priv->ucode_ver),
1383 IWL_UCODE_MINOR(priv->ucode_ver),
1384 IWL_UCODE_API(priv->ucode_ver),
1385 IWL_UCODE_SERIAL(priv->ucode_ver));
1386
1387 if (build)
1388 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1389
1390 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1391 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1392 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1393 ? "OTP" : "EEPROM", eeprom_ver);
1394
1395 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1396 priv->ucode_ver);
1397 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
1398 inst_size);
1399 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
1400 data_size);
1401 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
1402 init_size);
1403 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
1404 init_data_size);
1405 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
1406 boot_size);
1407
1408 /* Verify size of file vs. image size info in file's header */
1409 if (ucode_raw->size !=
1410 priv->cfg->ops->ucode->get_header_size(api_ver) +
1411 inst_size + data_size + init_size +
1412 init_data_size + boot_size) {
1413
1414 IWL_DEBUG_INFO(priv,
1415 "uCode file size %d does not match expected size\n",
1416 (int)ucode_raw->size);
1417 ret = -EINVAL;
1418 goto err_release;
1419 }
1420
1421 /* Verify that uCode images will fit in card's SRAM */
1422 if (inst_size > priv->hw_params.max_inst_size) {
1423 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
1424 inst_size);
1425 ret = -EINVAL;
1426 goto err_release;
1427 }
1428
1429 if (data_size > priv->hw_params.max_data_size) {
1430 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
1431 data_size);
1432 ret = -EINVAL;
1433 goto err_release;
1434 }
1435 if (init_size > priv->hw_params.max_inst_size) {
1436 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1437 init_size);
1438 ret = -EINVAL;
1439 goto err_release;
1440 }
1441 if (init_data_size > priv->hw_params.max_data_size) {
1442 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
1443 init_data_size);
1444 ret = -EINVAL;
1445 goto err_release;
1446 }
1447 if (boot_size > priv->hw_params.max_bsm_size) {
1448 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1449 boot_size);
1450 ret = -EINVAL;
1451 goto err_release;
1452 }
1453
1454 /* Allocate ucode buffers for card's bus-master loading ... */
1455
1456 /* Runtime instructions and 2 copies of data:
1457 * 1) unmodified from disk
1458 * 2) backup cache for save/restore during power-downs */
1459 priv->ucode_code.len = inst_size;
1460 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1461
1462 priv->ucode_data.len = data_size;
1463 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1464
1465 priv->ucode_data_backup.len = data_size;
1466 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1467
1468 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1469 !priv->ucode_data_backup.v_addr)
1470 goto err_pci_alloc;
1471
1472 /* Initialization instructions and data */
1473 if (init_size && init_data_size) {
1474 priv->ucode_init.len = init_size;
1475 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1476
1477 priv->ucode_init_data.len = init_data_size;
1478 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1479
1480 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1481 goto err_pci_alloc;
1482 }
1483
1484 /* Bootstrap (instructions only, no data) */
1485 if (boot_size) {
1486 priv->ucode_boot.len = boot_size;
1487 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1488
1489 if (!priv->ucode_boot.v_addr)
1490 goto err_pci_alloc;
1491 }
1492
1493 /* Copy images into buffers for card's bus-master reads ... */
1494
1495 /* Runtime instructions (first block of data in file) */
1496 len = inst_size;
1497 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
1498 memcpy(priv->ucode_code.v_addr, src, len);
1499 src += len;
1500
1501 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1502 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1503
1504 /* Runtime data (2nd block)
1505 * NOTE: Copy into backup buffer will be done in iwl_up() */
1506 len = data_size;
1507 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
1508 memcpy(priv->ucode_data.v_addr, src, len);
1509 memcpy(priv->ucode_data_backup.v_addr, src, len);
1510 src += len;
1511
1512 /* Initialization instructions (3rd block) */
1513 if (init_size) {
1514 len = init_size;
1515 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1516 len);
1517 memcpy(priv->ucode_init.v_addr, src, len);
1518 src += len;
1519 }
1520
1521 /* Initialization data (4th block) */
1522 if (init_data_size) {
1523 len = init_data_size;
1524 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1525 len);
1526 memcpy(priv->ucode_init_data.v_addr, src, len);
1527 src += len;
1528 }
1529
1530 /* Bootstrap instructions (5th block) */
1531 len = boot_size;
1532 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
1533 memcpy(priv->ucode_boot.v_addr, src, len);
1534
1535 /* We have our copies now, allow OS release its copies */
1536 release_firmware(ucode_raw);
1537 return 0;
1538
1539 err_pci_alloc:
1540 IWL_ERR(priv, "failed to allocate pci memory\n");
1541 ret = -ENOMEM;
1542 iwl_dealloc_ucode_pci(priv);
1543
1544 err_release:
1545 release_firmware(ucode_raw);
1546
1547 error:
1548 return ret;
1549 }
1550
1551 #ifdef CONFIG_IWLWIFI_DEBUG
1552 static const char *desc_lookup_text[] = {
1553 "OK",
1554 "FAIL",
1555 "BAD_PARAM",
1556 "BAD_CHECKSUM",
1557 "NMI_INTERRUPT_WDG",
1558 "SYSASSERT",
1559 "FATAL_ERROR",
1560 "BAD_COMMAND",
1561 "HW_ERROR_TUNE_LOCK",
1562 "HW_ERROR_TEMPERATURE",
1563 "ILLEGAL_CHAN_FREQ",
1564 "VCC_NOT_STABLE",
1565 "FH_ERROR",
1566 "NMI_INTERRUPT_HOST",
1567 "NMI_INTERRUPT_ACTION_PT",
1568 "NMI_INTERRUPT_UNKNOWN",
1569 "UCODE_VERSION_MISMATCH",
1570 "HW_ERROR_ABS_LOCK",
1571 "HW_ERROR_CAL_LOCK_FAIL",
1572 "NMI_INTERRUPT_INST_ACTION_PT",
1573 "NMI_INTERRUPT_DATA_ACTION_PT",
1574 "NMI_TRM_HW_ER",
1575 "NMI_INTERRUPT_TRM",
1576 "NMI_INTERRUPT_BREAK_POINT"
1577 "DEBUG_0",
1578 "DEBUG_1",
1579 "DEBUG_2",
1580 "DEBUG_3",
1581 "UNKNOWN"
1582 };
1583
1584 static const char *desc_lookup(int i)
1585 {
1586 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1587
1588 if (i < 0 || i > max)
1589 i = max;
1590
1591 return desc_lookup_text[i];
1592 }
1593
1594 #define ERROR_START_OFFSET (1 * sizeof(u32))
1595 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1596
1597 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1598 {
1599 u32 data2, line;
1600 u32 desc, time, count, base, data1;
1601 u32 blink1, blink2, ilink1, ilink2;
1602
1603 if (priv->ucode_type == UCODE_INIT)
1604 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1605 else
1606 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1607
1608 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1609 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1610 return;
1611 }
1612
1613 count = iwl_read_targ_mem(priv, base);
1614
1615 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1616 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1617 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1618 priv->status, count);
1619 }
1620
1621 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1622 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1623 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1624 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1625 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1626 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1627 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1628 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1629 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1630
1631 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1632 blink1, blink2, ilink1, ilink2);
1633
1634 IWL_ERR(priv, "Desc Time "
1635 "data1 data2 line\n");
1636 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1637 desc_lookup(desc), desc, time, data1, data2, line);
1638 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1639 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1640 ilink1, ilink2);
1641
1642 }
1643
1644 #define EVENT_START_OFFSET (4 * sizeof(u32))
1645
1646 /**
1647 * iwl_print_event_log - Dump error event log to syslog
1648 *
1649 */
1650 static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1651 u32 num_events, u32 mode)
1652 {
1653 u32 i;
1654 u32 base; /* SRAM byte address of event log header */
1655 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1656 u32 ptr; /* SRAM byte address of log data */
1657 u32 ev, time, data; /* event log data */
1658
1659 if (num_events == 0)
1660 return;
1661 if (priv->ucode_type == UCODE_INIT)
1662 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1663 else
1664 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1665
1666 if (mode == 0)
1667 event_size = 2 * sizeof(u32);
1668 else
1669 event_size = 3 * sizeof(u32);
1670
1671 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1672
1673 /* "time" is actually "data" for mode 0 (no timestamp).
1674 * place event id # at far right for easier visual parsing. */
1675 for (i = 0; i < num_events; i++) {
1676 ev = iwl_read_targ_mem(priv, ptr);
1677 ptr += sizeof(u32);
1678 time = iwl_read_targ_mem(priv, ptr);
1679 ptr += sizeof(u32);
1680 if (mode == 0) {
1681 /* data, ev */
1682 trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
1683 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1684 } else {
1685 data = iwl_read_targ_mem(priv, ptr);
1686 ptr += sizeof(u32);
1687 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1688 time, data, ev);
1689 trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
1690 }
1691 }
1692 }
1693
1694 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1695 {
1696 u32 base; /* SRAM byte address of event log header */
1697 u32 capacity; /* event log capacity in # entries */
1698 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1699 u32 num_wraps; /* # times uCode wrapped to top of log */
1700 u32 next_entry; /* index of next entry to be written by uCode */
1701 u32 size; /* # entries that we'll print */
1702
1703 if (priv->ucode_type == UCODE_INIT)
1704 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1705 else
1706 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1707
1708 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1709 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1710 return;
1711 }
1712
1713 /* event log header */
1714 capacity = iwl_read_targ_mem(priv, base);
1715 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1716 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1717 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1718
1719 size = num_wraps ? capacity : next_entry;
1720
1721 /* bail out if nothing in log */
1722 if (size == 0) {
1723 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1724 return;
1725 }
1726
1727 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1728 size, num_wraps);
1729
1730 /* if uCode has wrapped back to top of log, start at the oldest entry,
1731 * i.e the next one that uCode would fill. */
1732 if (num_wraps)
1733 iwl_print_event_log(priv, next_entry,
1734 capacity - next_entry, mode);
1735 /* (then/else) start at top of log */
1736 iwl_print_event_log(priv, 0, next_entry, mode);
1737
1738 }
1739 #endif
1740
1741 /**
1742 * iwl_alive_start - called after REPLY_ALIVE notification received
1743 * from protocol/runtime uCode (initialization uCode's
1744 * Alive gets handled by iwl_init_alive_start()).
1745 */
1746 static void iwl_alive_start(struct iwl_priv *priv)
1747 {
1748 int ret = 0;
1749
1750 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
1751
1752 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1753 /* We had an error bringing up the hardware, so take it
1754 * all the way back down so we can try again */
1755 IWL_DEBUG_INFO(priv, "Alive failed.\n");
1756 goto restart;
1757 }
1758
1759 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1760 * This is a paranoid check, because we would not have gotten the
1761 * "runtime" alive if code weren't properly loaded. */
1762 if (iwl_verify_ucode(priv)) {
1763 /* Runtime instruction load was bad;
1764 * take it all the way back down so we can try again */
1765 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
1766 goto restart;
1767 }
1768
1769 iwl_clear_stations_table(priv);
1770 ret = priv->cfg->ops->lib->alive_notify(priv);
1771 if (ret) {
1772 IWL_WARN(priv,
1773 "Could not complete ALIVE transition [ntf]: %d\n", ret);
1774 goto restart;
1775 }
1776
1777 /* After the ALIVE response, we can send host commands to the uCode */
1778 set_bit(STATUS_ALIVE, &priv->status);
1779
1780 if (iwl_is_rfkill(priv))
1781 return;
1782
1783 ieee80211_wake_queues(priv->hw);
1784
1785 priv->active_rate = priv->rates_mask;
1786 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1787
1788 /* Configure Tx antenna selection based on H/W config */
1789 if (priv->cfg->ops->hcmd->set_tx_ant)
1790 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
1791
1792 if (iwl_is_associated(priv)) {
1793 struct iwl_rxon_cmd *active_rxon =
1794 (struct iwl_rxon_cmd *)&priv->active_rxon;
1795 /* apply any changes in staging */
1796 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
1797 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1798 } else {
1799 /* Initialize our rx_config data */
1800 iwl_connection_init_rx_config(priv, priv->iw_mode);
1801
1802 if (priv->cfg->ops->hcmd->set_rxon_chain)
1803 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1804
1805 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1806 }
1807
1808 /* Configure Bluetooth device coexistence support */
1809 iwl_send_bt_config(priv);
1810
1811 iwl_reset_run_time_calib(priv);
1812
1813 /* Configure the adapter for unassociated operation */
1814 iwlcore_commit_rxon(priv);
1815
1816 /* At this point, the NIC is initialized and operational */
1817 iwl_rf_kill_ct_config(priv);
1818
1819 iwl_leds_init(priv);
1820
1821 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
1822 set_bit(STATUS_READY, &priv->status);
1823 wake_up_interruptible(&priv->wait_command_queue);
1824
1825 iwl_power_update_mode(priv, true);
1826
1827 /* reassociate for ADHOC mode */
1828 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1829 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1830 priv->vif);
1831 if (beacon)
1832 iwl_mac_beacon_update(priv->hw, beacon);
1833 }
1834
1835
1836 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
1837 iwl_set_mode(priv, priv->iw_mode);
1838
1839 return;
1840
1841 restart:
1842 queue_work(priv->workqueue, &priv->restart);
1843 }
1844
1845 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
1846
1847 static void __iwl_down(struct iwl_priv *priv)
1848 {
1849 unsigned long flags;
1850 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
1851
1852 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
1853
1854 if (!exit_pending)
1855 set_bit(STATUS_EXIT_PENDING, &priv->status);
1856
1857 iwl_clear_stations_table(priv);
1858
1859 /* Unblock any waiting calls */
1860 wake_up_interruptible_all(&priv->wait_command_queue);
1861
1862 /* Wipe out the EXIT_PENDING status bit if we are not actually
1863 * exiting the module */
1864 if (!exit_pending)
1865 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1866
1867 /* stop and reset the on-board processor */
1868 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1869
1870 /* tell the device to stop sending interrupts */
1871 spin_lock_irqsave(&priv->lock, flags);
1872 iwl_disable_interrupts(priv);
1873 spin_unlock_irqrestore(&priv->lock, flags);
1874 iwl_synchronize_irq(priv);
1875
1876 if (priv->mac80211_registered)
1877 ieee80211_stop_queues(priv->hw);
1878
1879 /* If we have not previously called iwl_init() then
1880 * clear all bits but the RF Kill bit and return */
1881 if (!iwl_is_init(priv)) {
1882 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1883 STATUS_RF_KILL_HW |
1884 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1885 STATUS_GEO_CONFIGURED |
1886 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1887 STATUS_EXIT_PENDING;
1888 goto exit;
1889 }
1890
1891 /* ...otherwise clear out all the status bits but the RF Kill
1892 * bit and continue taking the NIC down. */
1893 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1894 STATUS_RF_KILL_HW |
1895 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1896 STATUS_GEO_CONFIGURED |
1897 test_bit(STATUS_FW_ERROR, &priv->status) <<
1898 STATUS_FW_ERROR |
1899 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1900 STATUS_EXIT_PENDING;
1901
1902 /* device going down, Stop using ICT table */
1903 iwl_disable_ict(priv);
1904 spin_lock_irqsave(&priv->lock, flags);
1905 iwl_clear_bit(priv, CSR_GP_CNTRL,
1906 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1907 spin_unlock_irqrestore(&priv->lock, flags);
1908
1909 iwl_txq_ctx_stop(priv);
1910 iwl_rxq_stop(priv);
1911
1912 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1913 APMG_CLK_VAL_DMA_CLK_RQT);
1914
1915 udelay(5);
1916
1917 /* Stop the device, and put it in low power state */
1918 priv->cfg->ops->lib->apm_ops.stop(priv);
1919
1920 exit:
1921 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
1922
1923 if (priv->ibss_beacon)
1924 dev_kfree_skb(priv->ibss_beacon);
1925 priv->ibss_beacon = NULL;
1926
1927 /* clear out any free frames */
1928 iwl_clear_free_frames(priv);
1929 }
1930
1931 static void iwl_down(struct iwl_priv *priv)
1932 {
1933 mutex_lock(&priv->mutex);
1934 __iwl_down(priv);
1935 mutex_unlock(&priv->mutex);
1936
1937 iwl_cancel_deferred_work(priv);
1938 }
1939
1940 #define HW_READY_TIMEOUT (50)
1941
1942 static int iwl_set_hw_ready(struct iwl_priv *priv)
1943 {
1944 int ret = 0;
1945
1946 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1947 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1948
1949 /* See if we got it */
1950 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1951 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1952 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1953 HW_READY_TIMEOUT);
1954 if (ret != -ETIMEDOUT)
1955 priv->hw_ready = true;
1956 else
1957 priv->hw_ready = false;
1958
1959 IWL_DEBUG_INFO(priv, "hardware %s\n",
1960 (priv->hw_ready == 1) ? "ready" : "not ready");
1961 return ret;
1962 }
1963
1964 static int iwl_prepare_card_hw(struct iwl_priv *priv)
1965 {
1966 int ret = 0;
1967
1968 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
1969
1970 ret = iwl_set_hw_ready(priv);
1971 if (priv->hw_ready)
1972 return ret;
1973
1974 /* If HW is not ready, prepare the conditions to check again */
1975 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1976 CSR_HW_IF_CONFIG_REG_PREPARE);
1977
1978 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1979 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1980 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1981
1982 /* HW should be ready by now, check again. */
1983 if (ret != -ETIMEDOUT)
1984 iwl_set_hw_ready(priv);
1985
1986 return ret;
1987 }
1988
1989 #define MAX_HW_RESTARTS 5
1990
1991 static int __iwl_up(struct iwl_priv *priv)
1992 {
1993 int i;
1994 int ret;
1995
1996 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
1997 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
1998 return -EIO;
1999 }
2000
2001 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2002 IWL_ERR(priv, "ucode not available for device bringup\n");
2003 return -EIO;
2004 }
2005
2006 iwl_prepare_card_hw(priv);
2007
2008 if (!priv->hw_ready) {
2009 IWL_WARN(priv, "Exit HW not ready\n");
2010 return -EIO;
2011 }
2012
2013 /* If platform's RF_KILL switch is NOT set to KILL */
2014 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2015 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2016 else
2017 set_bit(STATUS_RF_KILL_HW, &priv->status);
2018
2019 if (iwl_is_rfkill(priv)) {
2020 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2021
2022 iwl_enable_interrupts(priv);
2023 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2024 return 0;
2025 }
2026
2027 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2028
2029 ret = iwl_hw_nic_init(priv);
2030 if (ret) {
2031 IWL_ERR(priv, "Unable to init nic\n");
2032 return ret;
2033 }
2034
2035 /* make sure rfkill handshake bits are cleared */
2036 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2037 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2038 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2039
2040 /* clear (again), then enable host interrupts */
2041 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2042 iwl_enable_interrupts(priv);
2043
2044 /* really make sure rfkill handshake bits are cleared */
2045 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2046 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2047
2048 /* Copy original ucode data image from disk into backup cache.
2049 * This will be used to initialize the on-board processor's
2050 * data SRAM for a clean start when the runtime program first loads. */
2051 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2052 priv->ucode_data.len);
2053
2054 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2055
2056 iwl_clear_stations_table(priv);
2057
2058 /* load bootstrap state machine,
2059 * load bootstrap program into processor's memory,
2060 * prepare to load the "initialize" uCode */
2061 ret = priv->cfg->ops->lib->load_ucode(priv);
2062
2063 if (ret) {
2064 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2065 ret);
2066 continue;
2067 }
2068
2069 /* start card; "initialize" will load runtime ucode */
2070 iwl_nic_start(priv);
2071
2072 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2073
2074 return 0;
2075 }
2076
2077 set_bit(STATUS_EXIT_PENDING, &priv->status);
2078 __iwl_down(priv);
2079 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2080
2081 /* tried to restart and config the device for as long as our
2082 * patience could withstand */
2083 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2084 return -EIO;
2085 }
2086
2087
2088 /*****************************************************************************
2089 *
2090 * Workqueue callbacks
2091 *
2092 *****************************************************************************/
2093
2094 static void iwl_bg_init_alive_start(struct work_struct *data)
2095 {
2096 struct iwl_priv *priv =
2097 container_of(data, struct iwl_priv, init_alive_start.work);
2098
2099 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2100 return;
2101
2102 mutex_lock(&priv->mutex);
2103 priv->cfg->ops->lib->init_alive_start(priv);
2104 mutex_unlock(&priv->mutex);
2105 }
2106
2107 static void iwl_bg_alive_start(struct work_struct *data)
2108 {
2109 struct iwl_priv *priv =
2110 container_of(data, struct iwl_priv, alive_start.work);
2111
2112 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2113 return;
2114
2115 /* enable dram interrupt */
2116 iwl_reset_ict(priv);
2117
2118 mutex_lock(&priv->mutex);
2119 iwl_alive_start(priv);
2120 mutex_unlock(&priv->mutex);
2121 }
2122
2123 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2124 {
2125 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2126 run_time_calib_work);
2127
2128 mutex_lock(&priv->mutex);
2129
2130 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2131 test_bit(STATUS_SCANNING, &priv->status)) {
2132 mutex_unlock(&priv->mutex);
2133 return;
2134 }
2135
2136 if (priv->start_calib) {
2137 iwl_chain_noise_calibration(priv, &priv->statistics);
2138
2139 iwl_sensitivity_calibration(priv, &priv->statistics);
2140 }
2141
2142 mutex_unlock(&priv->mutex);
2143 return;
2144 }
2145
2146 static void iwl_bg_up(struct work_struct *data)
2147 {
2148 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
2149
2150 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2151 return;
2152
2153 mutex_lock(&priv->mutex);
2154 __iwl_up(priv);
2155 mutex_unlock(&priv->mutex);
2156 }
2157
2158 static void iwl_bg_restart(struct work_struct *data)
2159 {
2160 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2161
2162 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2163 return;
2164
2165 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2166 mutex_lock(&priv->mutex);
2167 priv->vif = NULL;
2168 priv->is_open = 0;
2169 mutex_unlock(&priv->mutex);
2170 iwl_down(priv);
2171 ieee80211_restart_hw(priv->hw);
2172 } else {
2173 iwl_down(priv);
2174 queue_work(priv->workqueue, &priv->up);
2175 }
2176 }
2177
2178 static void iwl_bg_rx_replenish(struct work_struct *data)
2179 {
2180 struct iwl_priv *priv =
2181 container_of(data, struct iwl_priv, rx_replenish);
2182
2183 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2184 return;
2185
2186 mutex_lock(&priv->mutex);
2187 iwl_rx_replenish(priv);
2188 mutex_unlock(&priv->mutex);
2189 }
2190
2191 #define IWL_DELAY_NEXT_SCAN (HZ*2)
2192
2193 void iwl_post_associate(struct iwl_priv *priv)
2194 {
2195 struct ieee80211_conf *conf = NULL;
2196 int ret = 0;
2197 unsigned long flags;
2198
2199 if (priv->iw_mode == NL80211_IFTYPE_AP) {
2200 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
2201 return;
2202 }
2203
2204 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
2205 priv->assoc_id, priv->active_rxon.bssid_addr);
2206
2207
2208 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2209 return;
2210
2211
2212 if (!priv->vif || !priv->is_open)
2213 return;
2214
2215 iwl_scan_cancel_timeout(priv, 200);
2216
2217 conf = ieee80211_get_hw_conf(priv->hw);
2218
2219 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2220 iwlcore_commit_rxon(priv);
2221
2222 iwl_setup_rxon_timing(priv);
2223 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2224 sizeof(priv->rxon_timing), &priv->rxon_timing);
2225 if (ret)
2226 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2227 "Attempting to continue.\n");
2228
2229 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2230
2231 iwl_set_rxon_ht(priv, &priv->current_ht_config);
2232
2233 if (priv->cfg->ops->hcmd->set_rxon_chain)
2234 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2235
2236 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2237
2238 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
2239 priv->assoc_id, priv->beacon_int);
2240
2241 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2242 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2243 else
2244 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2245
2246 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2247 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2248 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2249 else
2250 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2251
2252 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2253 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2254
2255 }
2256
2257 iwlcore_commit_rxon(priv);
2258
2259 switch (priv->iw_mode) {
2260 case NL80211_IFTYPE_STATION:
2261 break;
2262
2263 case NL80211_IFTYPE_ADHOC:
2264
2265 /* assume default assoc id */
2266 priv->assoc_id = 1;
2267
2268 iwl_rxon_add_station(priv, priv->bssid, 0);
2269 iwl_send_beacon_cmd(priv);
2270
2271 break;
2272
2273 default:
2274 IWL_ERR(priv, "%s Should not be called in %d mode\n",
2275 __func__, priv->iw_mode);
2276 break;
2277 }
2278
2279 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2280 priv->assoc_station_added = 1;
2281
2282 spin_lock_irqsave(&priv->lock, flags);
2283 iwl_activate_qos(priv, 0);
2284 spin_unlock_irqrestore(&priv->lock, flags);
2285
2286 /* the chain noise calibration will enabled PM upon completion
2287 * If chain noise has already been run, then we need to enable
2288 * power management here */
2289 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
2290 iwl_power_update_mode(priv, false);
2291
2292 /* Enable Rx differential gain and sensitivity calibrations */
2293 iwl_chain_noise_reset(priv);
2294 priv->start_calib = 1;
2295
2296 }
2297
2298 /*****************************************************************************
2299 *
2300 * mac80211 entry point functions
2301 *
2302 *****************************************************************************/
2303
2304 #define UCODE_READY_TIMEOUT (4 * HZ)
2305
2306 /*
2307 * Not a mac80211 entry point function, but it fits in with all the
2308 * other mac80211 functions grouped here.
2309 */
2310 static int iwl_setup_mac(struct iwl_priv *priv)
2311 {
2312 int ret;
2313 struct ieee80211_hw *hw = priv->hw;
2314 hw->rate_control_algorithm = "iwl-agn-rs";
2315
2316 /* Tell mac80211 our characteristics */
2317 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2318 IEEE80211_HW_NOISE_DBM |
2319 IEEE80211_HW_AMPDU_AGGREGATION |
2320 IEEE80211_HW_SPECTRUM_MGMT;
2321
2322 if (!priv->cfg->broken_powersave)
2323 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2324 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2325
2326 hw->sta_data_size = sizeof(struct iwl_station_priv);
2327 hw->wiphy->interface_modes =
2328 BIT(NL80211_IFTYPE_STATION) |
2329 BIT(NL80211_IFTYPE_ADHOC);
2330
2331 hw->wiphy->custom_regulatory = true;
2332
2333 /* Firmware does not support this */
2334 hw->wiphy->disable_beacon_hints = true;
2335
2336 /*
2337 * For now, disable PS by default because it affects
2338 * RX performance significantly.
2339 */
2340 hw->wiphy->ps_default = false;
2341
2342 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2343 /* we create the 802.11 header and a zero-length SSID element */
2344 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2345
2346 /* Default value; 4 EDCA QOS priorities */
2347 hw->queues = 4;
2348
2349 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2350
2351 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2352 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2353 &priv->bands[IEEE80211_BAND_2GHZ];
2354 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2355 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2356 &priv->bands[IEEE80211_BAND_5GHZ];
2357
2358 ret = ieee80211_register_hw(priv->hw);
2359 if (ret) {
2360 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2361 return ret;
2362 }
2363 priv->mac80211_registered = 1;
2364
2365 return 0;
2366 }
2367
2368
2369 static int iwl_mac_start(struct ieee80211_hw *hw)
2370 {
2371 struct iwl_priv *priv = hw->priv;
2372 int ret;
2373
2374 IWL_DEBUG_MAC80211(priv, "enter\n");
2375
2376 /* we should be verifying the device is ready to be opened */
2377 mutex_lock(&priv->mutex);
2378
2379 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2380 * ucode filename and max sizes are card-specific. */
2381
2382 if (!priv->ucode_code.len) {
2383 ret = iwl_read_ucode(priv);
2384 if (ret) {
2385 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
2386 mutex_unlock(&priv->mutex);
2387 return ret;
2388 }
2389 }
2390
2391 ret = __iwl_up(priv);
2392
2393 mutex_unlock(&priv->mutex);
2394
2395 if (ret)
2396 return ret;
2397
2398 if (iwl_is_rfkill(priv))
2399 goto out;
2400
2401 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2402
2403 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2404 * mac80211 will not be run successfully. */
2405 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2406 test_bit(STATUS_READY, &priv->status),
2407 UCODE_READY_TIMEOUT);
2408 if (!ret) {
2409 if (!test_bit(STATUS_READY, &priv->status)) {
2410 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2411 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2412 return -ETIMEDOUT;
2413 }
2414 }
2415
2416 iwl_led_start(priv);
2417
2418 out:
2419 priv->is_open = 1;
2420 IWL_DEBUG_MAC80211(priv, "leave\n");
2421 return 0;
2422 }
2423
2424 static void iwl_mac_stop(struct ieee80211_hw *hw)
2425 {
2426 struct iwl_priv *priv = hw->priv;
2427
2428 IWL_DEBUG_MAC80211(priv, "enter\n");
2429
2430 if (!priv->is_open)
2431 return;
2432
2433 priv->is_open = 0;
2434
2435 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
2436 /* stop mac, cancel any scan request and clear
2437 * RXON_FILTER_ASSOC_MSK BIT
2438 */
2439 mutex_lock(&priv->mutex);
2440 iwl_scan_cancel_timeout(priv, 100);
2441 mutex_unlock(&priv->mutex);
2442 }
2443
2444 iwl_down(priv);
2445
2446 flush_workqueue(priv->workqueue);
2447
2448 /* enable interrupts again in order to receive rfkill changes */
2449 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2450 iwl_enable_interrupts(priv);
2451
2452 IWL_DEBUG_MAC80211(priv, "leave\n");
2453 }
2454
2455 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2456 {
2457 struct iwl_priv *priv = hw->priv;
2458
2459 IWL_DEBUG_MACDUMP(priv, "enter\n");
2460
2461 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2462 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2463
2464 if (iwl_tx_skb(priv, skb))
2465 dev_kfree_skb_any(skb);
2466
2467 IWL_DEBUG_MACDUMP(priv, "leave\n");
2468 return NETDEV_TX_OK;
2469 }
2470
2471 void iwl_config_ap(struct iwl_priv *priv)
2472 {
2473 int ret = 0;
2474 unsigned long flags;
2475
2476 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2477 return;
2478
2479 /* The following should be done only at AP bring up */
2480 if (!iwl_is_associated(priv)) {
2481
2482 /* RXON - unassoc (to set timing command) */
2483 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2484 iwlcore_commit_rxon(priv);
2485
2486 /* RXON Timing */
2487 iwl_setup_rxon_timing(priv);
2488 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2489 sizeof(priv->rxon_timing), &priv->rxon_timing);
2490 if (ret)
2491 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2492 "Attempting to continue.\n");
2493
2494 if (priv->cfg->ops->hcmd->set_rxon_chain)
2495 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2496
2497 /* FIXME: what should be the assoc_id for AP? */
2498 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2499 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2500 priv->staging_rxon.flags |=
2501 RXON_FLG_SHORT_PREAMBLE_MSK;
2502 else
2503 priv->staging_rxon.flags &=
2504 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2505
2506 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2507 if (priv->assoc_capability &
2508 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2509 priv->staging_rxon.flags |=
2510 RXON_FLG_SHORT_SLOT_MSK;
2511 else
2512 priv->staging_rxon.flags &=
2513 ~RXON_FLG_SHORT_SLOT_MSK;
2514
2515 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2516 priv->staging_rxon.flags &=
2517 ~RXON_FLG_SHORT_SLOT_MSK;
2518 }
2519 /* restore RXON assoc */
2520 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2521 iwlcore_commit_rxon(priv);
2522 spin_lock_irqsave(&priv->lock, flags);
2523 iwl_activate_qos(priv, 1);
2524 spin_unlock_irqrestore(&priv->lock, flags);
2525 iwl_add_bcast_station(priv);
2526 }
2527 iwl_send_beacon_cmd(priv);
2528
2529 /* FIXME - we need to add code here to detect a totally new
2530 * configuration, reset the AP, unassoc, rxon timing, assoc,
2531 * clear sta table, add BCAST sta... */
2532 }
2533
2534 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
2535 struct ieee80211_key_conf *keyconf, const u8 *addr,
2536 u32 iv32, u16 *phase1key)
2537 {
2538
2539 struct iwl_priv *priv = hw->priv;
2540 IWL_DEBUG_MAC80211(priv, "enter\n");
2541
2542 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
2543
2544 IWL_DEBUG_MAC80211(priv, "leave\n");
2545 }
2546
2547 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2548 struct ieee80211_vif *vif,
2549 struct ieee80211_sta *sta,
2550 struct ieee80211_key_conf *key)
2551 {
2552 struct iwl_priv *priv = hw->priv;
2553 const u8 *addr;
2554 int ret;
2555 u8 sta_id;
2556 bool is_default_wep_key = false;
2557
2558 IWL_DEBUG_MAC80211(priv, "enter\n");
2559
2560 if (priv->cfg->mod_params->sw_crypto) {
2561 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2562 return -EOPNOTSUPP;
2563 }
2564 addr = sta ? sta->addr : iwl_bcast_addr;
2565 sta_id = iwl_find_station(priv, addr);
2566 if (sta_id == IWL_INVALID_STATION) {
2567 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
2568 addr);
2569 return -EINVAL;
2570
2571 }
2572
2573 mutex_lock(&priv->mutex);
2574 iwl_scan_cancel_timeout(priv, 100);
2575 mutex_unlock(&priv->mutex);
2576
2577 /* If we are getting WEP group key and we didn't receive any key mapping
2578 * so far, we are in legacy wep mode (group key only), otherwise we are
2579 * in 1X mode.
2580 * In legacy wep mode, we use another host command to the uCode */
2581 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
2582 priv->iw_mode != NL80211_IFTYPE_AP) {
2583 if (cmd == SET_KEY)
2584 is_default_wep_key = !priv->key_mapping_key;
2585 else
2586 is_default_wep_key =
2587 (key->hw_key_idx == HW_KEY_DEFAULT);
2588 }
2589
2590 switch (cmd) {
2591 case SET_KEY:
2592 if (is_default_wep_key)
2593 ret = iwl_set_default_wep_key(priv, key);
2594 else
2595 ret = iwl_set_dynamic_key(priv, key, sta_id);
2596
2597 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2598 break;
2599 case DISABLE_KEY:
2600 if (is_default_wep_key)
2601 ret = iwl_remove_default_wep_key(priv, key);
2602 else
2603 ret = iwl_remove_dynamic_key(priv, key, sta_id);
2604
2605 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2606 break;
2607 default:
2608 ret = -EINVAL;
2609 }
2610
2611 IWL_DEBUG_MAC80211(priv, "leave\n");
2612
2613 return ret;
2614 }
2615
2616 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
2617 enum ieee80211_ampdu_mlme_action action,
2618 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
2619 {
2620 struct iwl_priv *priv = hw->priv;
2621 int ret;
2622
2623 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2624 sta->addr, tid);
2625
2626 if (!(priv->cfg->sku & IWL_SKU_N))
2627 return -EACCES;
2628
2629 switch (action) {
2630 case IEEE80211_AMPDU_RX_START:
2631 IWL_DEBUG_HT(priv, "start Rx\n");
2632 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
2633 case IEEE80211_AMPDU_RX_STOP:
2634 IWL_DEBUG_HT(priv, "stop Rx\n");
2635 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2636 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2637 return 0;
2638 else
2639 return ret;
2640 case IEEE80211_AMPDU_TX_START:
2641 IWL_DEBUG_HT(priv, "start Tx\n");
2642 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
2643 case IEEE80211_AMPDU_TX_STOP:
2644 IWL_DEBUG_HT(priv, "stop Tx\n");
2645 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2646 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2647 return 0;
2648 else
2649 return ret;
2650 default:
2651 IWL_DEBUG_HT(priv, "unknown\n");
2652 return -EINVAL;
2653 break;
2654 }
2655 return 0;
2656 }
2657
2658 static int iwl_mac_get_stats(struct ieee80211_hw *hw,
2659 struct ieee80211_low_level_stats *stats)
2660 {
2661 struct iwl_priv *priv = hw->priv;
2662
2663 priv = hw->priv;
2664 IWL_DEBUG_MAC80211(priv, "enter\n");
2665 IWL_DEBUG_MAC80211(priv, "leave\n");
2666
2667 return 0;
2668 }
2669
2670 /*****************************************************************************
2671 *
2672 * sysfs attributes
2673 *
2674 *****************************************************************************/
2675
2676 #ifdef CONFIG_IWLWIFI_DEBUG
2677
2678 /*
2679 * The following adds a new attribute to the sysfs representation
2680 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
2681 * used for controlling the debug level.
2682 *
2683 * See the level definitions in iwl for details.
2684 *
2685 * The debug_level being managed using sysfs below is a per device debug
2686 * level that is used instead of the global debug level if it (the per
2687 * device debug level) is set.
2688 */
2689 static ssize_t show_debug_level(struct device *d,
2690 struct device_attribute *attr, char *buf)
2691 {
2692 struct iwl_priv *priv = dev_get_drvdata(d);
2693 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
2694 }
2695 static ssize_t store_debug_level(struct device *d,
2696 struct device_attribute *attr,
2697 const char *buf, size_t count)
2698 {
2699 struct iwl_priv *priv = dev_get_drvdata(d);
2700 unsigned long val;
2701 int ret;
2702
2703 ret = strict_strtoul(buf, 0, &val);
2704 if (ret)
2705 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
2706 else {
2707 priv->debug_level = val;
2708 if (iwl_alloc_traffic_mem(priv))
2709 IWL_ERR(priv,
2710 "Not enough memory to generate traffic log\n");
2711 }
2712 return strnlen(buf, count);
2713 }
2714
2715 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2716 show_debug_level, store_debug_level);
2717
2718
2719 #endif /* CONFIG_IWLWIFI_DEBUG */
2720
2721
2722 static ssize_t show_temperature(struct device *d,
2723 struct device_attribute *attr, char *buf)
2724 {
2725 struct iwl_priv *priv = dev_get_drvdata(d);
2726
2727 if (!iwl_is_alive(priv))
2728 return -EAGAIN;
2729
2730 return sprintf(buf, "%d\n", priv->temperature);
2731 }
2732
2733 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2734
2735 static ssize_t show_tx_power(struct device *d,
2736 struct device_attribute *attr, char *buf)
2737 {
2738 struct iwl_priv *priv = dev_get_drvdata(d);
2739
2740 if (!iwl_is_ready_rf(priv))
2741 return sprintf(buf, "off\n");
2742 else
2743 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
2744 }
2745
2746 static ssize_t store_tx_power(struct device *d,
2747 struct device_attribute *attr,
2748 const char *buf, size_t count)
2749 {
2750 struct iwl_priv *priv = dev_get_drvdata(d);
2751 unsigned long val;
2752 int ret;
2753
2754 ret = strict_strtoul(buf, 10, &val);
2755 if (ret)
2756 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
2757 else {
2758 ret = iwl_set_tx_power(priv, val, false);
2759 if (ret)
2760 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
2761 ret);
2762 else
2763 ret = count;
2764 }
2765 return ret;
2766 }
2767
2768 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2769
2770 static ssize_t show_flags(struct device *d,
2771 struct device_attribute *attr, char *buf)
2772 {
2773 struct iwl_priv *priv = dev_get_drvdata(d);
2774
2775 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2776 }
2777
2778 static ssize_t store_flags(struct device *d,
2779 struct device_attribute *attr,
2780 const char *buf, size_t count)
2781 {
2782 struct iwl_priv *priv = dev_get_drvdata(d);
2783 unsigned long val;
2784 u32 flags;
2785 int ret = strict_strtoul(buf, 0, &val);
2786 if (ret)
2787 return ret;
2788 flags = (u32)val;
2789
2790 mutex_lock(&priv->mutex);
2791 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2792 /* Cancel any currently running scans... */
2793 if (iwl_scan_cancel_timeout(priv, 100))
2794 IWL_WARN(priv, "Could not cancel scan.\n");
2795 else {
2796 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
2797 priv->staging_rxon.flags = cpu_to_le32(flags);
2798 iwlcore_commit_rxon(priv);
2799 }
2800 }
2801 mutex_unlock(&priv->mutex);
2802
2803 return count;
2804 }
2805
2806 static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2807
2808 static ssize_t show_filter_flags(struct device *d,
2809 struct device_attribute *attr, char *buf)
2810 {
2811 struct iwl_priv *priv = dev_get_drvdata(d);
2812
2813 return sprintf(buf, "0x%04X\n",
2814 le32_to_cpu(priv->active_rxon.filter_flags));
2815 }
2816
2817 static ssize_t store_filter_flags(struct device *d,
2818 struct device_attribute *attr,
2819 const char *buf, size_t count)
2820 {
2821 struct iwl_priv *priv = dev_get_drvdata(d);
2822 unsigned long val;
2823 u32 filter_flags;
2824 int ret = strict_strtoul(buf, 0, &val);
2825 if (ret)
2826 return ret;
2827 filter_flags = (u32)val;
2828
2829 mutex_lock(&priv->mutex);
2830 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2831 /* Cancel any currently running scans... */
2832 if (iwl_scan_cancel_timeout(priv, 100))
2833 IWL_WARN(priv, "Could not cancel scan.\n");
2834 else {
2835 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
2836 "0x%04X\n", filter_flags);
2837 priv->staging_rxon.filter_flags =
2838 cpu_to_le32(filter_flags);
2839 iwlcore_commit_rxon(priv);
2840 }
2841 }
2842 mutex_unlock(&priv->mutex);
2843
2844 return count;
2845 }
2846
2847 static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2848 store_filter_flags);
2849
2850
2851 static ssize_t show_statistics(struct device *d,
2852 struct device_attribute *attr, char *buf)
2853 {
2854 struct iwl_priv *priv = dev_get_drvdata(d);
2855 u32 size = sizeof(struct iwl_notif_statistics);
2856 u32 len = 0, ofs = 0;
2857 u8 *data = (u8 *)&priv->statistics;
2858 int rc = 0;
2859
2860 if (!iwl_is_alive(priv))
2861 return -EAGAIN;
2862
2863 mutex_lock(&priv->mutex);
2864 rc = iwl_send_statistics_request(priv, 0);
2865 mutex_unlock(&priv->mutex);
2866
2867 if (rc) {
2868 len = sprintf(buf,
2869 "Error sending statistics request: 0x%08X\n", rc);
2870 return len;
2871 }
2872
2873 while (size && (PAGE_SIZE - len)) {
2874 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2875 PAGE_SIZE - len, 1);
2876 len = strlen(buf);
2877 if (PAGE_SIZE - len)
2878 buf[len++] = '\n';
2879
2880 ofs += 16;
2881 size -= min(size, 16U);
2882 }
2883
2884 return len;
2885 }
2886
2887 static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2888
2889 static ssize_t show_rts_ht_protection(struct device *d,
2890 struct device_attribute *attr, char *buf)
2891 {
2892 struct iwl_priv *priv = dev_get_drvdata(d);
2893
2894 return sprintf(buf, "%s\n",
2895 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
2896 }
2897
2898 static ssize_t store_rts_ht_protection(struct device *d,
2899 struct device_attribute *attr,
2900 const char *buf, size_t count)
2901 {
2902 struct iwl_priv *priv = dev_get_drvdata(d);
2903 unsigned long val;
2904 int ret;
2905
2906 ret = strict_strtoul(buf, 10, &val);
2907 if (ret)
2908 IWL_INFO(priv, "Input is not in decimal form.\n");
2909 else {
2910 if (!iwl_is_associated(priv))
2911 priv->cfg->use_rts_for_ht = val ? true : false;
2912 else
2913 IWL_ERR(priv, "Sta associated with AP - "
2914 "Change protection mechanism is not allowed\n");
2915 ret = count;
2916 }
2917 return ret;
2918 }
2919
2920 static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
2921 show_rts_ht_protection, store_rts_ht_protection);
2922
2923
2924 /*****************************************************************************
2925 *
2926 * driver setup and teardown
2927 *
2928 *****************************************************************************/
2929
2930 static void iwl_setup_deferred_work(struct iwl_priv *priv)
2931 {
2932 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
2933
2934 init_waitqueue_head(&priv->wait_command_queue);
2935
2936 INIT_WORK(&priv->up, iwl_bg_up);
2937 INIT_WORK(&priv->restart, iwl_bg_restart);
2938 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
2939 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
2940 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
2941 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2942 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2943
2944 iwl_setup_scan_deferred_work(priv);
2945
2946 if (priv->cfg->ops->lib->setup_deferred_work)
2947 priv->cfg->ops->lib->setup_deferred_work(priv);
2948
2949 init_timer(&priv->statistics_periodic);
2950 priv->statistics_periodic.data = (unsigned long)priv;
2951 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
2952
2953 if (!priv->cfg->use_isr_legacy)
2954 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2955 iwl_irq_tasklet, (unsigned long)priv);
2956 else
2957 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2958 iwl_irq_tasklet_legacy, (unsigned long)priv);
2959 }
2960
2961 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
2962 {
2963 if (priv->cfg->ops->lib->cancel_deferred_work)
2964 priv->cfg->ops->lib->cancel_deferred_work(priv);
2965
2966 cancel_delayed_work_sync(&priv->init_alive_start);
2967 cancel_delayed_work(&priv->scan_check);
2968 cancel_delayed_work(&priv->alive_start);
2969 cancel_work_sync(&priv->beacon_update);
2970 del_timer_sync(&priv->statistics_periodic);
2971 }
2972
2973 static void iwl_init_hw_rates(struct iwl_priv *priv,
2974 struct ieee80211_rate *rates)
2975 {
2976 int i;
2977
2978 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
2979 rates[i].bitrate = iwl_rates[i].ieee * 5;
2980 rates[i].hw_value = i; /* Rate scaling will work on indexes */
2981 rates[i].hw_value_short = i;
2982 rates[i].flags = 0;
2983 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
2984 /*
2985 * If CCK != 1M then set short preamble rate flag.
2986 */
2987 rates[i].flags |=
2988 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
2989 0 : IEEE80211_RATE_SHORT_PREAMBLE;
2990 }
2991 }
2992 }
2993
2994 static int iwl_init_drv(struct iwl_priv *priv)
2995 {
2996 int ret;
2997
2998 priv->ibss_beacon = NULL;
2999
3000 spin_lock_init(&priv->lock);
3001 spin_lock_init(&priv->sta_lock);
3002 spin_lock_init(&priv->hcmd_lock);
3003
3004 INIT_LIST_HEAD(&priv->free_frames);
3005
3006 mutex_init(&priv->mutex);
3007
3008 /* Clear the driver's (not device's) station table */
3009 iwl_clear_stations_table(priv);
3010
3011 priv->ieee_channels = NULL;
3012 priv->ieee_rates = NULL;
3013 priv->band = IEEE80211_BAND_2GHZ;
3014
3015 priv->iw_mode = NL80211_IFTYPE_STATION;
3016 if (priv->cfg->support_sm_ps)
3017 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DYNAMIC;
3018 else
3019 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
3020
3021 /* Choose which receivers/antennas to use */
3022 if (priv->cfg->ops->hcmd->set_rxon_chain)
3023 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3024
3025 iwl_init_scan_params(priv);
3026
3027 iwl_reset_qos(priv);
3028
3029 priv->qos_data.qos_active = 0;
3030 priv->qos_data.qos_cap.val = 0;
3031
3032 priv->rates_mask = IWL_RATES_MASK;
3033 /* Set the tx_power_user_lmt to the lowest power level
3034 * this value will get overwritten by channel max power avg
3035 * from eeprom */
3036 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3037
3038 ret = iwl_init_channel_map(priv);
3039 if (ret) {
3040 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3041 goto err;
3042 }
3043
3044 ret = iwlcore_init_geos(priv);
3045 if (ret) {
3046 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3047 goto err_free_channel_map;
3048 }
3049 iwl_init_hw_rates(priv, priv->ieee_rates);
3050
3051 return 0;
3052
3053 err_free_channel_map:
3054 iwl_free_channel_map(priv);
3055 err:
3056 return ret;
3057 }
3058
3059 static void iwl_uninit_drv(struct iwl_priv *priv)
3060 {
3061 iwl_calib_free_results(priv);
3062 iwlcore_free_geos(priv);
3063 iwl_free_channel_map(priv);
3064 kfree(priv->scan);
3065 }
3066
3067 static struct attribute *iwl_sysfs_entries[] = {
3068 &dev_attr_flags.attr,
3069 &dev_attr_filter_flags.attr,
3070 &dev_attr_statistics.attr,
3071 &dev_attr_temperature.attr,
3072 &dev_attr_tx_power.attr,
3073 &dev_attr_rts_ht_protection.attr,
3074 #ifdef CONFIG_IWLWIFI_DEBUG
3075 &dev_attr_debug_level.attr,
3076 #endif
3077 NULL
3078 };
3079
3080 static struct attribute_group iwl_attribute_group = {
3081 .name = NULL, /* put in device directory */
3082 .attrs = iwl_sysfs_entries,
3083 };
3084
3085 static struct ieee80211_ops iwl_hw_ops = {
3086 .tx = iwl_mac_tx,
3087 .start = iwl_mac_start,
3088 .stop = iwl_mac_stop,
3089 .add_interface = iwl_mac_add_interface,
3090 .remove_interface = iwl_mac_remove_interface,
3091 .config = iwl_mac_config,
3092 .configure_filter = iwl_configure_filter,
3093 .set_key = iwl_mac_set_key,
3094 .update_tkip_key = iwl_mac_update_tkip_key,
3095 .get_stats = iwl_mac_get_stats,
3096 .get_tx_stats = iwl_mac_get_tx_stats,
3097 .conf_tx = iwl_mac_conf_tx,
3098 .reset_tsf = iwl_mac_reset_tsf,
3099 .bss_info_changed = iwl_bss_info_changed,
3100 .ampdu_action = iwl_mac_ampdu_action,
3101 .hw_scan = iwl_mac_hw_scan
3102 };
3103
3104 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3105 {
3106 int err = 0;
3107 struct iwl_priv *priv;
3108 struct ieee80211_hw *hw;
3109 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3110 unsigned long flags;
3111 u16 pci_cmd;
3112
3113 /************************
3114 * 1. Allocating HW data
3115 ************************/
3116
3117 /* Disabling hardware scan means that mac80211 will perform scans
3118 * "the hard way", rather than using device's scan. */
3119 if (cfg->mod_params->disable_hw_scan) {
3120 if (iwl_debug_level & IWL_DL_INFO)
3121 dev_printk(KERN_DEBUG, &(pdev->dev),
3122 "Disabling hw_scan\n");
3123 iwl_hw_ops.hw_scan = NULL;
3124 }
3125
3126 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
3127 if (!hw) {
3128 err = -ENOMEM;
3129 goto out;
3130 }
3131 priv = hw->priv;
3132 /* At this point both hw and priv are allocated. */
3133
3134 SET_IEEE80211_DEV(hw, &pdev->dev);
3135
3136 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3137 priv->cfg = cfg;
3138 priv->pci_dev = pdev;
3139 priv->inta_mask = CSR_INI_SET_MASK;
3140
3141 #ifdef CONFIG_IWLWIFI_DEBUG
3142 atomic_set(&priv->restrict_refcnt, 0);
3143 #endif
3144 if (iwl_alloc_traffic_mem(priv))
3145 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3146
3147 /**************************
3148 * 2. Initializing PCI bus
3149 **************************/
3150 if (pci_enable_device(pdev)) {
3151 err = -ENODEV;
3152 goto out_ieee80211_free_hw;
3153 }
3154
3155 pci_set_master(pdev);
3156
3157 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3158 if (!err)
3159 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3160 if (err) {
3161 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3162 if (!err)
3163 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3164 /* both attempts failed: */
3165 if (err) {
3166 IWL_WARN(priv, "No suitable DMA available.\n");
3167 goto out_pci_disable_device;
3168 }
3169 }
3170
3171 err = pci_request_regions(pdev, DRV_NAME);
3172 if (err)
3173 goto out_pci_disable_device;
3174
3175 pci_set_drvdata(pdev, priv);
3176
3177
3178 /***********************
3179 * 3. Read REV register
3180 ***********************/
3181 priv->hw_base = pci_iomap(pdev, 0, 0);
3182 if (!priv->hw_base) {
3183 err = -ENODEV;
3184 goto out_pci_release_regions;
3185 }
3186
3187 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3188 (unsigned long long) pci_resource_len(pdev, 0));
3189 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3190
3191 /* this spin lock will be used in apm_ops.init and EEPROM access
3192 * we should init now
3193 */
3194 spin_lock_init(&priv->reg_lock);
3195 iwl_hw_detect(priv);
3196 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
3197 priv->cfg->name, priv->hw_rev);
3198
3199 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3200 * PCI Tx retries from interfering with C3 CPU state */
3201 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3202
3203 iwl_prepare_card_hw(priv);
3204 if (!priv->hw_ready) {
3205 IWL_WARN(priv, "Failed, HW not ready\n");
3206 goto out_iounmap;
3207 }
3208
3209 /*****************
3210 * 4. Read EEPROM
3211 *****************/
3212 /* Read the EEPROM */
3213 err = iwl_eeprom_init(priv);
3214 if (err) {
3215 IWL_ERR(priv, "Unable to init EEPROM\n");
3216 goto out_iounmap;
3217 }
3218 err = iwl_eeprom_check_version(priv);
3219 if (err)
3220 goto out_free_eeprom;
3221
3222 /* extract MAC Address */
3223 iwl_eeprom_get_mac(priv, priv->mac_addr);
3224 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
3225 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3226
3227 /************************
3228 * 5. Setup HW constants
3229 ************************/
3230 if (iwl_set_hw_params(priv)) {
3231 IWL_ERR(priv, "failed to set hw parameters\n");
3232 goto out_free_eeprom;
3233 }
3234
3235 /*******************
3236 * 6. Setup priv
3237 *******************/
3238
3239 err = iwl_init_drv(priv);
3240 if (err)
3241 goto out_free_eeprom;
3242 /* At this point both hw and priv are initialized. */
3243
3244 /********************
3245 * 7. Setup services
3246 ********************/
3247 spin_lock_irqsave(&priv->lock, flags);
3248 iwl_disable_interrupts(priv);
3249 spin_unlock_irqrestore(&priv->lock, flags);
3250
3251 pci_enable_msi(priv->pci_dev);
3252
3253 iwl_alloc_isr_ict(priv);
3254 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3255 IRQF_SHARED, DRV_NAME, priv);
3256 if (err) {
3257 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3258 goto out_disable_msi;
3259 }
3260 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
3261 if (err) {
3262 IWL_ERR(priv, "failed to create sysfs device attributes\n");
3263 goto out_free_irq;
3264 }
3265
3266 iwl_setup_deferred_work(priv);
3267 iwl_setup_rx_handlers(priv);
3268
3269 /**********************************
3270 * 8. Setup and register mac80211
3271 **********************************/
3272
3273 /* enable interrupts if needed: hw bug w/a */
3274 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3275 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3276 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3277 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3278 }
3279
3280 iwl_enable_interrupts(priv);
3281
3282 err = iwl_setup_mac(priv);
3283 if (err)
3284 goto out_remove_sysfs;
3285
3286 err = iwl_dbgfs_register(priv, DRV_NAME);
3287 if (err)
3288 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
3289
3290 /* If platform's RF_KILL switch is NOT set to KILL */
3291 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3292 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3293 else
3294 set_bit(STATUS_RF_KILL_HW, &priv->status);
3295
3296 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3297 test_bit(STATUS_RF_KILL_HW, &priv->status));
3298
3299 iwl_power_initialize(priv);
3300 iwl_tt_initialize(priv);
3301 return 0;
3302
3303 out_remove_sysfs:
3304 destroy_workqueue(priv->workqueue);
3305 priv->workqueue = NULL;
3306 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3307 out_free_irq:
3308 free_irq(priv->pci_dev->irq, priv);
3309 iwl_free_isr_ict(priv);
3310 out_disable_msi:
3311 pci_disable_msi(priv->pci_dev);
3312 iwl_uninit_drv(priv);
3313 out_free_eeprom:
3314 iwl_eeprom_free(priv);
3315 out_iounmap:
3316 pci_iounmap(pdev, priv->hw_base);
3317 out_pci_release_regions:
3318 pci_set_drvdata(pdev, NULL);
3319 pci_release_regions(pdev);
3320 out_pci_disable_device:
3321 pci_disable_device(pdev);
3322 out_ieee80211_free_hw:
3323 iwl_free_traffic_mem(priv);
3324 ieee80211_free_hw(priv->hw);
3325 out:
3326 return err;
3327 }
3328
3329 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3330 {
3331 struct iwl_priv *priv = pci_get_drvdata(pdev);
3332 unsigned long flags;
3333
3334 if (!priv)
3335 return;
3336
3337 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3338
3339 iwl_dbgfs_unregister(priv);
3340 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3341
3342 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3343 * to be called and iwl_down since we are removing the device
3344 * we need to set STATUS_EXIT_PENDING bit.
3345 */
3346 set_bit(STATUS_EXIT_PENDING, &priv->status);
3347 if (priv->mac80211_registered) {
3348 ieee80211_unregister_hw(priv->hw);
3349 priv->mac80211_registered = 0;
3350 } else {
3351 iwl_down(priv);
3352 }
3353
3354 /*
3355 * Make sure device is reset to low power before unloading driver.
3356 * This may be redundant with iwl_down(), but there are paths to
3357 * run iwl_down() without calling apm_ops.stop(), and there are
3358 * paths to avoid running iwl_down() at all before leaving driver.
3359 * This (inexpensive) call *makes sure* device is reset.
3360 */
3361 priv->cfg->ops->lib->apm_ops.stop(priv);
3362
3363 iwl_tt_exit(priv);
3364
3365 /* make sure we flush any pending irq or
3366 * tasklet for the driver
3367 */
3368 spin_lock_irqsave(&priv->lock, flags);
3369 iwl_disable_interrupts(priv);
3370 spin_unlock_irqrestore(&priv->lock, flags);
3371
3372 iwl_synchronize_irq(priv);
3373
3374 iwl_dealloc_ucode_pci(priv);
3375
3376 if (priv->rxq.bd)
3377 iwl_rx_queue_free(priv, &priv->rxq);
3378 iwl_hw_txq_ctx_free(priv);
3379
3380 iwl_clear_stations_table(priv);
3381 iwl_eeprom_free(priv);
3382
3383
3384 /*netif_stop_queue(dev); */
3385 flush_workqueue(priv->workqueue);
3386
3387 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3388 * priv->workqueue... so we can't take down the workqueue
3389 * until now... */
3390 destroy_workqueue(priv->workqueue);
3391 priv->workqueue = NULL;
3392 iwl_free_traffic_mem(priv);
3393
3394 free_irq(priv->pci_dev->irq, priv);
3395 pci_disable_msi(priv->pci_dev);
3396 pci_iounmap(pdev, priv->hw_base);
3397 pci_release_regions(pdev);
3398 pci_disable_device(pdev);
3399 pci_set_drvdata(pdev, NULL);
3400
3401 iwl_uninit_drv(priv);
3402
3403 iwl_free_isr_ict(priv);
3404
3405 if (priv->ibss_beacon)
3406 dev_kfree_skb(priv->ibss_beacon);
3407
3408 ieee80211_free_hw(priv->hw);
3409 }
3410
3411
3412 /*****************************************************************************
3413 *
3414 * driver and module entry point
3415 *
3416 *****************************************************************************/
3417
3418 /* Hardware specific file defines the PCI IDs table for that hardware module */
3419 static struct pci_device_id iwl_hw_card_ids[] = {
3420 #ifdef CONFIG_IWL4965
3421 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3422 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
3423 #endif /* CONFIG_IWL4965 */
3424 #ifdef CONFIG_IWL5000
3425 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3426 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3427 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3428 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3429 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3430 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
3431 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
3432 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3433 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3434 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
3435 /* 5350 WiFi/WiMax */
3436 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3437 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3438 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
3439 /* 5150 Wifi/WiMax */
3440 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3441 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
3442
3443 /* 6x00 Series */
3444 {IWL_PCI_DEVICE(0x008D, 0x1301, iwl6000h_2agn_cfg)},
3445 {IWL_PCI_DEVICE(0x008D, 0x1321, iwl6000h_2agn_cfg)},
3446 {IWL_PCI_DEVICE(0x008D, 0x1326, iwl6000h_2abg_cfg)},
3447 {IWL_PCI_DEVICE(0x008D, 0x1306, iwl6000h_2abg_cfg)},
3448 {IWL_PCI_DEVICE(0x008D, 0x1307, iwl6000h_2bg_cfg)},
3449 {IWL_PCI_DEVICE(0x008E, 0x1311, iwl6000h_2agn_cfg)},
3450 {IWL_PCI_DEVICE(0x008E, 0x1316, iwl6000h_2abg_cfg)},
3451
3452 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3453 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3454 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3455 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3456 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3457 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3458 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3459 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3460 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3461 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3462
3463 /* 6x50 WiFi/WiMax Series */
3464 {IWL_PCI_DEVICE(0x0086, 0x1101, iwl6050_3agn_cfg)},
3465 {IWL_PCI_DEVICE(0x0086, 0x1121, iwl6050_3agn_cfg)},
3466 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3467 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3468 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3469 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
3470 {IWL_PCI_DEVICE(0x0088, 0x1111, iwl6050_3agn_cfg)},
3471 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3472 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3473
3474 /* 1000 Series WiFi */
3475 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3476 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3477 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3478 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3479 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3480 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3481 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3482 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3483 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3484 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3485 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3486 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
3487 #endif /* CONFIG_IWL5000 */
3488
3489 {0}
3490 };
3491 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3492
3493 static struct pci_driver iwl_driver = {
3494 .name = DRV_NAME,
3495 .id_table = iwl_hw_card_ids,
3496 .probe = iwl_pci_probe,
3497 .remove = __devexit_p(iwl_pci_remove),
3498 #ifdef CONFIG_PM
3499 .suspend = iwl_pci_suspend,
3500 .resume = iwl_pci_resume,
3501 #endif
3502 };
3503
3504 static int __init iwl_init(void)
3505 {
3506
3507 int ret;
3508 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3509 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
3510
3511 ret = iwlagn_rate_control_register();
3512 if (ret) {
3513 printk(KERN_ERR DRV_NAME
3514 "Unable to register rate control algorithm: %d\n", ret);
3515 return ret;
3516 }
3517
3518 ret = pci_register_driver(&iwl_driver);
3519 if (ret) {
3520 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
3521 goto error_register;
3522 }
3523
3524 return ret;
3525
3526 error_register:
3527 iwlagn_rate_control_unregister();
3528 return ret;
3529 }
3530
3531 static void __exit iwl_exit(void)
3532 {
3533 pci_unregister_driver(&iwl_driver);
3534 iwlagn_rate_control_unregister();
3535 }
3536
3537 module_exit(iwl_exit);
3538 module_init(iwl_init);
3539
3540 #ifdef CONFIG_IWLWIFI_DEBUG
3541 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
3542 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
3543 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
3544 MODULE_PARM_DESC(debug, "debug output mask");
3545 #endif
3546
Linux kernel - Deliverables
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