1 /******************************************************************************
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/version.h>
32 #include <net/mac80211.h>
34 struct iwl_priv
; /* FIXME: remove */
35 #include "iwl-debug.h"
36 #include "iwl-eeprom.h"
37 #include "iwl-dev.h" /* FIXME: remove */
40 #include "iwl-rfkill.h"
41 #include "iwl-power.h"
44 MODULE_DESCRIPTION("iwl core");
45 MODULE_VERSION(IWLWIFI_VERSION
);
46 MODULE_AUTHOR(DRV_COPYRIGHT
);
47 MODULE_LICENSE("GPL");
49 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
64 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
70 const struct iwl_rate_info iwl_rates
[IWL_RATE_COUNT
] = {
71 IWL_DECLARE_RATE_INFO(1, INV
, INV
, 2, INV
, 2, INV
, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, INV
, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, INV
, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, INV
, 9, 12, 9, 12, 5, 18), /* 11mbps */
75 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 54, 48, INV
, 48, INV
, 48, INV
),/* 54mbps */
83 IWL_DECLARE_RATE_INFO(60, 60, 48, INV
, 48, INV
, 48, INV
),/* 60mbps */
84 /* FIXME:RS: ^^ should be INV (legacy) */
86 EXPORT_SYMBOL(iwl_rates
);
89 * translate ucode response to mac80211 tx status control values
91 void iwl_hwrate_to_tx_control(struct iwl_priv
*priv
, u32 rate_n_flags
,
92 struct ieee80211_tx_info
*control
)
96 control
->antenna_sel_tx
=
97 ((rate_n_flags
& RATE_MCS_ANT_ABC_MSK
) >> RATE_MCS_ANT_POS
);
98 if (rate_n_flags
& RATE_MCS_HT_MSK
)
99 control
->flags
|= IEEE80211_TX_CTL_OFDM_HT
;
100 if (rate_n_flags
& RATE_MCS_GF_MSK
)
101 control
->flags
|= IEEE80211_TX_CTL_GREEN_FIELD
;
102 if (rate_n_flags
& RATE_MCS_FAT_MSK
)
103 control
->flags
|= IEEE80211_TX_CTL_40_MHZ_WIDTH
;
104 if (rate_n_flags
& RATE_MCS_DUP_MSK
)
105 control
->flags
|= IEEE80211_TX_CTL_DUP_DATA
;
106 if (rate_n_flags
& RATE_MCS_SGI_MSK
)
107 control
->flags
|= IEEE80211_TX_CTL_SHORT_GI
;
108 rate_index
= iwl_hwrate_to_plcp_idx(rate_n_flags
);
109 if (control
->band
== IEEE80211_BAND_5GHZ
)
110 rate_index
-= IWL_FIRST_OFDM_RATE
;
111 control
->tx_rate_idx
= rate_index
;
113 EXPORT_SYMBOL(iwl_hwrate_to_tx_control
);
115 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags
)
120 if (rate_n_flags
& RATE_MCS_HT_MSK
) {
121 idx
= (rate_n_flags
& 0xff);
123 if (idx
>= IWL_RATE_MIMO2_6M_PLCP
)
124 idx
= idx
- IWL_RATE_MIMO2_6M_PLCP
;
126 idx
+= IWL_FIRST_OFDM_RATE
;
127 /* skip 9M not supported in ht*/
128 if (idx
>= IWL_RATE_9M_INDEX
)
130 if ((idx
>= IWL_FIRST_OFDM_RATE
) && (idx
<= IWL_LAST_OFDM_RATE
))
133 /* legacy rate format, search for match in table */
135 for (idx
= 0; idx
< ARRAY_SIZE(iwl_rates
); idx
++)
136 if (iwl_rates
[idx
].plcp
== (rate_n_flags
& 0xFF))
142 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx
);
146 const u8 iwl_bcast_addr
[ETH_ALEN
] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
147 EXPORT_SYMBOL(iwl_bcast_addr
);
150 /* This function both allocates and initializes hw and priv. */
151 struct ieee80211_hw
*iwl_alloc_all(struct iwl_cfg
*cfg
,
152 struct ieee80211_ops
*hw_ops
)
154 struct iwl_priv
*priv
;
156 /* mac80211 allocates memory for this device instance, including
157 * space for this driver's private structure */
158 struct ieee80211_hw
*hw
=
159 ieee80211_alloc_hw(sizeof(struct iwl_priv
), hw_ops
);
161 IWL_ERROR("Can not allocate network device\n");
171 EXPORT_SYMBOL(iwl_alloc_all
);
173 void iwl_hw_detect(struct iwl_priv
*priv
)
175 priv
->hw_rev
= _iwl_read32(priv
, CSR_HW_REV
);
176 priv
->hw_wa_rev
= _iwl_read32(priv
, CSR_HW_REV_WA_REG
);
177 pci_read_config_byte(priv
->pci_dev
, PCI_REVISION_ID
, &priv
->rev_id
);
179 EXPORT_SYMBOL(iwl_hw_detect
);
181 /* Tell nic where to find the "keep warm" buffer */
182 int iwl_kw_init(struct iwl_priv
*priv
)
187 spin_lock_irqsave(&priv
->lock
, flags
);
188 ret
= iwl_grab_nic_access(priv
);
192 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
,
193 priv
->kw
.dma_addr
>> 4);
194 iwl_release_nic_access(priv
);
196 spin_unlock_irqrestore(&priv
->lock
, flags
);
200 int iwl_kw_alloc(struct iwl_priv
*priv
)
202 struct pci_dev
*dev
= priv
->pci_dev
;
203 struct iwl_kw
*kw
= &priv
->kw
;
205 kw
->size
= IWL_KW_SIZE
;
206 kw
->v_addr
= pci_alloc_consistent(dev
, kw
->size
, &kw
->dma_addr
);
214 * iwl_kw_free - Free the "keep warm" buffer
216 void iwl_kw_free(struct iwl_priv
*priv
)
218 struct pci_dev
*dev
= priv
->pci_dev
;
219 struct iwl_kw
*kw
= &priv
->kw
;
222 pci_free_consistent(dev
, kw
->size
, kw
->v_addr
, kw
->dma_addr
);
223 memset(kw
, 0, sizeof(*kw
));
227 int iwl_hw_nic_init(struct iwl_priv
*priv
)
230 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
234 spin_lock_irqsave(&priv
->lock
, flags
);
235 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
236 iwl_write32(priv
, CSR_INT_COALESCING
, 512 / 32);
237 spin_unlock_irqrestore(&priv
->lock
, flags
);
239 ret
= priv
->cfg
->ops
->lib
->apm_ops
.set_pwr_src(priv
, IWL_PWR_SRC_VMAIN
);
241 priv
->cfg
->ops
->lib
->apm_ops
.config(priv
);
243 /* Allocate the RX queue, or reset if it is already allocated */
245 ret
= iwl_rx_queue_alloc(priv
);
247 IWL_ERROR("Unable to initialize Rx queue\n");
251 iwl_rx_queue_reset(priv
, rxq
);
253 iwl_rx_replenish(priv
);
255 iwl_rx_init(priv
, rxq
);
257 spin_lock_irqsave(&priv
->lock
, flags
);
259 rxq
->need_update
= 1;
260 iwl_rx_queue_update_write_ptr(priv
, rxq
);
262 spin_unlock_irqrestore(&priv
->lock
, flags
);
264 /* Allocate and init all Tx and Command queues */
265 ret
= iwl_txq_ctx_reset(priv
);
269 set_bit(STATUS_INIT
, &priv
->status
);
273 EXPORT_SYMBOL(iwl_hw_nic_init
);
276 * iwlcore_clear_stations_table - Clear the driver's station table
278 * NOTE: This does not clear or otherwise alter the device's station table.
280 void iwlcore_clear_stations_table(struct iwl_priv
*priv
)
284 spin_lock_irqsave(&priv
->sta_lock
, flags
);
286 priv
->num_stations
= 0;
287 memset(priv
->stations
, 0, sizeof(priv
->stations
));
289 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
291 EXPORT_SYMBOL(iwlcore_clear_stations_table
);
293 void iwl_reset_qos(struct iwl_priv
*priv
)
302 spin_lock_irqsave(&priv
->lock
, flags
);
303 priv
->qos_data
.qos_active
= 0;
305 if (priv
->iw_mode
== IEEE80211_IF_TYPE_IBSS
) {
306 if (priv
->qos_data
.qos_enable
)
307 priv
->qos_data
.qos_active
= 1;
308 if (!(priv
->active_rate
& 0xfff0)) {
312 } else if (priv
->iw_mode
== IEEE80211_IF_TYPE_AP
) {
313 if (priv
->qos_data
.qos_enable
)
314 priv
->qos_data
.qos_active
= 1;
315 } else if (!(priv
->staging_rxon
.flags
& RXON_FLG_SHORT_SLOT_MSK
)) {
320 if (priv
->qos_data
.qos_active
)
323 priv
->qos_data
.def_qos_parm
.ac
[0].cw_min
= cpu_to_le16(cw_min
);
324 priv
->qos_data
.def_qos_parm
.ac
[0].cw_max
= cpu_to_le16(cw_max
);
325 priv
->qos_data
.def_qos_parm
.ac
[0].aifsn
= aifs
;
326 priv
->qos_data
.def_qos_parm
.ac
[0].edca_txop
= 0;
327 priv
->qos_data
.def_qos_parm
.ac
[0].reserved1
= 0;
329 if (priv
->qos_data
.qos_active
) {
331 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
= cpu_to_le16(cw_min
);
332 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
= cpu_to_le16(cw_max
);
333 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 7;
334 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
= 0;
335 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
338 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
339 cpu_to_le16((cw_min
+ 1) / 2 - 1);
340 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
342 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 2;
344 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
347 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
349 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
352 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
353 cpu_to_le16((cw_min
+ 1) / 4 - 1);
354 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
355 cpu_to_le16((cw_max
+ 1) / 2 - 1);
356 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 2;
357 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
359 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
362 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
365 for (i
= 1; i
< 4; i
++) {
366 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
368 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
370 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= aifs
;
371 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
= 0;
372 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
375 IWL_DEBUG_QOS("set QoS to default \n");
377 spin_unlock_irqrestore(&priv
->lock
, flags
);
379 EXPORT_SYMBOL(iwl_reset_qos
);
381 #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
382 #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
383 static void iwlcore_init_ht_hw_capab(const struct iwl_priv
*priv
,
384 struct ieee80211_ht_info
*ht_info
,
385 enum ieee80211_band band
)
387 u16 max_bit_rate
= 0;
388 u8 rx_chains_num
= priv
->hw_params
.rx_chains_num
;
389 u8 tx_chains_num
= priv
->hw_params
.tx_chains_num
;
392 memset(ht_info
->supp_mcs_set
, 0, 16);
394 ht_info
->ht_supported
= 1;
396 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_GRN_FLD
;
397 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_SGI_20
;
398 ht_info
->cap
|= (u16
)(IEEE80211_HT_CAP_MIMO_PS
&
399 (IWL_MIMO_PS_NONE
<< 2));
401 max_bit_rate
= MAX_BIT_RATE_20_MHZ
;
402 if (priv
->hw_params
.fat_channel
& BIT(band
)) {
403 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_SUP_WIDTH
;
404 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_SGI_40
;
405 ht_info
->supp_mcs_set
[4] = 0x01;
406 max_bit_rate
= MAX_BIT_RATE_40_MHZ
;
409 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
410 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_MAX_AMSDU
;
412 ht_info
->ampdu_factor
= CFG_HT_RX_AMPDU_FACTOR_DEF
;
413 ht_info
->ampdu_density
= CFG_HT_MPDU_DENSITY_DEF
;
415 ht_info
->supp_mcs_set
[0] = 0xFF;
416 if (rx_chains_num
>= 2)
417 ht_info
->supp_mcs_set
[1] = 0xFF;
418 if (rx_chains_num
>= 3)
419 ht_info
->supp_mcs_set
[2] = 0xFF;
421 /* Highest supported Rx data rate */
422 max_bit_rate
*= rx_chains_num
;
423 ht_info
->supp_mcs_set
[10] = (u8
)(max_bit_rate
& 0x00FF);
424 ht_info
->supp_mcs_set
[11] = (u8
)((max_bit_rate
& 0xFF00) >> 8);
426 /* Tx MCS capabilities */
427 ht_info
->supp_mcs_set
[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED
;
428 if (tx_chains_num
!= rx_chains_num
) {
429 ht_info
->supp_mcs_set
[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF
;
430 ht_info
->supp_mcs_set
[12] |= ((tx_chains_num
- 1) << 2);
434 static void iwlcore_init_hw_rates(struct iwl_priv
*priv
,
435 struct ieee80211_rate
*rates
)
439 for (i
= 0; i
< IWL_RATE_COUNT
; i
++) {
440 rates
[i
].bitrate
= iwl_rates
[i
].ieee
* 5;
441 rates
[i
].hw_value
= i
; /* Rate scaling will work on indexes */
442 rates
[i
].hw_value_short
= i
;
444 if ((i
> IWL_LAST_OFDM_RATE
) || (i
< IWL_FIRST_OFDM_RATE
)) {
446 * If CCK != 1M then set short preamble rate flag.
449 (iwl_rates
[i
].plcp
== IWL_RATE_1M_PLCP
) ?
450 0 : IEEE80211_RATE_SHORT_PREAMBLE
;
456 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
458 static int iwlcore_init_geos(struct iwl_priv
*priv
)
460 struct iwl_channel_info
*ch
;
461 struct ieee80211_supported_band
*sband
;
462 struct ieee80211_channel
*channels
;
463 struct ieee80211_channel
*geo_ch
;
464 struct ieee80211_rate
*rates
;
467 if (priv
->bands
[IEEE80211_BAND_2GHZ
].n_bitrates
||
468 priv
->bands
[IEEE80211_BAND_5GHZ
].n_bitrates
) {
469 IWL_DEBUG_INFO("Geography modes already initialized.\n");
470 set_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
474 channels
= kzalloc(sizeof(struct ieee80211_channel
) *
475 priv
->channel_count
, GFP_KERNEL
);
479 rates
= kzalloc((sizeof(struct ieee80211_rate
) * (IWL_RATE_COUNT
+ 1)),
486 /* 5.2GHz channels start after the 2.4GHz channels */
487 sband
= &priv
->bands
[IEEE80211_BAND_5GHZ
];
488 sband
->channels
= &channels
[ARRAY_SIZE(iwl_eeprom_band_1
)];
490 sband
->bitrates
= &rates
[IWL_FIRST_OFDM_RATE
];
491 sband
->n_bitrates
= IWL_RATE_COUNT
- IWL_FIRST_OFDM_RATE
;
493 iwlcore_init_ht_hw_capab(priv
, &sband
->ht_info
, IEEE80211_BAND_5GHZ
);
495 sband
= &priv
->bands
[IEEE80211_BAND_2GHZ
];
496 sband
->channels
= channels
;
498 sband
->bitrates
= rates
;
499 sband
->n_bitrates
= IWL_RATE_COUNT
;
501 iwlcore_init_ht_hw_capab(priv
, &sband
->ht_info
, IEEE80211_BAND_2GHZ
);
503 priv
->ieee_channels
= channels
;
504 priv
->ieee_rates
= rates
;
506 iwlcore_init_hw_rates(priv
, rates
);
508 for (i
= 0; i
< priv
->channel_count
; i
++) {
509 ch
= &priv
->channel_info
[i
];
511 /* FIXME: might be removed if scan is OK */
512 if (!is_channel_valid(ch
))
515 if (is_channel_a_band(ch
))
516 sband
= &priv
->bands
[IEEE80211_BAND_5GHZ
];
518 sband
= &priv
->bands
[IEEE80211_BAND_2GHZ
];
520 geo_ch
= &sband
->channels
[sband
->n_channels
++];
522 geo_ch
->center_freq
=
523 ieee80211_channel_to_frequency(ch
->channel
);
524 geo_ch
->max_power
= ch
->max_power_avg
;
525 geo_ch
->max_antenna_gain
= 0xff;
526 geo_ch
->hw_value
= ch
->channel
;
528 if (is_channel_valid(ch
)) {
529 if (!(ch
->flags
& EEPROM_CHANNEL_IBSS
))
530 geo_ch
->flags
|= IEEE80211_CHAN_NO_IBSS
;
532 if (!(ch
->flags
& EEPROM_CHANNEL_ACTIVE
))
533 geo_ch
->flags
|= IEEE80211_CHAN_PASSIVE_SCAN
;
535 if (ch
->flags
& EEPROM_CHANNEL_RADAR
)
536 geo_ch
->flags
|= IEEE80211_CHAN_RADAR
;
538 geo_ch
->flags
|= ch
->fat_extension_channel
;
540 if (ch
->max_power_avg
> priv
->tx_power_channel_lmt
)
541 priv
->tx_power_channel_lmt
= ch
->max_power_avg
;
543 geo_ch
->flags
|= IEEE80211_CHAN_DISABLED
;
546 /* Save flags for reg domain usage */
547 geo_ch
->orig_flags
= geo_ch
->flags
;
549 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
550 ch
->channel
, geo_ch
->center_freq
,
551 is_channel_a_band(ch
) ? "5.2" : "2.4",
552 geo_ch
->flags
& IEEE80211_CHAN_DISABLED
?
553 "restricted" : "valid",
557 if ((priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
== 0) &&
558 priv
->cfg
->sku
& IWL_SKU_A
) {
559 printk(KERN_INFO DRV_NAME
560 ": Incorrectly detected BG card as ABG. Please send "
561 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
562 priv
->pci_dev
->device
, priv
->pci_dev
->subsystem_device
);
563 priv
->cfg
->sku
&= ~IWL_SKU_A
;
566 printk(KERN_INFO DRV_NAME
567 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
568 priv
->bands
[IEEE80211_BAND_2GHZ
].n_channels
,
569 priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
);
572 set_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
578 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
580 static void iwlcore_free_geos(struct iwl_priv
*priv
)
582 kfree(priv
->ieee_channels
);
583 kfree(priv
->ieee_rates
);
584 clear_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
587 static u8
is_single_rx_stream(struct iwl_priv
*priv
)
589 return !priv
->current_ht_config
.is_ht
||
590 ((priv
->current_ht_config
.supp_mcs_set
[1] == 0) &&
591 (priv
->current_ht_config
.supp_mcs_set
[2] == 0)) ||
592 priv
->ps_mode
== IWL_MIMO_PS_STATIC
;
595 static u8
iwl_is_channel_extension(struct iwl_priv
*priv
,
596 enum ieee80211_band band
,
597 u16 channel
, u8 extension_chan_offset
)
599 const struct iwl_channel_info
*ch_info
;
601 ch_info
= iwl_get_channel_info(priv
, band
, channel
);
602 if (!is_channel_valid(ch_info
))
605 if (extension_chan_offset
== IEEE80211_HT_IE_CHA_SEC_ABOVE
)
606 return !(ch_info
->fat_extension_channel
&
607 IEEE80211_CHAN_NO_FAT_ABOVE
);
608 else if (extension_chan_offset
== IEEE80211_HT_IE_CHA_SEC_BELOW
)
609 return !(ch_info
->fat_extension_channel
&
610 IEEE80211_CHAN_NO_FAT_BELOW
);
615 u8
iwl_is_fat_tx_allowed(struct iwl_priv
*priv
,
616 struct ieee80211_ht_info
*sta_ht_inf
)
618 struct iwl_ht_info
*iwl_ht_conf
= &priv
->current_ht_config
;
620 if ((!iwl_ht_conf
->is_ht
) ||
621 (iwl_ht_conf
->supported_chan_width
!= IWL_CHANNEL_WIDTH_40MHZ
) ||
622 (iwl_ht_conf
->extension_chan_offset
== IEEE80211_HT_IE_CHA_SEC_NONE
))
626 if ((!sta_ht_inf
->ht_supported
) ||
627 (!(sta_ht_inf
->cap
& IEEE80211_HT_CAP_SUP_WIDTH
)))
631 return iwl_is_channel_extension(priv
, priv
->band
,
632 iwl_ht_conf
->control_channel
,
633 iwl_ht_conf
->extension_chan_offset
);
635 EXPORT_SYMBOL(iwl_is_fat_tx_allowed
);
637 void iwl_set_rxon_ht(struct iwl_priv
*priv
, struct iwl_ht_info
*ht_info
)
639 struct iwl_rxon_cmd
*rxon
= &priv
->staging_rxon
;
645 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
646 if (iwl_is_fat_tx_allowed(priv
, NULL
))
647 rxon
->flags
|= RXON_FLG_CHANNEL_MODE_MIXED_MSK
;
649 rxon
->flags
&= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK
|
650 RXON_FLG_CHANNEL_MODE_PURE_40_MSK
);
652 if (le16_to_cpu(rxon
->channel
) != ht_info
->control_channel
) {
653 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
654 le16_to_cpu(rxon
->channel
),
655 ht_info
->control_channel
);
659 /* Note: control channel is opposite of extension channel */
660 switch (ht_info
->extension_chan_offset
) {
661 case IEEE80211_HT_IE_CHA_SEC_ABOVE
:
662 rxon
->flags
&= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
);
664 case IEEE80211_HT_IE_CHA_SEC_BELOW
:
665 rxon
->flags
|= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
;
667 case IEEE80211_HT_IE_CHA_SEC_NONE
:
669 rxon
->flags
&= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK
;
673 val
= ht_info
->ht_protection
;
675 rxon
->flags
|= cpu_to_le32(val
<< RXON_FLG_HT_OPERATING_MODE_POS
);
677 iwl_set_rxon_chain(priv
);
679 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
680 "rxon flags 0x%X operation mode :0x%X "
681 "extension channel offset 0x%x "
683 ht_info
->supp_mcs_set
[0],
684 ht_info
->supp_mcs_set
[1],
685 ht_info
->supp_mcs_set
[2],
686 le32_to_cpu(rxon
->flags
), ht_info
->ht_protection
,
687 ht_info
->extension_chan_offset
,
688 ht_info
->control_channel
);
691 EXPORT_SYMBOL(iwl_set_rxon_ht
);
694 * Determine how many receiver/antenna chains to use.
695 * More provides better reception via diversity. Fewer saves power.
696 * MIMO (dual stream) requires at least 2, but works better with 3.
697 * This does not determine *which* chains to use, just how many.
699 static int iwlcore_get_rx_chain_counter(struct iwl_priv
*priv
,
700 u8
*idle_state
, u8
*rx_state
)
702 u8 is_single
= is_single_rx_stream(priv
);
703 u8 is_cam
= test_bit(STATUS_POWER_PMI
, &priv
->status
) ? 0 : 1;
705 /* # of Rx chains to use when expecting MIMO. */
706 if (is_single
|| (!is_cam
&& (priv
->ps_mode
== IWL_MIMO_PS_STATIC
)))
711 /* # Rx chains when idling and maybe trying to save power */
712 switch (priv
->ps_mode
) {
713 case IWL_MIMO_PS_STATIC
:
714 case IWL_MIMO_PS_DYNAMIC
:
715 *idle_state
= (is_cam
) ? 2 : 1;
717 case IWL_MIMO_PS_NONE
:
718 *idle_state
= (is_cam
) ? *rx_state
: 1;
729 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
731 * Selects how many and which Rx receivers/antennas/chains to use.
732 * This should not be used for scan command ... it puts data in wrong place.
734 void iwl_set_rxon_chain(struct iwl_priv
*priv
)
736 u8 is_single
= is_single_rx_stream(priv
);
737 u8 idle_state
, rx_state
;
739 priv
->staging_rxon
.rx_chain
= 0;
740 rx_state
= idle_state
= 3;
742 /* Tell uCode which antennas are actually connected.
743 * Before first association, we assume all antennas are connected.
744 * Just after first association, iwl_chain_noise_calibration()
745 * checks which antennas actually *are* connected. */
746 priv
->staging_rxon
.rx_chain
|=
747 cpu_to_le16(priv
->hw_params
.valid_rx_ant
<<
748 RXON_RX_CHAIN_VALID_POS
);
750 /* How many receivers should we use? */
751 iwlcore_get_rx_chain_counter(priv
, &idle_state
, &rx_state
);
752 priv
->staging_rxon
.rx_chain
|=
753 cpu_to_le16(rx_state
<< RXON_RX_CHAIN_MIMO_CNT_POS
);
754 priv
->staging_rxon
.rx_chain
|=
755 cpu_to_le16(idle_state
<< RXON_RX_CHAIN_CNT_POS
);
757 if (!is_single
&& (rx_state
>= 2) &&
758 !test_bit(STATUS_POWER_PMI
, &priv
->status
))
759 priv
->staging_rxon
.rx_chain
|= RXON_RX_CHAIN_MIMO_FORCE_MSK
;
761 priv
->staging_rxon
.rx_chain
&= ~RXON_RX_CHAIN_MIMO_FORCE_MSK
;
763 IWL_DEBUG_ASSOC("rx chain %X\n", priv
->staging_rxon
.rx_chain
);
765 EXPORT_SYMBOL(iwl_set_rxon_chain
);
768 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
769 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
770 * @channel: Any channel valid for the requested phymode
772 * In addition to setting the staging RXON, priv->phymode is also set.
774 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
775 * in the staging RXON flag structure based on the phymode
777 int iwl_set_rxon_channel(struct iwl_priv
*priv
,
778 enum ieee80211_band band
,
781 if (!iwl_get_channel_info(priv
, band
, channel
)) {
782 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
787 if ((le16_to_cpu(priv
->staging_rxon
.channel
) == channel
) &&
788 (priv
->band
== band
))
791 priv
->staging_rxon
.channel
= cpu_to_le16(channel
);
792 if (band
== IEEE80211_BAND_5GHZ
)
793 priv
->staging_rxon
.flags
&= ~RXON_FLG_BAND_24G_MSK
;
795 priv
->staging_rxon
.flags
|= RXON_FLG_BAND_24G_MSK
;
799 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel
, band
);
803 EXPORT_SYMBOL(iwl_set_rxon_channel
);
805 int iwl_setup_mac(struct iwl_priv
*priv
)
808 struct ieee80211_hw
*hw
= priv
->hw
;
809 hw
->rate_control_algorithm
= "iwl-4965-rs";
811 /* Tell mac80211 our characteristics */
812 hw
->flags
= IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE
|
813 IEEE80211_HW_SIGNAL_DBM
|
814 IEEE80211_HW_NOISE_DBM
;
815 /* Default value; 4 EDCA QOS priorities */
817 /* Enhanced value; more queues, to support 11n aggregation */
818 hw
->ampdu_queues
= 12;
820 hw
->conf
.beacon_int
= 100;
822 if (priv
->bands
[IEEE80211_BAND_2GHZ
].n_channels
)
823 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
824 &priv
->bands
[IEEE80211_BAND_2GHZ
];
825 if (priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
)
826 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
827 &priv
->bands
[IEEE80211_BAND_5GHZ
];
829 ret
= ieee80211_register_hw(priv
->hw
);
831 IWL_ERROR("Failed to register hw (error %d)\n", ret
);
834 priv
->mac80211_registered
= 1;
838 EXPORT_SYMBOL(iwl_setup_mac
);
841 int iwl_init_drv(struct iwl_priv
*priv
)
846 priv
->retry_rate
= 1;
847 priv
->ibss_beacon
= NULL
;
849 spin_lock_init(&priv
->lock
);
850 spin_lock_init(&priv
->power_data
.lock
);
851 spin_lock_init(&priv
->sta_lock
);
852 spin_lock_init(&priv
->hcmd_lock
);
853 spin_lock_init(&priv
->lq_mngr
.lock
);
855 for (i
= 0; i
< IWL_IBSS_MAC_HASH_SIZE
; i
++)
856 INIT_LIST_HEAD(&priv
->ibss_mac_hash
[i
]);
858 INIT_LIST_HEAD(&priv
->free_frames
);
860 mutex_init(&priv
->mutex
);
862 /* Clear the driver's (not device's) station table */
863 iwlcore_clear_stations_table(priv
);
865 priv
->data_retry_limit
= -1;
866 priv
->ieee_channels
= NULL
;
867 priv
->ieee_rates
= NULL
;
868 priv
->band
= IEEE80211_BAND_2GHZ
;
870 priv
->iw_mode
= IEEE80211_IF_TYPE_STA
;
872 priv
->use_ant_b_for_management_frame
= 1; /* start with ant B */
873 priv
->ps_mode
= IWL_MIMO_PS_NONE
;
875 /* Choose which receivers/antennas to use */
876 iwl_set_rxon_chain(priv
);
877 iwl_init_scan_params(priv
);
879 if (priv
->cfg
->mod_params
->enable_qos
)
880 priv
->qos_data
.qos_enable
= 1;
884 priv
->qos_data
.qos_active
= 0;
885 priv
->qos_data
.qos_cap
.val
= 0;
887 iwl_set_rxon_channel(priv
, IEEE80211_BAND_2GHZ
, 6);
889 priv
->rates_mask
= IWL_RATES_MASK
;
890 /* If power management is turned on, default to AC mode */
891 priv
->power_mode
= IWL_POWER_AC
;
892 priv
->tx_power_user_lmt
= IWL_TX_POWER_TARGET_POWER_MAX
;
894 ret
= iwl_init_channel_map(priv
);
896 IWL_ERROR("initializing regulatory failed: %d\n", ret
);
900 ret
= iwlcore_init_geos(priv
);
902 IWL_ERROR("initializing geos failed: %d\n", ret
);
903 goto err_free_channel_map
;
908 err_free_channel_map
:
909 iwl_free_channel_map(priv
);
913 EXPORT_SYMBOL(iwl_init_drv
);
915 void iwl_free_calib_results(struct iwl_priv
*priv
)
917 kfree(priv
->calib_results
.lo_res
);
918 priv
->calib_results
.lo_res
= NULL
;
919 priv
->calib_results
.lo_res_len
= 0;
921 kfree(priv
->calib_results
.tx_iq_res
);
922 priv
->calib_results
.tx_iq_res
= NULL
;
923 priv
->calib_results
.tx_iq_res_len
= 0;
925 kfree(priv
->calib_results
.tx_iq_perd_res
);
926 priv
->calib_results
.tx_iq_perd_res
= NULL
;
927 priv
->calib_results
.tx_iq_perd_res_len
= 0;
929 EXPORT_SYMBOL(iwl_free_calib_results
);
931 int iwl_set_tx_power(struct iwl_priv
*priv
, s8 tx_power
, bool force
)
934 if (tx_power
< IWL_TX_POWER_TARGET_POWER_MIN
) {
935 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
936 priv
->tx_power_user_lmt
);
940 if (tx_power
> IWL_TX_POWER_TARGET_POWER_MAX
) {
941 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
942 priv
->tx_power_user_lmt
);
946 if (priv
->tx_power_user_lmt
!= tx_power
)
949 priv
->tx_power_user_lmt
= tx_power
;
951 if (force
&& priv
->cfg
->ops
->lib
->send_tx_power
)
952 ret
= priv
->cfg
->ops
->lib
->send_tx_power(priv
);
956 EXPORT_SYMBOL(iwl_set_tx_power
);
959 void iwl_uninit_drv(struct iwl_priv
*priv
)
961 iwl_free_calib_results(priv
);
962 iwlcore_free_geos(priv
);
963 iwl_free_channel_map(priv
);
966 EXPORT_SYMBOL(iwl_uninit_drv
);
970 /* Low level driver call this function to update iwlcore with
973 int iwlcore_low_level_notify(struct iwl_priv
*priv
,
974 enum iwlcore_card_notify notify
)
978 case IWLCORE_INIT_EVT
:
979 ret
= iwl_rfkill_init(priv
);
981 IWL_ERROR("Unable to initialize RFKILL system. "
982 "Ignoring error: %d\n", ret
);
983 iwl_power_initialize(priv
);
985 case IWLCORE_START_EVT
:
986 iwl_power_update_mode(priv
, 1);
988 case IWLCORE_STOP_EVT
:
990 case IWLCORE_REMOVE_EVT
:
991 iwl_rfkill_unregister(priv
);
997 EXPORT_SYMBOL(iwlcore_low_level_notify
);
999 int iwl_send_statistics_request(struct iwl_priv
*priv
, u8 flags
)
1002 struct iwl_host_cmd cmd
= {
1003 .id
= REPLY_STATISTICS_CMD
,
1004 .meta
.flags
= flags
,
1005 .len
= sizeof(stat_flags
),
1006 .data
= (u8
*) &stat_flags
,
1008 return iwl_send_cmd(priv
, &cmd
);
1010 EXPORT_SYMBOL(iwl_send_statistics_request
);
1013 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1014 * using sample data 100 bytes apart. If these sample points are good,
1015 * it's a pretty good bet that everything between them is good, too.
1017 static int iwlcore_verify_inst_sparse(struct iwl_priv
*priv
, __le32
*image
, u32 len
)
1024 IWL_DEBUG_INFO("ucode inst image size is %u\n", len
);
1026 ret
= iwl_grab_nic_access(priv
);
1030 for (i
= 0; i
< len
; i
+= 100, image
+= 100/sizeof(u32
)) {
1031 /* read data comes through single port, auto-incr addr */
1032 /* NOTE: Use the debugless read so we don't flood kernel log
1033 * if IWL_DL_IO is set */
1034 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
,
1035 i
+ RTC_INST_LOWER_BOUND
);
1036 val
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
1037 if (val
!= le32_to_cpu(*image
)) {
1045 iwl_release_nic_access(priv
);
1051 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1052 * looking at all data.
1054 static int iwl_verify_inst_full(struct iwl_priv
*priv
, __le32
*image
,
1062 IWL_DEBUG_INFO("ucode inst image size is %u\n", len
);
1064 ret
= iwl_grab_nic_access(priv
);
1068 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
, RTC_INST_LOWER_BOUND
);
1071 for (; len
> 0; len
-= sizeof(u32
), image
++) {
1072 /* read data comes through single port, auto-incr addr */
1073 /* NOTE: Use the debugless read so we don't flood kernel log
1074 * if IWL_DL_IO is set */
1075 val
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
1076 if (val
!= le32_to_cpu(*image
)) {
1077 IWL_ERROR("uCode INST section is invalid at "
1078 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1079 save_len
- len
, val
, le32_to_cpu(*image
));
1087 iwl_release_nic_access(priv
);
1091 ("ucode image in INSTRUCTION memory is good\n");
1097 * iwl_verify_ucode - determine which instruction image is in SRAM,
1098 * and verify its contents
1100 int iwl_verify_ucode(struct iwl_priv
*priv
)
1107 image
= (__le32
*)priv
->ucode_boot
.v_addr
;
1108 len
= priv
->ucode_boot
.len
;
1109 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1111 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1115 /* Try initialize */
1116 image
= (__le32
*)priv
->ucode_init
.v_addr
;
1117 len
= priv
->ucode_init
.len
;
1118 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1120 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1124 /* Try runtime/protocol */
1125 image
= (__le32
*)priv
->ucode_code
.v_addr
;
1126 len
= priv
->ucode_code
.len
;
1127 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1129 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1133 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1135 /* Since nothing seems to match, show first several data entries in
1136 * instruction SRAM, so maybe visual inspection will give a clue.
1137 * Selection of bootstrap image (vs. other images) is arbitrary. */
1138 image
= (__le32
*)priv
->ucode_boot
.v_addr
;
1139 len
= priv
->ucode_boot
.len
;
1140 ret
= iwl_verify_inst_full(priv
, image
, len
);
1144 EXPORT_SYMBOL(iwl_verify_ucode
);
1147 static const char *desc_lookup(int i
)
1155 return "BAD_CHECKSUM";
1157 return "NMI_INTERRUPT";
1161 return "FATAL_ERROR";
1167 #define ERROR_START_OFFSET (1 * sizeof(u32))
1168 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1170 void iwl_dump_nic_error_log(struct iwl_priv
*priv
)
1173 u32 desc
, time
, count
, base
, data1
;
1174 u32 blink1
, blink2
, ilink1
, ilink2
;
1177 if (priv
->ucode_type
== UCODE_INIT
)
1178 base
= le32_to_cpu(priv
->card_alive_init
.error_event_table_ptr
);
1180 base
= le32_to_cpu(priv
->card_alive
.error_event_table_ptr
);
1182 if (!priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
1183 IWL_ERROR("Not valid error log pointer 0x%08X\n", base
);
1187 ret
= iwl_grab_nic_access(priv
);
1189 IWL_WARNING("Can not read from adapter at this time.\n");
1193 count
= iwl_read_targ_mem(priv
, base
);
1195 if (ERROR_START_OFFSET
<= count
* ERROR_ELEM_SIZE
) {
1196 IWL_ERROR("Start IWL Error Log Dump:\n");
1197 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv
->status
, count
);
1200 desc
= iwl_read_targ_mem(priv
, base
+ 1 * sizeof(u32
));
1201 blink1
= iwl_read_targ_mem(priv
, base
+ 3 * sizeof(u32
));
1202 blink2
= iwl_read_targ_mem(priv
, base
+ 4 * sizeof(u32
));
1203 ilink1
= iwl_read_targ_mem(priv
, base
+ 5 * sizeof(u32
));
1204 ilink2
= iwl_read_targ_mem(priv
, base
+ 6 * sizeof(u32
));
1205 data1
= iwl_read_targ_mem(priv
, base
+ 7 * sizeof(u32
));
1206 data2
= iwl_read_targ_mem(priv
, base
+ 8 * sizeof(u32
));
1207 line
= iwl_read_targ_mem(priv
, base
+ 9 * sizeof(u32
));
1208 time
= iwl_read_targ_mem(priv
, base
+ 11 * sizeof(u32
));
1210 IWL_ERROR("Desc Time "
1211 "data1 data2 line\n");
1212 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1213 desc_lookup(desc
), desc
, time
, data1
, data2
, line
);
1214 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1215 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1
, blink2
,
1218 iwl_release_nic_access(priv
);
1220 EXPORT_SYMBOL(iwl_dump_nic_error_log
);
1222 #define EVENT_START_OFFSET (4 * sizeof(u32))
1225 * iwl_print_event_log - Dump error event log to syslog
1227 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1229 void iwl_print_event_log(struct iwl_priv
*priv
, u32 start_idx
,
1230 u32 num_events
, u32 mode
)
1233 u32 base
; /* SRAM byte address of event log header */
1234 u32 event_size
; /* 2 u32s, or 3 u32s if timestamp recorded */
1235 u32 ptr
; /* SRAM byte address of log data */
1236 u32 ev
, time
, data
; /* event log data */
1238 if (num_events
== 0)
1240 if (priv
->ucode_type
== UCODE_INIT
)
1241 base
= le32_to_cpu(priv
->card_alive_init
.log_event_table_ptr
);
1243 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
1246 event_size
= 2 * sizeof(u32
);
1248 event_size
= 3 * sizeof(u32
);
1250 ptr
= base
+ EVENT_START_OFFSET
+ (start_idx
* event_size
);
1252 /* "time" is actually "data" for mode 0 (no timestamp).
1253 * place event id # at far right for easier visual parsing. */
1254 for (i
= 0; i
< num_events
; i
++) {
1255 ev
= iwl_read_targ_mem(priv
, ptr
);
1257 time
= iwl_read_targ_mem(priv
, ptr
);
1261 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time
, ev
);
1263 data
= iwl_read_targ_mem(priv
, ptr
);
1265 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1270 EXPORT_SYMBOL(iwl_print_event_log
);
1273 void iwl_dump_nic_event_log(struct iwl_priv
*priv
)
1276 u32 base
; /* SRAM byte address of event log header */
1277 u32 capacity
; /* event log capacity in # entries */
1278 u32 mode
; /* 0 - no timestamp, 1 - timestamp recorded */
1279 u32 num_wraps
; /* # times uCode wrapped to top of log */
1280 u32 next_entry
; /* index of next entry to be written by uCode */
1281 u32 size
; /* # entries that we'll print */
1283 if (priv
->ucode_type
== UCODE_INIT
)
1284 base
= le32_to_cpu(priv
->card_alive_init
.log_event_table_ptr
);
1286 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
1288 if (!priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
1289 IWL_ERROR("Invalid event log pointer 0x%08X\n", base
);
1293 ret
= iwl_grab_nic_access(priv
);
1295 IWL_WARNING("Can not read from adapter at this time.\n");
1299 /* event log header */
1300 capacity
= iwl_read_targ_mem(priv
, base
);
1301 mode
= iwl_read_targ_mem(priv
, base
+ (1 * sizeof(u32
)));
1302 num_wraps
= iwl_read_targ_mem(priv
, base
+ (2 * sizeof(u32
)));
1303 next_entry
= iwl_read_targ_mem(priv
, base
+ (3 * sizeof(u32
)));
1305 size
= num_wraps
? capacity
: next_entry
;
1307 /* bail out if nothing in log */
1309 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1310 iwl_release_nic_access(priv
);
1314 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1317 /* if uCode has wrapped back to top of log, start at the oldest entry,
1318 * i.e the next one that uCode would fill. */
1320 iwl_print_event_log(priv
, next_entry
,
1321 capacity
- next_entry
, mode
);
1322 /* (then/else) start at top of log */
1323 iwl_print_event_log(priv
, 0, next_entry
, mode
);
1325 iwl_release_nic_access(priv
);
1327 EXPORT_SYMBOL(iwl_dump_nic_event_log
);
1329 void iwl_rf_kill_ct_config(struct iwl_priv
*priv
)
1331 struct iwl_ct_kill_config cmd
;
1332 unsigned long flags
;
1335 spin_lock_irqsave(&priv
->lock
, flags
);
1336 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
,
1337 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT
);
1338 spin_unlock_irqrestore(&priv
->lock
, flags
);
1340 cmd
.critical_temperature_R
=
1341 cpu_to_le32(priv
->hw_params
.ct_kill_threshold
);
1343 ret
= iwl_send_cmd_pdu(priv
, REPLY_CT_KILL_CONFIG_CMD
,
1346 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1348 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1349 "critical temperature is %d\n",
1350 cmd
.critical_temperature_R
);
1352 EXPORT_SYMBOL(iwl_rf_kill_ct_config
);