1 /******************************************************************************
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <net/mac80211.h>
33 struct iwl_priv
; /* FIXME: remove */
34 #include "iwl-debug.h"
35 #include "iwl-eeprom.h"
36 #include "iwl-dev.h" /* FIXME: remove */
39 #include "iwl-rfkill.h"
40 #include "iwl-power.h"
43 MODULE_DESCRIPTION("iwl core");
44 MODULE_VERSION(IWLWIFI_VERSION
);
45 MODULE_AUTHOR(DRV_COPYRIGHT
);
46 MODULE_LICENSE("GPL");
48 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_SISO_##s##M_PLCP, \
51 IWL_RATE_MIMO2_##s##M_PLCP,\
52 IWL_RATE_MIMO3_##s##M_PLCP,\
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX }
63 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
69 const struct iwl_rate_info iwl_rates
[IWL_RATE_COUNT
] = {
70 IWL_DECLARE_RATE_INFO(1, INV
, INV
, 2, INV
, 2, INV
, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, INV
, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, INV
, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, INV
, 9, 12, 9, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 54, 48, INV
, 48, INV
, 48, INV
),/* 54mbps */
82 IWL_DECLARE_RATE_INFO(60, 60, 48, INV
, 48, INV
, 48, INV
),/* 60mbps */
83 /* FIXME:RS: ^^ should be INV (legacy) */
85 EXPORT_SYMBOL(iwl_rates
);
88 * translate ucode response to mac80211 tx status control values
90 void iwl_hwrate_to_tx_control(struct iwl_priv
*priv
, u32 rate_n_flags
,
91 struct ieee80211_tx_info
*control
)
95 control
->antenna_sel_tx
=
96 ((rate_n_flags
& RATE_MCS_ANT_ABC_MSK
) >> RATE_MCS_ANT_POS
);
97 if (rate_n_flags
& RATE_MCS_HT_MSK
)
98 control
->flags
|= IEEE80211_TX_CTL_OFDM_HT
;
99 if (rate_n_flags
& RATE_MCS_GF_MSK
)
100 control
->flags
|= IEEE80211_TX_CTL_GREEN_FIELD
;
101 if (rate_n_flags
& RATE_MCS_FAT_MSK
)
102 control
->flags
|= IEEE80211_TX_CTL_40_MHZ_WIDTH
;
103 if (rate_n_flags
& RATE_MCS_DUP_MSK
)
104 control
->flags
|= IEEE80211_TX_CTL_DUP_DATA
;
105 if (rate_n_flags
& RATE_MCS_SGI_MSK
)
106 control
->flags
|= IEEE80211_TX_CTL_SHORT_GI
;
107 rate_index
= iwl_hwrate_to_plcp_idx(rate_n_flags
);
108 if (control
->band
== IEEE80211_BAND_5GHZ
)
109 rate_index
-= IWL_FIRST_OFDM_RATE
;
110 control
->tx_rate_idx
= rate_index
;
112 EXPORT_SYMBOL(iwl_hwrate_to_tx_control
);
114 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags
)
119 if (rate_n_flags
& RATE_MCS_HT_MSK
) {
120 idx
= (rate_n_flags
& 0xff);
122 if (idx
>= IWL_RATE_MIMO2_6M_PLCP
)
123 idx
= idx
- IWL_RATE_MIMO2_6M_PLCP
;
125 idx
+= IWL_FIRST_OFDM_RATE
;
126 /* skip 9M not supported in ht*/
127 if (idx
>= IWL_RATE_9M_INDEX
)
129 if ((idx
>= IWL_FIRST_OFDM_RATE
) && (idx
<= IWL_LAST_OFDM_RATE
))
132 /* legacy rate format, search for match in table */
134 for (idx
= 0; idx
< ARRAY_SIZE(iwl_rates
); idx
++)
135 if (iwl_rates
[idx
].plcp
== (rate_n_flags
& 0xFF))
141 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx
);
145 const u8 iwl_bcast_addr
[ETH_ALEN
] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
146 EXPORT_SYMBOL(iwl_bcast_addr
);
149 /* This function both allocates and initializes hw and priv. */
150 struct ieee80211_hw
*iwl_alloc_all(struct iwl_cfg
*cfg
,
151 struct ieee80211_ops
*hw_ops
)
153 struct iwl_priv
*priv
;
155 /* mac80211 allocates memory for this device instance, including
156 * space for this driver's private structure */
157 struct ieee80211_hw
*hw
=
158 ieee80211_alloc_hw(sizeof(struct iwl_priv
), hw_ops
);
160 IWL_ERROR("Can not allocate network device\n");
170 EXPORT_SYMBOL(iwl_alloc_all
);
172 void iwl_hw_detect(struct iwl_priv
*priv
)
174 priv
->hw_rev
= _iwl_read32(priv
, CSR_HW_REV
);
175 priv
->hw_wa_rev
= _iwl_read32(priv
, CSR_HW_REV_WA_REG
);
176 pci_read_config_byte(priv
->pci_dev
, PCI_REVISION_ID
, &priv
->rev_id
);
178 EXPORT_SYMBOL(iwl_hw_detect
);
180 /* Tell nic where to find the "keep warm" buffer */
181 int iwl_kw_init(struct iwl_priv
*priv
)
186 spin_lock_irqsave(&priv
->lock
, flags
);
187 ret
= iwl_grab_nic_access(priv
);
191 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
,
192 priv
->kw
.dma_addr
>> 4);
193 iwl_release_nic_access(priv
);
195 spin_unlock_irqrestore(&priv
->lock
, flags
);
199 int iwl_kw_alloc(struct iwl_priv
*priv
)
201 struct pci_dev
*dev
= priv
->pci_dev
;
202 struct iwl_kw
*kw
= &priv
->kw
;
204 kw
->size
= IWL_KW_SIZE
;
205 kw
->v_addr
= pci_alloc_consistent(dev
, kw
->size
, &kw
->dma_addr
);
213 * iwl_kw_free - Free the "keep warm" buffer
215 void iwl_kw_free(struct iwl_priv
*priv
)
217 struct pci_dev
*dev
= priv
->pci_dev
;
218 struct iwl_kw
*kw
= &priv
->kw
;
221 pci_free_consistent(dev
, kw
->size
, kw
->v_addr
, kw
->dma_addr
);
222 memset(kw
, 0, sizeof(*kw
));
226 int iwl_hw_nic_init(struct iwl_priv
*priv
)
229 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
233 spin_lock_irqsave(&priv
->lock
, flags
);
234 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
235 iwl_write32(priv
, CSR_INT_COALESCING
, 512 / 32);
236 spin_unlock_irqrestore(&priv
->lock
, flags
);
238 ret
= priv
->cfg
->ops
->lib
->apm_ops
.set_pwr_src(priv
, IWL_PWR_SRC_VMAIN
);
240 priv
->cfg
->ops
->lib
->apm_ops
.config(priv
);
242 /* Allocate the RX queue, or reset if it is already allocated */
244 ret
= iwl_rx_queue_alloc(priv
);
246 IWL_ERROR("Unable to initialize Rx queue\n");
250 iwl_rx_queue_reset(priv
, rxq
);
252 iwl_rx_replenish(priv
);
254 iwl_rx_init(priv
, rxq
);
256 spin_lock_irqsave(&priv
->lock
, flags
);
258 rxq
->need_update
= 1;
259 iwl_rx_queue_update_write_ptr(priv
, rxq
);
261 spin_unlock_irqrestore(&priv
->lock
, flags
);
263 /* Allocate and init all Tx and Command queues */
264 ret
= iwl_txq_ctx_reset(priv
);
268 set_bit(STATUS_INIT
, &priv
->status
);
272 EXPORT_SYMBOL(iwl_hw_nic_init
);
275 * iwl_clear_stations_table - Clear the driver's station table
277 * NOTE: This does not clear or otherwise alter the device's station table.
279 void iwl_clear_stations_table(struct iwl_priv
*priv
)
283 spin_lock_irqsave(&priv
->sta_lock
, flags
);
285 if (iwl_is_alive(priv
) &&
286 !test_bit(STATUS_EXIT_PENDING
, &priv
->status
) &&
287 iwl_send_cmd_pdu_async(priv
, REPLY_REMOVE_ALL_STA
, 0, NULL
, NULL
))
288 IWL_ERROR("Couldn't clear the station table\n");
290 priv
->num_stations
= 0;
291 memset(priv
->stations
, 0, sizeof(priv
->stations
));
293 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
295 EXPORT_SYMBOL(iwl_clear_stations_table
);
297 void iwl_reset_qos(struct iwl_priv
*priv
)
306 spin_lock_irqsave(&priv
->lock
, flags
);
307 priv
->qos_data
.qos_active
= 0;
309 if (priv
->iw_mode
== NL80211_IFTYPE_ADHOC
) {
310 if (priv
->qos_data
.qos_enable
)
311 priv
->qos_data
.qos_active
= 1;
312 if (!(priv
->active_rate
& 0xfff0)) {
316 } else if (priv
->iw_mode
== NL80211_IFTYPE_AP
) {
317 if (priv
->qos_data
.qos_enable
)
318 priv
->qos_data
.qos_active
= 1;
319 } else if (!(priv
->staging_rxon
.flags
& RXON_FLG_SHORT_SLOT_MSK
)) {
324 if (priv
->qos_data
.qos_active
)
327 priv
->qos_data
.def_qos_parm
.ac
[0].cw_min
= cpu_to_le16(cw_min
);
328 priv
->qos_data
.def_qos_parm
.ac
[0].cw_max
= cpu_to_le16(cw_max
);
329 priv
->qos_data
.def_qos_parm
.ac
[0].aifsn
= aifs
;
330 priv
->qos_data
.def_qos_parm
.ac
[0].edca_txop
= 0;
331 priv
->qos_data
.def_qos_parm
.ac
[0].reserved1
= 0;
333 if (priv
->qos_data
.qos_active
) {
335 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
= cpu_to_le16(cw_min
);
336 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
= cpu_to_le16(cw_max
);
337 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 7;
338 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
= 0;
339 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
342 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
343 cpu_to_le16((cw_min
+ 1) / 2 - 1);
344 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
346 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 2;
348 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
351 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
353 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
356 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
357 cpu_to_le16((cw_min
+ 1) / 4 - 1);
358 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
359 cpu_to_le16((cw_max
+ 1) / 2 - 1);
360 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 2;
361 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
363 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
366 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
369 for (i
= 1; i
< 4; i
++) {
370 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
372 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
374 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= aifs
;
375 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
= 0;
376 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
379 IWL_DEBUG_QOS("set QoS to default \n");
381 spin_unlock_irqrestore(&priv
->lock
, flags
);
383 EXPORT_SYMBOL(iwl_reset_qos
);
385 #define MAX_BIT_RATE_40_MHZ 0x96 /* 150 Mbps */
386 #define MAX_BIT_RATE_20_MHZ 0x48 /* 72 Mbps */
387 static void iwlcore_init_ht_hw_capab(const struct iwl_priv
*priv
,
388 struct ieee80211_ht_info
*ht_info
,
389 enum ieee80211_band band
)
391 u16 max_bit_rate
= 0;
392 u8 rx_chains_num
= priv
->hw_params
.rx_chains_num
;
393 u8 tx_chains_num
= priv
->hw_params
.tx_chains_num
;
396 memset(ht_info
->supp_mcs_set
, 0, 16);
398 ht_info
->ht_supported
= 1;
400 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_GRN_FLD
;
401 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_SGI_20
;
402 ht_info
->cap
|= (u16
)(IEEE80211_HT_CAP_SM_PS
&
403 (WLAN_HT_CAP_SM_PS_DISABLED
<< 2));
405 max_bit_rate
= MAX_BIT_RATE_20_MHZ
;
406 if (priv
->hw_params
.fat_channel
& BIT(band
)) {
407 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_SUP_WIDTH
;
408 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_SGI_40
;
409 ht_info
->supp_mcs_set
[4] = 0x01;
410 max_bit_rate
= MAX_BIT_RATE_40_MHZ
;
413 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
414 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_MAX_AMSDU
;
416 ht_info
->ampdu_factor
= CFG_HT_RX_AMPDU_FACTOR_DEF
;
417 ht_info
->ampdu_density
= CFG_HT_MPDU_DENSITY_DEF
;
419 ht_info
->supp_mcs_set
[0] = 0xFF;
420 if (rx_chains_num
>= 2)
421 ht_info
->supp_mcs_set
[1] = 0xFF;
422 if (rx_chains_num
>= 3)
423 ht_info
->supp_mcs_set
[2] = 0xFF;
425 /* Highest supported Rx data rate */
426 max_bit_rate
*= rx_chains_num
;
427 ht_info
->supp_mcs_set
[10] = (u8
)(max_bit_rate
& 0x00FF);
428 ht_info
->supp_mcs_set
[11] = (u8
)((max_bit_rate
& 0xFF00) >> 8);
430 /* Tx MCS capabilities */
431 ht_info
->supp_mcs_set
[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED
;
432 if (tx_chains_num
!= rx_chains_num
) {
433 ht_info
->supp_mcs_set
[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF
;
434 ht_info
->supp_mcs_set
[12] |= ((tx_chains_num
- 1) << 2);
438 static void iwlcore_init_hw_rates(struct iwl_priv
*priv
,
439 struct ieee80211_rate
*rates
)
443 for (i
= 0; i
< IWL_RATE_COUNT
; i
++) {
444 rates
[i
].bitrate
= iwl_rates
[i
].ieee
* 5;
445 rates
[i
].hw_value
= i
; /* Rate scaling will work on indexes */
446 rates
[i
].hw_value_short
= i
;
448 if ((i
> IWL_LAST_OFDM_RATE
) || (i
< IWL_FIRST_OFDM_RATE
)) {
450 * If CCK != 1M then set short preamble rate flag.
453 (iwl_rates
[i
].plcp
== IWL_RATE_1M_PLCP
) ?
454 0 : IEEE80211_RATE_SHORT_PREAMBLE
;
460 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
462 static int iwlcore_init_geos(struct iwl_priv
*priv
)
464 struct iwl_channel_info
*ch
;
465 struct ieee80211_supported_band
*sband
;
466 struct ieee80211_channel
*channels
;
467 struct ieee80211_channel
*geo_ch
;
468 struct ieee80211_rate
*rates
;
471 if (priv
->bands
[IEEE80211_BAND_2GHZ
].n_bitrates
||
472 priv
->bands
[IEEE80211_BAND_5GHZ
].n_bitrates
) {
473 IWL_DEBUG_INFO("Geography modes already initialized.\n");
474 set_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
478 channels
= kzalloc(sizeof(struct ieee80211_channel
) *
479 priv
->channel_count
, GFP_KERNEL
);
483 rates
= kzalloc((sizeof(struct ieee80211_rate
) * (IWL_RATE_COUNT
+ 1)),
490 /* 5.2GHz channels start after the 2.4GHz channels */
491 sband
= &priv
->bands
[IEEE80211_BAND_5GHZ
];
492 sband
->channels
= &channels
[ARRAY_SIZE(iwl_eeprom_band_1
)];
494 sband
->bitrates
= &rates
[IWL_FIRST_OFDM_RATE
];
495 sband
->n_bitrates
= IWL_RATE_COUNT
- IWL_FIRST_OFDM_RATE
;
497 if (priv
->cfg
->sku
& IWL_SKU_N
)
498 iwlcore_init_ht_hw_capab(priv
, &sband
->ht_info
,
499 IEEE80211_BAND_5GHZ
);
501 sband
= &priv
->bands
[IEEE80211_BAND_2GHZ
];
502 sband
->channels
= channels
;
504 sband
->bitrates
= rates
;
505 sband
->n_bitrates
= IWL_RATE_COUNT
;
507 if (priv
->cfg
->sku
& IWL_SKU_N
)
508 iwlcore_init_ht_hw_capab(priv
, &sband
->ht_info
,
509 IEEE80211_BAND_2GHZ
);
511 priv
->ieee_channels
= channels
;
512 priv
->ieee_rates
= rates
;
514 iwlcore_init_hw_rates(priv
, rates
);
516 for (i
= 0; i
< priv
->channel_count
; i
++) {
517 ch
= &priv
->channel_info
[i
];
519 /* FIXME: might be removed if scan is OK */
520 if (!is_channel_valid(ch
))
523 if (is_channel_a_band(ch
))
524 sband
= &priv
->bands
[IEEE80211_BAND_5GHZ
];
526 sband
= &priv
->bands
[IEEE80211_BAND_2GHZ
];
528 geo_ch
= &sband
->channels
[sband
->n_channels
++];
530 geo_ch
->center_freq
=
531 ieee80211_channel_to_frequency(ch
->channel
);
532 geo_ch
->max_power
= ch
->max_power_avg
;
533 geo_ch
->max_antenna_gain
= 0xff;
534 geo_ch
->hw_value
= ch
->channel
;
536 if (is_channel_valid(ch
)) {
537 if (!(ch
->flags
& EEPROM_CHANNEL_IBSS
))
538 geo_ch
->flags
|= IEEE80211_CHAN_NO_IBSS
;
540 if (!(ch
->flags
& EEPROM_CHANNEL_ACTIVE
))
541 geo_ch
->flags
|= IEEE80211_CHAN_PASSIVE_SCAN
;
543 if (ch
->flags
& EEPROM_CHANNEL_RADAR
)
544 geo_ch
->flags
|= IEEE80211_CHAN_RADAR
;
546 geo_ch
->flags
|= ch
->fat_extension_channel
;
548 if (ch
->max_power_avg
> priv
->tx_power_channel_lmt
)
549 priv
->tx_power_channel_lmt
= ch
->max_power_avg
;
551 geo_ch
->flags
|= IEEE80211_CHAN_DISABLED
;
554 /* Save flags for reg domain usage */
555 geo_ch
->orig_flags
= geo_ch
->flags
;
557 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
558 ch
->channel
, geo_ch
->center_freq
,
559 is_channel_a_band(ch
) ? "5.2" : "2.4",
560 geo_ch
->flags
& IEEE80211_CHAN_DISABLED
?
561 "restricted" : "valid",
565 if ((priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
== 0) &&
566 priv
->cfg
->sku
& IWL_SKU_A
) {
567 printk(KERN_INFO DRV_NAME
568 ": Incorrectly detected BG card as ABG. Please send "
569 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
570 priv
->pci_dev
->device
, priv
->pci_dev
->subsystem_device
);
571 priv
->cfg
->sku
&= ~IWL_SKU_A
;
574 printk(KERN_INFO DRV_NAME
575 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
576 priv
->bands
[IEEE80211_BAND_2GHZ
].n_channels
,
577 priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
);
580 set_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
586 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
588 static void iwlcore_free_geos(struct iwl_priv
*priv
)
590 kfree(priv
->ieee_channels
);
591 kfree(priv
->ieee_rates
);
592 clear_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
595 static bool is_single_rx_stream(struct iwl_priv
*priv
)
597 return !priv
->current_ht_config
.is_ht
||
598 ((priv
->current_ht_config
.supp_mcs_set
[1] == 0) &&
599 (priv
->current_ht_config
.supp_mcs_set
[2] == 0));
602 static u8
iwl_is_channel_extension(struct iwl_priv
*priv
,
603 enum ieee80211_band band
,
604 u16 channel
, u8 extension_chan_offset
)
606 const struct iwl_channel_info
*ch_info
;
608 ch_info
= iwl_get_channel_info(priv
, band
, channel
);
609 if (!is_channel_valid(ch_info
))
612 if (extension_chan_offset
== IEEE80211_HT_IE_CHA_SEC_ABOVE
)
613 return !(ch_info
->fat_extension_channel
&
614 IEEE80211_CHAN_NO_FAT_ABOVE
);
615 else if (extension_chan_offset
== IEEE80211_HT_IE_CHA_SEC_BELOW
)
616 return !(ch_info
->fat_extension_channel
&
617 IEEE80211_CHAN_NO_FAT_BELOW
);
622 u8
iwl_is_fat_tx_allowed(struct iwl_priv
*priv
,
623 struct ieee80211_ht_info
*sta_ht_inf
)
625 struct iwl_ht_info
*iwl_ht_conf
= &priv
->current_ht_config
;
627 if ((!iwl_ht_conf
->is_ht
) ||
628 (iwl_ht_conf
->supported_chan_width
!= IWL_CHANNEL_WIDTH_40MHZ
) ||
629 (iwl_ht_conf
->extension_chan_offset
== IEEE80211_HT_IE_CHA_SEC_NONE
))
633 if ((!sta_ht_inf
->ht_supported
) ||
634 (!(sta_ht_inf
->cap
& IEEE80211_HT_CAP_SUP_WIDTH
)))
638 return iwl_is_channel_extension(priv
, priv
->band
,
639 iwl_ht_conf
->control_channel
,
640 iwl_ht_conf
->extension_chan_offset
);
642 EXPORT_SYMBOL(iwl_is_fat_tx_allowed
);
644 void iwl_set_rxon_ht(struct iwl_priv
*priv
, struct iwl_ht_info
*ht_info
)
646 struct iwl_rxon_cmd
*rxon
= &priv
->staging_rxon
;
649 if (!ht_info
->is_ht
) {
650 rxon
->flags
&= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK
|
651 RXON_FLG_CHANNEL_MODE_PURE_40_MSK
|
652 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
|
653 RXON_FLG_FAT_PROT_MSK
|
654 RXON_FLG_HT_PROT_MSK
);
658 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
659 if (iwl_is_fat_tx_allowed(priv
, NULL
))
660 rxon
->flags
|= RXON_FLG_CHANNEL_MODE_MIXED_MSK
;
662 rxon
->flags
&= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK
|
663 RXON_FLG_CHANNEL_MODE_PURE_40_MSK
);
665 if (le16_to_cpu(rxon
->channel
) != ht_info
->control_channel
) {
666 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
667 le16_to_cpu(rxon
->channel
),
668 ht_info
->control_channel
);
672 /* Note: control channel is opposite of extension channel */
673 switch (ht_info
->extension_chan_offset
) {
674 case IEEE80211_HT_IE_CHA_SEC_ABOVE
:
675 rxon
->flags
&= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
);
677 case IEEE80211_HT_IE_CHA_SEC_BELOW
:
678 rxon
->flags
|= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
;
680 case IEEE80211_HT_IE_CHA_SEC_NONE
:
682 rxon
->flags
&= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK
;
686 val
= ht_info
->ht_protection
;
688 rxon
->flags
|= cpu_to_le32(val
<< RXON_FLG_HT_OPERATING_MODE_POS
);
690 iwl_set_rxon_chain(priv
);
692 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
693 "rxon flags 0x%X operation mode :0x%X "
694 "extension channel offset 0x%x "
696 ht_info
->supp_mcs_set
[0],
697 ht_info
->supp_mcs_set
[1],
698 ht_info
->supp_mcs_set
[2],
699 le32_to_cpu(rxon
->flags
), ht_info
->ht_protection
,
700 ht_info
->extension_chan_offset
,
701 ht_info
->control_channel
);
704 EXPORT_SYMBOL(iwl_set_rxon_ht
);
706 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
707 #define IWL_NUM_RX_CHAINS_SINGLE 2
708 #define IWL_NUM_IDLE_CHAINS_DUAL 2
709 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
711 /* Determine how many receiver/antenna chains to use.
712 * More provides better reception via diversity. Fewer saves power.
713 * MIMO (dual stream) requires at least 2, but works better with 3.
714 * This does not determine *which* chains to use, just how many.
716 static int iwl_get_active_rx_chain_count(struct iwl_priv
*priv
)
718 bool is_single
= is_single_rx_stream(priv
);
719 bool is_cam
= !test_bit(STATUS_POWER_PMI
, &priv
->status
);
721 /* # of Rx chains to use when expecting MIMO. */
722 if (is_single
|| (!is_cam
&& (priv
->current_ht_config
.sm_ps
==
723 WLAN_HT_CAP_SM_PS_STATIC
)))
724 return IWL_NUM_RX_CHAINS_SINGLE
;
726 return IWL_NUM_RX_CHAINS_MULTIPLE
;
729 static int iwl_get_idle_rx_chain_count(struct iwl_priv
*priv
, int active_cnt
)
732 bool is_cam
= !test_bit(STATUS_POWER_PMI
, &priv
->status
);
733 /* # Rx chains when idling and maybe trying to save power */
734 switch (priv
->current_ht_config
.sm_ps
) {
735 case WLAN_HT_CAP_SM_PS_STATIC
:
736 case WLAN_HT_CAP_SM_PS_DYNAMIC
:
737 idle_cnt
= (is_cam
) ? IWL_NUM_IDLE_CHAINS_DUAL
:
738 IWL_NUM_IDLE_CHAINS_SINGLE
;
740 case WLAN_HT_CAP_SM_PS_DISABLED
:
741 idle_cnt
= (is_cam
) ? active_cnt
: IWL_NUM_IDLE_CHAINS_SINGLE
;
743 case WLAN_HT_CAP_SM_PS_INVALID
:
745 IWL_ERROR("invalide mimo ps mode %d\n",
746 priv
->current_ht_config
.sm_ps
);
755 static u8
iwl_count_chain_bitmap(u32 chain_bitmap
)
758 res
= (chain_bitmap
& BIT(0)) >> 0;
759 res
+= (chain_bitmap
& BIT(1)) >> 1;
760 res
+= (chain_bitmap
& BIT(2)) >> 2;
761 res
+= (chain_bitmap
& BIT(4)) >> 4;
766 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
768 * Selects how many and which Rx receivers/antennas/chains to use.
769 * This should not be used for scan command ... it puts data in wrong place.
771 void iwl_set_rxon_chain(struct iwl_priv
*priv
)
773 bool is_single
= is_single_rx_stream(priv
);
774 bool is_cam
= !test_bit(STATUS_POWER_PMI
, &priv
->status
);
775 u8 idle_rx_cnt
, active_rx_cnt
, valid_rx_cnt
;
779 /* Tell uCode which antennas are actually connected.
780 * Before first association, we assume all antennas are connected.
781 * Just after first association, iwl_chain_noise_calibration()
782 * checks which antennas actually *are* connected. */
783 if (priv
->chain_noise_data
.active_chains
)
784 active_chains
= priv
->chain_noise_data
.active_chains
;
786 active_chains
= priv
->hw_params
.valid_rx_ant
;
788 rx_chain
= active_chains
<< RXON_RX_CHAIN_VALID_POS
;
790 /* How many receivers should we use? */
791 active_rx_cnt
= iwl_get_active_rx_chain_count(priv
);
792 idle_rx_cnt
= iwl_get_idle_rx_chain_count(priv
, active_rx_cnt
);
795 /* correct rx chain count according hw settings
796 * and chain noise calibration
798 valid_rx_cnt
= iwl_count_chain_bitmap(active_chains
);
799 if (valid_rx_cnt
< active_rx_cnt
)
800 active_rx_cnt
= valid_rx_cnt
;
802 if (valid_rx_cnt
< idle_rx_cnt
)
803 idle_rx_cnt
= valid_rx_cnt
;
805 rx_chain
|= active_rx_cnt
<< RXON_RX_CHAIN_MIMO_CNT_POS
;
806 rx_chain
|= idle_rx_cnt
<< RXON_RX_CHAIN_CNT_POS
;
808 priv
->staging_rxon
.rx_chain
= cpu_to_le16(rx_chain
);
810 if (!is_single
&& (active_rx_cnt
>= IWL_NUM_RX_CHAINS_SINGLE
) && is_cam
)
811 priv
->staging_rxon
.rx_chain
|= RXON_RX_CHAIN_MIMO_FORCE_MSK
;
813 priv
->staging_rxon
.rx_chain
&= ~RXON_RX_CHAIN_MIMO_FORCE_MSK
;
815 IWL_DEBUG_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
816 priv
->staging_rxon
.rx_chain
,
817 active_rx_cnt
, idle_rx_cnt
);
819 WARN_ON(active_rx_cnt
== 0 || idle_rx_cnt
== 0 ||
820 active_rx_cnt
< idle_rx_cnt
);
822 EXPORT_SYMBOL(iwl_set_rxon_chain
);
825 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
826 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
827 * @channel: Any channel valid for the requested phymode
829 * In addition to setting the staging RXON, priv->phymode is also set.
831 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
832 * in the staging RXON flag structure based on the phymode
834 int iwl_set_rxon_channel(struct iwl_priv
*priv
, struct ieee80211_channel
*ch
)
836 enum ieee80211_band band
= ch
->band
;
837 u16 channel
= ieee80211_frequency_to_channel(ch
->center_freq
);
839 if (!iwl_get_channel_info(priv
, band
, channel
)) {
840 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
845 if ((le16_to_cpu(priv
->staging_rxon
.channel
) == channel
) &&
846 (priv
->band
== band
))
849 priv
->staging_rxon
.channel
= cpu_to_le16(channel
);
850 if (band
== IEEE80211_BAND_5GHZ
)
851 priv
->staging_rxon
.flags
&= ~RXON_FLG_BAND_24G_MSK
;
853 priv
->staging_rxon
.flags
|= RXON_FLG_BAND_24G_MSK
;
857 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel
, band
);
861 EXPORT_SYMBOL(iwl_set_rxon_channel
);
863 int iwl_setup_mac(struct iwl_priv
*priv
)
866 struct ieee80211_hw
*hw
= priv
->hw
;
867 hw
->rate_control_algorithm
= "iwl-agn-rs";
869 /* Tell mac80211 our characteristics */
870 hw
->flags
= IEEE80211_HW_SIGNAL_DBM
|
871 IEEE80211_HW_NOISE_DBM
;
872 hw
->wiphy
->interface_modes
=
873 BIT(NL80211_IFTYPE_AP
) |
874 BIT(NL80211_IFTYPE_STATION
) |
875 BIT(NL80211_IFTYPE_ADHOC
);
876 /* Default value; 4 EDCA QOS priorities */
878 /* queues to support 11n aggregation */
879 if (priv
->cfg
->sku
& IWL_SKU_N
)
880 hw
->ampdu_queues
= priv
->cfg
->mod_params
->num_of_ampdu_queues
;
882 hw
->conf
.beacon_int
= 100;
883 hw
->max_listen_interval
= IWL_CONN_MAX_LISTEN_INTERVAL
;
885 if (priv
->bands
[IEEE80211_BAND_2GHZ
].n_channels
)
886 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
887 &priv
->bands
[IEEE80211_BAND_2GHZ
];
888 if (priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
)
889 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
890 &priv
->bands
[IEEE80211_BAND_5GHZ
];
892 ret
= ieee80211_register_hw(priv
->hw
);
894 IWL_ERROR("Failed to register hw (error %d)\n", ret
);
897 priv
->mac80211_registered
= 1;
901 EXPORT_SYMBOL(iwl_setup_mac
);
903 int iwl_set_hw_params(struct iwl_priv
*priv
)
905 priv
->hw_params
.sw_crypto
= priv
->cfg
->mod_params
->sw_crypto
;
906 priv
->hw_params
.max_rxq_size
= RX_QUEUE_SIZE
;
907 priv
->hw_params
.max_rxq_log
= RX_QUEUE_SIZE_LOG
;
908 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
909 priv
->hw_params
.rx_buf_size
= IWL_RX_BUF_SIZE_8K
;
911 priv
->hw_params
.rx_buf_size
= IWL_RX_BUF_SIZE_4K
;
912 priv
->hw_params
.max_pkt_size
= priv
->hw_params
.rx_buf_size
- 256;
914 if (priv
->cfg
->mod_params
->disable_11n
)
915 priv
->cfg
->sku
&= ~IWL_SKU_N
;
917 /* Device-specific setup */
918 return priv
->cfg
->ops
->lib
->set_hw_params(priv
);
920 EXPORT_SYMBOL(iwl_set_hw_params
);
922 int iwl_init_drv(struct iwl_priv
*priv
)
926 priv
->retry_rate
= 1;
927 priv
->ibss_beacon
= NULL
;
929 spin_lock_init(&priv
->lock
);
930 spin_lock_init(&priv
->power_data
.lock
);
931 spin_lock_init(&priv
->sta_lock
);
932 spin_lock_init(&priv
->hcmd_lock
);
934 INIT_LIST_HEAD(&priv
->free_frames
);
936 mutex_init(&priv
->mutex
);
938 /* Clear the driver's (not device's) station table */
939 iwl_clear_stations_table(priv
);
941 priv
->data_retry_limit
= -1;
942 priv
->ieee_channels
= NULL
;
943 priv
->ieee_rates
= NULL
;
944 priv
->band
= IEEE80211_BAND_2GHZ
;
946 priv
->iw_mode
= NL80211_IFTYPE_STATION
;
948 priv
->use_ant_b_for_management_frame
= 1; /* start with ant B */
949 priv
->current_ht_config
.sm_ps
= WLAN_HT_CAP_SM_PS_DISABLED
;
951 /* Choose which receivers/antennas to use */
952 iwl_set_rxon_chain(priv
);
953 iwl_init_scan_params(priv
);
955 if (priv
->cfg
->mod_params
->enable_qos
)
956 priv
->qos_data
.qos_enable
= 1;
960 priv
->qos_data
.qos_active
= 0;
961 priv
->qos_data
.qos_cap
.val
= 0;
963 priv
->rates_mask
= IWL_RATES_MASK
;
964 /* If power management is turned on, default to AC mode */
965 priv
->power_mode
= IWL_POWER_AC
;
966 priv
->tx_power_user_lmt
= IWL_TX_POWER_TARGET_POWER_MAX
;
968 ret
= iwl_init_channel_map(priv
);
970 IWL_ERROR("initializing regulatory failed: %d\n", ret
);
974 ret
= iwlcore_init_geos(priv
);
976 IWL_ERROR("initializing geos failed: %d\n", ret
);
977 goto err_free_channel_map
;
982 err_free_channel_map
:
983 iwl_free_channel_map(priv
);
987 EXPORT_SYMBOL(iwl_init_drv
);
989 int iwl_set_tx_power(struct iwl_priv
*priv
, s8 tx_power
, bool force
)
992 if (tx_power
< IWL_TX_POWER_TARGET_POWER_MIN
) {
993 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
994 priv
->tx_power_user_lmt
);
998 if (tx_power
> IWL_TX_POWER_TARGET_POWER_MAX
) {
999 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1000 priv
->tx_power_user_lmt
);
1004 if (priv
->tx_power_user_lmt
!= tx_power
)
1007 priv
->tx_power_user_lmt
= tx_power
;
1009 if (force
&& priv
->cfg
->ops
->lib
->send_tx_power
)
1010 ret
= priv
->cfg
->ops
->lib
->send_tx_power(priv
);
1014 EXPORT_SYMBOL(iwl_set_tx_power
);
1016 void iwl_uninit_drv(struct iwl_priv
*priv
)
1018 iwl_calib_free_results(priv
);
1019 iwlcore_free_geos(priv
);
1020 iwl_free_channel_map(priv
);
1023 EXPORT_SYMBOL(iwl_uninit_drv
);
1025 int iwl_send_statistics_request(struct iwl_priv
*priv
, u8 flags
)
1028 struct iwl_host_cmd cmd
= {
1029 .id
= REPLY_STATISTICS_CMD
,
1030 .meta
.flags
= flags
,
1031 .len
= sizeof(stat_flags
),
1032 .data
= (u8
*) &stat_flags
,
1034 return iwl_send_cmd(priv
, &cmd
);
1036 EXPORT_SYMBOL(iwl_send_statistics_request
);
1039 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1040 * using sample data 100 bytes apart. If these sample points are good,
1041 * it's a pretty good bet that everything between them is good, too.
1043 static int iwlcore_verify_inst_sparse(struct iwl_priv
*priv
, __le32
*image
, u32 len
)
1050 IWL_DEBUG_INFO("ucode inst image size is %u\n", len
);
1052 ret
= iwl_grab_nic_access(priv
);
1056 for (i
= 0; i
< len
; i
+= 100, image
+= 100/sizeof(u32
)) {
1057 /* read data comes through single port, auto-incr addr */
1058 /* NOTE: Use the debugless read so we don't flood kernel log
1059 * if IWL_DL_IO is set */
1060 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
,
1061 i
+ RTC_INST_LOWER_BOUND
);
1062 val
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
1063 if (val
!= le32_to_cpu(*image
)) {
1071 iwl_release_nic_access(priv
);
1077 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1078 * looking at all data.
1080 static int iwl_verify_inst_full(struct iwl_priv
*priv
, __le32
*image
,
1088 IWL_DEBUG_INFO("ucode inst image size is %u\n", len
);
1090 ret
= iwl_grab_nic_access(priv
);
1094 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
, RTC_INST_LOWER_BOUND
);
1097 for (; len
> 0; len
-= sizeof(u32
), image
++) {
1098 /* read data comes through single port, auto-incr addr */
1099 /* NOTE: Use the debugless read so we don't flood kernel log
1100 * if IWL_DL_IO is set */
1101 val
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
1102 if (val
!= le32_to_cpu(*image
)) {
1103 IWL_ERROR("uCode INST section is invalid at "
1104 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1105 save_len
- len
, val
, le32_to_cpu(*image
));
1113 iwl_release_nic_access(priv
);
1117 ("ucode image in INSTRUCTION memory is good\n");
1123 * iwl_verify_ucode - determine which instruction image is in SRAM,
1124 * and verify its contents
1126 int iwl_verify_ucode(struct iwl_priv
*priv
)
1133 image
= (__le32
*)priv
->ucode_boot
.v_addr
;
1134 len
= priv
->ucode_boot
.len
;
1135 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1137 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1141 /* Try initialize */
1142 image
= (__le32
*)priv
->ucode_init
.v_addr
;
1143 len
= priv
->ucode_init
.len
;
1144 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1146 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1150 /* Try runtime/protocol */
1151 image
= (__le32
*)priv
->ucode_code
.v_addr
;
1152 len
= priv
->ucode_code
.len
;
1153 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1155 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1159 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1161 /* Since nothing seems to match, show first several data entries in
1162 * instruction SRAM, so maybe visual inspection will give a clue.
1163 * Selection of bootstrap image (vs. other images) is arbitrary. */
1164 image
= (__le32
*)priv
->ucode_boot
.v_addr
;
1165 len
= priv
->ucode_boot
.len
;
1166 ret
= iwl_verify_inst_full(priv
, image
, len
);
1170 EXPORT_SYMBOL(iwl_verify_ucode
);
1172 static const char *desc_lookup(int i
)
1180 return "BAD_CHECKSUM";
1182 return "NMI_INTERRUPT";
1186 return "FATAL_ERROR";
1192 #define ERROR_START_OFFSET (1 * sizeof(u32))
1193 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1195 void iwl_dump_nic_error_log(struct iwl_priv
*priv
)
1198 u32 desc
, time
, count
, base
, data1
;
1199 u32 blink1
, blink2
, ilink1
, ilink2
;
1202 if (priv
->ucode_type
== UCODE_INIT
)
1203 base
= le32_to_cpu(priv
->card_alive_init
.error_event_table_ptr
);
1205 base
= le32_to_cpu(priv
->card_alive
.error_event_table_ptr
);
1207 if (!priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
1208 IWL_ERROR("Not valid error log pointer 0x%08X\n", base
);
1212 ret
= iwl_grab_nic_access(priv
);
1214 IWL_WARNING("Can not read from adapter at this time.\n");
1218 count
= iwl_read_targ_mem(priv
, base
);
1220 if (ERROR_START_OFFSET
<= count
* ERROR_ELEM_SIZE
) {
1221 IWL_ERROR("Start IWL Error Log Dump:\n");
1222 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv
->status
, count
);
1225 desc
= iwl_read_targ_mem(priv
, base
+ 1 * sizeof(u32
));
1226 blink1
= iwl_read_targ_mem(priv
, base
+ 3 * sizeof(u32
));
1227 blink2
= iwl_read_targ_mem(priv
, base
+ 4 * sizeof(u32
));
1228 ilink1
= iwl_read_targ_mem(priv
, base
+ 5 * sizeof(u32
));
1229 ilink2
= iwl_read_targ_mem(priv
, base
+ 6 * sizeof(u32
));
1230 data1
= iwl_read_targ_mem(priv
, base
+ 7 * sizeof(u32
));
1231 data2
= iwl_read_targ_mem(priv
, base
+ 8 * sizeof(u32
));
1232 line
= iwl_read_targ_mem(priv
, base
+ 9 * sizeof(u32
));
1233 time
= iwl_read_targ_mem(priv
, base
+ 11 * sizeof(u32
));
1235 IWL_ERROR("Desc Time "
1236 "data1 data2 line\n");
1237 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1238 desc_lookup(desc
), desc
, time
, data1
, data2
, line
);
1239 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1240 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1
, blink2
,
1243 iwl_release_nic_access(priv
);
1245 EXPORT_SYMBOL(iwl_dump_nic_error_log
);
1247 #define EVENT_START_OFFSET (4 * sizeof(u32))
1250 * iwl_print_event_log - Dump error event log to syslog
1252 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
1254 static void iwl_print_event_log(struct iwl_priv
*priv
, u32 start_idx
,
1255 u32 num_events
, u32 mode
)
1258 u32 base
; /* SRAM byte address of event log header */
1259 u32 event_size
; /* 2 u32s, or 3 u32s if timestamp recorded */
1260 u32 ptr
; /* SRAM byte address of log data */
1261 u32 ev
, time
, data
; /* event log data */
1263 if (num_events
== 0)
1265 if (priv
->ucode_type
== UCODE_INIT
)
1266 base
= le32_to_cpu(priv
->card_alive_init
.log_event_table_ptr
);
1268 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
1271 event_size
= 2 * sizeof(u32
);
1273 event_size
= 3 * sizeof(u32
);
1275 ptr
= base
+ EVENT_START_OFFSET
+ (start_idx
* event_size
);
1277 /* "time" is actually "data" for mode 0 (no timestamp).
1278 * place event id # at far right for easier visual parsing. */
1279 for (i
= 0; i
< num_events
; i
++) {
1280 ev
= iwl_read_targ_mem(priv
, ptr
);
1282 time
= iwl_read_targ_mem(priv
, ptr
);
1286 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time
, ev
);
1288 data
= iwl_read_targ_mem(priv
, ptr
);
1290 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1296 void iwl_dump_nic_event_log(struct iwl_priv
*priv
)
1299 u32 base
; /* SRAM byte address of event log header */
1300 u32 capacity
; /* event log capacity in # entries */
1301 u32 mode
; /* 0 - no timestamp, 1 - timestamp recorded */
1302 u32 num_wraps
; /* # times uCode wrapped to top of log */
1303 u32 next_entry
; /* index of next entry to be written by uCode */
1304 u32 size
; /* # entries that we'll print */
1306 if (priv
->ucode_type
== UCODE_INIT
)
1307 base
= le32_to_cpu(priv
->card_alive_init
.log_event_table_ptr
);
1309 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
1311 if (!priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
1312 IWL_ERROR("Invalid event log pointer 0x%08X\n", base
);
1316 ret
= iwl_grab_nic_access(priv
);
1318 IWL_WARNING("Can not read from adapter at this time.\n");
1322 /* event log header */
1323 capacity
= iwl_read_targ_mem(priv
, base
);
1324 mode
= iwl_read_targ_mem(priv
, base
+ (1 * sizeof(u32
)));
1325 num_wraps
= iwl_read_targ_mem(priv
, base
+ (2 * sizeof(u32
)));
1326 next_entry
= iwl_read_targ_mem(priv
, base
+ (3 * sizeof(u32
)));
1328 size
= num_wraps
? capacity
: next_entry
;
1330 /* bail out if nothing in log */
1332 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1333 iwl_release_nic_access(priv
);
1337 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1340 /* if uCode has wrapped back to top of log, start at the oldest entry,
1341 * i.e the next one that uCode would fill. */
1343 iwl_print_event_log(priv
, next_entry
,
1344 capacity
- next_entry
, mode
);
1345 /* (then/else) start at top of log */
1346 iwl_print_event_log(priv
, 0, next_entry
, mode
);
1348 iwl_release_nic_access(priv
);
1350 EXPORT_SYMBOL(iwl_dump_nic_event_log
);
1352 void iwl_rf_kill_ct_config(struct iwl_priv
*priv
)
1354 struct iwl_ct_kill_config cmd
;
1355 unsigned long flags
;
1358 spin_lock_irqsave(&priv
->lock
, flags
);
1359 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
,
1360 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT
);
1361 spin_unlock_irqrestore(&priv
->lock
, flags
);
1363 cmd
.critical_temperature_R
=
1364 cpu_to_le32(priv
->hw_params
.ct_kill_threshold
);
1366 ret
= iwl_send_cmd_pdu(priv
, REPLY_CT_KILL_CONFIG_CMD
,
1369 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1371 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1372 "critical temperature is %d\n",
1373 cmd
.critical_temperature_R
);
1375 EXPORT_SYMBOL(iwl_rf_kill_ct_config
);
1380 * Use: Sets the device's internal card state to enable, disable, or halt
1382 * When in the 'enable' state the card operates as normal.
1383 * When in the 'disable' state, the card enters into a low power mode.
1384 * When in the 'halt' state, the card is shut down and must be fully
1385 * restarted to come back on.
1387 static int iwl_send_card_state(struct iwl_priv
*priv
, u32 flags
, u8 meta_flag
)
1389 struct iwl_host_cmd cmd
= {
1390 .id
= REPLY_CARD_STATE_CMD
,
1393 .meta
.flags
= meta_flag
,
1396 return iwl_send_cmd(priv
, &cmd
);
1399 void iwl_radio_kill_sw_disable_radio(struct iwl_priv
*priv
)
1401 unsigned long flags
;
1403 if (test_bit(STATUS_RF_KILL_SW
, &priv
->status
))
1406 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1408 iwl_scan_cancel(priv
);
1409 /* FIXME: This is a workaround for AP */
1410 if (priv
->iw_mode
!= NL80211_IFTYPE_AP
) {
1411 spin_lock_irqsave(&priv
->lock
, flags
);
1412 iwl_write32(priv
, CSR_UCODE_DRV_GP1_SET
,
1413 CSR_UCODE_SW_BIT_RFKILL
);
1414 spin_unlock_irqrestore(&priv
->lock
, flags
);
1415 /* call the host command only if no hw rf-kill set */
1416 if (!test_bit(STATUS_RF_KILL_HW
, &priv
->status
) &&
1418 iwl_send_card_state(priv
,
1419 CARD_STATE_CMD_DISABLE
, 0);
1420 set_bit(STATUS_RF_KILL_SW
, &priv
->status
);
1421 /* make sure mac80211 stop sending Tx frame */
1422 if (priv
->mac80211_registered
)
1423 ieee80211_stop_queues(priv
->hw
);
1426 EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio
);
1428 int iwl_radio_kill_sw_enable_radio(struct iwl_priv
*priv
)
1430 unsigned long flags
;
1432 if (!test_bit(STATUS_RF_KILL_SW
, &priv
->status
))
1435 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1437 spin_lock_irqsave(&priv
->lock
, flags
);
1438 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1440 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1441 * notification where it will clear SW rfkill status.
1442 * Setting it here would break the handler. Only if the
1443 * interface is down we can set here since we don't
1444 * receive any further notification.
1447 clear_bit(STATUS_RF_KILL_SW
, &priv
->status
);
1448 spin_unlock_irqrestore(&priv
->lock
, flags
);
1453 spin_lock_irqsave(&priv
->lock
, flags
);
1454 iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
1455 if (!iwl_grab_nic_access(priv
))
1456 iwl_release_nic_access(priv
);
1457 spin_unlock_irqrestore(&priv
->lock
, flags
);
1459 if (test_bit(STATUS_RF_KILL_HW
, &priv
->status
)) {
1460 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1461 "disabled by HW switch\n");
1465 /* If the driver is already loaded, it will receive
1466 * CARD_STATE_NOTIFICATION notifications and the handler will
1467 * call restart to reload the driver.
1471 EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio
);