1 /******************************************************************************
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/version.h>
32 #include <net/mac80211.h>
34 struct iwl_priv
; /* FIXME: remove */
35 #include "iwl-debug.h"
36 #include "iwl-eeprom.h"
37 #include "iwl-dev.h" /* FIXME: remove */
40 #include "iwl-rfkill.h"
41 #include "iwl-power.h"
44 MODULE_DESCRIPTION("iwl core");
45 MODULE_VERSION(IWLWIFI_VERSION
);
46 MODULE_AUTHOR(DRV_COPYRIGHT
);
47 MODULE_LICENSE("GPL");
49 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
64 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
70 const struct iwl_rate_info iwl_rates
[IWL_RATE_COUNT
] = {
71 IWL_DECLARE_RATE_INFO(1, INV
, INV
, 2, INV
, 2, INV
, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, INV
, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, INV
, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, INV
, 9, 12, 9, 12, 5, 18), /* 11mbps */
75 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 54, 48, INV
, 48, INV
, 48, INV
),/* 54mbps */
83 IWL_DECLARE_RATE_INFO(60, 60, 48, INV
, 48, INV
, 48, INV
),/* 60mbps */
84 /* FIXME:RS: ^^ should be INV (legacy) */
86 EXPORT_SYMBOL(iwl_rates
);
89 const u8 iwl_bcast_addr
[ETH_ALEN
] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
90 EXPORT_SYMBOL(iwl_bcast_addr
);
93 /* This function both allocates and initializes hw and priv. */
94 struct ieee80211_hw
*iwl_alloc_all(struct iwl_cfg
*cfg
,
95 struct ieee80211_ops
*hw_ops
)
97 struct iwl_priv
*priv
;
99 /* mac80211 allocates memory for this device instance, including
100 * space for this driver's private structure */
101 struct ieee80211_hw
*hw
=
102 ieee80211_alloc_hw(sizeof(struct iwl_priv
), hw_ops
);
104 IWL_ERROR("Can not allocate network device\n");
114 EXPORT_SYMBOL(iwl_alloc_all
);
116 void iwl_hw_detect(struct iwl_priv
*priv
)
118 priv
->hw_rev
= _iwl_read32(priv
, CSR_HW_REV
);
119 priv
->hw_wa_rev
= _iwl_read32(priv
, CSR_HW_REV_WA_REG
);
120 pci_read_config_byte(priv
->pci_dev
, PCI_REVISION_ID
, &priv
->rev_id
);
122 EXPORT_SYMBOL(iwl_hw_detect
);
124 /* Tell nic where to find the "keep warm" buffer */
125 int iwl_kw_init(struct iwl_priv
*priv
)
130 spin_lock_irqsave(&priv
->lock
, flags
);
131 ret
= iwl_grab_nic_access(priv
);
135 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
,
136 priv
->kw
.dma_addr
>> 4);
137 iwl_release_nic_access(priv
);
139 spin_unlock_irqrestore(&priv
->lock
, flags
);
143 int iwl_kw_alloc(struct iwl_priv
*priv
)
145 struct pci_dev
*dev
= priv
->pci_dev
;
146 struct iwl_kw
*kw
= &priv
->kw
;
148 kw
->size
= IWL_KW_SIZE
;
149 kw
->v_addr
= pci_alloc_consistent(dev
, kw
->size
, &kw
->dma_addr
);
157 * iwl_kw_free - Free the "keep warm" buffer
159 void iwl_kw_free(struct iwl_priv
*priv
)
161 struct pci_dev
*dev
= priv
->pci_dev
;
162 struct iwl_kw
*kw
= &priv
->kw
;
165 pci_free_consistent(dev
, kw
->size
, kw
->v_addr
, kw
->dma_addr
);
166 memset(kw
, 0, sizeof(*kw
));
170 int iwl_hw_nic_init(struct iwl_priv
*priv
)
173 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
177 spin_lock_irqsave(&priv
->lock
, flags
);
178 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
179 iwl_write32(priv
, CSR_INT_COALESCING
, 512 / 32);
180 spin_unlock_irqrestore(&priv
->lock
, flags
);
182 ret
= priv
->cfg
->ops
->lib
->apm_ops
.set_pwr_src(priv
, IWL_PWR_SRC_VMAIN
);
184 priv
->cfg
->ops
->lib
->apm_ops
.config(priv
);
186 /* Allocate the RX queue, or reset if it is already allocated */
188 ret
= iwl_rx_queue_alloc(priv
);
190 IWL_ERROR("Unable to initialize Rx queue\n");
194 iwl_rx_queue_reset(priv
, rxq
);
196 iwl_rx_replenish(priv
);
198 iwl_rx_init(priv
, rxq
);
200 spin_lock_irqsave(&priv
->lock
, flags
);
202 rxq
->need_update
= 1;
203 iwl_rx_queue_update_write_ptr(priv
, rxq
);
205 spin_unlock_irqrestore(&priv
->lock
, flags
);
207 /* Allocate and init all Tx and Command queues */
208 ret
= iwl_txq_ctx_reset(priv
);
212 set_bit(STATUS_INIT
, &priv
->status
);
216 EXPORT_SYMBOL(iwl_hw_nic_init
);
219 * iwlcore_clear_stations_table - Clear the driver's station table
221 * NOTE: This does not clear or otherwise alter the device's station table.
223 void iwlcore_clear_stations_table(struct iwl_priv
*priv
)
227 spin_lock_irqsave(&priv
->sta_lock
, flags
);
229 priv
->num_stations
= 0;
230 memset(priv
->stations
, 0, sizeof(priv
->stations
));
232 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
234 EXPORT_SYMBOL(iwlcore_clear_stations_table
);
236 void iwl_reset_qos(struct iwl_priv
*priv
)
245 spin_lock_irqsave(&priv
->lock
, flags
);
246 priv
->qos_data
.qos_active
= 0;
248 if (priv
->iw_mode
== IEEE80211_IF_TYPE_IBSS
) {
249 if (priv
->qos_data
.qos_enable
)
250 priv
->qos_data
.qos_active
= 1;
251 if (!(priv
->active_rate
& 0xfff0)) {
255 } else if (priv
->iw_mode
== IEEE80211_IF_TYPE_AP
) {
256 if (priv
->qos_data
.qos_enable
)
257 priv
->qos_data
.qos_active
= 1;
258 } else if (!(priv
->staging_rxon
.flags
& RXON_FLG_SHORT_SLOT_MSK
)) {
263 if (priv
->qos_data
.qos_active
)
266 priv
->qos_data
.def_qos_parm
.ac
[0].cw_min
= cpu_to_le16(cw_min
);
267 priv
->qos_data
.def_qos_parm
.ac
[0].cw_max
= cpu_to_le16(cw_max
);
268 priv
->qos_data
.def_qos_parm
.ac
[0].aifsn
= aifs
;
269 priv
->qos_data
.def_qos_parm
.ac
[0].edca_txop
= 0;
270 priv
->qos_data
.def_qos_parm
.ac
[0].reserved1
= 0;
272 if (priv
->qos_data
.qos_active
) {
274 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
= cpu_to_le16(cw_min
);
275 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
= cpu_to_le16(cw_max
);
276 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 7;
277 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
= 0;
278 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
281 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
282 cpu_to_le16((cw_min
+ 1) / 2 - 1);
283 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
285 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 2;
287 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
290 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
292 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
295 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
296 cpu_to_le16((cw_min
+ 1) / 4 - 1);
297 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
298 cpu_to_le16((cw_max
+ 1) / 2 - 1);
299 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 2;
300 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
302 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
305 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
308 for (i
= 1; i
< 4; i
++) {
309 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
311 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
313 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= aifs
;
314 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
= 0;
315 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
318 IWL_DEBUG_QOS("set QoS to default \n");
320 spin_unlock_irqrestore(&priv
->lock
, flags
);
322 EXPORT_SYMBOL(iwl_reset_qos
);
324 #ifdef CONFIG_IWL4965_HT
325 #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
326 #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
327 static void iwlcore_init_ht_hw_capab(const struct iwl_priv
*priv
,
328 struct ieee80211_ht_info
*ht_info
,
329 enum ieee80211_band band
)
331 u16 max_bit_rate
= 0;
332 u8 rx_chains_num
= priv
->hw_params
.rx_chains_num
;
333 u8 tx_chains_num
= priv
->hw_params
.tx_chains_num
;
336 memset(ht_info
->supp_mcs_set
, 0, 16);
338 ht_info
->ht_supported
= 1;
340 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_GRN_FLD
;
341 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_SGI_20
;
342 ht_info
->cap
|= (u16
)(IEEE80211_HT_CAP_MIMO_PS
&
343 (IWL_MIMO_PS_NONE
<< 2));
345 max_bit_rate
= MAX_BIT_RATE_20_MHZ
;
346 if (priv
->hw_params
.fat_channel
& BIT(band
)) {
347 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_SUP_WIDTH
;
348 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_SGI_40
;
349 ht_info
->supp_mcs_set
[4] = 0x01;
350 max_bit_rate
= MAX_BIT_RATE_40_MHZ
;
353 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
354 ht_info
->cap
|= (u16
)IEEE80211_HT_CAP_MAX_AMSDU
;
356 ht_info
->ampdu_factor
= CFG_HT_RX_AMPDU_FACTOR_DEF
;
357 ht_info
->ampdu_density
= CFG_HT_MPDU_DENSITY_DEF
;
359 ht_info
->supp_mcs_set
[0] = 0xFF;
360 if (rx_chains_num
>= 2)
361 ht_info
->supp_mcs_set
[1] = 0xFF;
362 if (rx_chains_num
>= 3)
363 ht_info
->supp_mcs_set
[2] = 0xFF;
365 /* Highest supported Rx data rate */
366 max_bit_rate
*= rx_chains_num
;
367 ht_info
->supp_mcs_set
[10] = (u8
)(max_bit_rate
& 0x00FF);
368 ht_info
->supp_mcs_set
[11] = (u8
)((max_bit_rate
& 0xFF00) >> 8);
370 /* Tx MCS capabilities */
371 ht_info
->supp_mcs_set
[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED
;
372 if (tx_chains_num
!= rx_chains_num
) {
373 ht_info
->supp_mcs_set
[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF
;
374 ht_info
->supp_mcs_set
[12] |= ((tx_chains_num
- 1) << 2);
378 static inline void iwlcore_init_ht_hw_capab(const struct iwl_priv
*priv
,
379 struct ieee80211_ht_info
*ht_info
,
380 enum ieee80211_band band
)
383 #endif /* CONFIG_IWL4965_HT */
385 static void iwlcore_init_hw_rates(struct iwl_priv
*priv
,
386 struct ieee80211_rate
*rates
)
390 for (i
= 0; i
< IWL_RATE_COUNT
; i
++) {
391 rates
[i
].bitrate
= iwl_rates
[i
].ieee
* 5;
392 rates
[i
].hw_value
= i
; /* Rate scaling will work on indexes */
393 rates
[i
].hw_value_short
= i
;
395 if ((i
> IWL_LAST_OFDM_RATE
) || (i
< IWL_FIRST_OFDM_RATE
)) {
397 * If CCK != 1M then set short preamble rate flag.
400 (iwl_rates
[i
].plcp
== IWL_RATE_1M_PLCP
) ?
401 0 : IEEE80211_RATE_SHORT_PREAMBLE
;
407 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
409 static int iwlcore_init_geos(struct iwl_priv
*priv
)
411 struct iwl_channel_info
*ch
;
412 struct ieee80211_supported_band
*sband
;
413 struct ieee80211_channel
*channels
;
414 struct ieee80211_channel
*geo_ch
;
415 struct ieee80211_rate
*rates
;
418 if (priv
->bands
[IEEE80211_BAND_2GHZ
].n_bitrates
||
419 priv
->bands
[IEEE80211_BAND_5GHZ
].n_bitrates
) {
420 IWL_DEBUG_INFO("Geography modes already initialized.\n");
421 set_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
425 channels
= kzalloc(sizeof(struct ieee80211_channel
) *
426 priv
->channel_count
, GFP_KERNEL
);
430 rates
= kzalloc((sizeof(struct ieee80211_rate
) * (IWL_RATE_COUNT
+ 1)),
437 /* 5.2GHz channels start after the 2.4GHz channels */
438 sband
= &priv
->bands
[IEEE80211_BAND_5GHZ
];
439 sband
->channels
= &channels
[ARRAY_SIZE(iwl_eeprom_band_1
)];
441 sband
->bitrates
= &rates
[IWL_FIRST_OFDM_RATE
];
442 sband
->n_bitrates
= IWL_RATE_COUNT
- IWL_FIRST_OFDM_RATE
;
444 iwlcore_init_ht_hw_capab(priv
, &sband
->ht_info
, IEEE80211_BAND_5GHZ
);
446 sband
= &priv
->bands
[IEEE80211_BAND_2GHZ
];
447 sband
->channels
= channels
;
449 sband
->bitrates
= rates
;
450 sband
->n_bitrates
= IWL_RATE_COUNT
;
452 iwlcore_init_ht_hw_capab(priv
, &sband
->ht_info
, IEEE80211_BAND_2GHZ
);
454 priv
->ieee_channels
= channels
;
455 priv
->ieee_rates
= rates
;
457 iwlcore_init_hw_rates(priv
, rates
);
459 for (i
= 0; i
< priv
->channel_count
; i
++) {
460 ch
= &priv
->channel_info
[i
];
462 /* FIXME: might be removed if scan is OK */
463 if (!is_channel_valid(ch
))
466 if (is_channel_a_band(ch
))
467 sband
= &priv
->bands
[IEEE80211_BAND_5GHZ
];
469 sband
= &priv
->bands
[IEEE80211_BAND_2GHZ
];
471 geo_ch
= &sband
->channels
[sband
->n_channels
++];
473 geo_ch
->center_freq
=
474 ieee80211_channel_to_frequency(ch
->channel
);
475 geo_ch
->max_power
= ch
->max_power_avg
;
476 geo_ch
->max_antenna_gain
= 0xff;
477 geo_ch
->hw_value
= ch
->channel
;
479 if (is_channel_valid(ch
)) {
480 if (!(ch
->flags
& EEPROM_CHANNEL_IBSS
))
481 geo_ch
->flags
|= IEEE80211_CHAN_NO_IBSS
;
483 if (!(ch
->flags
& EEPROM_CHANNEL_ACTIVE
))
484 geo_ch
->flags
|= IEEE80211_CHAN_PASSIVE_SCAN
;
486 if (ch
->flags
& EEPROM_CHANNEL_RADAR
)
487 geo_ch
->flags
|= IEEE80211_CHAN_RADAR
;
489 if (ch
->max_power_avg
> priv
->max_channel_txpower_limit
)
490 priv
->max_channel_txpower_limit
=
493 geo_ch
->flags
|= IEEE80211_CHAN_DISABLED
;
496 /* Save flags for reg domain usage */
497 geo_ch
->orig_flags
= geo_ch
->flags
;
499 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
500 ch
->channel
, geo_ch
->center_freq
,
501 is_channel_a_band(ch
) ? "5.2" : "2.4",
502 geo_ch
->flags
& IEEE80211_CHAN_DISABLED
?
503 "restricted" : "valid",
507 if ((priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
== 0) &&
508 priv
->cfg
->sku
& IWL_SKU_A
) {
509 printk(KERN_INFO DRV_NAME
510 ": Incorrectly detected BG card as ABG. Please send "
511 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
512 priv
->pci_dev
->device
, priv
->pci_dev
->subsystem_device
);
513 priv
->cfg
->sku
&= ~IWL_SKU_A
;
516 printk(KERN_INFO DRV_NAME
517 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
518 priv
->bands
[IEEE80211_BAND_2GHZ
].n_channels
,
519 priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
);
521 if (priv
->bands
[IEEE80211_BAND_2GHZ
].n_channels
)
522 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
523 &priv
->bands
[IEEE80211_BAND_2GHZ
];
524 if (priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
)
525 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
526 &priv
->bands
[IEEE80211_BAND_5GHZ
];
528 set_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
534 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
536 void iwlcore_free_geos(struct iwl_priv
*priv
)
538 kfree(priv
->ieee_channels
);
539 kfree(priv
->ieee_rates
);
540 clear_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
542 EXPORT_SYMBOL(iwlcore_free_geos
);
544 #ifdef CONFIG_IWL4965_HT
545 static u8
is_single_rx_stream(struct iwl_priv
*priv
)
547 return !priv
->current_ht_config
.is_ht
||
548 ((priv
->current_ht_config
.supp_mcs_set
[1] == 0) &&
549 (priv
->current_ht_config
.supp_mcs_set
[2] == 0)) ||
550 priv
->ps_mode
== IWL_MIMO_PS_STATIC
;
552 static u8
iwl_is_channel_extension(struct iwl_priv
*priv
,
553 enum ieee80211_band band
,
554 u16 channel
, u8 extension_chan_offset
)
556 const struct iwl_channel_info
*ch_info
;
558 ch_info
= iwl_get_channel_info(priv
, band
, channel
);
559 if (!is_channel_valid(ch_info
))
562 if (extension_chan_offset
== IWL_EXT_CHANNEL_OFFSET_NONE
)
565 if ((ch_info
->fat_extension_channel
== extension_chan_offset
) ||
566 (ch_info
->fat_extension_channel
== HT_IE_EXT_CHANNEL_MAX
))
572 u8
iwl_is_fat_tx_allowed(struct iwl_priv
*priv
,
573 struct ieee80211_ht_info
*sta_ht_inf
)
575 struct iwl_ht_info
*iwl_ht_conf
= &priv
->current_ht_config
;
577 if ((!iwl_ht_conf
->is_ht
) ||
578 (iwl_ht_conf
->supported_chan_width
!= IWL_CHANNEL_WIDTH_40MHZ
) ||
579 (iwl_ht_conf
->extension_chan_offset
== IWL_EXT_CHANNEL_OFFSET_NONE
))
583 if ((!sta_ht_inf
->ht_supported
) ||
584 (!(sta_ht_inf
->cap
& IEEE80211_HT_CAP_SUP_WIDTH
)))
588 return iwl_is_channel_extension(priv
, priv
->band
,
589 iwl_ht_conf
->control_channel
,
590 iwl_ht_conf
->extension_chan_offset
);
592 EXPORT_SYMBOL(iwl_is_fat_tx_allowed
);
594 void iwl_set_rxon_ht(struct iwl_priv
*priv
, struct iwl_ht_info
*ht_info
)
596 struct iwl_rxon_cmd
*rxon
= &priv
->staging_rxon
;
602 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
603 if (iwl_is_fat_tx_allowed(priv
, NULL
))
604 rxon
->flags
|= RXON_FLG_CHANNEL_MODE_MIXED_MSK
;
606 rxon
->flags
&= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK
|
607 RXON_FLG_CHANNEL_MODE_PURE_40_MSK
);
609 if (le16_to_cpu(rxon
->channel
) != ht_info
->control_channel
) {
610 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
611 le16_to_cpu(rxon
->channel
),
612 ht_info
->control_channel
);
613 rxon
->channel
= cpu_to_le16(ht_info
->control_channel
);
617 /* Note: control channel is opposite of extension channel */
618 switch (ht_info
->extension_chan_offset
) {
619 case IWL_EXT_CHANNEL_OFFSET_ABOVE
:
620 rxon
->flags
&= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
);
622 case IWL_EXT_CHANNEL_OFFSET_BELOW
:
623 rxon
->flags
|= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
;
625 case IWL_EXT_CHANNEL_OFFSET_NONE
:
627 rxon
->flags
&= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK
;
631 val
= ht_info
->ht_protection
;
633 rxon
->flags
|= cpu_to_le32(val
<< RXON_FLG_HT_OPERATING_MODE_POS
);
635 iwl_set_rxon_chain(priv
);
637 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
638 "rxon flags 0x%X operation mode :0x%X "
639 "extension channel offset 0x%x "
641 ht_info
->supp_mcs_set
[0],
642 ht_info
->supp_mcs_set
[1],
643 ht_info
->supp_mcs_set
[2],
644 le32_to_cpu(rxon
->flags
), ht_info
->ht_protection
,
645 ht_info
->extension_chan_offset
,
646 ht_info
->control_channel
);
649 EXPORT_SYMBOL(iwl_set_rxon_ht
);
652 static inline u8
is_single_rx_stream(struct iwl_priv
*priv
)
656 #endif /*CONFIG_IWL4965_HT */
659 * Determine how many receiver/antenna chains to use.
660 * More provides better reception via diversity. Fewer saves power.
661 * MIMO (dual stream) requires at least 2, but works better with 3.
662 * This does not determine *which* chains to use, just how many.
664 static int iwlcore_get_rx_chain_counter(struct iwl_priv
*priv
,
665 u8
*idle_state
, u8
*rx_state
)
667 u8 is_single
= is_single_rx_stream(priv
);
668 u8 is_cam
= test_bit(STATUS_POWER_PMI
, &priv
->status
) ? 0 : 1;
670 /* # of Rx chains to use when expecting MIMO. */
671 if (is_single
|| (!is_cam
&& (priv
->ps_mode
== IWL_MIMO_PS_STATIC
)))
676 /* # Rx chains when idling and maybe trying to save power */
677 switch (priv
->ps_mode
) {
678 case IWL_MIMO_PS_STATIC
:
679 case IWL_MIMO_PS_DYNAMIC
:
680 *idle_state
= (is_cam
) ? 2 : 1;
682 case IWL_MIMO_PS_NONE
:
683 *idle_state
= (is_cam
) ? *rx_state
: 1;
694 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
696 * Selects how many and which Rx receivers/antennas/chains to use.
697 * This should not be used for scan command ... it puts data in wrong place.
699 void iwl_set_rxon_chain(struct iwl_priv
*priv
)
701 u8 is_single
= is_single_rx_stream(priv
);
702 u8 idle_state
, rx_state
;
704 priv
->staging_rxon
.rx_chain
= 0;
705 rx_state
= idle_state
= 3;
707 /* Tell uCode which antennas are actually connected.
708 * Before first association, we assume all antennas are connected.
709 * Just after first association, iwl_chain_noise_calibration()
710 * checks which antennas actually *are* connected. */
711 priv
->staging_rxon
.rx_chain
|=
712 cpu_to_le16(priv
->hw_params
.valid_rx_ant
<<
713 RXON_RX_CHAIN_VALID_POS
);
715 /* How many receivers should we use? */
716 iwlcore_get_rx_chain_counter(priv
, &idle_state
, &rx_state
);
717 priv
->staging_rxon
.rx_chain
|=
718 cpu_to_le16(rx_state
<< RXON_RX_CHAIN_MIMO_CNT_POS
);
719 priv
->staging_rxon
.rx_chain
|=
720 cpu_to_le16(idle_state
<< RXON_RX_CHAIN_CNT_POS
);
722 if (!is_single
&& (rx_state
>= 2) &&
723 !test_bit(STATUS_POWER_PMI
, &priv
->status
))
724 priv
->staging_rxon
.rx_chain
|= RXON_RX_CHAIN_MIMO_FORCE_MSK
;
726 priv
->staging_rxon
.rx_chain
&= ~RXON_RX_CHAIN_MIMO_FORCE_MSK
;
728 IWL_DEBUG_ASSOC("rx chain %X\n", priv
->staging_rxon
.rx_chain
);
730 EXPORT_SYMBOL(iwl_set_rxon_chain
);
733 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
734 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
735 * @channel: Any channel valid for the requested phymode
737 * In addition to setting the staging RXON, priv->phymode is also set.
739 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
740 * in the staging RXON flag structure based on the phymode
742 int iwl_set_rxon_channel(struct iwl_priv
*priv
,
743 enum ieee80211_band band
,
746 if (!iwl_get_channel_info(priv
, band
, channel
)) {
747 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
752 if ((le16_to_cpu(priv
->staging_rxon
.channel
) == channel
) &&
753 (priv
->band
== band
))
756 priv
->staging_rxon
.channel
= cpu_to_le16(channel
);
757 if (band
== IEEE80211_BAND_5GHZ
)
758 priv
->staging_rxon
.flags
&= ~RXON_FLG_BAND_24G_MSK
;
760 priv
->staging_rxon
.flags
|= RXON_FLG_BAND_24G_MSK
;
764 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel
, band
);
768 EXPORT_SYMBOL(iwl_set_rxon_channel
);
770 static void iwlcore_init_hw(struct iwl_priv
*priv
)
772 struct ieee80211_hw
*hw
= priv
->hw
;
773 hw
->rate_control_algorithm
= "iwl-4965-rs";
775 /* Tell mac80211 our characteristics */
776 hw
->flags
= IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE
|
777 IEEE80211_HW_SIGNAL_DBM
|
778 IEEE80211_HW_NOISE_DBM
;
779 /* Default value; 4 EDCA QOS priorities */
781 #ifdef CONFIG_IWL4965_HT
782 /* Enhanced value; more queues, to support 11n aggregation */
783 hw
->ampdu_queues
= 12;
784 #endif /* CONFIG_IWL4965_HT */
787 static int iwlcore_init_drv(struct iwl_priv
*priv
)
792 priv
->retry_rate
= 1;
793 priv
->ibss_beacon
= NULL
;
795 spin_lock_init(&priv
->lock
);
796 spin_lock_init(&priv
->power_data
.lock
);
797 spin_lock_init(&priv
->sta_lock
);
798 spin_lock_init(&priv
->hcmd_lock
);
799 spin_lock_init(&priv
->lq_mngr
.lock
);
801 for (i
= 0; i
< IWL_IBSS_MAC_HASH_SIZE
; i
++)
802 INIT_LIST_HEAD(&priv
->ibss_mac_hash
[i
]);
804 INIT_LIST_HEAD(&priv
->free_frames
);
806 mutex_init(&priv
->mutex
);
808 /* Clear the driver's (not device's) station table */
809 iwlcore_clear_stations_table(priv
);
811 priv
->data_retry_limit
= -1;
812 priv
->ieee_channels
= NULL
;
813 priv
->ieee_rates
= NULL
;
814 priv
->band
= IEEE80211_BAND_2GHZ
;
816 priv
->iw_mode
= IEEE80211_IF_TYPE_STA
;
818 priv
->use_ant_b_for_management_frame
= 1; /* start with ant B */
819 priv
->ps_mode
= IWL_MIMO_PS_NONE
;
821 /* Choose which receivers/antennas to use */
822 iwl_set_rxon_chain(priv
);
826 priv
->qos_data
.qos_active
= 0;
827 priv
->qos_data
.qos_cap
.val
= 0;
829 iwl_set_rxon_channel(priv
, IEEE80211_BAND_2GHZ
, 6);
831 priv
->rates_mask
= IWL_RATES_MASK
;
832 /* If power management is turned on, default to AC mode */
833 priv
->power_mode
= IWL_POWER_AC
;
834 priv
->user_txpower_limit
= IWL_DEFAULT_TX_POWER
;
836 ret
= iwl_init_channel_map(priv
);
838 IWL_ERROR("initializing regulatory failed: %d\n", ret
);
842 ret
= iwlcore_init_geos(priv
);
844 IWL_ERROR("initializing geos failed: %d\n", ret
);
845 goto err_free_channel_map
;
848 ret
= ieee80211_register_hw(priv
->hw
);
850 IWL_ERROR("Failed to register network device (error %d)\n",
855 priv
->hw
->conf
.beacon_int
= 100;
856 priv
->mac80211_registered
= 1;
861 iwlcore_free_geos(priv
);
862 err_free_channel_map
:
863 iwl_free_channel_map(priv
);
868 int iwl_setup(struct iwl_priv
*priv
)
871 iwlcore_init_hw(priv
);
872 ret
= iwlcore_init_drv(priv
);
875 EXPORT_SYMBOL(iwl_setup
);
877 /* Low level driver call this function to update iwlcore with
880 int iwlcore_low_level_notify(struct iwl_priv
*priv
,
881 enum iwlcore_card_notify notify
)
885 case IWLCORE_INIT_EVT
:
886 ret
= iwl_rfkill_init(priv
);
888 IWL_ERROR("Unable to initialize RFKILL system. "
889 "Ignoring error: %d\n", ret
);
890 iwl_power_initialize(priv
);
892 case IWLCORE_START_EVT
:
893 iwl_power_update_mode(priv
, 1);
895 case IWLCORE_STOP_EVT
:
897 case IWLCORE_REMOVE_EVT
:
898 iwl_rfkill_unregister(priv
);
904 EXPORT_SYMBOL(iwlcore_low_level_notify
);
906 int iwl_send_statistics_request(struct iwl_priv
*priv
, u8 flags
)
909 struct iwl_host_cmd cmd
= {
910 .id
= REPLY_STATISTICS_CMD
,
912 .len
= sizeof(stat_flags
),
913 .data
= (u8
*) &stat_flags
,
915 return iwl_send_cmd(priv
, &cmd
);
917 EXPORT_SYMBOL(iwl_send_statistics_request
);
920 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
921 * using sample data 100 bytes apart. If these sample points are good,
922 * it's a pretty good bet that everything between them is good, too.
924 static int iwlcore_verify_inst_sparse(struct iwl_priv
*priv
, __le32
*image
, u32 len
)
931 IWL_DEBUG_INFO("ucode inst image size is %u\n", len
);
933 ret
= iwl_grab_nic_access(priv
);
937 for (i
= 0; i
< len
; i
+= 100, image
+= 100/sizeof(u32
)) {
938 /* read data comes through single port, auto-incr addr */
939 /* NOTE: Use the debugless read so we don't flood kernel log
940 * if IWL_DL_IO is set */
941 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
,
942 i
+ RTC_INST_LOWER_BOUND
);
943 val
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
944 if (val
!= le32_to_cpu(*image
)) {
952 iwl_release_nic_access(priv
);
958 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
959 * looking at all data.
961 static int iwl_verify_inst_full(struct iwl_priv
*priv
, __le32
*image
,
969 IWL_DEBUG_INFO("ucode inst image size is %u\n", len
);
971 ret
= iwl_grab_nic_access(priv
);
975 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
, RTC_INST_LOWER_BOUND
);
978 for (; len
> 0; len
-= sizeof(u32
), image
++) {
979 /* read data comes through single port, auto-incr addr */
980 /* NOTE: Use the debugless read so we don't flood kernel log
981 * if IWL_DL_IO is set */
982 val
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
983 if (val
!= le32_to_cpu(*image
)) {
984 IWL_ERROR("uCode INST section is invalid at "
985 "offset 0x%x, is 0x%x, s/b 0x%x\n",
986 save_len
- len
, val
, le32_to_cpu(*image
));
994 iwl_release_nic_access(priv
);
998 ("ucode image in INSTRUCTION memory is good\n");
1004 * iwl_verify_ucode - determine which instruction image is in SRAM,
1005 * and verify its contents
1007 int iwl_verify_ucode(struct iwl_priv
*priv
)
1014 image
= (__le32
*)priv
->ucode_boot
.v_addr
;
1015 len
= priv
->ucode_boot
.len
;
1016 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1018 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1022 /* Try initialize */
1023 image
= (__le32
*)priv
->ucode_init
.v_addr
;
1024 len
= priv
->ucode_init
.len
;
1025 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1027 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1031 /* Try runtime/protocol */
1032 image
= (__le32
*)priv
->ucode_code
.v_addr
;
1033 len
= priv
->ucode_code
.len
;
1034 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1036 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1040 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1042 /* Since nothing seems to match, show first several data entries in
1043 * instruction SRAM, so maybe visual inspection will give a clue.
1044 * Selection of bootstrap image (vs. other images) is arbitrary. */
1045 image
= (__le32
*)priv
->ucode_boot
.v_addr
;
1046 len
= priv
->ucode_boot
.len
;
1047 ret
= iwl_verify_inst_full(priv
, image
, len
);
1051 EXPORT_SYMBOL(iwl_verify_ucode
);