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Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-rc-fixes-2.6
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <net/mac80211.h>
32
33 struct iwl_priv; /* FIXME: remove */
34 #include "iwl-debug.h"
35 #include "iwl-eeprom.h"
36 #include "iwl-dev.h" /* FIXME: remove */
37 #include "iwl-core.h"
38 #include "iwl-io.h"
39 #include "iwl-rfkill.h"
40 #include "iwl-power.h"
41
42
43 MODULE_DESCRIPTION("iwl core");
44 MODULE_VERSION(IWLWIFI_VERSION);
45 MODULE_AUTHOR(DRV_COPYRIGHT);
46 MODULE_LICENSE("GPL");
47
48 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_SISO_##s##M_PLCP, \
51 IWL_RATE_MIMO2_##s##M_PLCP,\
52 IWL_RATE_MIMO3_##s##M_PLCP,\
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX }
60
61 /*
62 * Parameter order:
63 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
64 *
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
67 *
68 */
69 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
70 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
82 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
83 /* FIXME:RS: ^^ should be INV (legacy) */
84 };
85 EXPORT_SYMBOL(iwl_rates);
86
87 /**
88 * translate ucode response to mac80211 tx status control values
89 */
90 void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
91 struct ieee80211_tx_info *control)
92 {
93 int rate_index;
94
95 control->antenna_sel_tx =
96 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
97 if (rate_n_flags & RATE_MCS_HT_MSK)
98 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
99 if (rate_n_flags & RATE_MCS_GF_MSK)
100 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
101 if (rate_n_flags & RATE_MCS_FAT_MSK)
102 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
103 if (rate_n_flags & RATE_MCS_DUP_MSK)
104 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
105 if (rate_n_flags & RATE_MCS_SGI_MSK)
106 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
107 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
108 if (control->band == IEEE80211_BAND_5GHZ)
109 rate_index -= IWL_FIRST_OFDM_RATE;
110 control->tx_rate_idx = rate_index;
111 }
112 EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
113
114 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
115 {
116 int idx = 0;
117
118 /* HT rate format */
119 if (rate_n_flags & RATE_MCS_HT_MSK) {
120 idx = (rate_n_flags & 0xff);
121
122 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
123 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
124
125 idx += IWL_FIRST_OFDM_RATE;
126 /* skip 9M not supported in ht*/
127 if (idx >= IWL_RATE_9M_INDEX)
128 idx += 1;
129 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
130 return idx;
131
132 /* legacy rate format, search for match in table */
133 } else {
134 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
135 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
136 return idx;
137 }
138
139 return -1;
140 }
141 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
142
143
144
145 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
146 EXPORT_SYMBOL(iwl_bcast_addr);
147
148
149 /* This function both allocates and initializes hw and priv. */
150 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
151 struct ieee80211_ops *hw_ops)
152 {
153 struct iwl_priv *priv;
154
155 /* mac80211 allocates memory for this device instance, including
156 * space for this driver's private structure */
157 struct ieee80211_hw *hw =
158 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
159 if (hw == NULL) {
160 IWL_ERROR("Can not allocate network device\n");
161 goto out;
162 }
163
164 priv = hw->priv;
165 priv->hw = hw;
166
167 out:
168 return hw;
169 }
170 EXPORT_SYMBOL(iwl_alloc_all);
171
172 void iwl_hw_detect(struct iwl_priv *priv)
173 {
174 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
175 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
176 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
177 }
178 EXPORT_SYMBOL(iwl_hw_detect);
179
180 /* Tell nic where to find the "keep warm" buffer */
181 int iwl_kw_init(struct iwl_priv *priv)
182 {
183 unsigned long flags;
184 int ret;
185
186 spin_lock_irqsave(&priv->lock, flags);
187 ret = iwl_grab_nic_access(priv);
188 if (ret)
189 goto out;
190
191 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
192 priv->kw.dma_addr >> 4);
193 iwl_release_nic_access(priv);
194 out:
195 spin_unlock_irqrestore(&priv->lock, flags);
196 return ret;
197 }
198
199 int iwl_kw_alloc(struct iwl_priv *priv)
200 {
201 struct pci_dev *dev = priv->pci_dev;
202 struct iwl_kw *kw = &priv->kw;
203
204 kw->size = IWL_KW_SIZE;
205 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
206 if (!kw->v_addr)
207 return -ENOMEM;
208
209 return 0;
210 }
211
212 /**
213 * iwl_kw_free - Free the "keep warm" buffer
214 */
215 void iwl_kw_free(struct iwl_priv *priv)
216 {
217 struct pci_dev *dev = priv->pci_dev;
218 struct iwl_kw *kw = &priv->kw;
219
220 if (kw->v_addr) {
221 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
222 memset(kw, 0, sizeof(*kw));
223 }
224 }
225
226 int iwl_hw_nic_init(struct iwl_priv *priv)
227 {
228 unsigned long flags;
229 struct iwl_rx_queue *rxq = &priv->rxq;
230 int ret;
231
232 /* nic_init */
233 spin_lock_irqsave(&priv->lock, flags);
234 priv->cfg->ops->lib->apm_ops.init(priv);
235 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
236 spin_unlock_irqrestore(&priv->lock, flags);
237
238 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
239
240 priv->cfg->ops->lib->apm_ops.config(priv);
241
242 /* Allocate the RX queue, or reset if it is already allocated */
243 if (!rxq->bd) {
244 ret = iwl_rx_queue_alloc(priv);
245 if (ret) {
246 IWL_ERROR("Unable to initialize Rx queue\n");
247 return -ENOMEM;
248 }
249 } else
250 iwl_rx_queue_reset(priv, rxq);
251
252 iwl_rx_replenish(priv);
253
254 iwl_rx_init(priv, rxq);
255
256 spin_lock_irqsave(&priv->lock, flags);
257
258 rxq->need_update = 1;
259 iwl_rx_queue_update_write_ptr(priv, rxq);
260
261 spin_unlock_irqrestore(&priv->lock, flags);
262
263 /* Allocate and init all Tx and Command queues */
264 ret = iwl_txq_ctx_reset(priv);
265 if (ret)
266 return ret;
267
268 set_bit(STATUS_INIT, &priv->status);
269
270 return 0;
271 }
272 EXPORT_SYMBOL(iwl_hw_nic_init);
273
274 /**
275 * iwl_clear_stations_table - Clear the driver's station table
276 *
277 * NOTE: This does not clear or otherwise alter the device's station table.
278 */
279 void iwl_clear_stations_table(struct iwl_priv *priv)
280 {
281 unsigned long flags;
282
283 spin_lock_irqsave(&priv->sta_lock, flags);
284
285 if (iwl_is_alive(priv) &&
286 !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
287 iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
288 IWL_ERROR("Couldn't clear the station table\n");
289
290 priv->num_stations = 0;
291 memset(priv->stations, 0, sizeof(priv->stations));
292
293 spin_unlock_irqrestore(&priv->sta_lock, flags);
294 }
295 EXPORT_SYMBOL(iwl_clear_stations_table);
296
297 void iwl_reset_qos(struct iwl_priv *priv)
298 {
299 u16 cw_min = 15;
300 u16 cw_max = 1023;
301 u8 aifs = 2;
302 u8 is_legacy = 0;
303 unsigned long flags;
304 int i;
305
306 spin_lock_irqsave(&priv->lock, flags);
307 priv->qos_data.qos_active = 0;
308
309 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
310 if (priv->qos_data.qos_enable)
311 priv->qos_data.qos_active = 1;
312 if (!(priv->active_rate & 0xfff0)) {
313 cw_min = 31;
314 is_legacy = 1;
315 }
316 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
317 if (priv->qos_data.qos_enable)
318 priv->qos_data.qos_active = 1;
319 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
320 cw_min = 31;
321 is_legacy = 1;
322 }
323
324 if (priv->qos_data.qos_active)
325 aifs = 3;
326
327 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
328 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
329 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
330 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
331 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
332
333 if (priv->qos_data.qos_active) {
334 i = 1;
335 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
336 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
337 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
338 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
339 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
340
341 i = 2;
342 priv->qos_data.def_qos_parm.ac[i].cw_min =
343 cpu_to_le16((cw_min + 1) / 2 - 1);
344 priv->qos_data.def_qos_parm.ac[i].cw_max =
345 cpu_to_le16(cw_max);
346 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
347 if (is_legacy)
348 priv->qos_data.def_qos_parm.ac[i].edca_txop =
349 cpu_to_le16(6016);
350 else
351 priv->qos_data.def_qos_parm.ac[i].edca_txop =
352 cpu_to_le16(3008);
353 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
354
355 i = 3;
356 priv->qos_data.def_qos_parm.ac[i].cw_min =
357 cpu_to_le16((cw_min + 1) / 4 - 1);
358 priv->qos_data.def_qos_parm.ac[i].cw_max =
359 cpu_to_le16((cw_max + 1) / 2 - 1);
360 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
361 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
362 if (is_legacy)
363 priv->qos_data.def_qos_parm.ac[i].edca_txop =
364 cpu_to_le16(3264);
365 else
366 priv->qos_data.def_qos_parm.ac[i].edca_txop =
367 cpu_to_le16(1504);
368 } else {
369 for (i = 1; i < 4; i++) {
370 priv->qos_data.def_qos_parm.ac[i].cw_min =
371 cpu_to_le16(cw_min);
372 priv->qos_data.def_qos_parm.ac[i].cw_max =
373 cpu_to_le16(cw_max);
374 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
375 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
376 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
377 }
378 }
379 IWL_DEBUG_QOS("set QoS to default \n");
380
381 spin_unlock_irqrestore(&priv->lock, flags);
382 }
383 EXPORT_SYMBOL(iwl_reset_qos);
384
385 #define MAX_BIT_RATE_40_MHZ 0x96 /* 150 Mbps */
386 #define MAX_BIT_RATE_20_MHZ 0x48 /* 72 Mbps */
387 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
388 struct ieee80211_ht_info *ht_info,
389 enum ieee80211_band band)
390 {
391 u16 max_bit_rate = 0;
392 u8 rx_chains_num = priv->hw_params.rx_chains_num;
393 u8 tx_chains_num = priv->hw_params.tx_chains_num;
394
395 ht_info->cap = 0;
396 memset(ht_info->supp_mcs_set, 0, 16);
397
398 ht_info->ht_supported = 1;
399
400 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
401 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
402 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
403 (IWL_MIMO_PS_NONE << 2));
404
405 max_bit_rate = MAX_BIT_RATE_20_MHZ;
406 if (priv->hw_params.fat_channel & BIT(band)) {
407 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
408 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
409 ht_info->supp_mcs_set[4] = 0x01;
410 max_bit_rate = MAX_BIT_RATE_40_MHZ;
411 }
412
413 if (priv->cfg->mod_params->amsdu_size_8K)
414 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
415
416 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
417 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
418
419 ht_info->supp_mcs_set[0] = 0xFF;
420 if (rx_chains_num >= 2)
421 ht_info->supp_mcs_set[1] = 0xFF;
422 if (rx_chains_num >= 3)
423 ht_info->supp_mcs_set[2] = 0xFF;
424
425 /* Highest supported Rx data rate */
426 max_bit_rate *= rx_chains_num;
427 ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
428 ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
429
430 /* Tx MCS capabilities */
431 ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
432 if (tx_chains_num != rx_chains_num) {
433 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
434 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
435 }
436 }
437
438 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
439 struct ieee80211_rate *rates)
440 {
441 int i;
442
443 for (i = 0; i < IWL_RATE_COUNT; i++) {
444 rates[i].bitrate = iwl_rates[i].ieee * 5;
445 rates[i].hw_value = i; /* Rate scaling will work on indexes */
446 rates[i].hw_value_short = i;
447 rates[i].flags = 0;
448 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
449 /*
450 * If CCK != 1M then set short preamble rate flag.
451 */
452 rates[i].flags |=
453 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
454 0 : IEEE80211_RATE_SHORT_PREAMBLE;
455 }
456 }
457 }
458
459 /**
460 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
461 */
462 static int iwlcore_init_geos(struct iwl_priv *priv)
463 {
464 struct iwl_channel_info *ch;
465 struct ieee80211_supported_band *sband;
466 struct ieee80211_channel *channels;
467 struct ieee80211_channel *geo_ch;
468 struct ieee80211_rate *rates;
469 int i = 0;
470
471 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
472 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
473 IWL_DEBUG_INFO("Geography modes already initialized.\n");
474 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
475 return 0;
476 }
477
478 channels = kzalloc(sizeof(struct ieee80211_channel) *
479 priv->channel_count, GFP_KERNEL);
480 if (!channels)
481 return -ENOMEM;
482
483 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
484 GFP_KERNEL);
485 if (!rates) {
486 kfree(channels);
487 return -ENOMEM;
488 }
489
490 /* 5.2GHz channels start after the 2.4GHz channels */
491 sband = &priv->bands[IEEE80211_BAND_5GHZ];
492 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
493 /* just OFDM */
494 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
495 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
496
497 if (priv->cfg->sku & IWL_SKU_N)
498 iwlcore_init_ht_hw_capab(priv, &sband->ht_info,
499 IEEE80211_BAND_5GHZ);
500
501 sband = &priv->bands[IEEE80211_BAND_2GHZ];
502 sband->channels = channels;
503 /* OFDM & CCK */
504 sband->bitrates = rates;
505 sband->n_bitrates = IWL_RATE_COUNT;
506
507 if (priv->cfg->sku & IWL_SKU_N)
508 iwlcore_init_ht_hw_capab(priv, &sband->ht_info,
509 IEEE80211_BAND_2GHZ);
510
511 priv->ieee_channels = channels;
512 priv->ieee_rates = rates;
513
514 iwlcore_init_hw_rates(priv, rates);
515
516 for (i = 0; i < priv->channel_count; i++) {
517 ch = &priv->channel_info[i];
518
519 /* FIXME: might be removed if scan is OK */
520 if (!is_channel_valid(ch))
521 continue;
522
523 if (is_channel_a_band(ch))
524 sband = &priv->bands[IEEE80211_BAND_5GHZ];
525 else
526 sband = &priv->bands[IEEE80211_BAND_2GHZ];
527
528 geo_ch = &sband->channels[sband->n_channels++];
529
530 geo_ch->center_freq =
531 ieee80211_channel_to_frequency(ch->channel);
532 geo_ch->max_power = ch->max_power_avg;
533 geo_ch->max_antenna_gain = 0xff;
534 geo_ch->hw_value = ch->channel;
535
536 if (is_channel_valid(ch)) {
537 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
538 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
539
540 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
541 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
542
543 if (ch->flags & EEPROM_CHANNEL_RADAR)
544 geo_ch->flags |= IEEE80211_CHAN_RADAR;
545
546 geo_ch->flags |= ch->fat_extension_channel;
547
548 if (ch->max_power_avg > priv->tx_power_channel_lmt)
549 priv->tx_power_channel_lmt = ch->max_power_avg;
550 } else {
551 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
552 }
553
554 /* Save flags for reg domain usage */
555 geo_ch->orig_flags = geo_ch->flags;
556
557 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
558 ch->channel, geo_ch->center_freq,
559 is_channel_a_band(ch) ? "5.2" : "2.4",
560 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
561 "restricted" : "valid",
562 geo_ch->flags);
563 }
564
565 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
566 priv->cfg->sku & IWL_SKU_A) {
567 printk(KERN_INFO DRV_NAME
568 ": Incorrectly detected BG card as ABG. Please send "
569 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
570 priv->pci_dev->device, priv->pci_dev->subsystem_device);
571 priv->cfg->sku &= ~IWL_SKU_A;
572 }
573
574 printk(KERN_INFO DRV_NAME
575 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
576 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
577 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
578
579
580 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
581
582 return 0;
583 }
584
585 /*
586 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
587 */
588 static void iwlcore_free_geos(struct iwl_priv *priv)
589 {
590 kfree(priv->ieee_channels);
591 kfree(priv->ieee_rates);
592 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
593 }
594
595 static u8 is_single_rx_stream(struct iwl_priv *priv)
596 {
597 return !priv->current_ht_config.is_ht ||
598 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
599 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
600 priv->ps_mode == IWL_MIMO_PS_STATIC;
601 }
602
603 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
604 enum ieee80211_band band,
605 u16 channel, u8 extension_chan_offset)
606 {
607 const struct iwl_channel_info *ch_info;
608
609 ch_info = iwl_get_channel_info(priv, band, channel);
610 if (!is_channel_valid(ch_info))
611 return 0;
612
613 if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE)
614 return !(ch_info->fat_extension_channel &
615 IEEE80211_CHAN_NO_FAT_ABOVE);
616 else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW)
617 return !(ch_info->fat_extension_channel &
618 IEEE80211_CHAN_NO_FAT_BELOW);
619
620 return 0;
621 }
622
623 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
624 struct ieee80211_ht_info *sta_ht_inf)
625 {
626 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
627
628 if ((!iwl_ht_conf->is_ht) ||
629 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
630 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE))
631 return 0;
632
633 if (sta_ht_inf) {
634 if ((!sta_ht_inf->ht_supported) ||
635 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
636 return 0;
637 }
638
639 return iwl_is_channel_extension(priv, priv->band,
640 iwl_ht_conf->control_channel,
641 iwl_ht_conf->extension_chan_offset);
642 }
643 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
644
645 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
646 {
647 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
648 u32 val;
649
650 if (!ht_info->is_ht)
651 return;
652
653 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
654 if (iwl_is_fat_tx_allowed(priv, NULL))
655 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
656 else
657 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
658 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
659
660 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
661 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
662 le16_to_cpu(rxon->channel),
663 ht_info->control_channel);
664 return;
665 }
666
667 /* Note: control channel is opposite of extension channel */
668 switch (ht_info->extension_chan_offset) {
669 case IEEE80211_HT_IE_CHA_SEC_ABOVE:
670 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
671 break;
672 case IEEE80211_HT_IE_CHA_SEC_BELOW:
673 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
674 break;
675 case IEEE80211_HT_IE_CHA_SEC_NONE:
676 default:
677 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
678 break;
679 }
680
681 val = ht_info->ht_protection;
682
683 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
684
685 iwl_set_rxon_chain(priv);
686
687 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
688 "rxon flags 0x%X operation mode :0x%X "
689 "extension channel offset 0x%x "
690 "control chan %d\n",
691 ht_info->supp_mcs_set[0],
692 ht_info->supp_mcs_set[1],
693 ht_info->supp_mcs_set[2],
694 le32_to_cpu(rxon->flags), ht_info->ht_protection,
695 ht_info->extension_chan_offset,
696 ht_info->control_channel);
697 return;
698 }
699 EXPORT_SYMBOL(iwl_set_rxon_ht);
700
701 /*
702 * Determine how many receiver/antenna chains to use.
703 * More provides better reception via diversity. Fewer saves power.
704 * MIMO (dual stream) requires at least 2, but works better with 3.
705 * This does not determine *which* chains to use, just how many.
706 */
707 static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
708 u8 *idle_state, u8 *rx_state)
709 {
710 u8 is_single = is_single_rx_stream(priv);
711 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
712
713 /* # of Rx chains to use when expecting MIMO. */
714 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
715 *rx_state = 2;
716 else
717 *rx_state = 3;
718
719 /* # Rx chains when idling and maybe trying to save power */
720 switch (priv->ps_mode) {
721 case IWL_MIMO_PS_STATIC:
722 case IWL_MIMO_PS_DYNAMIC:
723 *idle_state = (is_cam) ? 2 : 1;
724 break;
725 case IWL_MIMO_PS_NONE:
726 *idle_state = (is_cam) ? *rx_state : 1;
727 break;
728 default:
729 *idle_state = 1;
730 break;
731 }
732
733 return 0;
734 }
735
736 /**
737 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
738 *
739 * Selects how many and which Rx receivers/antennas/chains to use.
740 * This should not be used for scan command ... it puts data in wrong place.
741 */
742 void iwl_set_rxon_chain(struct iwl_priv *priv)
743 {
744 u8 is_single = is_single_rx_stream(priv);
745 u8 idle_state, rx_state;
746
747 priv->staging_rxon.rx_chain = 0;
748 rx_state = idle_state = 3;
749
750 /* Tell uCode which antennas are actually connected.
751 * Before first association, we assume all antennas are connected.
752 * Just after first association, iwl_chain_noise_calibration()
753 * checks which antennas actually *are* connected. */
754 priv->staging_rxon.rx_chain |=
755 cpu_to_le16(priv->hw_params.valid_rx_ant <<
756 RXON_RX_CHAIN_VALID_POS);
757
758 /* How many receivers should we use? */
759 iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
760 priv->staging_rxon.rx_chain |=
761 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
762 priv->staging_rxon.rx_chain |=
763 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
764
765 if (!is_single && (rx_state >= 2) &&
766 !test_bit(STATUS_POWER_PMI, &priv->status))
767 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
768 else
769 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
770
771 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
772 }
773 EXPORT_SYMBOL(iwl_set_rxon_chain);
774
775 /**
776 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
777 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
778 * @channel: Any channel valid for the requested phymode
779
780 * In addition to setting the staging RXON, priv->phymode is also set.
781 *
782 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
783 * in the staging RXON flag structure based on the phymode
784 */
785 int iwl_set_rxon_channel(struct iwl_priv *priv,
786 enum ieee80211_band band,
787 u16 channel)
788 {
789 if (!iwl_get_channel_info(priv, band, channel)) {
790 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
791 channel, band);
792 return -EINVAL;
793 }
794
795 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
796 (priv->band == band))
797 return 0;
798
799 priv->staging_rxon.channel = cpu_to_le16(channel);
800 if (band == IEEE80211_BAND_5GHZ)
801 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
802 else
803 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
804
805 priv->band = band;
806
807 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
808
809 return 0;
810 }
811 EXPORT_SYMBOL(iwl_set_rxon_channel);
812
813 int iwl_setup_mac(struct iwl_priv *priv)
814 {
815 int ret;
816 struct ieee80211_hw *hw = priv->hw;
817 hw->rate_control_algorithm = "iwl-agn-rs";
818
819 /* Tell mac80211 our characteristics */
820 hw->flags = IEEE80211_HW_SIGNAL_DBM |
821 IEEE80211_HW_NOISE_DBM;
822 /* Default value; 4 EDCA QOS priorities */
823 hw->queues = 4;
824 /* queues to support 11n aggregation */
825 if (priv->cfg->sku & IWL_SKU_N)
826 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
827
828 hw->conf.beacon_int = 100;
829 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
830
831 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
832 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
833 &priv->bands[IEEE80211_BAND_2GHZ];
834 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
835 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
836 &priv->bands[IEEE80211_BAND_5GHZ];
837
838 ret = ieee80211_register_hw(priv->hw);
839 if (ret) {
840 IWL_ERROR("Failed to register hw (error %d)\n", ret);
841 return ret;
842 }
843 priv->mac80211_registered = 1;
844
845 return 0;
846 }
847 EXPORT_SYMBOL(iwl_setup_mac);
848
849 int iwl_set_hw_params(struct iwl_priv *priv)
850 {
851 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
852 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
853 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
854 if (priv->cfg->mod_params->amsdu_size_8K)
855 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
856 else
857 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
858 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
859
860 if (priv->cfg->mod_params->disable_11n)
861 priv->cfg->sku &= ~IWL_SKU_N;
862
863 /* Device-specific setup */
864 return priv->cfg->ops->lib->set_hw_params(priv);
865 }
866 EXPORT_SYMBOL(iwl_set_hw_params);
867
868 int iwl_init_drv(struct iwl_priv *priv)
869 {
870 int ret;
871
872 priv->retry_rate = 1;
873 priv->ibss_beacon = NULL;
874
875 spin_lock_init(&priv->lock);
876 spin_lock_init(&priv->power_data.lock);
877 spin_lock_init(&priv->sta_lock);
878 spin_lock_init(&priv->hcmd_lock);
879 spin_lock_init(&priv->lq_mngr.lock);
880
881 INIT_LIST_HEAD(&priv->free_frames);
882
883 mutex_init(&priv->mutex);
884
885 /* Clear the driver's (not device's) station table */
886 iwl_clear_stations_table(priv);
887
888 priv->data_retry_limit = -1;
889 priv->ieee_channels = NULL;
890 priv->ieee_rates = NULL;
891 priv->band = IEEE80211_BAND_2GHZ;
892
893 priv->iw_mode = IEEE80211_IF_TYPE_STA;
894
895 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
896 priv->ps_mode = IWL_MIMO_PS_NONE;
897
898 /* Choose which receivers/antennas to use */
899 iwl_set_rxon_chain(priv);
900 iwl_init_scan_params(priv);
901
902 if (priv->cfg->mod_params->enable_qos)
903 priv->qos_data.qos_enable = 1;
904
905 iwl_reset_qos(priv);
906
907 priv->qos_data.qos_active = 0;
908 priv->qos_data.qos_cap.val = 0;
909
910 iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
911
912 priv->rates_mask = IWL_RATES_MASK;
913 /* If power management is turned on, default to AC mode */
914 priv->power_mode = IWL_POWER_AC;
915 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
916
917 ret = iwl_init_channel_map(priv);
918 if (ret) {
919 IWL_ERROR("initializing regulatory failed: %d\n", ret);
920 goto err;
921 }
922
923 ret = iwlcore_init_geos(priv);
924 if (ret) {
925 IWL_ERROR("initializing geos failed: %d\n", ret);
926 goto err_free_channel_map;
927 }
928
929 return 0;
930
931 err_free_channel_map:
932 iwl_free_channel_map(priv);
933 err:
934 return ret;
935 }
936 EXPORT_SYMBOL(iwl_init_drv);
937
938 void iwl_free_calib_results(struct iwl_priv *priv)
939 {
940 kfree(priv->calib_results.lo_res);
941 priv->calib_results.lo_res = NULL;
942 priv->calib_results.lo_res_len = 0;
943
944 kfree(priv->calib_results.tx_iq_res);
945 priv->calib_results.tx_iq_res = NULL;
946 priv->calib_results.tx_iq_res_len = 0;
947
948 kfree(priv->calib_results.tx_iq_perd_res);
949 priv->calib_results.tx_iq_perd_res = NULL;
950 priv->calib_results.tx_iq_perd_res_len = 0;
951 }
952 EXPORT_SYMBOL(iwl_free_calib_results);
953
954 int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
955 {
956 int ret = 0;
957 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
958 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
959 priv->tx_power_user_lmt);
960 return -EINVAL;
961 }
962
963 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
964 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
965 priv->tx_power_user_lmt);
966 return -EINVAL;
967 }
968
969 if (priv->tx_power_user_lmt != tx_power)
970 force = true;
971
972 priv->tx_power_user_lmt = tx_power;
973
974 if (force && priv->cfg->ops->lib->send_tx_power)
975 ret = priv->cfg->ops->lib->send_tx_power(priv);
976
977 return ret;
978 }
979 EXPORT_SYMBOL(iwl_set_tx_power);
980
981
982 void iwl_uninit_drv(struct iwl_priv *priv)
983 {
984 iwl_free_calib_results(priv);
985 iwlcore_free_geos(priv);
986 iwl_free_channel_map(priv);
987 kfree(priv->scan);
988 }
989 EXPORT_SYMBOL(iwl_uninit_drv);
990
991 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
992 {
993 u32 stat_flags = 0;
994 struct iwl_host_cmd cmd = {
995 .id = REPLY_STATISTICS_CMD,
996 .meta.flags = flags,
997 .len = sizeof(stat_flags),
998 .data = (u8 *) &stat_flags,
999 };
1000 return iwl_send_cmd(priv, &cmd);
1001 }
1002 EXPORT_SYMBOL(iwl_send_statistics_request);
1003
1004 /**
1005 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1006 * using sample data 100 bytes apart. If these sample points are good,
1007 * it's a pretty good bet that everything between them is good, too.
1008 */
1009 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1010 {
1011 u32 val;
1012 int ret = 0;
1013 u32 errcnt = 0;
1014 u32 i;
1015
1016 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1017
1018 ret = iwl_grab_nic_access(priv);
1019 if (ret)
1020 return ret;
1021
1022 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1023 /* read data comes through single port, auto-incr addr */
1024 /* NOTE: Use the debugless read so we don't flood kernel log
1025 * if IWL_DL_IO is set */
1026 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1027 i + RTC_INST_LOWER_BOUND);
1028 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1029 if (val != le32_to_cpu(*image)) {
1030 ret = -EIO;
1031 errcnt++;
1032 if (errcnt >= 3)
1033 break;
1034 }
1035 }
1036
1037 iwl_release_nic_access(priv);
1038
1039 return ret;
1040 }
1041
1042 /**
1043 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1044 * looking at all data.
1045 */
1046 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1047 u32 len)
1048 {
1049 u32 val;
1050 u32 save_len = len;
1051 int ret = 0;
1052 u32 errcnt;
1053
1054 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1055
1056 ret = iwl_grab_nic_access(priv);
1057 if (ret)
1058 return ret;
1059
1060 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1061
1062 errcnt = 0;
1063 for (; len > 0; len -= sizeof(u32), image++) {
1064 /* read data comes through single port, auto-incr addr */
1065 /* NOTE: Use the debugless read so we don't flood kernel log
1066 * if IWL_DL_IO is set */
1067 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1068 if (val != le32_to_cpu(*image)) {
1069 IWL_ERROR("uCode INST section is invalid at "
1070 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1071 save_len - len, val, le32_to_cpu(*image));
1072 ret = -EIO;
1073 errcnt++;
1074 if (errcnt >= 20)
1075 break;
1076 }
1077 }
1078
1079 iwl_release_nic_access(priv);
1080
1081 if (!errcnt)
1082 IWL_DEBUG_INFO
1083 ("ucode image in INSTRUCTION memory is good\n");
1084
1085 return ret;
1086 }
1087
1088 /**
1089 * iwl_verify_ucode - determine which instruction image is in SRAM,
1090 * and verify its contents
1091 */
1092 int iwl_verify_ucode(struct iwl_priv *priv)
1093 {
1094 __le32 *image;
1095 u32 len;
1096 int ret;
1097
1098 /* Try bootstrap */
1099 image = (__le32 *)priv->ucode_boot.v_addr;
1100 len = priv->ucode_boot.len;
1101 ret = iwlcore_verify_inst_sparse(priv, image, len);
1102 if (!ret) {
1103 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1104 return 0;
1105 }
1106
1107 /* Try initialize */
1108 image = (__le32 *)priv->ucode_init.v_addr;
1109 len = priv->ucode_init.len;
1110 ret = iwlcore_verify_inst_sparse(priv, image, len);
1111 if (!ret) {
1112 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1113 return 0;
1114 }
1115
1116 /* Try runtime/protocol */
1117 image = (__le32 *)priv->ucode_code.v_addr;
1118 len = priv->ucode_code.len;
1119 ret = iwlcore_verify_inst_sparse(priv, image, len);
1120 if (!ret) {
1121 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1122 return 0;
1123 }
1124
1125 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1126
1127 /* Since nothing seems to match, show first several data entries in
1128 * instruction SRAM, so maybe visual inspection will give a clue.
1129 * Selection of bootstrap image (vs. other images) is arbitrary. */
1130 image = (__le32 *)priv->ucode_boot.v_addr;
1131 len = priv->ucode_boot.len;
1132 ret = iwl_verify_inst_full(priv, image, len);
1133
1134 return ret;
1135 }
1136 EXPORT_SYMBOL(iwl_verify_ucode);
1137
1138
1139 static const char *desc_lookup(int i)
1140 {
1141 switch (i) {
1142 case 1:
1143 return "FAIL";
1144 case 2:
1145 return "BAD_PARAM";
1146 case 3:
1147 return "BAD_CHECKSUM";
1148 case 4:
1149 return "NMI_INTERRUPT";
1150 case 5:
1151 return "SYSASSERT";
1152 case 6:
1153 return "FATAL_ERROR";
1154 }
1155
1156 return "UNKNOWN";
1157 }
1158
1159 #define ERROR_START_OFFSET (1 * sizeof(u32))
1160 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1161
1162 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1163 {
1164 u32 data2, line;
1165 u32 desc, time, count, base, data1;
1166 u32 blink1, blink2, ilink1, ilink2;
1167 int ret;
1168
1169 if (priv->ucode_type == UCODE_INIT)
1170 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1171 else
1172 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1173
1174 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1175 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1176 return;
1177 }
1178
1179 ret = iwl_grab_nic_access(priv);
1180 if (ret) {
1181 IWL_WARNING("Can not read from adapter at this time.\n");
1182 return;
1183 }
1184
1185 count = iwl_read_targ_mem(priv, base);
1186
1187 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1188 IWL_ERROR("Start IWL Error Log Dump:\n");
1189 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1190 }
1191
1192 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1193 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1194 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1195 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1196 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1197 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1198 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1199 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1200 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1201
1202 IWL_ERROR("Desc Time "
1203 "data1 data2 line\n");
1204 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1205 desc_lookup(desc), desc, time, data1, data2, line);
1206 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1207 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1208 ilink1, ilink2);
1209
1210 iwl_release_nic_access(priv);
1211 }
1212 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1213
1214 #define EVENT_START_OFFSET (4 * sizeof(u32))
1215
1216 /**
1217 * iwl_print_event_log - Dump error event log to syslog
1218 *
1219 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1220 */
1221 void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1222 u32 num_events, u32 mode)
1223 {
1224 u32 i;
1225 u32 base; /* SRAM byte address of event log header */
1226 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1227 u32 ptr; /* SRAM byte address of log data */
1228 u32 ev, time, data; /* event log data */
1229
1230 if (num_events == 0)
1231 return;
1232 if (priv->ucode_type == UCODE_INIT)
1233 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1234 else
1235 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1236
1237 if (mode == 0)
1238 event_size = 2 * sizeof(u32);
1239 else
1240 event_size = 3 * sizeof(u32);
1241
1242 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1243
1244 /* "time" is actually "data" for mode 0 (no timestamp).
1245 * place event id # at far right for easier visual parsing. */
1246 for (i = 0; i < num_events; i++) {
1247 ev = iwl_read_targ_mem(priv, ptr);
1248 ptr += sizeof(u32);
1249 time = iwl_read_targ_mem(priv, ptr);
1250 ptr += sizeof(u32);
1251 if (mode == 0) {
1252 /* data, ev */
1253 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1254 } else {
1255 data = iwl_read_targ_mem(priv, ptr);
1256 ptr += sizeof(u32);
1257 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1258 time, data, ev);
1259 }
1260 }
1261 }
1262 EXPORT_SYMBOL(iwl_print_event_log);
1263
1264
1265 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1266 {
1267 int ret;
1268 u32 base; /* SRAM byte address of event log header */
1269 u32 capacity; /* event log capacity in # entries */
1270 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1271 u32 num_wraps; /* # times uCode wrapped to top of log */
1272 u32 next_entry; /* index of next entry to be written by uCode */
1273 u32 size; /* # entries that we'll print */
1274
1275 if (priv->ucode_type == UCODE_INIT)
1276 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1277 else
1278 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1279
1280 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1281 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1282 return;
1283 }
1284
1285 ret = iwl_grab_nic_access(priv);
1286 if (ret) {
1287 IWL_WARNING("Can not read from adapter at this time.\n");
1288 return;
1289 }
1290
1291 /* event log header */
1292 capacity = iwl_read_targ_mem(priv, base);
1293 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1294 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1295 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1296
1297 size = num_wraps ? capacity : next_entry;
1298
1299 /* bail out if nothing in log */
1300 if (size == 0) {
1301 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1302 iwl_release_nic_access(priv);
1303 return;
1304 }
1305
1306 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1307 size, num_wraps);
1308
1309 /* if uCode has wrapped back to top of log, start at the oldest entry,
1310 * i.e the next one that uCode would fill. */
1311 if (num_wraps)
1312 iwl_print_event_log(priv, next_entry,
1313 capacity - next_entry, mode);
1314 /* (then/else) start at top of log */
1315 iwl_print_event_log(priv, 0, next_entry, mode);
1316
1317 iwl_release_nic_access(priv);
1318 }
1319 EXPORT_SYMBOL(iwl_dump_nic_event_log);
1320
1321 void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1322 {
1323 struct iwl_ct_kill_config cmd;
1324 unsigned long flags;
1325 int ret = 0;
1326
1327 spin_lock_irqsave(&priv->lock, flags);
1328 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1329 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1330 spin_unlock_irqrestore(&priv->lock, flags);
1331
1332 cmd.critical_temperature_R =
1333 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1334
1335 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1336 sizeof(cmd), &cmd);
1337 if (ret)
1338 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1339 else
1340 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1341 "critical temperature is %d\n",
1342 cmd.critical_temperature_R);
1343 }
1344 EXPORT_SYMBOL(iwl_rf_kill_ct_config);
1345
1346 /*
1347 * CARD_STATE_CMD
1348 *
1349 * Use: Sets the device's internal card state to enable, disable, or halt
1350 *
1351 * When in the 'enable' state the card operates as normal.
1352 * When in the 'disable' state, the card enters into a low power mode.
1353 * When in the 'halt' state, the card is shut down and must be fully
1354 * restarted to come back on.
1355 */
1356 static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1357 {
1358 struct iwl_host_cmd cmd = {
1359 .id = REPLY_CARD_STATE_CMD,
1360 .len = sizeof(u32),
1361 .data = &flags,
1362 .meta.flags = meta_flag,
1363 };
1364
1365 return iwl_send_cmd(priv, &cmd);
1366 }
1367
1368 void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1369 {
1370 unsigned long flags;
1371
1372 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1373 return;
1374
1375 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1376
1377 iwl_scan_cancel(priv);
1378 /* FIXME: This is a workaround for AP */
1379 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
1380 spin_lock_irqsave(&priv->lock, flags);
1381 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1382 CSR_UCODE_SW_BIT_RFKILL);
1383 spin_unlock_irqrestore(&priv->lock, flags);
1384 /* call the host command only if no hw rf-kill set */
1385 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1386 iwl_is_ready(priv))
1387 iwl_send_card_state(priv,
1388 CARD_STATE_CMD_DISABLE, 0);
1389 set_bit(STATUS_RF_KILL_SW, &priv->status);
1390 /* make sure mac80211 stop sending Tx frame */
1391 if (priv->mac80211_registered)
1392 ieee80211_stop_queues(priv->hw);
1393 }
1394 }
1395 EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1396
1397 int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1398 {
1399 unsigned long flags;
1400
1401 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1402 return 0;
1403
1404 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1405
1406 spin_lock_irqsave(&priv->lock, flags);
1407 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1408
1409 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1410 * notification where it will clear SW rfkill status.
1411 * Setting it here would break the handler. Only if the
1412 * interface is down we can set here since we don't
1413 * receive any further notification.
1414 */
1415 if (!priv->is_open)
1416 clear_bit(STATUS_RF_KILL_SW, &priv->status);
1417 spin_unlock_irqrestore(&priv->lock, flags);
1418
1419 /* wake up ucode */
1420 msleep(10);
1421
1422 spin_lock_irqsave(&priv->lock, flags);
1423 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1424 if (!iwl_grab_nic_access(priv))
1425 iwl_release_nic_access(priv);
1426 spin_unlock_irqrestore(&priv->lock, flags);
1427
1428 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1429 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1430 "disabled by HW switch\n");
1431 return 0;
1432 }
1433
1434 /* If the driver is already loaded, it will receive
1435 * CARD_STATE_NOTIFICATION notifications and the handler will
1436 * call restart to reload the driver.
1437 */
1438 return 1;
1439 }
1440 EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
Linux kernel - Deliverables
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