drivers/net/wireless/iwlwifi/iwl-csr.h

   1 /******************************************************************************
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   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
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   8  * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
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  10  * This program is free software; you can redistribute it and/or modify
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  17  * General Public License for more details.
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  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  48  *    from this software without specific prior written permission.
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  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #ifndef __iwl_csr_h__
  64 #define __iwl_csr_h__
  65 /*
  66  * CSR (control and status registers)
  67  *
  68  * CSR registers are mapped directly into PCI bus space, and are accessible
  69  * whenever platform supplies power to device, even when device is in
  70  * low power states due to driver-invoked device resets
  71  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
  72  *
  73  * Use iwl_write32() and iwl_read32() family to access these registers;
  74  * these provide simple PCI bus access, without waking up the MAC.
  75  * Do not use iwl_write_direct32() family for these registers;
  76  * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
  77  * The MAC (uCode processor, etc.) does not need to be powered up for accessing
  78  * the CSR registers.
  79  *
  80  * NOTE:  Device does need to be awake in order to read this memory
  81  *        via CSR_EEPROM and CSR_OTP registers
  82  */
  83 #define CSR_BASE    (0x000)
  84
  85 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
  86 #define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
  87 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
  88 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
  89 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
  90 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
  91 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
  92 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
  93
  94 /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
  95 #define CSR_INT_PERIODIC_REG    (CSR_BASE+0x005)
  96
  97 /*
  98  * Hardware revision info
  99  * Bit fields:
 100  * 31-8:  Reserved
 101  *  7-4:  Type of device:  see CSR_HW_REV_TYPE_xxx definitions
 102  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
 103  *  1-0:  "Dash" (-) value, as in A-1, etc.
 104  *
 105  * NOTE:  Revision step affects calculation of CCK txpower for 4965.
 106  * NOTE:  See also CSR_HW_REV_WA_REG (work-around for bug in 4965).
 107  */
 108 #define CSR_HW_REV              (CSR_BASE+0x028)
 109
 110 /*
 111  * EEPROM and OTP (one-time-programmable) memory reads
 112  *
 113  * NOTE:  Device must be awake, initialized via apm_ops.init(),
 114  *        in order to read.
 115  */
 116 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
 117 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
 118 #define CSR_OTP_GP_REG          (CSR_BASE+0x034)
 119
 120 #define CSR_GIO_REG             (CSR_BASE+0x03C)
 121 #define CSR_GP_UCODE_REG        (CSR_BASE+0x048)
 122 #define CSR_GP_DRIVER_REG       (CSR_BASE+0x050)
 123
 124 /*
 125  * UCODE-DRIVER GP (general purpose) mailbox registers.
 126  * SET/CLR registers set/clear bit(s) if "1" is written.
 127  */
 128 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
 129 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
 130 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
 131 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
 132
 133 #define CSR_LED_REG             (CSR_BASE+0x094)
 134 #define CSR_DRAM_INT_TBL_REG    (CSR_BASE+0x0A0)
 135
 136 /* GIO Chicken Bits (PCI Express bus link power management) */
 137 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
 138
 139 /* Analog phase-lock-loop configuration  */
 140 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
 141
 142 /*
 143  * CSR Hardware Revision Workaround Register.  Indicates hardware rev;
 144  * "step" determines CCK backoff for txpower calculation.  Used for 4965 only.
 145  * See also CSR_HW_REV register.
 146  * Bit fields:
 147  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
 148  *  1-0:  "Dash" (-) value, as in C-1, etc.
 149  */
 150 #define CSR_HW_REV_WA_REG               (CSR_BASE+0x22C)
 151
 152 #define CSR_DBG_HPET_MEM_REG            (CSR_BASE+0x240)
 153 #define CSR_DBG_LINK_PWR_MGMT_REG       (CSR_BASE+0x250)
 154
 155 /* Bits for CSR_HW_IF_CONFIG_REG */
 156 #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R       (0x00000010)
 157 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER      (0x00000C00)
 158 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI         (0x00000100)
 159 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI       (0x00000200)
 160
 161 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB         (0x00000100)
 162 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM         (0x00000200)
 163 #define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC            (0x00000400)
 164 #define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE         (0x00000800)
 165 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
 166 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)
 167
 168 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A   (0x00080000)
 169 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
 170 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY      (0x00400000) /* PCI_OWN_SEM */
 171 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
 172 #define CSR_HW_IF_CONFIG_REG_PREPARE              (0x08000000) /* WAKE_ME */
 173
 174 #define CSR_INT_PERIODIC_DIS                    (0x00) /* disable periodic int*/
 175 #define CSR_INT_PERIODIC_ENA                    (0xFF) /* 255*32 usec ~ 8 msec*/
 176
 177 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 178  * acknowledged (reset) by host writing "1" to flagged bits. */
 179 #define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
 180 #define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
 181 #define CSR_INT_BIT_RX_PERIODIC  (1 << 28) /* Rx periodic */
 182 #define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
 183 #define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
 184 #define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
 185 #define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
 186 #define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
 187 #define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses, 3945 */
 188 #define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
 189 #define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
 190
 191 #define CSR_INI_SET_MASK        (CSR_INT_BIT_FH_RX   | \
 192                                  CSR_INT_BIT_HW_ERR  | \
 193                                  CSR_INT_BIT_FH_TX   | \
 194                                  CSR_INT_BIT_SW_ERR  | \
 195                                  CSR_INT_BIT_RF_KILL | \
 196                                  CSR_INT_BIT_SW_RX   | \
 197                                  CSR_INT_BIT_WAKEUP  | \
 198                                  CSR_INT_BIT_ALIVE)
 199
 200 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
 201 #define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
 202 #define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
 203 #define CSR39_FH_INT_BIT_RX_CHNL2  (1 << 18) /* Rx channel 2 (3945 only) */
 204 #define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
 205 #define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
 206 #define CSR39_FH_INT_BIT_TX_CHNL6  (1 << 6)  /* Tx channel 6 (3945 only) */
 207 #define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
 208 #define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
 209
 210 #define CSR39_FH_INT_RX_MASK    (CSR_FH_INT_BIT_HI_PRIOR | \
 211                                  CSR39_FH_INT_BIT_RX_CHNL2 | \
 212                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 213                                  CSR_FH_INT_BIT_RX_CHNL0)
 214
 215
 216 #define CSR39_FH_INT_TX_MASK    (CSR39_FH_INT_BIT_TX_CHNL6 | \
 217                                  CSR_FH_INT_BIT_TX_CHNL1 | \
 218                                  CSR_FH_INT_BIT_TX_CHNL0)
 219
 220 #define CSR49_FH_INT_RX_MASK    (CSR_FH_INT_BIT_HI_PRIOR | \
 221                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 222                                  CSR_FH_INT_BIT_RX_CHNL0)
 223
 224 #define CSR49_FH_INT_TX_MASK    (CSR_FH_INT_BIT_TX_CHNL1 | \
 225                                  CSR_FH_INT_BIT_TX_CHNL0)
 226
 227 /* GPIO */
 228 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
 229 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
 230 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)
 231
 232 /* RESET */
 233 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
 234 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
 235 #define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
 236 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
 237 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
 238 #define CSR_RESET_LINK_PWR_MGMT_DISABLED             (0x80000000)
 239
 240 /*
 241  * GP (general purpose) CONTROL REGISTER
 242  * Bit fields:
 243  *    27:  HW_RF_KILL_SW
 244  *         Indicates state of (platform's) hardware RF-Kill switch
 245  * 26-24:  POWER_SAVE_TYPE
 246  *         Indicates current power-saving mode:
 247  *         000 -- No power saving
 248  *         001 -- MAC power-down
 249  *         010 -- PHY (radio) power-down
 250  *         011 -- Error
 251  *   9-6:  SYS_CONFIG
 252  *         Indicates current system configuration, reflecting pins on chip
 253  *         as forced high/low by device circuit board.
 254  *     4:  GOING_TO_SLEEP
 255  *         Indicates MAC is entering a power-saving sleep power-down.
 256  *         Not a good time to access device-internal resources.
 257  *     3:  MAC_ACCESS_REQ
 258  *         Host sets this to request and maintain MAC wakeup, to allow host
 259  *         access to device-internal resources.  Host must wait for
 260  *         MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
 261  *         device registers.
 262  *     2:  INIT_DONE
 263  *         Host sets this to put device into fully operational D0 power mode.
 264  *         Host resets this after SW_RESET to put device into low power mode.
 265  *     0:  MAC_CLOCK_READY
 266  *         Indicates MAC (ucode processor, etc.) is powered up and can run.
 267  *         Internal resources are accessible.
 268  *         NOTE:  This does not indicate that the processor is actually running.
 269  *         NOTE:  This does not indicate that 4965 or 3945 has completed
 270  *                init or post-power-down restore of internal SRAM memory.
 271  *                Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
 272  *                SRAM is restored and uCode is in normal operation mode.
 273  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
 274  *                do not need to save/restore it.
 275  *         NOTE:  After device reset, this bit remains "0" until host sets
 276  *                INIT_DONE
 277  */
 278 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
 279 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
 280 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
 281 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
 282
 283 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)
 284
 285 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
 286 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
 287 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
 288
 289
 290 /* HW REV */
 291 #define CSR_HW_REV_TYPE_MSK            (0x00000F0)
 292 #define CSR_HW_REV_TYPE_3945           (0x00000D0)
 293 #define CSR_HW_REV_TYPE_4965           (0x0000000)
 294 #define CSR_HW_REV_TYPE_5300           (0x0000020)
 295 #define CSR_HW_REV_TYPE_5350           (0x0000030)
 296 #define CSR_HW_REV_TYPE_5100           (0x0000050)
 297 #define CSR_HW_REV_TYPE_5150           (0x0000040)
 298 #define CSR_HW_REV_TYPE_1000           (0x0000060)
 299 #define CSR_HW_REV_TYPE_6x00           (0x0000070)
 300 #define CSR_HW_REV_TYPE_6x50           (0x0000080)
 301 #define CSR_HW_REV_TYPE_NONE           (0x00000F0)
 302
 303 /* EEPROM REG */
 304 #define CSR_EEPROM_REG_READ_VALID_MSK   (0x00000001)
 305 #define CSR_EEPROM_REG_BIT_CMD          (0x00000002)
 306 #define CSR_EEPROM_REG_MSK_ADDR         (0x0000FFFC)
 307 #define CSR_EEPROM_REG_MSK_DATA         (0xFFFF0000)
 308
 309 /* EEPROM GP */
 310 #define CSR_EEPROM_GP_VALID_MSK         (0x00000007) /* signature */
 311 #define CSR_EEPROM_GP_IF_OWNER_MSK      (0x00000180)
 312 #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP    (0x00000000)
 313 #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP          (0x00000001)
 314 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K         (0x00000002)
 315 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K         (0x00000004)
 316
 317 /* One-time-programmable memory general purpose reg */
 318 #define CSR_OTP_GP_REG_DEVICE_SELECT    (0x00010000) /* 0 - EEPROM, 1 - OTP */
 319 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE  (0x00020000) /* 0 - absolute, 1 - relative */
 320 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK          (0x00100000) /* bit 20 */
 321 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK        (0x00200000) /* bit 21 */
 322
 323 /* GP REG */
 324 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000) /* bit 24/25 */
 325 #define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
 326 #define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
 327 #define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
 328 #define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)
 329
 330
 331 /* CSR GIO */
 332 #define CSR_GIO_REG_VAL_L0S_ENABLED     (0x00000002)
 333
 334 /*
 335  * UCODE-DRIVER GP (general purpose) mailbox register 1
 336  * Host driver and uCode write and/or read this register to communicate with
 337  * each other.
 338  * Bit fields:
 339  *     4:  UCODE_DISABLE
 340  *         Host sets this to request permanent halt of uCode, same as
 341  *         sending CARD_STATE command with "halt" bit set.
 342  *     3:  CT_KILL_EXIT
 343  *         Host sets this to request exit from CT_KILL state, i.e. host thinks
 344  *         device temperature is low enough to continue normal operation.
 345  *     2:  CMD_BLOCKED
 346  *         Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
 347  *         to release uCode to clear all Tx and command queues, enter
 348  *         unassociated mode, and power down.
 349  *         NOTE:  Some devices also use HBUS_TARG_MBX_C register for this bit.
 350  *     1:  SW_BIT_RFKILL
 351  *         Host sets this when issuing CARD_STATE command to request
 352  *         device sleep.
 353  *     0:  MAC_SLEEP
 354  *         uCode sets this when preparing a power-saving power-down.
 355  *         uCode resets this when power-up is complete and SRAM is sane.
 356  *         NOTE:  3945/4965 saves internal SRAM data to host when powering down,
 357  *                and must restore this data after powering back up.
 358  *                MAC_SLEEP is the best indication that restore is complete.
 359  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
 360  *                do not need to save/restore it.
 361  */
 362 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
 363 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
 364 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
 365 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
 366
 367 /* GP Driver */
 368 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK         (0x00000003)
 369 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB     (0x00000000)
 370 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB     (0x00000001)
 371 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA     (0x00000002)
 372
 373
 374 /* GIO Chicken Bits (PCI Express bus link power management) */
 375 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
 376 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
 377
 378 /* LED */
 379 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
 380 #define CSR_LED_REG_TRUN_ON (0x78)
 381 #define CSR_LED_REG_TRUN_OFF (0x38)
 382
 383 /* ANA_PLL */
 384 #define CSR39_ANA_PLL_CFG_VAL        (0x01000000)
 385 #define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
 386
 387 /* HPET MEM debug */
 388 #define CSR_DBG_HPET_MEM_REG_VAL        (0xFFFF0000)
 389
 390 /* DRAM INT TABLE */
 391 #define CSR_DRAM_INT_TBL_ENABLE         (1 << 31)
 392 #define CSR_DRAM_INIT_TBL_WRAP_CHECK    (1 << 27)
 393
 394 /*
 395  * HBUS (Host-side Bus)
 396  *
 397  * HBUS registers are mapped directly into PCI bus space, but are used
 398  * to indirectly access device's internal memory or registers that
 399  * may be powered-down.
 400  *
 401  * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
 402  * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
 403  * to make sure the MAC (uCode processor, etc.) is powered up for accessing
 404  * internal resources.
 405  *
 406  * Do not use iwl_write32()/iwl_read32() family to access these registers;
 407  * these provide only simple PCI bus access, without waking up the MAC.
 408  */
 409 #define HBUS_BASE       (0x400)
 410
 411 /*
 412  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
 413  * structures, error log, event log, verifying uCode load).
 414  * First write to address register, then read from or write to data register
 415  * to complete the job.  Once the address register is set up, accesses to
 416  * data registers auto-increment the address by one dword.
 417  * Bit usage for address registers (read or write):
 418  *  0-31:  memory address within device
 419  */
 420 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
 421 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
 422 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
 423 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
 424
 425 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
 426 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
 427 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
 428
 429 /*
 430  * Registers for accessing device's internal peripheral registers
 431  * (e.g. SCD, BSM, etc.).  First write to address register,
 432  * then read from or write to data register to complete the job.
 433  * Bit usage for address registers (read or write):
 434  *  0-15:  register address (offset) within device
 435  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
 436  */
 437 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
 438 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
 439 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
 440 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
 441
 442 /*
 443  * Per-Tx-queue write pointer (index, really!)
 444  * Indicates index to next TFD that driver will fill (1 past latest filled).
 445  * Bit usage:
 446  *  0-7:  queue write index
 447  * 11-8:  queue selector
 448  */
 449 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
 450
 451 #endif /* !__iwl_csr_h__ */