drivers/net/wireless/iwlwifi/iwl-fh.h

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
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  17  * General Public License for more details.
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  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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  23  *
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  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
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  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63
  64 /****************************/
  65 /* Flow Handler Definitions */
  66 /****************************/
  67
  68 /**
  69  * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
  70  * Addresses are offsets from device's PCI hardware base address.
  71  */
  72 #define FH_MEM_LOWER_BOUND                   (0x1000)
  73 #define FH_MEM_UPPER_BOUND                   (0x1EF0)
  74
  75 /**
  76  * Keep-Warm (KW) buffer base address.
  77  *
  78  * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
  79  * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
  80  * DRAM access when 4965 is Txing or Rxing.  The dummy accesses prevent host
  81  * from going into a power-savings mode that would cause higher DRAM latency,
  82  * and possible data over/under-runs, before all Tx/Rx is complete.
  83  *
  84  * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
  85  * of the buffer, which must be 4K aligned.  Once this is set up, the 4965
  86  * automatically invokes keep-warm accesses when normal accesses might not
  87  * be sufficient to maintain fast DRAM response.
  88  *
  89  * Bit fields:
  90  *  31-0:  Keep-warm buffer physical base address [35:4], must be 4K aligned
  91  */
  92 #define FH_KW_MEM_ADDR_REG                   (FH_MEM_LOWER_BOUND + 0x97C)
  93
  94
  95 /**
  96  * TFD Circular Buffers Base (CBBC) addresses
  97  *
  98  * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
  99  * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
 100  * (see struct iwl_tfd_frame).  These 16 pointer registers are offset by 0x04
 101  * bytes from one another.  Each TFD circular buffer in DRAM must be 256-byte
 102  * aligned (address bits 0-7 must be 0).
 103  *
 104  * Bit fields in each pointer register:
 105  *  27-0: TFD CB physical base address [35:8], must be 256-byte aligned
 106  */
 107 #define FH_MEM_CBBC_LOWER_BOUND          (FH_MEM_LOWER_BOUND + 0x9D0)
 108 #define FH_MEM_CBBC_UPPER_BOUND          (FH_MEM_LOWER_BOUND + 0xA10)
 109
 110 /* Find TFD CB base pointer for given queue (range 0-15). */
 111 #define FH_MEM_CBBC_QUEUE(x)  (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
 112
 113
 114 /**
 115  * Rx SRAM Control and Status Registers (RSCSR)
 116  *
 117  * These registers provide handshake between driver and 4965 for the Rx queue
 118  * (this queue handles *all* command responses, notifications, Rx data, etc.
 119  * sent from 4965 uCode to host driver).  Unlike Tx, there is only one Rx
 120  * queue, and only one Rx DMA/FIFO channel.  Also unlike Tx, which can
 121  * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
 122  * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
 123  * mapping between RBDs and RBs.
 124  *
 125  * Driver must allocate host DRAM memory for the following, and set the
 126  * physical address of each into 4965 registers:
 127  *
 128  * 1)  Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
 129  *     entries (although any power of 2, up to 4096, is selectable by driver).
 130  *     Each entry (1 dword) points to a receive buffer (RB) of consistent size
 131  *     (typically 4K, although 8K or 16K are also selectable by driver).
 132  *     Driver sets up RB size and number of RBDs in the CB via Rx config
 133  *     register FH_MEM_RCSR_CHNL0_CONFIG_REG.
 134  *
 135  *     Bit fields within one RBD:
 136  *     27-0:  Receive Buffer physical address bits [35:8], 256-byte aligned
 137  *
 138  *     Driver sets physical address [35:8] of base of RBD circular buffer
 139  *     into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
 140  *
 141  * 2)  Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
 142  *     (RBs) have been filled, via a "write pointer", actually the index of
 143  *     the RB's corresponding RBD within the circular buffer.  Driver sets
 144  *     physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
 145  *
 146  *     Bit fields in lower dword of Rx status buffer (upper dword not used
 147  *     by driver; see struct iwl4965_shared, val0):
 148  *     31-12:  Not used by driver
 149  *     11- 0:  Index of last filled Rx buffer descriptor
 150  *             (4965 writes, driver reads this value)
 151  *
 152  * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
 153  * enter pointers to these RBs into contiguous RBD circular buffer entries,
 154  * and update the 4965's "write" index register,
 155  * FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
 156  *
 157  * This "write" index corresponds to the *next* RBD that the driver will make
 158  * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
 159  * the circular buffer.  This value should initially be 0 (before preparing any
 160  * RBs), should be 8 after preparing the first 8 RBs (for example), and must
 161  * wrap back to 0 at the end of the circular buffer (but don't wrap before
 162  * "read" index has advanced past 1!  See below).
 163  * NOTE:  4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
 164  *
 165  * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
 166  * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
 167  * to tell the driver the index of the latest filled RBD.  The driver must
 168  * read this "read" index from DRAM after receiving an Rx interrupt from 4965.
 169  *
 170  * The driver must also internally keep track of a third index, which is the
 171  * next RBD to process.  When receiving an Rx interrupt, driver should process
 172  * all filled but unprocessed RBs up to, but not including, the RB
 173  * corresponding to the "read" index.  For example, if "read" index becomes "1",
 174  * driver may process the RB pointed to by RBD 0.  Depending on volume of
 175  * traffic, there may be many RBs to process.
 176  *
 177  * If read index == write index, 4965 thinks there is no room to put new data.
 178  * Due to this, the maximum number of filled RBs is 255, instead of 256.  To
 179  * be safe, make sure that there is a gap of at least 2 RBDs between "write"
 180  * and "read" indexes; that is, make sure that there are no more than 254
 181  * buffers waiting to be filled.
 182  */
 183 #define FH_MEM_RSCSR_LOWER_BOUND        (FH_MEM_LOWER_BOUND + 0xBC0)
 184 #define FH_MEM_RSCSR_UPPER_BOUND        (FH_MEM_LOWER_BOUND + 0xC00)
 185 #define FH_MEM_RSCSR_CHNL0              (FH_MEM_RSCSR_LOWER_BOUND)
 186
 187 /**
 188  * Physical base address of 8-byte Rx Status buffer.
 189  * Bit fields:
 190  *  31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
 191  */
 192 #define FH_RSCSR_CHNL0_STTS_WPTR_REG    (FH_MEM_RSCSR_CHNL0)
 193
 194 /**
 195  * Physical base address of Rx Buffer Descriptor Circular Buffer.
 196  * Bit fields:
 197  *  27-0:  RBD CD physical base address [35:8], must be 256-byte aligned.
 198  */
 199 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG   (FH_MEM_RSCSR_CHNL0 + 0x004)
 200
 201 /**
 202  * Rx write pointer (index, really!).
 203  * Bit fields:
 204  *  11-0:  Index of driver's most recent prepared-to-be-filled RBD, + 1.
 205  *         NOTE:  For 256-entry circular buffer, use only bits [7:0].
 206  */
 207 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG   (FH_MEM_RSCSR_CHNL0 + 0x008)
 208 #define FH_RSCSR_CHNL0_WPTR        (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
 209
 210
 211 /**
 212  * Rx Config/Status Registers (RCSR)
 213  * Rx Config Reg for channel 0 (only channel used)
 214  *
 215  * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
 216  * normal operation (see bit fields).
 217  *
 218  * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
 219  * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
 220  * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
 221  *
 222  * Bit fields:
 223  * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
 224  *        '10' operate normally
 225  * 29-24: reserved
 226  * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
 227  *        min "5" for 32 RBDs, max "12" for 4096 RBDs.
 228  * 19-18: reserved
 229  * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
 230  *        '10' 12K, '11' 16K.
 231  * 15-14: reserved
 232  * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
 233  * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
 234  *        typical value 0x10 (about 1/2 msec)
 235  *  3- 0: reserved
 236  */
 237 #define FH_MEM_RCSR_LOWER_BOUND      (FH_MEM_LOWER_BOUND + 0xC00)
 238 #define FH_MEM_RCSR_UPPER_BOUND      (FH_MEM_LOWER_BOUND + 0xCC0)
 239 #define FH_MEM_RCSR_CHNL0            (FH_MEM_RCSR_LOWER_BOUND)
 240
 241 #define FH_MEM_RCSR_CHNL0_CONFIG_REG    (FH_MEM_RCSR_CHNL0)
 242
 243 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
 244 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK   (0x00001000) /* bits 12 */
 245 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
 246 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK   (0x00030000) /* bits 16-17 */
 247 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
 248 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
 249
 250 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS        (20)
 251 #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS      (4)
 252 #define RX_RB_TIMEOUT   (0x10)
 253
 254 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL         (0x00000000)
 255 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL     (0x40000000)
 256 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL        (0x80000000)
 257
 258 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K    (0x00000000)
 259 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K    (0x00010000)
 260 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K   (0x00020000)
 261 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K   (0x00030000)
 262
 263 #define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY              (0x00000004)
 264 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL    (0x00000000)
 265 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL  (0x00001000)
 266
 267
 268 /**
 269  * Rx Shared Status Registers (RSSR)
 270  *
 271  * After stopping Rx DMA channel (writing 0 to
 272  * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
 273  * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
 274  *
 275  * Bit fields:
 276  *  24:  1 = Channel 0 is idle
 277  *
 278  * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
 279  * contain default values that should not be altered by the driver.
 280  */
 281 #define FH_MEM_RSSR_LOWER_BOUND           (FH_MEM_LOWER_BOUND + 0xC40)
 282 #define FH_MEM_RSSR_UPPER_BOUND           (FH_MEM_LOWER_BOUND + 0xD00)
 283
 284 #define FH_MEM_RSSR_SHARED_CTRL_REG       (FH_MEM_RSSR_LOWER_BOUND)
 285 #define FH_MEM_RSSR_RX_STATUS_REG       (FH_MEM_RSSR_LOWER_BOUND + 0x004)
 286 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
 287                                         (FH_MEM_RSSR_LOWER_BOUND + 0x008)
 288
 289 #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE       (0x01000000)
 290
 291 #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
 292
 293 /**
 294  * Transmit DMA Channel Control/Status Registers (TCSR)
 295  *
 296  * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
 297  * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
 298  * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
 299  *
 300  * To use a Tx DMA channel, driver must initialize its
 301  * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
 302  *
 303  * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 304  * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
 305  *
 306  * All other bits should be 0.
 307  *
 308  * Bit fields:
 309  * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
 310  *        '10' operate normally
 311  * 29- 4: Reserved, set to "0"
 312  *     3: Enable internal DMA requests (1, normal operation), disable (0)
 313  *  2- 0: Reserved, set to "0"
 314  */
 315 #define FH_TCSR_LOWER_BOUND  (FH_MEM_LOWER_BOUND + 0xD00)
 316 #define FH_TCSR_UPPER_BOUND  (FH_MEM_LOWER_BOUND + 0xE60)
 317
 318 /* Find Control/Status reg for given Tx DMA/FIFO channel */
 319 #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
 320         (FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
 321
 322 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL    (0x00000000)
 323 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL     (0x00000008)
 324
 325 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE            (0x00000000)
 326 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF        (0x40000000)
 327 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE           (0x80000000)
 328
 329 #define FH_TCSR_CHNL_NUM                            (7)
 330
 331 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY          (0x00000000)
 332 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT           (0x00002000)
 333 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID          (0x00000003)
 334
 335 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT           (0x00000000)
 336 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD          (0x00100000)
 337 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD           (0x00200000)
 338
 339 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM      (20)
 340 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX      (12)
 341 #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
 342         (FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
 343 #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
 344           (FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x4)
 345 #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
 346          (FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x8)
 347
 348 /**
 349  * Tx Shared Status Registers (TSSR)
 350  *
 351  * After stopping Tx DMA channel (writing 0 to
 352  * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
 353  * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
 354  * (channel's buffers empty | no pending requests).
 355  *
 356  * Bit fields:
 357  * 31-24:  1 = Channel buffers empty (channel 7:0)
 358  * 23-16:  1 = No pending requests (channel 7:0)
 359  */
 360 #define FH_TSSR_LOWER_BOUND             (FH_MEM_LOWER_BOUND + 0xEA0)
 361 #define FH_TSSR_UPPER_BOUND             (FH_MEM_LOWER_BOUND + 0xEC0)
 362
 363 #define FH_TSSR_TX_STATUS_REG   (FH_TSSR_LOWER_BOUND + 0x010)
 364
 365 #define FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) ((1 << (_chnl)) << 24)
 366 #define FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) ((1 << (_chnl)) << 16)
 367
 368 #define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
 369         (FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
 370         FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
 371
 372
 373
 374 #define FH_REGS_LOWER_BOUND                  (0x1000)
 375 #define FH_REGS_UPPER_BOUND                  (0x2000)
 376
 377 /* Tx service channels */
 378 #define FH_SRVC_CHNL                                (9)
 379 #define FH_SRVC_LOWER_BOUND          (FH_REGS_LOWER_BOUND + 0x9C8)
 380 #define FH_SRVC_UPPER_BOUND          (FH_REGS_LOWER_BOUND + 0x9D0)
 381 #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
 382                 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
 383
 384 /* TFDB  Area - TFDs buffer table */
 385 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK      (0xFFFFFFFF)
 386 #define FH_TFDIB_LOWER_BOUND       (FH_REGS_LOWER_BOUND + 0x900)
 387 #define FH_TFDIB_UPPER_BOUND       (FH_REGS_LOWER_BOUND + 0x958)
 388 #define FH_TFDIB_CTRL0_REG(_chnl)  (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
 389 #define FH_TFDIB_CTRL1_REG(_chnl)  (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
 390
 391 /* TCSR: tx_config register values */
 392 #define FH_RSCSR_FRAME_SIZE_MSK (0x00003FFF)    /* bits 0-13 */
 393