1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
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8 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
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21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
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61 *****************************************************************************/
63 #ifndef __iwl_prph_h__
64 #define __iwl_prph_h__
67 * Registers in this file are internal, not PCI bus memory mapped.
68 * Driver accesses these via HBUS_TARG_PRPH_* registers.
70 #define PRPH_BASE (0x00000)
71 #define PRPH_END (0xFFFFF)
73 /* APMG (power management) constants */
74 #define APMG_BASE (PRPH_BASE + 0x3000)
75 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
76 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
77 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
78 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
79 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
80 #define APMG_RFKILL_REG (APMG_BASE + 0x0014)
81 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
82 #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
84 #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
85 #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
87 #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
89 #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
91 #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
92 #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
93 #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x01000000)
97 * BSM (Bootstrap State Machine)
99 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
100 * in special SRAM that does not power down when the embedded control
101 * processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
103 * When powering back up after sleeps (or during initial uCode load), the BSM
104 * internally loads the short bootstrap program from the special SRAM into the
105 * embedded processor's instruction SRAM, and starts the processor so it runs
106 * the bootstrap program.
108 * This bootstrap program loads (via PCI busmaster DMA) instructions and data
109 * images for a uCode program from host DRAM locations. The host driver
110 * indicates DRAM locations and sizes for instruction and data images via the
111 * four BSM_DRAM_* registers. Once the bootstrap program loads the new program,
112 * the new program starts automatically.
114 * The uCode used for open-source drivers includes two programs:
116 * 1) Initialization -- performs hardware calibration and sets up some
117 * internal data, then notifies host via "initialize alive" notification
118 * (struct iwl_init_alive_resp) that it has completed all of its work.
119 * After signal from host, it then loads and starts the runtime program.
120 * The initialization program must be used when initially setting up the
121 * NIC after loading the driver.
123 * 2) Runtime/Protocol -- performs all normal runtime operations. This
124 * notifies host via "alive" notification (struct iwl_alive_resp) that it
125 * is ready to be used.
127 * When initializing the NIC, the host driver does the following procedure:
129 * 1) Load bootstrap program (instructions only, no data image for bootstrap)
130 * into bootstrap memory. Use dword writes starting at BSM_SRAM_LOWER_BOUND
132 * 2) Point (via BSM_DRAM_*) to the "initialize" uCode data and instruction
133 * images in host DRAM.
135 * 3) Set up BSM to copy from BSM SRAM into uCode instruction SRAM when asked:
136 * BSM_WR_MEM_SRC_REG = 0
137 * BSM_WR_MEM_DST_REG = RTC_INST_LOWER_BOUND
138 * BSM_WR_MEM_DWCOUNT_REG = # dwords in bootstrap instruction image
140 * 4) Load bootstrap into instruction SRAM:
141 * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START
143 * 5) Wait for load completion:
144 * Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0
146 * 6) Enable future boot loads whenever NIC's power management triggers it:
147 * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START_EN
149 * 7) Start the NIC by removing all reset bits:
152 * The bootstrap uCode (already in instruction SRAM) loads initialization
153 * uCode. Initialization uCode performs data initialization, sends
154 * "initialize alive" notification to host, and waits for a signal from
155 * host to load runtime code.
157 * 4) Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction
158 * images in host DRAM. The last register loaded must be the instruction
159 * bytecount register ("1" in MSbit tells initialization uCode to load
160 * the runtime uCode):
161 * BSM_DRAM_INST_BYTECOUNT_REG = bytecount | BSM_DRAM_INST_LOAD
163 * 5) Wait for "alive" notification, then issue normal runtime commands.
165 * Data caching during power-downs:
167 * Just before the embedded controller powers down (e.g for automatic
168 * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA)
169 * a current snapshot of the embedded processor's data SRAM into host DRAM.
170 * This caches the data while the embedded processor's memory is powered down.
171 * Location and size are controlled by BSM_DRAM_DATA_* registers.
173 * NOTE: Instruction SRAM does not need to be saved, since that doesn't
174 * change during operation; the original image (from uCode distribution
175 * file) can be used for reload.
177 * When powering back up, the BSM loads the bootstrap program. Bootstrap looks
178 * at the BSM_DRAM_* registers, which now point to the runtime instruction
179 * image and the cached (modified) runtime data (*not* the initialization
180 * uCode). Bootstrap reloads these runtime images into SRAM, and restarts the
181 * uCode from where it left off before the power-down.
183 * NOTE: Initialization uCode does *not* run as part of the save/restore
186 * This save/restore method is mostly for autonomous power management during
187 * normal operation (result of POWER_TABLE_CMD). Platform suspend/resume and
188 * RFKILL should use complete restarts (with total re-initialization) of uCode,
189 * allowing total shutdown (including BSM memory).
191 * Note that, during normal operation, the host DRAM that held the initial
192 * startup data for the runtime code is now being used as a backup data cache
193 * for modified data! If you need to completely re-initialize the NIC, make
194 * sure that you use the runtime data image from the uCode distribution file,
195 * not the modified/saved runtime data. You may want to store a separate
196 * "clean" runtime data image in DRAM to avoid disk reads of distribution file.
200 #define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */
201 #define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup*/
202 #define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */
205 #define BSM_BASE (PRPH_BASE + 0x3400)
206 #define BSM_END (PRPH_BASE + 0x3800)
208 #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */
209 #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */
210 #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */
211 #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */
212 #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */
215 * Pointers and size regs for bootstrap load and data SRAM save/restore.
216 * NOTE: 3945 pointers use bits 31:0 of DRAM address.
217 * 4965 pointers use bits 35:4 of DRAM address.
219 #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090)
220 #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094)
221 #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098)
222 #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C)
225 * BSM special memory, stays powered on during power-save sleeps.
226 * Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1)
228 #define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
229 #define BSM_SRAM_SIZE (1024) /* bytes */
232 /* 3945 Tx scheduler registers */
233 #define ALM_SCD_BASE (PRPH_BASE + 0x2E00)
234 #define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)
235 #define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)
236 #define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010)
237 #define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014)
238 #define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020)
239 #define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
240 #define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
245 * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs
246 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
247 * host DRAM. It steers each frame's Tx command (which contains the frame
248 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
249 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
250 * but one DMA channel may take input from several queues.
252 * Tx DMA channels have dedicated purposes. For 4965, they are used as follows:
254 * 0 -- EDCA BK (background) frames, lowest priority
255 * 1 -- EDCA BE (best effort) frames, normal priority
256 * 2 -- EDCA VI (video) frames, higher priority
257 * 3 -- EDCA VO (voice) and management frames, highest priority
258 * 4 -- Commands (e.g. RXON, etc.)
259 * 5 -- HCCA short frames
260 * 6 -- HCCA long frames
261 * 7 -- not used by driver (device-internal only)
263 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
264 * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to
265 * support 11n aggregation via EDCA DMA channels.
267 * The driver sets up each queue to work in one of two modes:
269 * 1) Scheduler-Ack, in which the scheduler automatically supports a
270 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
271 * contains TFDs for a unique combination of Recipient Address (RA)
272 * and Traffic Identifier (TID), that is, traffic of a given
273 * Quality-Of-Service (QOS) priority, destined for a single station.
275 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
276 * each frame within the BA window, including whether it's been transmitted,
277 * and whether it's been acknowledged by the receiving station. The device
278 * automatically processes block-acks received from the receiving STA,
279 * and reschedules un-acked frames to be retransmitted (successful
280 * Tx completion may end up being out-of-order).
282 * The driver must maintain the queue's Byte Count table in host DRAM
283 * (struct iwl4965_sched_queue_byte_cnt_tbl) for this mode.
284 * This mode does not support fragmentation.
286 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
287 * The device may automatically retry Tx, but will retry only one frame
288 * at a time, until receiving ACK from receiving station, or reaching
289 * retry limit and giving up.
291 * The command queue (#4) must use this mode!
292 * This mode does not require use of the Byte Count table in host DRAM.
294 * Driver controls scheduler operation via 3 means:
295 * 1) Scheduler registers
296 * 2) Shared scheduler data base in internal 4956 SRAM
297 * 3) Shared data in host DRAM
301 * When loading, driver should allocate memory for:
302 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
303 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
304 * (1024 bytes for each queue).
306 * After receiving "Alive" response from uCode, driver must initialize
307 * the scheduler (especially for queue #4, the command queue, otherwise
308 * the driver can't issue commands!):
312 * Max Tx window size is the max number of contiguous TFDs that the scheduler
313 * can keep track of at one time when creating block-ack chains of frames.
314 * Note that "64" matches the number of ack bits in a block-ack packet.
315 * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize
316 * IWL49_SCD_CONTEXT_QUEUE_OFFSET(x) values.
318 #define SCD_WIN_SIZE 64
319 #define SCD_FRAME_LIMIT 64
321 /* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */
322 #define IWL49_SCD_START_OFFSET 0xa02c00
325 * 4965 tells driver SRAM address for internal scheduler structs via this reg.
326 * Value is valid only after "Alive" response from uCode.
328 #define IWL49_SCD_SRAM_BASE_ADDR (IWL49_SCD_START_OFFSET + 0x0)
331 * Driver may need to update queue-empty bits after changing queue's
332 * write and read pointers (indexes) during (re-)initialization (i.e. when
333 * scheduler is not tracking what's happening).
335 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit
336 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty
337 * NOTE: This register is not used by Linux driver.
339 #define IWL49_SCD_EMPTY_BITS (IWL49_SCD_START_OFFSET + 0x4)
342 * Physical base address of array of byte count (BC) circular buffers (CBs).
343 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode.
344 * This register points to BC CB for queue 0, must be on 1024-byte boundary.
345 * Others are spaced by 1024 bytes.
346 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad.
347 * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff).
349 * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned.
351 #define IWL49_SCD_DRAM_BASE_ADDR (IWL49_SCD_START_OFFSET + 0x10)
354 * Enables any/all Tx DMA/FIFO channels.
355 * Scheduler generates requests for only the active channels.
356 * Set this to 0xff to enable all 8 channels (normal usage).
358 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7
360 #define IWL49_SCD_TXFACT (IWL49_SCD_START_OFFSET + 0x1c)
362 /* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */
363 #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
364 ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
367 * Queue (x) Write Pointers (indexes, really!), one for each Tx queue.
368 * Initialized and updated by driver as new TFDs are added to queue.
369 * NOTE: If using Block Ack, index must correspond to frame's
370 * Start Sequence Number; index = (SSN & 0xff)
371 * NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses?
373 #define IWL49_SCD_QUEUE_WRPTR(x) (IWL49_SCD_START_OFFSET + 0x24 + (x) * 4)
376 * Queue (x) Read Pointers (indexes, really!), one for each Tx queue.
377 * For FIFO mode, index indicates next frame to transmit.
378 * For Scheduler-ACK mode, index indicates first frame in Tx window.
379 * Initialized by driver, updated by scheduler.
381 #define IWL49_SCD_QUEUE_RDPTR(x) (IWL49_SCD_START_OFFSET + 0x64 + (x) * 4)
384 * Select which queues work in chain mode (1) vs. not (0).
385 * Use chain mode to build chains of aggregated frames.
388 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time
389 * NOTE: If driver sets up queue for chain mode, it should be also set up
390 * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x).
392 #define IWL49_SCD_QUEUECHAIN_SEL (IWL49_SCD_START_OFFSET + 0xd0)
395 * Select which queues interrupt driver when scheduler increments
396 * a queue's read pointer (index).
399 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled
400 * NOTE: This functionality is apparently a no-op; driver relies on interrupts
401 * from Rx queue to read Tx command responses and update Tx queues.
403 #define IWL49_SCD_INTERRUPT_MASK (IWL49_SCD_START_OFFSET + 0xe4)
406 * Queue search status registers. One for each queue.
407 * Sets up queue mode and assigns queue to Tx DMA channel.
409 * 19-10: Write mask/enable bits for bits 0-9
410 * 9: Driver should init to "0"
411 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).
412 * Driver should init to "1" for aggregation mode, or "0" otherwise.
413 * 7-6: Driver should init to "0"
414 * 5: Window Size Left; indicates whether scheduler can request
415 * another TFD, based on window size, etc. Driver should init
416 * this bit to "1" for aggregation mode, or "0" for non-agg.
417 * 4-1: Tx FIFO to use (range 0-7).
418 * 0: Queue is active (1), not active (0).
419 * Other bits should be written as "0"
421 * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled
422 * via SCD_QUEUECHAIN_SEL.
424 #define IWL49_SCD_QUEUE_STATUS_BITS(x)\
425 (IWL49_SCD_START_OFFSET + 0x104 + (x) * 4)
427 /* Bit field positions */
428 #define IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
429 #define IWL49_SCD_QUEUE_STTS_REG_POS_TXF (1)
430 #define IWL49_SCD_QUEUE_STTS_REG_POS_WSL (5)
431 #define IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)
434 #define IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)
435 #define IWL49_SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
438 * 4965 internal SRAM structures for scheduler, shared with driver ...
440 * Driver should clear and initialize the following areas after receiving
441 * "Alive" response from 4965 uCode, i.e. after initial
442 * uCode load, or after a uCode load done for error recovery:
444 * SCD_CONTEXT_DATA_OFFSET (size 128 bytes)
445 * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes)
446 * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes)
448 * Driver accesses SRAM via HBUS_TARG_MEM_* registers.
449 * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR.
450 * All OFFSET values must be added to this base address.
454 * Queue context. One 8-byte entry for each of 16 queues.
456 * Driver should clear this entire area (size 0x80) to 0 after receiving
457 * "Alive" notification from uCode. Additionally, driver should init
458 * each queue's entry as follows:
460 * LS Dword bit fields:
461 * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64.
463 * MS Dword bit fields:
464 * 16-22: Frame limit. Driver should init to 10 (0xa).
466 * Driver should init all other bits to 0.
468 * Init must be done after driver receives "Alive" response from 4965 uCode,
469 * and when setting up queue for aggregation.
471 #define IWL49_SCD_CONTEXT_DATA_OFFSET 0x380
472 #define IWL49_SCD_CONTEXT_QUEUE_OFFSET(x) \
473 (IWL49_SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
475 #define IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
476 #define IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
477 #define IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
478 #define IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
483 * Driver should clear this entire area (size 0x100) to 0 after receiving
484 * "Alive" notification from uCode. Area is used only by device itself;
485 * no other support (besides clearing) is required from driver.
487 #define IWL49_SCD_TX_STTS_BITMAP_OFFSET 0x400
490 * RAxTID to queue translation mapping.
492 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be
493 * for only one combination of receiver address (RA) and traffic ID (TID), i.e.
494 * one QOS priority level destined for one station (for this wireless link,
495 * not final destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit
496 * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK
497 * mode, the device ignores the mapping value.
499 * Bit fields, for each 16-bit map:
500 * 15-9: Reserved, set to 0
501 * 8-4: Index into device's station table for recipient station
502 * 3-0: Traffic ID (tid), range 0-15
504 * Driver should clear this entire area (size 32 bytes) to 0 after receiving
505 * "Alive" notification from uCode. To update a 16-bit map value, driver
506 * must read a dword-aligned value from device SRAM, replace the 16-bit map
507 * value of interest, and write the dword value back into device SRAM.
509 #define IWL49_SCD_TRANSLATE_TBL_OFFSET 0x500
511 /* Find translation table dword to read/write for given queue */
512 #define IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
513 ((IWL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
515 #define IWL49_SCD_TXFIFO_POS_TID (0)
516 #define IWL49_SCD_TXFIFO_POS_RA (4)
517 #define IWL49_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
520 #define IWL50_SCD_QUEUE_STTS_REG_POS_TXF (0)
521 #define IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
522 #define IWL50_SCD_QUEUE_STTS_REG_POS_WSL (4)
523 #define IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
524 #define IWL50_SCD_QUEUE_STTS_REG_MSK (0x00FF0000)
526 #define IWL50_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
527 #define IWL50_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
528 #define IWL50_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
529 #define IWL50_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
530 #define IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
531 #define IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
532 #define IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
533 #define IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
535 #define IWL50_SCD_CONTEXT_DATA_OFFSET (0x600)
536 #define IWL50_SCD_TX_STTS_BITMAP_OFFSET (0x7B1)
537 #define IWL50_SCD_TRANSLATE_TBL_OFFSET (0x7E0)
539 #define IWL50_SCD_CONTEXT_QUEUE_OFFSET(x)\
540 (IWL50_SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
542 #define IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
543 ((IWL50_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffc)
545 #define IWL50_SCD_QUEUECHAIN_SEL_ALL(x) (((1<<(x)) - 1) &\
546 (~(1<<IWL_CMD_QUEUE_NUM)))
548 #define IWL50_SCD_BASE (PRPH_BASE + 0xa02c00)
550 #define IWL50_SCD_SRAM_BASE_ADDR (IWL50_SCD_BASE + 0x0)
551 #define IWL50_SCD_DRAM_BASE_ADDR (IWL50_SCD_BASE + 0x8)
552 #define IWL50_SCD_AIT (IWL50_SCD_BASE + 0x0c)
553 #define IWL50_SCD_TXFACT (IWL50_SCD_BASE + 0x10)
554 #define IWL50_SCD_ACTIVE (IWL50_SCD_BASE + 0x14)
555 #define IWL50_SCD_QUEUE_WRPTR(x) (IWL50_SCD_BASE + 0x18 + (x) * 4)
556 #define IWL50_SCD_QUEUE_RDPTR(x) (IWL50_SCD_BASE + 0x68 + (x) * 4)
557 #define IWL50_SCD_QUEUECHAIN_SEL (IWL50_SCD_BASE + 0xe8)
558 #define IWL50_SCD_AGGR_SEL (IWL50_SCD_BASE + 0x248)
559 #define IWL50_SCD_INTERRUPT_MASK (IWL50_SCD_BASE + 0x108)
560 #define IWL50_SCD_QUEUE_STATUS_BITS(x) (IWL50_SCD_BASE + 0x10c + (x) * 4)
562 /*********************** END TX SCHEDULER *************************************/
564 #endif /* __iwl_prph_h__ */
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