1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/interrupt.h>
64 #include <linux/debugfs.h>
65 #include <linux/bitops.h>
66 #include <linux/gfp.h>
68 #include "iwl-trans.h"
69 #include "iwl-trans-pcie-int.h"
72 #include "iwl-shared.h"
73 #include "iwl-eeprom.h"
74 #include "iwl-agn-hw.h"
76 static int iwl_trans_rx_alloc(struct iwl_trans
*trans
)
78 struct iwl_trans_pcie
*trans_pcie
=
79 IWL_TRANS_GET_PCIE_TRANS(trans
);
80 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
81 struct device
*dev
= bus(trans
)->dev
;
83 memset(&trans_pcie
->rxq
, 0, sizeof(trans_pcie
->rxq
));
85 spin_lock_init(&rxq
->lock
);
87 if (WARN_ON(rxq
->bd
|| rxq
->rb_stts
))
90 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
91 rxq
->bd
= dma_alloc_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
92 &rxq
->bd_dma
, GFP_KERNEL
);
95 memset(rxq
->bd
, 0, sizeof(__le32
) * RX_QUEUE_SIZE
);
97 /*Allocate the driver's pointer to receive buffer status */
98 rxq
->rb_stts
= dma_alloc_coherent(dev
, sizeof(*rxq
->rb_stts
),
99 &rxq
->rb_stts_dma
, GFP_KERNEL
);
102 memset(rxq
->rb_stts
, 0, sizeof(*rxq
->rb_stts
));
107 dma_free_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
108 rxq
->bd
, rxq
->bd_dma
);
109 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
115 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans
*trans
)
117 struct iwl_trans_pcie
*trans_pcie
=
118 IWL_TRANS_GET_PCIE_TRANS(trans
);
119 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
122 /* Fill the rx_used queue with _all_ of the Rx buffers */
123 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
124 /* In the reset function, these buffers may have been allocated
125 * to an SKB, so we need to unmap and free potential storage */
126 if (rxq
->pool
[i
].page
!= NULL
) {
127 dma_unmap_page(bus(trans
)->dev
, rxq
->pool
[i
].page_dma
,
128 PAGE_SIZE
<< hw_params(trans
).rx_page_order
,
130 __free_pages(rxq
->pool
[i
].page
,
131 hw_params(trans
).rx_page_order
);
132 rxq
->pool
[i
].page
= NULL
;
134 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
138 static void iwl_trans_rx_hw_init(struct iwl_trans
*trans
,
139 struct iwl_rx_queue
*rxq
)
142 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
143 u32 rb_timeout
= RX_RB_TIMEOUT
; /* FIXME: RX_RB_TIMEOUT for all devices? */
145 if (iwlagn_mod_params
.amsdu_size_8K
)
146 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
148 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
151 iwl_write_direct32(bus(trans
), FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
153 /* Reset driver's Rx queue write index */
154 iwl_write_direct32(bus(trans
), FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
156 /* Tell device where to find RBD circular buffer in DRAM */
157 iwl_write_direct32(bus(trans
), FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
158 (u32
)(rxq
->bd_dma
>> 8));
160 /* Tell device where in DRAM to update its Rx status */
161 iwl_write_direct32(bus(trans
), FH_RSCSR_CHNL0_STTS_WPTR_REG
,
162 rxq
->rb_stts_dma
>> 4);
165 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
166 * the credit mechanism in 5000 HW RX FIFO
167 * Direct rx interrupts to hosts
168 * Rx buffer size 4 or 8k
172 iwl_write_direct32(bus(trans
), FH_MEM_RCSR_CHNL0_CONFIG_REG
,
173 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
174 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
175 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
176 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK
|
178 (rb_timeout
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
179 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
181 /* Set interrupt coalescing timer to default (2048 usecs) */
182 iwl_write8(bus(trans
), CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
185 static int iwl_rx_init(struct iwl_trans
*trans
)
187 struct iwl_trans_pcie
*trans_pcie
=
188 IWL_TRANS_GET_PCIE_TRANS(trans
);
189 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
195 err
= iwl_trans_rx_alloc(trans
);
200 spin_lock_irqsave(&rxq
->lock
, flags
);
201 INIT_LIST_HEAD(&rxq
->rx_free
);
202 INIT_LIST_HEAD(&rxq
->rx_used
);
204 iwl_trans_rxq_free_rx_bufs(trans
);
206 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
207 rxq
->queue
[i
] = NULL
;
209 /* Set us so that we have processed and used all buffers, but have
210 * not restocked the Rx queue with fresh buffers */
211 rxq
->read
= rxq
->write
= 0;
212 rxq
->write_actual
= 0;
214 spin_unlock_irqrestore(&rxq
->lock
, flags
);
216 iwlagn_rx_replenish(trans
);
218 iwl_trans_rx_hw_init(trans
, rxq
);
220 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
221 rxq
->need_update
= 1;
222 iwl_rx_queue_update_write_ptr(trans
, rxq
);
223 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
228 static void iwl_trans_pcie_rx_free(struct iwl_trans
*trans
)
230 struct iwl_trans_pcie
*trans_pcie
=
231 IWL_TRANS_GET_PCIE_TRANS(trans
);
232 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
236 /*if rxq->bd is NULL, it means that nothing has been allocated,
239 IWL_DEBUG_INFO(trans
, "Free NULL rx context\n");
243 spin_lock_irqsave(&rxq
->lock
, flags
);
244 iwl_trans_rxq_free_rx_bufs(trans
);
245 spin_unlock_irqrestore(&rxq
->lock
, flags
);
247 dma_free_coherent(bus(trans
)->dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
248 rxq
->bd
, rxq
->bd_dma
);
249 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
253 dma_free_coherent(bus(trans
)->dev
,
254 sizeof(struct iwl_rb_status
),
255 rxq
->rb_stts
, rxq
->rb_stts_dma
);
257 IWL_DEBUG_INFO(trans
, "Free rxq->rb_stts which is NULL\n");
258 memset(&rxq
->rb_stts_dma
, 0, sizeof(rxq
->rb_stts_dma
));
262 static int iwl_trans_rx_stop(struct iwl_trans
*trans
)
266 iwl_write_direct32(bus(trans
), FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
267 return iwl_poll_direct_bit(bus(trans
), FH_MEM_RSSR_RX_STATUS_REG
,
268 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
271 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans
*trans
,
272 struct iwl_dma_ptr
*ptr
, size_t size
)
274 if (WARN_ON(ptr
->addr
))
277 ptr
->addr
= dma_alloc_coherent(bus(trans
)->dev
, size
,
278 &ptr
->dma
, GFP_KERNEL
);
285 static inline void iwlagn_free_dma_ptr(struct iwl_trans
*trans
,
286 struct iwl_dma_ptr
*ptr
)
288 if (unlikely(!ptr
->addr
))
291 dma_free_coherent(bus(trans
)->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
292 memset(ptr
, 0, sizeof(*ptr
));
295 static int iwl_trans_txq_alloc(struct iwl_trans
*trans
,
296 struct iwl_tx_queue
*txq
, int slots_num
,
299 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
302 if (WARN_ON(txq
->meta
|| txq
->cmd
|| txq
->skbs
|| txq
->tfds
))
305 txq
->q
.n_window
= slots_num
;
307 txq
->meta
= kcalloc(slots_num
, sizeof(txq
->meta
[0]), GFP_KERNEL
);
308 txq
->cmd
= kcalloc(slots_num
, sizeof(txq
->cmd
[0]), GFP_KERNEL
);
310 if (!txq
->meta
|| !txq
->cmd
)
313 if (txq_id
== trans
->shrd
->cmd_queue
)
314 for (i
= 0; i
< slots_num
; i
++) {
315 txq
->cmd
[i
] = kmalloc(sizeof(struct iwl_device_cmd
),
321 /* Alloc driver data array and TFD circular buffer */
322 /* Driver private data, only for Tx (not command) queues,
323 * not shared with device. */
324 if (txq_id
!= trans
->shrd
->cmd_queue
) {
325 txq
->skbs
= kcalloc(TFD_QUEUE_SIZE_MAX
, sizeof(txq
->skbs
[0]),
328 IWL_ERR(trans
, "kmalloc for auxiliary BD "
329 "structures failed\n");
336 /* Circular buffer of transmit frame descriptors (TFDs),
337 * shared with device */
338 txq
->tfds
= dma_alloc_coherent(bus(trans
)->dev
, tfd_sz
,
339 &txq
->q
.dma_addr
, GFP_KERNEL
);
341 IWL_ERR(trans
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
350 /* since txq->cmd has been zeroed,
351 * all non allocated cmd[i] will be NULL */
352 if (txq
->cmd
&& txq_id
== trans
->shrd
->cmd_queue
)
353 for (i
= 0; i
< slots_num
; i
++)
364 static int iwl_trans_txq_init(struct iwl_trans
*trans
, struct iwl_tx_queue
*txq
,
365 int slots_num
, u32 txq_id
)
369 txq
->need_update
= 0;
370 memset(txq
->meta
, 0, sizeof(txq
->meta
[0]) * slots_num
);
373 * For the default queues 0-3, set up the swq_id
374 * already -- all others need to get one later
375 * (if they need one at all).
378 iwl_set_swq_id(txq
, txq_id
, txq_id
);
380 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
381 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
382 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
384 /* Initialize queue's high/low-water marks, and head/tail indexes */
385 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
391 * Tell nic where to find circular buffer of Tx Frame Descriptors for
392 * given Tx queue, and enable the DMA channel used for that queue.
393 * Circular buffer (TFD queue in DRAM) physical base address */
394 iwl_write_direct32(bus(trans
), FH_MEM_CBBC_QUEUE(txq_id
),
395 txq
->q
.dma_addr
>> 8);
401 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
403 static void iwl_tx_queue_unmap(struct iwl_trans
*trans
, int txq_id
)
405 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
406 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
407 struct iwl_queue
*q
= &txq
->q
;
408 enum dma_data_direction dma_dir
;
415 /* In the command queue, all the TBs are mapped as BIDI
416 * so unmap them as such.
418 if (txq_id
== trans
->shrd
->cmd_queue
) {
419 dma_dir
= DMA_BIDIRECTIONAL
;
420 lock
= &trans
->hcmd_lock
;
422 dma_dir
= DMA_TO_DEVICE
;
423 lock
= &trans
->shrd
->sta_lock
;
426 spin_lock_irqsave(lock
, flags
);
427 while (q
->write_ptr
!= q
->read_ptr
) {
428 /* The read_ptr needs to bound by q->n_window */
429 iwlagn_txq_free_tfd(trans
, txq
, get_cmd_index(q
, q
->read_ptr
),
431 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
433 spin_unlock_irqrestore(lock
, flags
);
437 * iwl_tx_queue_free - Deallocate DMA queue.
438 * @txq: Transmit queue to deallocate.
440 * Empty queue by removing and destroying all BD's.
442 * 0-fill, but do not free "txq" descriptor structure.
444 static void iwl_tx_queue_free(struct iwl_trans
*trans
, int txq_id
)
446 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
447 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
448 struct device
*dev
= bus(trans
)->dev
;
453 iwl_tx_queue_unmap(trans
, txq_id
);
455 /* De-alloc array of command/tx buffers */
457 if (txq_id
== trans
->shrd
->cmd_queue
)
458 for (i
= 0; i
< txq
->q
.n_window
; i
++)
461 /* De-alloc circular buffer of TFDs */
463 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
464 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
465 memset(&txq
->q
.dma_addr
, 0, sizeof(txq
->q
.dma_addr
));
468 /* De-alloc array of per-TFD driver data */
472 /* deallocate arrays */
478 /* 0-fill queue descriptor structure */
479 memset(txq
, 0, sizeof(*txq
));
483 * iwl_trans_tx_free - Free TXQ Context
485 * Destroy all TX DMA queues and structures
487 static void iwl_trans_pcie_tx_free(struct iwl_trans
*trans
)
490 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
493 if (trans_pcie
->txq
) {
495 txq_id
< hw_params(trans
).max_txq_num
; txq_id
++)
496 iwl_tx_queue_free(trans
, txq_id
);
499 kfree(trans_pcie
->txq
);
500 trans_pcie
->txq
= NULL
;
502 iwlagn_free_dma_ptr(trans
, &trans_pcie
->kw
);
504 iwlagn_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
508 * iwl_trans_tx_alloc - allocate TX context
509 * Allocate all Tx DMA structures and initialize them
514 static int iwl_trans_tx_alloc(struct iwl_trans
*trans
)
517 int txq_id
, slots_num
;
518 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
520 u16 scd_bc_tbls_size
= hw_params(trans
).max_txq_num
*
521 sizeof(struct iwlagn_scd_bc_tbl
);
523 /*It is not allowed to alloc twice, so warn when this happens.
524 * We cannot rely on the previous allocation, so free and fail */
525 if (WARN_ON(trans_pcie
->txq
)) {
530 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
533 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
537 /* Alloc keep-warm buffer */
538 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
540 IWL_ERR(trans
, "Keep Warm allocation failed\n");
544 trans_pcie
->txq
= kcalloc(hw_params(trans
).max_txq_num
,
545 sizeof(struct iwl_tx_queue
), GFP_KERNEL
);
546 if (!trans_pcie
->txq
) {
547 IWL_ERR(trans
, "Not enough memory for txq\n");
552 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
553 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++) {
554 slots_num
= (txq_id
== trans
->shrd
->cmd_queue
) ?
555 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
556 ret
= iwl_trans_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
559 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
567 iwl_trans_pcie_tx_free(trans
);
571 static int iwl_tx_init(struct iwl_trans
*trans
)
574 int txq_id
, slots_num
;
577 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
579 if (!trans_pcie
->txq
) {
580 ret
= iwl_trans_tx_alloc(trans
);
586 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
588 /* Turn off all Tx DMA fifos */
589 iwl_write_prph(bus(trans
), SCD_TXFACT
, 0);
591 /* Tell NIC where to find the "keep warm" buffer */
592 iwl_write_direct32(bus(trans
), FH_KW_MEM_ADDR_REG
,
593 trans_pcie
->kw
.dma
>> 4);
595 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
597 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
598 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++) {
599 slots_num
= (txq_id
== trans
->shrd
->cmd_queue
) ?
600 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
601 ret
= iwl_trans_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
604 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
611 /*Upon error, free only if we allocated something */
613 iwl_trans_pcie_tx_free(trans
);
617 static void iwl_set_pwr_vmain(struct iwl_trans
*trans
)
620 * (for documentation purposes)
621 * to set power to V_AUX, do:
623 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
624 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
625 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
626 ~APMG_PS_CTRL_MSK_PWR_SRC);
629 iwl_set_bits_mask_prph(bus(trans
), APMG_PS_CTRL_REG
,
630 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
631 ~APMG_PS_CTRL_MSK_PWR_SRC
);
634 static int iwl_nic_init(struct iwl_trans
*trans
)
639 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
640 iwl_apm_init(priv(trans
));
642 /* Set interrupt coalescing calibration timer to default (512 usecs) */
643 iwl_write8(bus(trans
), CSR_INT_COALESCING
,
644 IWL_HOST_INT_CALIB_TIMEOUT_DEF
);
646 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
648 iwl_set_pwr_vmain(trans
);
650 iwl_nic_config(priv(trans
));
652 /* Allocate the RX queue, or reset if it is already allocated */
655 /* Allocate or reset and init all Tx and Command queues */
656 if (iwl_tx_init(trans
))
659 if (hw_params(trans
).shadow_reg_enable
) {
660 /* enable shadow regs in HW */
661 iwl_set_bit(bus(trans
), CSR_MAC_SHADOW_REG_CTRL
,
665 set_bit(STATUS_INIT
, &trans
->shrd
->status
);
670 #define HW_READY_TIMEOUT (50)
672 /* Note: returns poll_bit return value, which is >= 0 if success */
673 static int iwl_set_hw_ready(struct iwl_trans
*trans
)
677 iwl_set_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
678 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
680 /* See if we got it */
681 ret
= iwl_poll_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
682 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
683 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
686 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
690 /* Note: returns standard 0/-ERROR code */
691 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans
*trans
)
695 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
697 ret
= iwl_set_hw_ready(trans
);
701 /* If HW is not ready, prepare the conditions to check again */
702 iwl_set_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
703 CSR_HW_IF_CONFIG_REG_PREPARE
);
705 ret
= iwl_poll_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
706 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
,
707 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
, 150000);
712 /* HW should be ready by now, check again. */
713 ret
= iwl_set_hw_ready(trans
);
719 #define IWL_AC_UNSET -1
721 struct queue_to_fifo_ac
{
725 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo
[] = {
726 { IWL_TX_FIFO_VO
, IEEE80211_AC_VO
, },
727 { IWL_TX_FIFO_VI
, IEEE80211_AC_VI
, },
728 { IWL_TX_FIFO_BE
, IEEE80211_AC_BE
, },
729 { IWL_TX_FIFO_BK
, IEEE80211_AC_BK
, },
730 { IWLAGN_CMD_FIFO_NUM
, IWL_AC_UNSET
, },
731 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
732 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
733 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
734 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
735 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
736 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
739 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo
[] = {
740 { IWL_TX_FIFO_VO
, IEEE80211_AC_VO
, },
741 { IWL_TX_FIFO_VI
, IEEE80211_AC_VI
, },
742 { IWL_TX_FIFO_BE
, IEEE80211_AC_BE
, },
743 { IWL_TX_FIFO_BK
, IEEE80211_AC_BK
, },
744 { IWL_TX_FIFO_BK_IPAN
, IEEE80211_AC_BK
, },
745 { IWL_TX_FIFO_BE_IPAN
, IEEE80211_AC_BE
, },
746 { IWL_TX_FIFO_VI_IPAN
, IEEE80211_AC_VI
, },
747 { IWL_TX_FIFO_VO_IPAN
, IEEE80211_AC_VO
, },
748 { IWL_TX_FIFO_BE_IPAN
, 2, },
749 { IWLAGN_CMD_FIFO_NUM
, IWL_AC_UNSET
, },
750 { IWL_TX_FIFO_AUX
, IWL_AC_UNSET
, },
753 static const u8 iwlagn_bss_ac_to_fifo
[] = {
759 static const u8 iwlagn_bss_ac_to_queue
[] = {
762 static const u8 iwlagn_pan_ac_to_fifo
[] = {
768 static const u8 iwlagn_pan_ac_to_queue
[] = {
772 static int iwl_trans_pcie_start_device(struct iwl_trans
*trans
)
775 struct iwl_trans_pcie
*trans_pcie
=
776 IWL_TRANS_GET_PCIE_TRANS(trans
);
778 trans
->shrd
->ucode_owner
= IWL_OWNERSHIP_DRIVER
;
779 trans_pcie
->ac_to_queue
[IWL_RXON_CTX_BSS
] = iwlagn_bss_ac_to_queue
;
780 trans_pcie
->ac_to_queue
[IWL_RXON_CTX_PAN
] = iwlagn_pan_ac_to_queue
;
782 trans_pcie
->ac_to_fifo
[IWL_RXON_CTX_BSS
] = iwlagn_bss_ac_to_fifo
;
783 trans_pcie
->ac_to_fifo
[IWL_RXON_CTX_PAN
] = iwlagn_pan_ac_to_fifo
;
785 trans_pcie
->mcast_queue
[IWL_RXON_CTX_BSS
] = 0;
786 trans_pcie
->mcast_queue
[IWL_RXON_CTX_PAN
] = IWL_IPAN_MCAST_QUEUE
;
788 if ((hw_params(trans
).sku
& EEPROM_SKU_CAP_AMT_ENABLE
) &&
789 iwl_trans_pcie_prepare_card_hw(trans
)) {
790 IWL_WARN(trans
, "Exit HW not ready\n");
794 /* If platform's RF_KILL switch is NOT set to KILL */
795 if (iwl_read32(bus(trans
), CSR_GP_CNTRL
) &
796 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
)
797 clear_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
799 set_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
801 if (iwl_is_rfkill(trans
->shrd
)) {
802 iwl_set_hw_rfkill_state(priv(trans
), true);
803 iwl_enable_interrupts(trans
);
807 iwl_write32(bus(trans
), CSR_INT
, 0xFFFFFFFF);
809 ret
= iwl_nic_init(trans
);
811 IWL_ERR(trans
, "Unable to init nic\n");
815 /* make sure rfkill handshake bits are cleared */
816 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
817 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
,
818 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
820 /* clear (again), then enable host interrupts */
821 iwl_write32(bus(trans
), CSR_INT
, 0xFFFFFFFF);
822 iwl_enable_interrupts(trans
);
824 /* really make sure rfkill handshake bits are cleared */
825 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
826 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
832 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
833 * must be called under priv->shrd->lock and mac access
835 static void iwl_trans_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
837 iwl_write_prph(bus(trans
), SCD_TXFACT
, mask
);
840 static void iwl_trans_pcie_tx_start(struct iwl_trans
*trans
)
842 const struct queue_to_fifo_ac
*queue_to_fifo
;
843 struct iwl_trans_pcie
*trans_pcie
=
844 IWL_TRANS_GET_PCIE_TRANS(trans
);
850 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
852 trans_pcie
->scd_base_addr
=
853 iwl_read_prph(bus(trans
), SCD_SRAM_BASE_ADDR
);
854 a
= trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_LOWER_BOUND
;
855 /* reset conext data memory */
856 for (; a
< trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_UPPER_BOUND
;
858 iwl_write_targ_mem(bus(trans
), a
, 0);
859 /* reset tx status memory */
860 for (; a
< trans_pcie
->scd_base_addr
+ SCD_TX_STTS_MEM_UPPER_BOUND
;
862 iwl_write_targ_mem(bus(trans
), a
, 0);
863 for (; a
< trans_pcie
->scd_base_addr
+
864 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans
).max_txq_num
);
866 iwl_write_targ_mem(bus(trans
), a
, 0);
868 iwl_write_prph(bus(trans
), SCD_DRAM_BASE_ADDR
,
869 trans_pcie
->scd_bc_tbls
.dma
>> 10);
871 /* Enable DMA channel */
872 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
873 iwl_write_direct32(bus(trans
), FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
874 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
875 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
877 /* Update FH chicken bits */
878 reg_val
= iwl_read_direct32(bus(trans
), FH_TX_CHICKEN_BITS_REG
);
879 iwl_write_direct32(bus(trans
), FH_TX_CHICKEN_BITS_REG
,
880 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
882 iwl_write_prph(bus(trans
), SCD_QUEUECHAIN_SEL
,
883 SCD_QUEUECHAIN_SEL_ALL(trans
));
884 iwl_write_prph(bus(trans
), SCD_AGGR_SEL
, 0);
886 /* initiate the queues */
887 for (i
= 0; i
< hw_params(trans
).max_txq_num
; i
++) {
888 iwl_write_prph(bus(trans
), SCD_QUEUE_RDPTR(i
), 0);
889 iwl_write_direct32(bus(trans
), HBUS_TARG_WRPTR
, 0 | (i
<< 8));
890 iwl_write_targ_mem(bus(trans
), trans_pcie
->scd_base_addr
+
891 SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
892 iwl_write_targ_mem(bus(trans
), trans_pcie
->scd_base_addr
+
893 SCD_CONTEXT_QUEUE_OFFSET(i
) +
896 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
897 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
899 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
900 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
903 iwl_write_prph(bus(trans
), SCD_INTERRUPT_MASK
,
904 IWL_MASK(0, hw_params(trans
).max_txq_num
));
906 /* Activate all Tx DMA/FIFO channels */
907 iwl_trans_txq_set_sched(trans
, IWL_MASK(0, 7));
909 /* map queues to FIFOs */
910 if (trans
->shrd
->valid_contexts
!= BIT(IWL_RXON_CTX_BSS
))
911 queue_to_fifo
= iwlagn_ipan_queue_to_tx_fifo
;
913 queue_to_fifo
= iwlagn_default_queue_to_tx_fifo
;
915 iwl_trans_set_wr_ptrs(trans
, trans
->shrd
->cmd_queue
, 0);
917 /* make sure all queue are not stopped */
918 memset(&trans_pcie
->queue_stopped
[0], 0,
919 sizeof(trans_pcie
->queue_stopped
));
920 for (i
= 0; i
< 4; i
++)
921 atomic_set(&trans_pcie
->queue_stop_count
[i
], 0);
923 /* reset to 0 to enable all the queue first */
924 trans_pcie
->txq_ctx_active_msk
= 0;
926 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo
) <
927 IWLAGN_FIRST_AMPDU_QUEUE
);
928 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo
) <
929 IWLAGN_FIRST_AMPDU_QUEUE
);
931 for (i
= 0; i
< IWLAGN_FIRST_AMPDU_QUEUE
; i
++) {
932 int fifo
= queue_to_fifo
[i
].fifo
;
933 int ac
= queue_to_fifo
[i
].ac
;
935 iwl_txq_ctx_activate(trans_pcie
, i
);
937 if (fifo
== IWL_TX_FIFO_UNUSED
)
940 if (ac
!= IWL_AC_UNSET
)
941 iwl_set_swq_id(&trans_pcie
->txq
[i
], ac
, i
);
942 iwl_trans_tx_queue_set_status(trans
, &trans_pcie
->txq
[i
],
946 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
948 /* Enable L1-Active */
949 iwl_clear_bits_prph(bus(trans
), APMG_PCIDEV_STT_REG
,
950 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
954 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
956 static int iwl_trans_tx_stop(struct iwl_trans
*trans
)
960 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
962 /* Turn off all Tx DMA fifos */
963 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
965 iwl_trans_txq_set_sched(trans
, 0);
967 /* Stop each Tx DMA channel, and wait for it to be idle */
968 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
969 iwl_write_direct32(bus(trans
),
970 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
971 if (iwl_poll_direct_bit(bus(trans
), FH_TSSR_TX_STATUS_REG
,
972 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
974 IWL_ERR(trans
, "Failing on timeout while stopping"
975 " DMA channel %d [0x%08x]", ch
,
976 iwl_read_direct32(bus(trans
),
977 FH_TSSR_TX_STATUS_REG
));
979 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
981 if (!trans_pcie
->txq
) {
982 IWL_WARN(trans
, "Stopping tx queues that aren't allocated...");
986 /* Unmap DMA from host system and free skb's */
987 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++)
988 iwl_tx_queue_unmap(trans
, txq_id
);
993 static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans
*trans
)
996 struct iwl_trans_pcie
*trans_pcie
=
997 IWL_TRANS_GET_PCIE_TRANS(trans
);
999 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
1000 iwl_disable_interrupts(trans
);
1001 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
1003 /* wait to make sure we flush pending tasklet*/
1004 synchronize_irq(bus(trans
)->irq
);
1005 tasklet_kill(&trans_pcie
->irq_tasklet
);
1008 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
1010 /* stop and reset the on-board processor */
1011 iwl_write32(bus(trans
), CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
1013 /* tell the device to stop sending interrupts */
1014 iwl_trans_pcie_disable_sync_irq(trans
);
1016 /* device going down, Stop using ICT table */
1017 iwl_disable_ict(trans
);
1020 * If a HW restart happens during firmware loading,
1021 * then the firmware loading might call this function
1022 * and later it might be called again due to the
1023 * restart. So don't process again if the device is
1026 if (test_bit(STATUS_DEVICE_ENABLED
, &trans
->shrd
->status
)) {
1027 iwl_trans_tx_stop(trans
);
1028 iwl_trans_rx_stop(trans
);
1030 /* Power-down device's busmaster DMA clocks */
1031 iwl_write_prph(bus(trans
), APMG_CLK_DIS_REG
,
1032 APMG_CLK_VAL_DMA_CLK_RQT
);
1036 /* Make sure (redundant) we've released our request to stay awake */
1037 iwl_clear_bit(bus(trans
), CSR_GP_CNTRL
,
1038 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1040 /* Stop the device, and put it in low power state */
1041 iwl_apm_stop(priv(trans
));
1044 static int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1045 struct iwl_device_cmd
*dev_cmd
, enum iwl_rxon_context_id ctx
,
1048 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1049 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1050 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1051 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*) dev_cmd
->payload
;
1052 struct iwl_cmd_meta
*out_meta
;
1053 struct iwl_tx_queue
*txq
;
1054 struct iwl_queue
*q
;
1056 dma_addr_t phys_addr
= 0;
1057 dma_addr_t txcmd_phys
;
1058 dma_addr_t scratch_phys
;
1059 u16 len
, firstlen
, secondlen
;
1061 u8 wait_write_ptr
= 0;
1064 bool is_agg
= false;
1065 __le16 fc
= hdr
->frame_control
;
1066 u8 hdr_len
= ieee80211_hdrlen(fc
);
1069 * Send this frame after DTIM -- there's a special queue
1070 * reserved for this for contexts that support AP mode.
1072 if (info
->flags
& IEEE80211_TX_CTL_SEND_AFTER_DTIM
) {
1073 txq_id
= trans_pcie
->mcast_queue
[ctx
];
1076 * The microcode will clear the more data
1077 * bit in the last frame it transmits.
1079 hdr
->frame_control
|=
1080 cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
1081 } else if (info
->flags
& IEEE80211_TX_CTL_TX_OFFCHAN
)
1082 txq_id
= IWL_AUX_QUEUE
;
1085 trans_pcie
->ac_to_queue
[ctx
][skb_get_queue_mapping(skb
)];
1087 if (ieee80211_is_data_qos(fc
) && !ieee80211_is_qos_nullfunc(fc
)) {
1089 struct iwl_tid_data
*tid_data
;
1090 qc
= ieee80211_get_qos_ctl(hdr
);
1091 tid
= qc
[0] & IEEE80211_QOS_CTL_TID_MASK
;
1092 tid_data
= &trans
->shrd
->tid_data
[sta_id
][tid
];
1094 if (WARN_ON_ONCE(tid
>= IWL_MAX_TID_COUNT
))
1097 seq_number
= tid_data
->seq_number
;
1098 seq_number
&= IEEE80211_SCTL_SEQ
;
1099 hdr
->seq_ctrl
= hdr
->seq_ctrl
&
1100 cpu_to_le16(IEEE80211_SCTL_FRAG
);
1101 hdr
->seq_ctrl
|= cpu_to_le16(seq_number
);
1103 /* aggregation is on for this <sta,tid> */
1104 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
1105 WARN_ON_ONCE(tid_data
->agg
.state
!= IWL_AGG_ON
);
1106 txq_id
= tid_data
->agg
.txq_id
;
1111 /* Copy MAC header from skb into command buffer */
1112 memcpy(tx_cmd
->hdr
, hdr
, hdr_len
);
1114 txq
= &trans_pcie
->txq
[txq_id
];
1117 /* Set up driver data for this TFD */
1118 txq
->skbs
[q
->write_ptr
] = skb
;
1119 txq
->cmd
[q
->write_ptr
] = dev_cmd
;
1121 dev_cmd
->hdr
.cmd
= REPLY_TX
;
1122 dev_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1123 INDEX_TO_SEQ(q
->write_ptr
)));
1125 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1126 out_meta
= &txq
->meta
[q
->write_ptr
];
1129 * Use the first empty entry in this queue's command buffer array
1130 * to contain the Tx command and MAC header concatenated together
1131 * (payload data will be in another buffer).
1132 * Size of this varies, due to varying MAC header length.
1133 * If end is not dword aligned, we'll have 2 extra bytes at the end
1134 * of the MAC header (device reads on dword boundaries).
1135 * We'll tell device about this padding later.
1137 len
= sizeof(struct iwl_tx_cmd
) +
1138 sizeof(struct iwl_cmd_header
) + hdr_len
;
1139 firstlen
= (len
+ 3) & ~3;
1141 /* Tell NIC about any 2-byte padding after MAC header */
1142 if (firstlen
!= len
)
1143 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1145 /* Physical address of this Tx command's header (not MAC header!),
1146 * within command buffer array. */
1147 txcmd_phys
= dma_map_single(bus(trans
)->dev
,
1148 &dev_cmd
->hdr
, firstlen
,
1150 if (unlikely(dma_mapping_error(bus(trans
)->dev
, txcmd_phys
)))
1152 dma_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
1153 dma_unmap_len_set(out_meta
, len
, firstlen
);
1155 if (!ieee80211_has_morefrags(fc
)) {
1156 txq
->need_update
= 1;
1159 txq
->need_update
= 0;
1162 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1163 * if any (802.11 null frames have no payload). */
1164 secondlen
= skb
->len
- hdr_len
;
1165 if (secondlen
> 0) {
1166 phys_addr
= dma_map_single(bus(trans
)->dev
, skb
->data
+ hdr_len
,
1167 secondlen
, DMA_TO_DEVICE
);
1168 if (unlikely(dma_mapping_error(bus(trans
)->dev
, phys_addr
))) {
1169 dma_unmap_single(bus(trans
)->dev
,
1170 dma_unmap_addr(out_meta
, mapping
),
1171 dma_unmap_len(out_meta
, len
),
1177 /* Attach buffers to TFD */
1178 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, txcmd_phys
, firstlen
, 1);
1180 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, phys_addr
,
1183 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
1184 offsetof(struct iwl_tx_cmd
, scratch
);
1186 /* take back ownership of DMA buffer to enable update */
1187 dma_sync_single_for_cpu(bus(trans
)->dev
, txcmd_phys
, firstlen
,
1189 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1190 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1192 IWL_DEBUG_TX(trans
, "sequence nr = 0X%x\n",
1193 le16_to_cpu(dev_cmd
->hdr
.sequence
));
1194 IWL_DEBUG_TX(trans
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
1195 iwl_print_hex_dump(trans
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
1196 iwl_print_hex_dump(trans
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
1198 /* Set up entry for this TFD in Tx byte-count array */
1200 iwl_trans_txq_update_byte_cnt_tbl(trans
, txq
,
1201 le16_to_cpu(tx_cmd
->len
));
1203 dma_sync_single_for_device(bus(trans
)->dev
, txcmd_phys
, firstlen
,
1206 trace_iwlwifi_dev_tx(priv(trans
),
1207 &((struct iwl_tfd
*)txq
->tfds
)[txq
->q
.write_ptr
],
1208 sizeof(struct iwl_tfd
),
1209 &dev_cmd
->hdr
, firstlen
,
1210 skb
->data
+ hdr_len
, secondlen
);
1212 /* Tell device the write index *just past* this latest filled TFD */
1213 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1214 iwl_txq_update_write_ptr(trans
, txq
);
1216 if (ieee80211_is_data_qos(fc
) && !ieee80211_is_qos_nullfunc(fc
)) {
1217 trans
->shrd
->tid_data
[sta_id
][tid
].tfds_in_queue
++;
1218 if (!ieee80211_has_morefrags(fc
))
1219 trans
->shrd
->tid_data
[sta_id
][tid
].seq_number
=
1224 * At this point the frame is "transmitted" successfully
1225 * and we will get a TX status notification eventually,
1226 * regardless of the value of ret. "ret" only indicates
1227 * whether or not we should update the write pointer.
1229 if (iwl_queue_space(q
) < q
->high_mark
) {
1230 if (wait_write_ptr
) {
1231 txq
->need_update
= 1;
1232 iwl_txq_update_write_ptr(trans
, txq
);
1234 iwl_stop_queue(trans
, txq
);
1240 static void iwl_trans_pcie_kick_nic(struct iwl_trans
*trans
)
1242 /* Remove all resets to allow NIC to operate */
1243 iwl_write32(bus(trans
), CSR_RESET
, 0);
1246 static int iwl_trans_pcie_request_irq(struct iwl_trans
*trans
)
1248 struct iwl_trans_pcie
*trans_pcie
=
1249 IWL_TRANS_GET_PCIE_TRANS(trans
);
1252 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
1254 tasklet_init(&trans_pcie
->irq_tasklet
, (void (*)(unsigned long))
1255 iwl_irq_tasklet
, (unsigned long)trans
);
1257 iwl_alloc_isr_ict(trans
);
1259 err
= request_irq(bus(trans
)->irq
, iwl_isr_ict
, IRQF_SHARED
,
1262 IWL_ERR(trans
, "Error allocating IRQ %d\n", bus(trans
)->irq
);
1263 iwl_free_isr_ict(trans
);
1267 INIT_WORK(&trans_pcie
->rx_replenish
, iwl_bg_rx_replenish
);
1271 static int iwlagn_txq_check_empty(struct iwl_trans
*trans
,
1272 int sta_id
, u8 tid
, int txq_id
)
1274 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1275 struct iwl_queue
*q
= &trans_pcie
->txq
[txq_id
].q
;
1276 struct iwl_tid_data
*tid_data
= &trans
->shrd
->tid_data
[sta_id
][tid
];
1278 lockdep_assert_held(&trans
->shrd
->sta_lock
);
1280 switch (trans
->shrd
->tid_data
[sta_id
][tid
].agg
.state
) {
1281 case IWL_EMPTYING_HW_QUEUE_DELBA
:
1282 /* We are reclaiming the last packet of the */
1283 /* aggregated HW queue */
1284 if ((txq_id
== tid_data
->agg
.txq_id
) &&
1285 (q
->read_ptr
== q
->write_ptr
)) {
1287 "HW queue empty: continue DELBA flow\n");
1288 iwl_trans_pcie_txq_agg_disable(trans
, txq_id
);
1289 tid_data
->agg
.state
= IWL_AGG_OFF
;
1290 iwl_stop_tx_ba_trans_ready(priv(trans
),
1293 iwl_wake_queue(trans
, &trans_pcie
->txq
[txq_id
]);
1296 case IWL_EMPTYING_HW_QUEUE_ADDBA
:
1297 /* We are reclaiming the last packet of the queue */
1298 if (tid_data
->tfds_in_queue
== 0) {
1300 "HW queue empty: continue ADDBA flow\n");
1301 tid_data
->agg
.state
= IWL_AGG_ON
;
1302 iwl_start_tx_ba_trans_ready(priv(trans
),
1314 static void iwl_free_tfds_in_queue(struct iwl_trans
*trans
,
1315 int sta_id
, int tid
, int freed
)
1317 lockdep_assert_held(&trans
->shrd
->sta_lock
);
1319 if (trans
->shrd
->tid_data
[sta_id
][tid
].tfds_in_queue
>= freed
)
1320 trans
->shrd
->tid_data
[sta_id
][tid
].tfds_in_queue
-= freed
;
1322 IWL_DEBUG_TX(trans
, "free more than tfds_in_queue (%u:%d)\n",
1323 trans
->shrd
->tid_data
[sta_id
][tid
].tfds_in_queue
,
1325 trans
->shrd
->tid_data
[sta_id
][tid
].tfds_in_queue
= 0;
1329 static void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int sta_id
, int tid
,
1330 int txq_id
, int ssn
, u32 status
,
1331 struct sk_buff_head
*skbs
)
1333 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1334 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
1335 enum iwl_agg_state agg_state
;
1336 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1337 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
1341 txq
->time_stamp
= jiffies
;
1343 if (txq
->sched_retry
) {
1345 trans
->shrd
->tid_data
[txq
->sta_id
][txq
->tid
].agg
.state
;
1346 cond
= (agg_state
!= IWL_EMPTYING_HW_QUEUE_DELBA
);
1348 cond
= (status
!= TX_STATUS_FAIL_PASSIVE_NO_RX
);
1351 if (txq
->q
.read_ptr
!= tfd_num
) {
1352 IWL_DEBUG_TX_REPLY(trans
, "Retry scheduler reclaim "
1353 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1354 ssn
, tfd_num
, txq_id
, txq
->swq_id
);
1355 freed
= iwl_tx_queue_reclaim(trans
, txq_id
, tfd_num
, skbs
);
1356 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
&& cond
)
1357 iwl_wake_queue(trans
, txq
);
1360 iwl_free_tfds_in_queue(trans
, sta_id
, tid
, freed
);
1361 iwlagn_txq_check_empty(trans
, sta_id
, tid
, txq_id
);
1364 static void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1366 iwl_trans_pcie_tx_free(trans
);
1367 iwl_trans_pcie_rx_free(trans
);
1368 free_irq(bus(trans
)->irq
, trans
);
1369 iwl_free_isr_ict(trans
);
1370 trans
->shrd
->trans
= NULL
;
1374 #ifdef CONFIG_PM_SLEEP
1375 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
1378 * This function is called when system goes into suspend state
1379 * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1380 * function first but since iwlagn_mac_stop() has no knowledge of
1381 * who the caller is,
1382 * it will not call apm_ops.stop() to stop the DMA operation.
1383 * Calling apm_ops.stop here to make sure we stop the DMA.
1385 * But of course ... if we have configured WoWLAN then we did other
1386 * things already :-)
1388 if (!trans
->shrd
->wowlan
) {
1389 iwl_apm_stop(priv(trans
));
1391 iwl_disable_interrupts(trans
);
1392 iwl_clear_bit(bus(trans
), CSR_GP_CNTRL
,
1393 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1399 static int iwl_trans_pcie_resume(struct iwl_trans
*trans
)
1401 bool hw_rfkill
= false;
1403 iwl_enable_interrupts(trans
);
1405 if (!(iwl_read32(bus(trans
), CSR_GP_CNTRL
) &
1406 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
))
1410 set_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
1412 clear_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
1414 iwl_set_hw_rfkill_state(priv(trans
), hw_rfkill
);
1418 #endif /* CONFIG_PM_SLEEP */
1420 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans
*trans
,
1421 enum iwl_rxon_context_id ctx
)
1424 struct iwl_trans_pcie
*trans_pcie
=
1425 IWL_TRANS_GET_PCIE_TRANS(trans
);
1427 for (ac
= 0; ac
< AC_NUM
; ac
++) {
1428 txq_id
= trans_pcie
->ac_to_queue
[ctx
][ac
];
1429 IWL_DEBUG_INFO(trans
, "Queue Status: Q[%d] %s\n",
1431 (atomic_read(&trans_pcie
->queue_stop_count
[ac
]) > 0)
1432 ? "stopped" : "awake");
1433 iwl_wake_queue(trans
, &trans_pcie
->txq
[txq_id
]);
1437 const struct iwl_trans_ops trans_ops_pcie
;
1439 static struct iwl_trans
*iwl_trans_pcie_alloc(struct iwl_shared
*shrd
)
1441 struct iwl_trans
*iwl_trans
= kzalloc(sizeof(struct iwl_trans
) +
1442 sizeof(struct iwl_trans_pcie
),
1445 struct iwl_trans_pcie
*trans_pcie
=
1446 IWL_TRANS_GET_PCIE_TRANS(iwl_trans
);
1447 iwl_trans
->ops
= &trans_ops_pcie
;
1448 iwl_trans
->shrd
= shrd
;
1449 trans_pcie
->trans
= iwl_trans
;
1450 spin_lock_init(&iwl_trans
->hcmd_lock
);
1456 static void iwl_trans_pcie_stop_queue(struct iwl_trans
*trans
, int txq_id
)
1458 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1460 iwl_stop_queue(trans
, &trans_pcie
->txq
[txq_id
]);
1463 #define IWL_FLUSH_WAIT_MS 2000
1465 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans
*trans
)
1467 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1468 struct iwl_tx_queue
*txq
;
1469 struct iwl_queue
*q
;
1471 unsigned long now
= jiffies
;
1474 /* waiting for all the tx frames complete might take a while */
1475 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1476 if (cnt
== trans
->shrd
->cmd_queue
)
1478 txq
= &trans_pcie
->txq
[cnt
];
1480 while (q
->read_ptr
!= q
->write_ptr
&& !time_after(jiffies
,
1481 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
)))
1484 if (q
->read_ptr
!= q
->write_ptr
) {
1485 IWL_ERR(trans
, "fail to flush all tx fifo queues\n");
1494 * On every watchdog tick we check (latest) time stamp. If it does not
1495 * change during timeout period and queue is not empty we reset firmware.
1497 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans
*trans
, int cnt
)
1499 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1500 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[cnt
];
1501 struct iwl_queue
*q
= &txq
->q
;
1502 unsigned long timeout
;
1504 if (q
->read_ptr
== q
->write_ptr
) {
1505 txq
->time_stamp
= jiffies
;
1509 timeout
= txq
->time_stamp
+
1510 msecs_to_jiffies(hw_params(trans
).wd_timeout
);
1512 if (time_after(jiffies
, timeout
)) {
1513 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", q
->id
,
1514 hw_params(trans
).wd_timeout
);
1515 IWL_ERR(trans
, "Current read_ptr %d write_ptr %d\n",
1516 q
->read_ptr
, q
->write_ptr
);
1523 static const char *get_fh_string(int cmd
)
1526 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG
);
1527 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG
);
1528 IWL_CMD(FH_RSCSR_CHNL0_WPTR
);
1529 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG
);
1530 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG
);
1531 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG
);
1532 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
);
1533 IWL_CMD(FH_TSSR_TX_STATUS_REG
);
1534 IWL_CMD(FH_TSSR_TX_ERROR_REG
);
1540 int iwl_dump_fh(struct iwl_trans
*trans
, char **buf
, bool display
)
1543 #ifdef CONFIG_IWLWIFI_DEBUG
1547 static const u32 fh_tbl
[] = {
1548 FH_RSCSR_CHNL0_STTS_WPTR_REG
,
1549 FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
1550 FH_RSCSR_CHNL0_WPTR
,
1551 FH_MEM_RCSR_CHNL0_CONFIG_REG
,
1552 FH_MEM_RSSR_SHARED_CTRL_REG
,
1553 FH_MEM_RSSR_RX_STATUS_REG
,
1554 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
,
1555 FH_TSSR_TX_STATUS_REG
,
1556 FH_TSSR_TX_ERROR_REG
1558 #ifdef CONFIG_IWLWIFI_DEBUG
1560 bufsz
= ARRAY_SIZE(fh_tbl
) * 48 + 40;
1561 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
1564 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1565 "FH register values:\n");
1566 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
1567 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1569 get_fh_string(fh_tbl
[i
]),
1570 iwl_read_direct32(bus(trans
), fh_tbl
[i
]));
1575 IWL_ERR(trans
, "FH register values:\n");
1576 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
1577 IWL_ERR(trans
, " %34s: 0X%08x\n",
1578 get_fh_string(fh_tbl
[i
]),
1579 iwl_read_direct32(bus(trans
), fh_tbl
[i
]));
1584 static const char *get_csr_string(int cmd
)
1587 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1588 IWL_CMD(CSR_INT_COALESCING
);
1590 IWL_CMD(CSR_INT_MASK
);
1591 IWL_CMD(CSR_FH_INT_STATUS
);
1592 IWL_CMD(CSR_GPIO_IN
);
1594 IWL_CMD(CSR_GP_CNTRL
);
1595 IWL_CMD(CSR_HW_REV
);
1596 IWL_CMD(CSR_EEPROM_REG
);
1597 IWL_CMD(CSR_EEPROM_GP
);
1598 IWL_CMD(CSR_OTP_GP_REG
);
1599 IWL_CMD(CSR_GIO_REG
);
1600 IWL_CMD(CSR_GP_UCODE_REG
);
1601 IWL_CMD(CSR_GP_DRIVER_REG
);
1602 IWL_CMD(CSR_UCODE_DRV_GP1
);
1603 IWL_CMD(CSR_UCODE_DRV_GP2
);
1604 IWL_CMD(CSR_LED_REG
);
1605 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1606 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1607 IWL_CMD(CSR_ANA_PLL_CFG
);
1608 IWL_CMD(CSR_HW_REV_WA_REG
);
1609 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1615 void iwl_dump_csr(struct iwl_trans
*trans
)
1618 static const u32 csr_tbl
[] = {
1619 CSR_HW_IF_CONFIG_REG
,
1637 CSR_DRAM_INT_TBL_REG
,
1638 CSR_GIO_CHICKEN_BITS
,
1641 CSR_DBG_HPET_MEM_REG
1643 IWL_ERR(trans
, "CSR values:\n");
1644 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1645 "CSR_INT_PERIODIC_REG)\n");
1646 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1647 IWL_ERR(trans
, " %25s: 0X%08x\n",
1648 get_csr_string(csr_tbl
[i
]),
1649 iwl_read32(bus(trans
), csr_tbl
[i
]));
1653 #ifdef CONFIG_IWLWIFI_DEBUGFS
1654 /* create and remove of files */
1655 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1656 if (!debugfs_create_file(#name, mode, parent, trans, \
1657 &iwl_dbgfs_##name##_ops)) \
1661 /* file operation */
1662 #define DEBUGFS_READ_FUNC(name) \
1663 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1664 char __user *user_buf, \
1665 size_t count, loff_t *ppos);
1667 #define DEBUGFS_WRITE_FUNC(name) \
1668 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1669 const char __user *user_buf, \
1670 size_t count, loff_t *ppos);
1673 static int iwl_dbgfs_open_file_generic(struct inode
*inode
, struct file
*file
)
1675 file
->private_data
= inode
->i_private
;
1679 #define DEBUGFS_READ_FILE_OPS(name) \
1680 DEBUGFS_READ_FUNC(name); \
1681 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1682 .read = iwl_dbgfs_##name##_read, \
1683 .open = iwl_dbgfs_open_file_generic, \
1684 .llseek = generic_file_llseek, \
1687 #define DEBUGFS_WRITE_FILE_OPS(name) \
1688 DEBUGFS_WRITE_FUNC(name); \
1689 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1690 .write = iwl_dbgfs_##name##_write, \
1691 .open = iwl_dbgfs_open_file_generic, \
1692 .llseek = generic_file_llseek, \
1695 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1696 DEBUGFS_READ_FUNC(name); \
1697 DEBUGFS_WRITE_FUNC(name); \
1698 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1699 .write = iwl_dbgfs_##name##_write, \
1700 .read = iwl_dbgfs_##name##_read, \
1701 .open = iwl_dbgfs_open_file_generic, \
1702 .llseek = generic_file_llseek, \
1705 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1706 char __user
*user_buf
,
1707 size_t count
, loff_t
*ppos
)
1709 struct iwl_trans
*trans
= file
->private_data
;
1710 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1711 struct iwl_tx_queue
*txq
;
1712 struct iwl_queue
*q
;
1717 const size_t bufsz
= sizeof(char) * 64 * hw_params(trans
).max_txq_num
;
1719 if (!trans_pcie
->txq
) {
1720 IWL_ERR(trans
, "txq not ready\n");
1723 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1727 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1728 txq
= &trans_pcie
->txq
[cnt
];
1730 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1731 "hwq %.2d: read=%u write=%u stop=%d"
1732 " swq_id=%#.2x (ac %d/hwq %d)\n",
1733 cnt
, q
->read_ptr
, q
->write_ptr
,
1734 !!test_bit(cnt
, trans_pcie
->queue_stopped
),
1735 txq
->swq_id
, txq
->swq_id
& 3,
1736 (txq
->swq_id
>> 2) & 0x1f);
1739 /* for the ACs, display the stop count too */
1740 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1741 " stop-count: %d\n",
1742 atomic_read(&trans_pcie
->queue_stop_count
[cnt
]));
1744 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1749 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1750 char __user
*user_buf
,
1751 size_t count
, loff_t
*ppos
) {
1752 struct iwl_trans
*trans
= file
->private_data
;
1753 struct iwl_trans_pcie
*trans_pcie
=
1754 IWL_TRANS_GET_PCIE_TRANS(trans
);
1755 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
1758 const size_t bufsz
= sizeof(buf
);
1760 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1762 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1764 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
1767 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
1768 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
1770 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1771 "closed_rb_num: Not Allocated\n");
1773 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1776 static ssize_t
iwl_dbgfs_log_event_read(struct file
*file
,
1777 char __user
*user_buf
,
1778 size_t count
, loff_t
*ppos
)
1780 struct iwl_trans
*trans
= file
->private_data
;
1783 ssize_t ret
= -ENOMEM
;
1785 ret
= pos
= iwl_dump_nic_event_log(trans
, true, &buf
, true);
1787 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1793 static ssize_t
iwl_dbgfs_log_event_write(struct file
*file
,
1794 const char __user
*user_buf
,
1795 size_t count
, loff_t
*ppos
)
1797 struct iwl_trans
*trans
= file
->private_data
;
1802 memset(buf
, 0, sizeof(buf
));
1803 buf_size
= min(count
, sizeof(buf
) - 1);
1804 if (copy_from_user(buf
, user_buf
, buf_size
))
1806 if (sscanf(buf
, "%d", &event_log_flag
) != 1)
1808 if (event_log_flag
== 1)
1809 iwl_dump_nic_event_log(trans
, true, NULL
, false);
1814 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
1815 char __user
*user_buf
,
1816 size_t count
, loff_t
*ppos
) {
1818 struct iwl_trans
*trans
= file
->private_data
;
1819 struct iwl_trans_pcie
*trans_pcie
=
1820 IWL_TRANS_GET_PCIE_TRANS(trans
);
1821 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1825 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
1828 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1830 IWL_ERR(trans
, "Can not allocate Buffer\n");
1834 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1835 "Interrupt Statistics Report:\n");
1837 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
1839 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
1841 if (isr_stats
->sw
|| isr_stats
->hw
) {
1842 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1843 "\tLast Restarting Code: 0x%X\n",
1844 isr_stats
->err_code
);
1846 #ifdef CONFIG_IWLWIFI_DEBUG
1847 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
1849 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
1852 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1853 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
1855 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
1858 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
1861 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1862 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
1864 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
1867 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
1868 isr_stats
->unhandled
);
1870 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1875 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
1876 const char __user
*user_buf
,
1877 size_t count
, loff_t
*ppos
)
1879 struct iwl_trans
*trans
= file
->private_data
;
1880 struct iwl_trans_pcie
*trans_pcie
=
1881 IWL_TRANS_GET_PCIE_TRANS(trans
);
1882 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1888 memset(buf
, 0, sizeof(buf
));
1889 buf_size
= min(count
, sizeof(buf
) - 1);
1890 if (copy_from_user(buf
, user_buf
, buf_size
))
1892 if (sscanf(buf
, "%x", &reset_flag
) != 1)
1894 if (reset_flag
== 0)
1895 memset(isr_stats
, 0, sizeof(*isr_stats
));
1900 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
1901 const char __user
*user_buf
,
1902 size_t count
, loff_t
*ppos
)
1904 struct iwl_trans
*trans
= file
->private_data
;
1909 memset(buf
, 0, sizeof(buf
));
1910 buf_size
= min(count
, sizeof(buf
) - 1);
1911 if (copy_from_user(buf
, user_buf
, buf_size
))
1913 if (sscanf(buf
, "%d", &csr
) != 1)
1916 iwl_dump_csr(trans
);
1921 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
1922 char __user
*user_buf
,
1923 size_t count
, loff_t
*ppos
)
1925 struct iwl_trans
*trans
= file
->private_data
;
1928 ssize_t ret
= -EFAULT
;
1930 ret
= pos
= iwl_dump_fh(trans
, &buf
, true);
1932 ret
= simple_read_from_buffer(user_buf
,
1933 count
, ppos
, buf
, pos
);
1940 DEBUGFS_READ_WRITE_FILE_OPS(log_event
);
1941 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
1942 DEBUGFS_READ_FILE_OPS(fh_reg
);
1943 DEBUGFS_READ_FILE_OPS(rx_queue
);
1944 DEBUGFS_READ_FILE_OPS(tx_queue
);
1945 DEBUGFS_WRITE_FILE_OPS(csr
);
1948 * Create the debugfs files and directories
1951 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1954 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
1955 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
1956 DEBUGFS_ADD_FILE(log_event
, dir
, S_IWUSR
| S_IRUSR
);
1957 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
1958 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
1959 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
1963 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1967 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1969 const struct iwl_trans_ops trans_ops_pcie
= {
1970 .alloc
= iwl_trans_pcie_alloc
,
1971 .request_irq
= iwl_trans_pcie_request_irq
,
1972 .start_device
= iwl_trans_pcie_start_device
,
1973 .prepare_card_hw
= iwl_trans_pcie_prepare_card_hw
,
1974 .stop_device
= iwl_trans_pcie_stop_device
,
1976 .tx_start
= iwl_trans_pcie_tx_start
,
1977 .wake_any_queue
= iwl_trans_pcie_wake_any_queue
,
1979 .send_cmd
= iwl_trans_pcie_send_cmd
,
1981 .tx
= iwl_trans_pcie_tx
,
1982 .reclaim
= iwl_trans_pcie_reclaim
,
1984 .tx_agg_disable
= iwl_trans_pcie_tx_agg_disable
,
1985 .tx_agg_alloc
= iwl_trans_pcie_tx_agg_alloc
,
1986 .tx_agg_setup
= iwl_trans_pcie_tx_agg_setup
,
1988 .kick_nic
= iwl_trans_pcie_kick_nic
,
1990 .free
= iwl_trans_pcie_free
,
1991 .stop_queue
= iwl_trans_pcie_stop_queue
,
1993 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
1995 .wait_tx_queue_empty
= iwl_trans_pcie_wait_tx_queue_empty
,
1996 .check_stuck_queue
= iwl_trans_pcie_check_stuck_queue
,
1998 #ifdef CONFIG_PM_SLEEP
1999 .suspend
= iwl_trans_pcie_suspend
,
2000 .resume
= iwl_trans_pcie_resume
,