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Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/interrupt.h>
64 #include <linux/debugfs.h>
65 #include <linux/bitops.h>
66 #include <linux/gfp.h>
67
68 #include "iwl-trans.h"
69 #include "iwl-trans-pcie-int.h"
70 #include "iwl-csr.h"
71 #include "iwl-prph.h"
72 #include "iwl-shared.h"
73 #include "iwl-eeprom.h"
74 #include "iwl-agn-hw.h"
75
76 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
77 {
78 struct iwl_trans_pcie *trans_pcie =
79 IWL_TRANS_GET_PCIE_TRANS(trans);
80 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
81 struct device *dev = bus(trans)->dev;
82
83 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
84
85 spin_lock_init(&rxq->lock);
86
87 if (WARN_ON(rxq->bd || rxq->rb_stts))
88 return -EINVAL;
89
90 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
91 rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
92 &rxq->bd_dma, GFP_KERNEL);
93 if (!rxq->bd)
94 goto err_bd;
95 memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
96
97 /*Allocate the driver's pointer to receive buffer status */
98 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
99 &rxq->rb_stts_dma, GFP_KERNEL);
100 if (!rxq->rb_stts)
101 goto err_rb_stts;
102 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
103
104 return 0;
105
106 err_rb_stts:
107 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
108 rxq->bd, rxq->bd_dma);
109 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
110 rxq->bd = NULL;
111 err_bd:
112 return -ENOMEM;
113 }
114
115 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
116 {
117 struct iwl_trans_pcie *trans_pcie =
118 IWL_TRANS_GET_PCIE_TRANS(trans);
119 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
120 int i;
121
122 /* Fill the rx_used queue with _all_ of the Rx buffers */
123 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
124 /* In the reset function, these buffers may have been allocated
125 * to an SKB, so we need to unmap and free potential storage */
126 if (rxq->pool[i].page != NULL) {
127 dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
128 PAGE_SIZE << hw_params(trans).rx_page_order,
129 DMA_FROM_DEVICE);
130 __free_pages(rxq->pool[i].page,
131 hw_params(trans).rx_page_order);
132 rxq->pool[i].page = NULL;
133 }
134 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
135 }
136 }
137
138 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
139 struct iwl_rx_queue *rxq)
140 {
141 u32 rb_size;
142 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
143 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
144
145 if (iwlagn_mod_params.amsdu_size_8K)
146 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
147 else
148 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
149
150 /* Stop Rx DMA */
151 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
152
153 /* Reset driver's Rx queue write index */
154 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
155
156 /* Tell device where to find RBD circular buffer in DRAM */
157 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
158 (u32)(rxq->bd_dma >> 8));
159
160 /* Tell device where in DRAM to update its Rx status */
161 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
162 rxq->rb_stts_dma >> 4);
163
164 /* Enable Rx DMA
165 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
166 * the credit mechanism in 5000 HW RX FIFO
167 * Direct rx interrupts to hosts
168 * Rx buffer size 4 or 8k
169 * RB timeout 0x10
170 * 256 RBDs
171 */
172 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
173 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
174 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
175 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
176 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
177 rb_size|
178 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
179 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
180
181 /* Set interrupt coalescing timer to default (2048 usecs) */
182 iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
183 }
184
185 static int iwl_rx_init(struct iwl_trans *trans)
186 {
187 struct iwl_trans_pcie *trans_pcie =
188 IWL_TRANS_GET_PCIE_TRANS(trans);
189 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
190
191 int i, err;
192 unsigned long flags;
193
194 if (!rxq->bd) {
195 err = iwl_trans_rx_alloc(trans);
196 if (err)
197 return err;
198 }
199
200 spin_lock_irqsave(&rxq->lock, flags);
201 INIT_LIST_HEAD(&rxq->rx_free);
202 INIT_LIST_HEAD(&rxq->rx_used);
203
204 iwl_trans_rxq_free_rx_bufs(trans);
205
206 for (i = 0; i < RX_QUEUE_SIZE; i++)
207 rxq->queue[i] = NULL;
208
209 /* Set us so that we have processed and used all buffers, but have
210 * not restocked the Rx queue with fresh buffers */
211 rxq->read = rxq->write = 0;
212 rxq->write_actual = 0;
213 rxq->free_count = 0;
214 spin_unlock_irqrestore(&rxq->lock, flags);
215
216 iwlagn_rx_replenish(trans);
217
218 iwl_trans_rx_hw_init(trans, rxq);
219
220 spin_lock_irqsave(&trans->shrd->lock, flags);
221 rxq->need_update = 1;
222 iwl_rx_queue_update_write_ptr(trans, rxq);
223 spin_unlock_irqrestore(&trans->shrd->lock, flags);
224
225 return 0;
226 }
227
228 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
229 {
230 struct iwl_trans_pcie *trans_pcie =
231 IWL_TRANS_GET_PCIE_TRANS(trans);
232 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
233
234 unsigned long flags;
235
236 /*if rxq->bd is NULL, it means that nothing has been allocated,
237 * exit now */
238 if (!rxq->bd) {
239 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
240 return;
241 }
242
243 spin_lock_irqsave(&rxq->lock, flags);
244 iwl_trans_rxq_free_rx_bufs(trans);
245 spin_unlock_irqrestore(&rxq->lock, flags);
246
247 dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
248 rxq->bd, rxq->bd_dma);
249 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
250 rxq->bd = NULL;
251
252 if (rxq->rb_stts)
253 dma_free_coherent(bus(trans)->dev,
254 sizeof(struct iwl_rb_status),
255 rxq->rb_stts, rxq->rb_stts_dma);
256 else
257 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
258 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
259 rxq->rb_stts = NULL;
260 }
261
262 static int iwl_trans_rx_stop(struct iwl_trans *trans)
263 {
264
265 /* stop Rx DMA */
266 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
267 return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
268 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
269 }
270
271 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
272 struct iwl_dma_ptr *ptr, size_t size)
273 {
274 if (WARN_ON(ptr->addr))
275 return -EINVAL;
276
277 ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
278 &ptr->dma, GFP_KERNEL);
279 if (!ptr->addr)
280 return -ENOMEM;
281 ptr->size = size;
282 return 0;
283 }
284
285 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
286 struct iwl_dma_ptr *ptr)
287 {
288 if (unlikely(!ptr->addr))
289 return;
290
291 dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
292 memset(ptr, 0, sizeof(*ptr));
293 }
294
295 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
296 struct iwl_tx_queue *txq, int slots_num,
297 u32 txq_id)
298 {
299 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
300 int i;
301
302 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
303 return -EINVAL;
304
305 txq->q.n_window = slots_num;
306
307 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
308 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
309
310 if (!txq->meta || !txq->cmd)
311 goto error;
312
313 if (txq_id == trans->shrd->cmd_queue)
314 for (i = 0; i < slots_num; i++) {
315 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
316 GFP_KERNEL);
317 if (!txq->cmd[i])
318 goto error;
319 }
320
321 /* Alloc driver data array and TFD circular buffer */
322 /* Driver private data, only for Tx (not command) queues,
323 * not shared with device. */
324 if (txq_id != trans->shrd->cmd_queue) {
325 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
326 GFP_KERNEL);
327 if (!txq->skbs) {
328 IWL_ERR(trans, "kmalloc for auxiliary BD "
329 "structures failed\n");
330 goto error;
331 }
332 } else {
333 txq->skbs = NULL;
334 }
335
336 /* Circular buffer of transmit frame descriptors (TFDs),
337 * shared with device */
338 txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
339 &txq->q.dma_addr, GFP_KERNEL);
340 if (!txq->tfds) {
341 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
342 goto error;
343 }
344 txq->q.id = txq_id;
345
346 return 0;
347 error:
348 kfree(txq->skbs);
349 txq->skbs = NULL;
350 /* since txq->cmd has been zeroed,
351 * all non allocated cmd[i] will be NULL */
352 if (txq->cmd && txq_id == trans->shrd->cmd_queue)
353 for (i = 0; i < slots_num; i++)
354 kfree(txq->cmd[i]);
355 kfree(txq->meta);
356 kfree(txq->cmd);
357 txq->meta = NULL;
358 txq->cmd = NULL;
359
360 return -ENOMEM;
361
362 }
363
364 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
365 int slots_num, u32 txq_id)
366 {
367 int ret;
368
369 txq->need_update = 0;
370 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
371
372 /*
373 * For the default queues 0-3, set up the swq_id
374 * already -- all others need to get one later
375 * (if they need one at all).
376 */
377 if (txq_id < 4)
378 iwl_set_swq_id(txq, txq_id, txq_id);
379
380 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
381 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
382 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
383
384 /* Initialize queue's high/low-water marks, and head/tail indexes */
385 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
386 txq_id);
387 if (ret)
388 return ret;
389
390 /*
391 * Tell nic where to find circular buffer of Tx Frame Descriptors for
392 * given Tx queue, and enable the DMA channel used for that queue.
393 * Circular buffer (TFD queue in DRAM) physical base address */
394 iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
395 txq->q.dma_addr >> 8);
396
397 return 0;
398 }
399
400 /**
401 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
402 */
403 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
404 {
405 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
406 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
407 struct iwl_queue *q = &txq->q;
408 enum dma_data_direction dma_dir;
409 unsigned long flags;
410
411 if (!q->n_bd)
412 return;
413
414 /* In the command queue, all the TBs are mapped as BIDI
415 * so unmap them as such.
416 */
417 if (txq_id == trans->shrd->cmd_queue)
418 dma_dir = DMA_BIDIRECTIONAL;
419 else
420 dma_dir = DMA_TO_DEVICE;
421
422 spin_lock_irqsave(&trans->shrd->sta_lock, flags);
423 while (q->write_ptr != q->read_ptr) {
424 /* The read_ptr needs to bound by q->n_window */
425 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
426 dma_dir);
427 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
428 }
429 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
430 }
431
432 /**
433 * iwl_tx_queue_free - Deallocate DMA queue.
434 * @txq: Transmit queue to deallocate.
435 *
436 * Empty queue by removing and destroying all BD's.
437 * Free all buffers.
438 * 0-fill, but do not free "txq" descriptor structure.
439 */
440 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
441 {
442 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
443 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
444 struct device *dev = bus(trans)->dev;
445 int i;
446 if (WARN_ON(!txq))
447 return;
448
449 iwl_tx_queue_unmap(trans, txq_id);
450
451 /* De-alloc array of command/tx buffers */
452
453 if (txq_id == trans->shrd->cmd_queue)
454 for (i = 0; i < txq->q.n_window; i++)
455 kfree(txq->cmd[i]);
456
457 /* De-alloc circular buffer of TFDs */
458 if (txq->q.n_bd) {
459 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
460 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
461 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
462 }
463
464 /* De-alloc array of per-TFD driver data */
465 kfree(txq->skbs);
466 txq->skbs = NULL;
467
468 /* deallocate arrays */
469 kfree(txq->cmd);
470 kfree(txq->meta);
471 txq->cmd = NULL;
472 txq->meta = NULL;
473
474 /* 0-fill queue descriptor structure */
475 memset(txq, 0, sizeof(*txq));
476 }
477
478 /**
479 * iwl_trans_tx_free - Free TXQ Context
480 *
481 * Destroy all TX DMA queues and structures
482 */
483 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
484 {
485 int txq_id;
486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
487
488 /* Tx queues */
489 if (trans_pcie->txq) {
490 for (txq_id = 0;
491 txq_id < hw_params(trans).max_txq_num; txq_id++)
492 iwl_tx_queue_free(trans, txq_id);
493 }
494
495 kfree(trans_pcie->txq);
496 trans_pcie->txq = NULL;
497
498 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
499
500 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
501 }
502
503 /**
504 * iwl_trans_tx_alloc - allocate TX context
505 * Allocate all Tx DMA structures and initialize them
506 *
507 * @param priv
508 * @return error code
509 */
510 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
511 {
512 int ret;
513 int txq_id, slots_num;
514 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
515
516 u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
517 sizeof(struct iwlagn_scd_bc_tbl);
518
519 /*It is not allowed to alloc twice, so warn when this happens.
520 * We cannot rely on the previous allocation, so free and fail */
521 if (WARN_ON(trans_pcie->txq)) {
522 ret = -EINVAL;
523 goto error;
524 }
525
526 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
527 scd_bc_tbls_size);
528 if (ret) {
529 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
530 goto error;
531 }
532
533 /* Alloc keep-warm buffer */
534 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
535 if (ret) {
536 IWL_ERR(trans, "Keep Warm allocation failed\n");
537 goto error;
538 }
539
540 trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
541 sizeof(struct iwl_tx_queue), GFP_KERNEL);
542 if (!trans_pcie->txq) {
543 IWL_ERR(trans, "Not enough memory for txq\n");
544 ret = ENOMEM;
545 goto error;
546 }
547
548 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
549 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
550 slots_num = (txq_id == trans->shrd->cmd_queue) ?
551 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
552 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
553 slots_num, txq_id);
554 if (ret) {
555 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
556 goto error;
557 }
558 }
559
560 return 0;
561
562 error:
563 iwl_trans_pcie_tx_free(trans);
564
565 return ret;
566 }
567 static int iwl_tx_init(struct iwl_trans *trans)
568 {
569 int ret;
570 int txq_id, slots_num;
571 unsigned long flags;
572 bool alloc = false;
573 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
574
575 if (!trans_pcie->txq) {
576 ret = iwl_trans_tx_alloc(trans);
577 if (ret)
578 goto error;
579 alloc = true;
580 }
581
582 spin_lock_irqsave(&trans->shrd->lock, flags);
583
584 /* Turn off all Tx DMA fifos */
585 iwl_write_prph(bus(trans), SCD_TXFACT, 0);
586
587 /* Tell NIC where to find the "keep warm" buffer */
588 iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
589 trans_pcie->kw.dma >> 4);
590
591 spin_unlock_irqrestore(&trans->shrd->lock, flags);
592
593 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
594 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
595 slots_num = (txq_id == trans->shrd->cmd_queue) ?
596 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
597 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
598 slots_num, txq_id);
599 if (ret) {
600 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
601 goto error;
602 }
603 }
604
605 return 0;
606 error:
607 /*Upon error, free only if we allocated something */
608 if (alloc)
609 iwl_trans_pcie_tx_free(trans);
610 return ret;
611 }
612
613 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
614 {
615 /*
616 * (for documentation purposes)
617 * to set power to V_AUX, do:
618
619 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
620 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
621 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
622 ~APMG_PS_CTRL_MSK_PWR_SRC);
623 */
624
625 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
626 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
627 ~APMG_PS_CTRL_MSK_PWR_SRC);
628 }
629
630 static int iwl_nic_init(struct iwl_trans *trans)
631 {
632 unsigned long flags;
633
634 /* nic_init */
635 spin_lock_irqsave(&trans->shrd->lock, flags);
636 iwl_apm_init(priv(trans));
637
638 /* Set interrupt coalescing calibration timer to default (512 usecs) */
639 iwl_write8(bus(trans), CSR_INT_COALESCING,
640 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
641
642 spin_unlock_irqrestore(&trans->shrd->lock, flags);
643
644 iwl_set_pwr_vmain(trans);
645
646 iwl_nic_config(priv(trans));
647
648 /* Allocate the RX queue, or reset if it is already allocated */
649 iwl_rx_init(trans);
650
651 /* Allocate or reset and init all Tx and Command queues */
652 if (iwl_tx_init(trans))
653 return -ENOMEM;
654
655 if (hw_params(trans).shadow_reg_enable) {
656 /* enable shadow regs in HW */
657 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
658 0x800FFFFF);
659 }
660
661 set_bit(STATUS_INIT, &trans->shrd->status);
662
663 return 0;
664 }
665
666 #define HW_READY_TIMEOUT (50)
667
668 /* Note: returns poll_bit return value, which is >= 0 if success */
669 static int iwl_set_hw_ready(struct iwl_trans *trans)
670 {
671 int ret;
672
673 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
674 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
675
676 /* See if we got it */
677 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
678 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
679 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
680 HW_READY_TIMEOUT);
681
682 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
683 return ret;
684 }
685
686 /* Note: returns standard 0/-ERROR code */
687 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
688 {
689 int ret;
690
691 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
692
693 ret = iwl_set_hw_ready(trans);
694 if (ret >= 0)
695 return 0;
696
697 /* If HW is not ready, prepare the conditions to check again */
698 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
699 CSR_HW_IF_CONFIG_REG_PREPARE);
700
701 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
702 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
703 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
704
705 if (ret < 0)
706 return ret;
707
708 /* HW should be ready by now, check again. */
709 ret = iwl_set_hw_ready(trans);
710 if (ret >= 0)
711 return 0;
712 return ret;
713 }
714
715 #define IWL_AC_UNSET -1
716
717 struct queue_to_fifo_ac {
718 s8 fifo, ac;
719 };
720
721 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
722 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
723 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
724 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
725 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
726 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
727 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
728 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
729 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
730 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
731 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
732 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
733 };
734
735 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
736 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
737 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
738 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
739 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
740 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
741 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
742 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
743 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
744 { IWL_TX_FIFO_BE_IPAN, 2, },
745 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
746 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
747 };
748
749 static const u8 iwlagn_bss_ac_to_fifo[] = {
750 IWL_TX_FIFO_VO,
751 IWL_TX_FIFO_VI,
752 IWL_TX_FIFO_BE,
753 IWL_TX_FIFO_BK,
754 };
755 static const u8 iwlagn_bss_ac_to_queue[] = {
756 0, 1, 2, 3,
757 };
758 static const u8 iwlagn_pan_ac_to_fifo[] = {
759 IWL_TX_FIFO_VO_IPAN,
760 IWL_TX_FIFO_VI_IPAN,
761 IWL_TX_FIFO_BE_IPAN,
762 IWL_TX_FIFO_BK_IPAN,
763 };
764 static const u8 iwlagn_pan_ac_to_queue[] = {
765 7, 6, 5, 4,
766 };
767
768 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
769 {
770 int ret;
771 struct iwl_trans_pcie *trans_pcie =
772 IWL_TRANS_GET_PCIE_TRANS(trans);
773
774 trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
775 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
776 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
777
778 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
779 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
780
781 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
782 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
783
784 if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
785 iwl_trans_pcie_prepare_card_hw(trans)) {
786 IWL_WARN(trans, "Exit HW not ready\n");
787 return -EIO;
788 }
789
790 /* If platform's RF_KILL switch is NOT set to KILL */
791 if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
792 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
793 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
794 else
795 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
796
797 if (iwl_is_rfkill(trans->shrd)) {
798 iwl_set_hw_rfkill_state(priv(trans), true);
799 iwl_enable_interrupts(trans);
800 return -ERFKILL;
801 }
802
803 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
804
805 ret = iwl_nic_init(trans);
806 if (ret) {
807 IWL_ERR(trans, "Unable to init nic\n");
808 return ret;
809 }
810
811 /* make sure rfkill handshake bits are cleared */
812 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
813 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
814 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
815
816 /* clear (again), then enable host interrupts */
817 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
818 iwl_enable_interrupts(trans);
819
820 /* really make sure rfkill handshake bits are cleared */
821 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
822 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
823
824 return 0;
825 }
826
827 /*
828 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
829 * must be called under priv->shrd->lock and mac access
830 */
831 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
832 {
833 iwl_write_prph(bus(trans), SCD_TXFACT, mask);
834 }
835
836 static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
837 {
838 const struct queue_to_fifo_ac *queue_to_fifo;
839 struct iwl_trans_pcie *trans_pcie =
840 IWL_TRANS_GET_PCIE_TRANS(trans);
841 u32 a;
842 unsigned long flags;
843 int i, chan;
844 u32 reg_val;
845
846 spin_lock_irqsave(&trans->shrd->lock, flags);
847
848 trans_pcie->scd_base_addr =
849 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
850 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
851 /* reset conext data memory */
852 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
853 a += 4)
854 iwl_write_targ_mem(bus(trans), a, 0);
855 /* reset tx status memory */
856 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
857 a += 4)
858 iwl_write_targ_mem(bus(trans), a, 0);
859 for (; a < trans_pcie->scd_base_addr +
860 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
861 a += 4)
862 iwl_write_targ_mem(bus(trans), a, 0);
863
864 iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
865 trans_pcie->scd_bc_tbls.dma >> 10);
866
867 /* Enable DMA channel */
868 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
869 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
870 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
871 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
872
873 /* Update FH chicken bits */
874 reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
875 iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
876 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
877
878 iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
879 SCD_QUEUECHAIN_SEL_ALL(trans));
880 iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
881
882 /* initiate the queues */
883 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
884 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
885 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
886 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
887 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
888 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
889 SCD_CONTEXT_QUEUE_OFFSET(i) +
890 sizeof(u32),
891 ((SCD_WIN_SIZE <<
892 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
893 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
894 ((SCD_FRAME_LIMIT <<
895 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
896 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
897 }
898
899 iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
900 IWL_MASK(0, hw_params(trans).max_txq_num));
901
902 /* Activate all Tx DMA/FIFO channels */
903 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
904
905 /* map queues to FIFOs */
906 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
907 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
908 else
909 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
910
911 iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
912
913 /* make sure all queue are not stopped */
914 memset(&trans_pcie->queue_stopped[0], 0,
915 sizeof(trans_pcie->queue_stopped));
916 for (i = 0; i < 4; i++)
917 atomic_set(&trans_pcie->queue_stop_count[i], 0);
918
919 /* reset to 0 to enable all the queue first */
920 trans_pcie->txq_ctx_active_msk = 0;
921
922 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
923 IWLAGN_FIRST_AMPDU_QUEUE);
924 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
925 IWLAGN_FIRST_AMPDU_QUEUE);
926
927 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
928 int fifo = queue_to_fifo[i].fifo;
929 int ac = queue_to_fifo[i].ac;
930
931 iwl_txq_ctx_activate(trans_pcie, i);
932
933 if (fifo == IWL_TX_FIFO_UNUSED)
934 continue;
935
936 if (ac != IWL_AC_UNSET)
937 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
938 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
939 fifo, 0);
940 }
941
942 spin_unlock_irqrestore(&trans->shrd->lock, flags);
943
944 /* Enable L1-Active */
945 iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
946 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
947 }
948
949 /**
950 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
951 */
952 static int iwl_trans_tx_stop(struct iwl_trans *trans)
953 {
954 int ch, txq_id;
955 unsigned long flags;
956 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
957
958 /* Turn off all Tx DMA fifos */
959 spin_lock_irqsave(&trans->shrd->lock, flags);
960
961 iwl_trans_txq_set_sched(trans, 0);
962
963 /* Stop each Tx DMA channel, and wait for it to be idle */
964 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
965 iwl_write_direct32(bus(trans),
966 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
967 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
968 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
969 1000))
970 IWL_ERR(trans, "Failing on timeout while stopping"
971 " DMA channel %d [0x%08x]", ch,
972 iwl_read_direct32(bus(trans),
973 FH_TSSR_TX_STATUS_REG));
974 }
975 spin_unlock_irqrestore(&trans->shrd->lock, flags);
976
977 if (!trans_pcie->txq) {
978 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
979 return 0;
980 }
981
982 /* Unmap DMA from host system and free skb's */
983 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
984 iwl_tx_queue_unmap(trans, txq_id);
985
986 return 0;
987 }
988
989 static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans)
990 {
991 unsigned long flags;
992 struct iwl_trans_pcie *trans_pcie =
993 IWL_TRANS_GET_PCIE_TRANS(trans);
994
995 spin_lock_irqsave(&trans->shrd->lock, flags);
996 iwl_disable_interrupts(trans);
997 spin_unlock_irqrestore(&trans->shrd->lock, flags);
998
999 /* wait to make sure we flush pending tasklet*/
1000 synchronize_irq(bus(trans)->irq);
1001 tasklet_kill(&trans_pcie->irq_tasklet);
1002 }
1003
1004 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1005 {
1006 /* stop and reset the on-board processor */
1007 iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1008
1009 /* tell the device to stop sending interrupts */
1010 iwl_trans_pcie_disable_sync_irq(trans);
1011
1012 /* device going down, Stop using ICT table */
1013 iwl_disable_ict(trans);
1014
1015 /*
1016 * If a HW restart happens during firmware loading,
1017 * then the firmware loading might call this function
1018 * and later it might be called again due to the
1019 * restart. So don't process again if the device is
1020 * already dead.
1021 */
1022 if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1023 iwl_trans_tx_stop(trans);
1024 iwl_trans_rx_stop(trans);
1025
1026 /* Power-down device's busmaster DMA clocks */
1027 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1028 APMG_CLK_VAL_DMA_CLK_RQT);
1029 udelay(5);
1030 }
1031
1032 /* Make sure (redundant) we've released our request to stay awake */
1033 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1034 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1035
1036 /* Stop the device, and put it in low power state */
1037 iwl_apm_stop(priv(trans));
1038 }
1039
1040 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1041 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1042 u8 sta_id)
1043 {
1044 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1045 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1046 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1047 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1048 struct iwl_cmd_meta *out_meta;
1049 struct iwl_tx_queue *txq;
1050 struct iwl_queue *q;
1051
1052 dma_addr_t phys_addr = 0;
1053 dma_addr_t txcmd_phys;
1054 dma_addr_t scratch_phys;
1055 u16 len, firstlen, secondlen;
1056 u16 seq_number = 0;
1057 u8 wait_write_ptr = 0;
1058 u8 txq_id;
1059 u8 tid = 0;
1060 bool is_agg = false;
1061 __le16 fc = hdr->frame_control;
1062 u8 hdr_len = ieee80211_hdrlen(fc);
1063
1064 /*
1065 * Send this frame after DTIM -- there's a special queue
1066 * reserved for this for contexts that support AP mode.
1067 */
1068 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1069 txq_id = trans_pcie->mcast_queue[ctx];
1070
1071 /*
1072 * The microcode will clear the more data
1073 * bit in the last frame it transmits.
1074 */
1075 hdr->frame_control |=
1076 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1077 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1078 txq_id = IWL_AUX_QUEUE;
1079 else
1080 txq_id =
1081 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1082
1083 if (ieee80211_is_data_qos(fc) && !ieee80211_is_qos_nullfunc(fc)) {
1084 u8 *qc = NULL;
1085 struct iwl_tid_data *tid_data;
1086 qc = ieee80211_get_qos_ctl(hdr);
1087 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1088 tid_data = &trans->shrd->tid_data[sta_id][tid];
1089
1090 if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT))
1091 return -1;
1092
1093 seq_number = tid_data->seq_number;
1094 seq_number &= IEEE80211_SCTL_SEQ;
1095 hdr->seq_ctrl = hdr->seq_ctrl &
1096 cpu_to_le16(IEEE80211_SCTL_FRAG);
1097 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1098 seq_number += 0x10;
1099 /* aggregation is on for this <sta,tid> */
1100 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1101 WARN_ON_ONCE(tid_data->agg.state != IWL_AGG_ON);
1102 txq_id = tid_data->agg.txq_id;
1103 is_agg = true;
1104 }
1105 }
1106
1107 /* Copy MAC header from skb into command buffer */
1108 memcpy(tx_cmd->hdr, hdr, hdr_len);
1109
1110 txq = &trans_pcie->txq[txq_id];
1111 q = &txq->q;
1112
1113 /* Set up driver data for this TFD */
1114 txq->skbs[q->write_ptr] = skb;
1115 txq->cmd[q->write_ptr] = dev_cmd;
1116
1117 dev_cmd->hdr.cmd = REPLY_TX;
1118 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1119 INDEX_TO_SEQ(q->write_ptr)));
1120
1121 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1122 out_meta = &txq->meta[q->write_ptr];
1123
1124 /*
1125 * Use the first empty entry in this queue's command buffer array
1126 * to contain the Tx command and MAC header concatenated together
1127 * (payload data will be in another buffer).
1128 * Size of this varies, due to varying MAC header length.
1129 * If end is not dword aligned, we'll have 2 extra bytes at the end
1130 * of the MAC header (device reads on dword boundaries).
1131 * We'll tell device about this padding later.
1132 */
1133 len = sizeof(struct iwl_tx_cmd) +
1134 sizeof(struct iwl_cmd_header) + hdr_len;
1135 firstlen = (len + 3) & ~3;
1136
1137 /* Tell NIC about any 2-byte padding after MAC header */
1138 if (firstlen != len)
1139 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1140
1141 /* Physical address of this Tx command's header (not MAC header!),
1142 * within command buffer array. */
1143 txcmd_phys = dma_map_single(bus(trans)->dev,
1144 &dev_cmd->hdr, firstlen,
1145 DMA_BIDIRECTIONAL);
1146 if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1147 return -1;
1148 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1149 dma_unmap_len_set(out_meta, len, firstlen);
1150
1151 if (!ieee80211_has_morefrags(fc)) {
1152 txq->need_update = 1;
1153 } else {
1154 wait_write_ptr = 1;
1155 txq->need_update = 0;
1156 }
1157
1158 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1159 * if any (802.11 null frames have no payload). */
1160 secondlen = skb->len - hdr_len;
1161 if (secondlen > 0) {
1162 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1163 secondlen, DMA_TO_DEVICE);
1164 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1165 dma_unmap_single(bus(trans)->dev,
1166 dma_unmap_addr(out_meta, mapping),
1167 dma_unmap_len(out_meta, len),
1168 DMA_BIDIRECTIONAL);
1169 return -1;
1170 }
1171 }
1172
1173 /* Attach buffers to TFD */
1174 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1175 if (secondlen > 0)
1176 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1177 secondlen, 0);
1178
1179 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1180 offsetof(struct iwl_tx_cmd, scratch);
1181
1182 /* take back ownership of DMA buffer to enable update */
1183 dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1184 DMA_BIDIRECTIONAL);
1185 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1186 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1187
1188 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1189 le16_to_cpu(dev_cmd->hdr.sequence));
1190 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1191 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1192 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1193
1194 /* Set up entry for this TFD in Tx byte-count array */
1195 if (is_agg)
1196 iwl_trans_txq_update_byte_cnt_tbl(trans, txq,
1197 le16_to_cpu(tx_cmd->len));
1198
1199 dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1200 DMA_BIDIRECTIONAL);
1201
1202 trace_iwlwifi_dev_tx(priv(trans),
1203 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1204 sizeof(struct iwl_tfd),
1205 &dev_cmd->hdr, firstlen,
1206 skb->data + hdr_len, secondlen);
1207
1208 /* Tell device the write index *just past* this latest filled TFD */
1209 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1210 iwl_txq_update_write_ptr(trans, txq);
1211
1212 if (ieee80211_is_data_qos(fc) && !ieee80211_is_qos_nullfunc(fc)) {
1213 trans->shrd->tid_data[sta_id][tid].tfds_in_queue++;
1214 if (!ieee80211_has_morefrags(fc))
1215 trans->shrd->tid_data[sta_id][tid].seq_number =
1216 seq_number;
1217 }
1218
1219 /*
1220 * At this point the frame is "transmitted" successfully
1221 * and we will get a TX status notification eventually,
1222 * regardless of the value of ret. "ret" only indicates
1223 * whether or not we should update the write pointer.
1224 */
1225 if (iwl_queue_space(q) < q->high_mark) {
1226 if (wait_write_ptr) {
1227 txq->need_update = 1;
1228 iwl_txq_update_write_ptr(trans, txq);
1229 } else {
1230 iwl_stop_queue(trans, txq);
1231 }
1232 }
1233 return 0;
1234 }
1235
1236 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1237 {
1238 /* Remove all resets to allow NIC to operate */
1239 iwl_write32(bus(trans), CSR_RESET, 0);
1240 }
1241
1242 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1243 {
1244 struct iwl_trans_pcie *trans_pcie =
1245 IWL_TRANS_GET_PCIE_TRANS(trans);
1246 int err;
1247
1248 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1249
1250 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1251 iwl_irq_tasklet, (unsigned long)trans);
1252
1253 iwl_alloc_isr_ict(trans);
1254
1255 err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1256 DRV_NAME, trans);
1257 if (err) {
1258 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1259 iwl_free_isr_ict(trans);
1260 return err;
1261 }
1262
1263 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1264 return 0;
1265 }
1266
1267 static int iwlagn_txq_check_empty(struct iwl_trans *trans,
1268 int sta_id, u8 tid, int txq_id)
1269 {
1270 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1271 struct iwl_queue *q = &trans_pcie->txq[txq_id].q;
1272 struct iwl_tid_data *tid_data = &trans->shrd->tid_data[sta_id][tid];
1273
1274 lockdep_assert_held(&trans->shrd->sta_lock);
1275
1276 switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
1277 case IWL_EMPTYING_HW_QUEUE_DELBA:
1278 /* We are reclaiming the last packet of the */
1279 /* aggregated HW queue */
1280 if ((txq_id == tid_data->agg.txq_id) &&
1281 (q->read_ptr == q->write_ptr)) {
1282 IWL_DEBUG_HT(trans,
1283 "HW queue empty: continue DELBA flow\n");
1284 iwl_trans_pcie_txq_agg_disable(trans, txq_id);
1285 tid_data->agg.state = IWL_AGG_OFF;
1286 iwl_stop_tx_ba_trans_ready(priv(trans),
1287 NUM_IWL_RXON_CTX,
1288 sta_id, tid);
1289 iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1290 }
1291 break;
1292 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1293 /* We are reclaiming the last packet of the queue */
1294 if (tid_data->tfds_in_queue == 0) {
1295 IWL_DEBUG_HT(trans,
1296 "HW queue empty: continue ADDBA flow\n");
1297 tid_data->agg.state = IWL_AGG_ON;
1298 iwl_start_tx_ba_trans_ready(priv(trans),
1299 NUM_IWL_RXON_CTX,
1300 sta_id, tid);
1301 }
1302 break;
1303 default:
1304 break;
1305 }
1306
1307 return 0;
1308 }
1309
1310 static void iwl_free_tfds_in_queue(struct iwl_trans *trans,
1311 int sta_id, int tid, int freed)
1312 {
1313 lockdep_assert_held(&trans->shrd->sta_lock);
1314
1315 if (trans->shrd->tid_data[sta_id][tid].tfds_in_queue >= freed)
1316 trans->shrd->tid_data[sta_id][tid].tfds_in_queue -= freed;
1317 else {
1318 IWL_DEBUG_TX(trans, "free more than tfds_in_queue (%u:%d)\n",
1319 trans->shrd->tid_data[sta_id][tid].tfds_in_queue,
1320 freed);
1321 trans->shrd->tid_data[sta_id][tid].tfds_in_queue = 0;
1322 }
1323 }
1324
1325 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1326 int txq_id, int ssn, u32 status,
1327 struct sk_buff_head *skbs)
1328 {
1329 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1330 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1331 enum iwl_agg_state agg_state;
1332 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1333 int tfd_num = ssn & (txq->q.n_bd - 1);
1334 int freed = 0;
1335 bool cond;
1336
1337 txq->time_stamp = jiffies;
1338
1339 if (txq->sched_retry) {
1340 agg_state =
1341 trans->shrd->tid_data[txq->sta_id][txq->tid].agg.state;
1342 cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
1343 } else {
1344 cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
1345 }
1346
1347 if (txq->q.read_ptr != tfd_num) {
1348 IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
1349 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1350 ssn , tfd_num, txq_id, txq->swq_id);
1351 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1352 if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
1353 iwl_wake_queue(trans, txq);
1354 }
1355
1356 iwl_free_tfds_in_queue(trans, sta_id, tid, freed);
1357 iwlagn_txq_check_empty(trans, sta_id, tid, txq_id);
1358 }
1359
1360 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1361 {
1362 iwl_trans_pcie_tx_free(trans);
1363 iwl_trans_pcie_rx_free(trans);
1364 free_irq(bus(trans)->irq, trans);
1365 iwl_free_isr_ict(trans);
1366 trans->shrd->trans = NULL;
1367 kfree(trans);
1368 }
1369
1370 #ifdef CONFIG_PM_SLEEP
1371 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1372 {
1373 /*
1374 * This function is called when system goes into suspend state
1375 * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1376 * function first but since iwlagn_mac_stop() has no knowledge of
1377 * who the caller is,
1378 * it will not call apm_ops.stop() to stop the DMA operation.
1379 * Calling apm_ops.stop here to make sure we stop the DMA.
1380 *
1381 * But of course ... if we have configured WoWLAN then we did other
1382 * things already :-)
1383 */
1384 if (!trans->shrd->wowlan) {
1385 iwl_apm_stop(priv(trans));
1386 } else {
1387 iwl_disable_interrupts(trans);
1388 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1389 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1390 }
1391
1392 return 0;
1393 }
1394
1395 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1396 {
1397 bool hw_rfkill = false;
1398
1399 iwl_enable_interrupts(trans);
1400
1401 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1402 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1403 hw_rfkill = true;
1404
1405 if (hw_rfkill)
1406 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1407 else
1408 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1409
1410 iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1411
1412 return 0;
1413 }
1414 #endif /* CONFIG_PM_SLEEP */
1415
1416 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1417 enum iwl_rxon_context_id ctx)
1418 {
1419 u8 ac, txq_id;
1420 struct iwl_trans_pcie *trans_pcie =
1421 IWL_TRANS_GET_PCIE_TRANS(trans);
1422
1423 for (ac = 0; ac < AC_NUM; ac++) {
1424 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1425 IWL_DEBUG_INFO(trans, "Queue Status: Q[%d] %s\n",
1426 ac,
1427 (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1428 ? "stopped" : "awake");
1429 iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1430 }
1431 }
1432
1433 const struct iwl_trans_ops trans_ops_pcie;
1434
1435 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1436 {
1437 struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1438 sizeof(struct iwl_trans_pcie),
1439 GFP_KERNEL);
1440 if (iwl_trans) {
1441 struct iwl_trans_pcie *trans_pcie =
1442 IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1443 iwl_trans->ops = &trans_ops_pcie;
1444 iwl_trans->shrd = shrd;
1445 trans_pcie->trans = iwl_trans;
1446 spin_lock_init(&iwl_trans->hcmd_lock);
1447 }
1448
1449 return iwl_trans;
1450 }
1451
1452 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id)
1453 {
1454 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1455
1456 iwl_stop_queue(trans, &trans_pcie->txq[txq_id]);
1457 }
1458
1459 #define IWL_FLUSH_WAIT_MS 2000
1460
1461 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1462 {
1463 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1464 struct iwl_tx_queue *txq;
1465 struct iwl_queue *q;
1466 int cnt;
1467 unsigned long now = jiffies;
1468 int ret = 0;
1469
1470 /* waiting for all the tx frames complete might take a while */
1471 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1472 if (cnt == trans->shrd->cmd_queue)
1473 continue;
1474 txq = &trans_pcie->txq[cnt];
1475 q = &txq->q;
1476 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1477 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1478 msleep(1);
1479
1480 if (q->read_ptr != q->write_ptr) {
1481 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1482 ret = -ETIMEDOUT;
1483 break;
1484 }
1485 }
1486 return ret;
1487 }
1488
1489 /*
1490 * On every watchdog tick we check (latest) time stamp. If it does not
1491 * change during timeout period and queue is not empty we reset firmware.
1492 */
1493 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1494 {
1495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1496 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1497 struct iwl_queue *q = &txq->q;
1498 unsigned long timeout;
1499
1500 if (q->read_ptr == q->write_ptr) {
1501 txq->time_stamp = jiffies;
1502 return 0;
1503 }
1504
1505 timeout = txq->time_stamp +
1506 msecs_to_jiffies(hw_params(trans).wd_timeout);
1507
1508 if (time_after(jiffies, timeout)) {
1509 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1510 hw_params(trans).wd_timeout);
1511 IWL_ERR(trans, "Current read_ptr %d write_ptr %d\n",
1512 q->read_ptr, q->write_ptr);
1513 return 1;
1514 }
1515
1516 return 0;
1517 }
1518
1519 static const char *get_fh_string(int cmd)
1520 {
1521 switch (cmd) {
1522 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1523 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1524 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1525 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1526 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1527 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1528 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1529 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1530 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1531 default:
1532 return "UNKNOWN";
1533 }
1534 }
1535
1536 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1537 {
1538 int i;
1539 #ifdef CONFIG_IWLWIFI_DEBUG
1540 int pos = 0;
1541 size_t bufsz = 0;
1542 #endif
1543 static const u32 fh_tbl[] = {
1544 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1545 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1546 FH_RSCSR_CHNL0_WPTR,
1547 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1548 FH_MEM_RSSR_SHARED_CTRL_REG,
1549 FH_MEM_RSSR_RX_STATUS_REG,
1550 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1551 FH_TSSR_TX_STATUS_REG,
1552 FH_TSSR_TX_ERROR_REG
1553 };
1554 #ifdef CONFIG_IWLWIFI_DEBUG
1555 if (display) {
1556 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1557 *buf = kmalloc(bufsz, GFP_KERNEL);
1558 if (!*buf)
1559 return -ENOMEM;
1560 pos += scnprintf(*buf + pos, bufsz - pos,
1561 "FH register values:\n");
1562 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1563 pos += scnprintf(*buf + pos, bufsz - pos,
1564 " %34s: 0X%08x\n",
1565 get_fh_string(fh_tbl[i]),
1566 iwl_read_direct32(bus(trans), fh_tbl[i]));
1567 }
1568 return pos;
1569 }
1570 #endif
1571 IWL_ERR(trans, "FH register values:\n");
1572 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1573 IWL_ERR(trans, " %34s: 0X%08x\n",
1574 get_fh_string(fh_tbl[i]),
1575 iwl_read_direct32(bus(trans), fh_tbl[i]));
1576 }
1577 return 0;
1578 }
1579
1580 static const char *get_csr_string(int cmd)
1581 {
1582 switch (cmd) {
1583 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1584 IWL_CMD(CSR_INT_COALESCING);
1585 IWL_CMD(CSR_INT);
1586 IWL_CMD(CSR_INT_MASK);
1587 IWL_CMD(CSR_FH_INT_STATUS);
1588 IWL_CMD(CSR_GPIO_IN);
1589 IWL_CMD(CSR_RESET);
1590 IWL_CMD(CSR_GP_CNTRL);
1591 IWL_CMD(CSR_HW_REV);
1592 IWL_CMD(CSR_EEPROM_REG);
1593 IWL_CMD(CSR_EEPROM_GP);
1594 IWL_CMD(CSR_OTP_GP_REG);
1595 IWL_CMD(CSR_GIO_REG);
1596 IWL_CMD(CSR_GP_UCODE_REG);
1597 IWL_CMD(CSR_GP_DRIVER_REG);
1598 IWL_CMD(CSR_UCODE_DRV_GP1);
1599 IWL_CMD(CSR_UCODE_DRV_GP2);
1600 IWL_CMD(CSR_LED_REG);
1601 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1602 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1603 IWL_CMD(CSR_ANA_PLL_CFG);
1604 IWL_CMD(CSR_HW_REV_WA_REG);
1605 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1606 default:
1607 return "UNKNOWN";
1608 }
1609 }
1610
1611 void iwl_dump_csr(struct iwl_trans *trans)
1612 {
1613 int i;
1614 static const u32 csr_tbl[] = {
1615 CSR_HW_IF_CONFIG_REG,
1616 CSR_INT_COALESCING,
1617 CSR_INT,
1618 CSR_INT_MASK,
1619 CSR_FH_INT_STATUS,
1620 CSR_GPIO_IN,
1621 CSR_RESET,
1622 CSR_GP_CNTRL,
1623 CSR_HW_REV,
1624 CSR_EEPROM_REG,
1625 CSR_EEPROM_GP,
1626 CSR_OTP_GP_REG,
1627 CSR_GIO_REG,
1628 CSR_GP_UCODE_REG,
1629 CSR_GP_DRIVER_REG,
1630 CSR_UCODE_DRV_GP1,
1631 CSR_UCODE_DRV_GP2,
1632 CSR_LED_REG,
1633 CSR_DRAM_INT_TBL_REG,
1634 CSR_GIO_CHICKEN_BITS,
1635 CSR_ANA_PLL_CFG,
1636 CSR_HW_REV_WA_REG,
1637 CSR_DBG_HPET_MEM_REG
1638 };
1639 IWL_ERR(trans, "CSR values:\n");
1640 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1641 "CSR_INT_PERIODIC_REG)\n");
1642 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1643 IWL_ERR(trans, " %25s: 0X%08x\n",
1644 get_csr_string(csr_tbl[i]),
1645 iwl_read32(bus(trans), csr_tbl[i]));
1646 }
1647 }
1648
1649 #ifdef CONFIG_IWLWIFI_DEBUGFS
1650 /* create and remove of files */
1651 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1652 if (!debugfs_create_file(#name, mode, parent, trans, \
1653 &iwl_dbgfs_##name##_ops)) \
1654 return -ENOMEM; \
1655 } while (0)
1656
1657 /* file operation */
1658 #define DEBUGFS_READ_FUNC(name) \
1659 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1660 char __user *user_buf, \
1661 size_t count, loff_t *ppos);
1662
1663 #define DEBUGFS_WRITE_FUNC(name) \
1664 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1665 const char __user *user_buf, \
1666 size_t count, loff_t *ppos);
1667
1668
1669 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1670 {
1671 file->private_data = inode->i_private;
1672 return 0;
1673 }
1674
1675 #define DEBUGFS_READ_FILE_OPS(name) \
1676 DEBUGFS_READ_FUNC(name); \
1677 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1678 .read = iwl_dbgfs_##name##_read, \
1679 .open = iwl_dbgfs_open_file_generic, \
1680 .llseek = generic_file_llseek, \
1681 };
1682
1683 #define DEBUGFS_WRITE_FILE_OPS(name) \
1684 DEBUGFS_WRITE_FUNC(name); \
1685 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1686 .write = iwl_dbgfs_##name##_write, \
1687 .open = iwl_dbgfs_open_file_generic, \
1688 .llseek = generic_file_llseek, \
1689 };
1690
1691 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1692 DEBUGFS_READ_FUNC(name); \
1693 DEBUGFS_WRITE_FUNC(name); \
1694 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1695 .write = iwl_dbgfs_##name##_write, \
1696 .read = iwl_dbgfs_##name##_read, \
1697 .open = iwl_dbgfs_open_file_generic, \
1698 .llseek = generic_file_llseek, \
1699 };
1700
1701 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1702 char __user *user_buf,
1703 size_t count, loff_t *ppos)
1704 {
1705 struct iwl_trans *trans = file->private_data;
1706 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1707 struct iwl_tx_queue *txq;
1708 struct iwl_queue *q;
1709 char *buf;
1710 int pos = 0;
1711 int cnt;
1712 int ret;
1713 const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1714
1715 if (!trans_pcie->txq) {
1716 IWL_ERR(trans, "txq not ready\n");
1717 return -EAGAIN;
1718 }
1719 buf = kzalloc(bufsz, GFP_KERNEL);
1720 if (!buf)
1721 return -ENOMEM;
1722
1723 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1724 txq = &trans_pcie->txq[cnt];
1725 q = &txq->q;
1726 pos += scnprintf(buf + pos, bufsz - pos,
1727 "hwq %.2d: read=%u write=%u stop=%d"
1728 " swq_id=%#.2x (ac %d/hwq %d)\n",
1729 cnt, q->read_ptr, q->write_ptr,
1730 !!test_bit(cnt, trans_pcie->queue_stopped),
1731 txq->swq_id, txq->swq_id & 3,
1732 (txq->swq_id >> 2) & 0x1f);
1733 if (cnt >= 4)
1734 continue;
1735 /* for the ACs, display the stop count too */
1736 pos += scnprintf(buf + pos, bufsz - pos,
1737 " stop-count: %d\n",
1738 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1739 }
1740 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1741 kfree(buf);
1742 return ret;
1743 }
1744
1745 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1746 char __user *user_buf,
1747 size_t count, loff_t *ppos) {
1748 struct iwl_trans *trans = file->private_data;
1749 struct iwl_trans_pcie *trans_pcie =
1750 IWL_TRANS_GET_PCIE_TRANS(trans);
1751 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1752 char buf[256];
1753 int pos = 0;
1754 const size_t bufsz = sizeof(buf);
1755
1756 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1757 rxq->read);
1758 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1759 rxq->write);
1760 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1761 rxq->free_count);
1762 if (rxq->rb_stts) {
1763 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1764 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1765 } else {
1766 pos += scnprintf(buf + pos, bufsz - pos,
1767 "closed_rb_num: Not Allocated\n");
1768 }
1769 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1770 }
1771
1772 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1773 char __user *user_buf,
1774 size_t count, loff_t *ppos)
1775 {
1776 struct iwl_trans *trans = file->private_data;
1777 char *buf;
1778 int pos = 0;
1779 ssize_t ret = -ENOMEM;
1780
1781 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1782 if (buf) {
1783 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1784 kfree(buf);
1785 }
1786 return ret;
1787 }
1788
1789 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1790 const char __user *user_buf,
1791 size_t count, loff_t *ppos)
1792 {
1793 struct iwl_trans *trans = file->private_data;
1794 u32 event_log_flag;
1795 char buf[8];
1796 int buf_size;
1797
1798 memset(buf, 0, sizeof(buf));
1799 buf_size = min(count, sizeof(buf) - 1);
1800 if (copy_from_user(buf, user_buf, buf_size))
1801 return -EFAULT;
1802 if (sscanf(buf, "%d", &event_log_flag) != 1)
1803 return -EFAULT;
1804 if (event_log_flag == 1)
1805 iwl_dump_nic_event_log(trans, true, NULL, false);
1806
1807 return count;
1808 }
1809
1810 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1811 char __user *user_buf,
1812 size_t count, loff_t *ppos) {
1813
1814 struct iwl_trans *trans = file->private_data;
1815 struct iwl_trans_pcie *trans_pcie =
1816 IWL_TRANS_GET_PCIE_TRANS(trans);
1817 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1818
1819 int pos = 0;
1820 char *buf;
1821 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1822 ssize_t ret;
1823
1824 buf = kzalloc(bufsz, GFP_KERNEL);
1825 if (!buf) {
1826 IWL_ERR(trans, "Can not allocate Buffer\n");
1827 return -ENOMEM;
1828 }
1829
1830 pos += scnprintf(buf + pos, bufsz - pos,
1831 "Interrupt Statistics Report:\n");
1832
1833 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1834 isr_stats->hw);
1835 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1836 isr_stats->sw);
1837 if (isr_stats->sw || isr_stats->hw) {
1838 pos += scnprintf(buf + pos, bufsz - pos,
1839 "\tLast Restarting Code: 0x%X\n",
1840 isr_stats->err_code);
1841 }
1842 #ifdef CONFIG_IWLWIFI_DEBUG
1843 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1844 isr_stats->sch);
1845 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1846 isr_stats->alive);
1847 #endif
1848 pos += scnprintf(buf + pos, bufsz - pos,
1849 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1850
1851 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1852 isr_stats->ctkill);
1853
1854 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1855 isr_stats->wakeup);
1856
1857 pos += scnprintf(buf + pos, bufsz - pos,
1858 "Rx command responses:\t\t %u\n", isr_stats->rx);
1859
1860 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1861 isr_stats->tx);
1862
1863 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1864 isr_stats->unhandled);
1865
1866 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1867 kfree(buf);
1868 return ret;
1869 }
1870
1871 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1872 const char __user *user_buf,
1873 size_t count, loff_t *ppos)
1874 {
1875 struct iwl_trans *trans = file->private_data;
1876 struct iwl_trans_pcie *trans_pcie =
1877 IWL_TRANS_GET_PCIE_TRANS(trans);
1878 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1879
1880 char buf[8];
1881 int buf_size;
1882 u32 reset_flag;
1883
1884 memset(buf, 0, sizeof(buf));
1885 buf_size = min(count, sizeof(buf) - 1);
1886 if (copy_from_user(buf, user_buf, buf_size))
1887 return -EFAULT;
1888 if (sscanf(buf, "%x", &reset_flag) != 1)
1889 return -EFAULT;
1890 if (reset_flag == 0)
1891 memset(isr_stats, 0, sizeof(*isr_stats));
1892
1893 return count;
1894 }
1895
1896 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1897 const char __user *user_buf,
1898 size_t count, loff_t *ppos)
1899 {
1900 struct iwl_trans *trans = file->private_data;
1901 char buf[8];
1902 int buf_size;
1903 int csr;
1904
1905 memset(buf, 0, sizeof(buf));
1906 buf_size = min(count, sizeof(buf) - 1);
1907 if (copy_from_user(buf, user_buf, buf_size))
1908 return -EFAULT;
1909 if (sscanf(buf, "%d", &csr) != 1)
1910 return -EFAULT;
1911
1912 iwl_dump_csr(trans);
1913
1914 return count;
1915 }
1916
1917 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1918 char __user *user_buf,
1919 size_t count, loff_t *ppos)
1920 {
1921 struct iwl_trans *trans = file->private_data;
1922 char *buf;
1923 int pos = 0;
1924 ssize_t ret = -EFAULT;
1925
1926 ret = pos = iwl_dump_fh(trans, &buf, true);
1927 if (buf) {
1928 ret = simple_read_from_buffer(user_buf,
1929 count, ppos, buf, pos);
1930 kfree(buf);
1931 }
1932
1933 return ret;
1934 }
1935
1936 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1937 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1938 DEBUGFS_READ_FILE_OPS(fh_reg);
1939 DEBUGFS_READ_FILE_OPS(rx_queue);
1940 DEBUGFS_READ_FILE_OPS(tx_queue);
1941 DEBUGFS_WRITE_FILE_OPS(csr);
1942
1943 /*
1944 * Create the debugfs files and directories
1945 *
1946 */
1947 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1948 struct dentry *dir)
1949 {
1950 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1951 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1952 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1953 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1954 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1955 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1956 return 0;
1957 }
1958 #else
1959 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1960 struct dentry *dir)
1961 { return 0; }
1962
1963 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1964
1965 const struct iwl_trans_ops trans_ops_pcie = {
1966 .alloc = iwl_trans_pcie_alloc,
1967 .request_irq = iwl_trans_pcie_request_irq,
1968 .start_device = iwl_trans_pcie_start_device,
1969 .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1970 .stop_device = iwl_trans_pcie_stop_device,
1971
1972 .tx_start = iwl_trans_pcie_tx_start,
1973 .wake_any_queue = iwl_trans_pcie_wake_any_queue,
1974
1975 .send_cmd = iwl_trans_pcie_send_cmd,
1976
1977 .tx = iwl_trans_pcie_tx,
1978 .reclaim = iwl_trans_pcie_reclaim,
1979
1980 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
1981 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
1982 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
1983
1984 .kick_nic = iwl_trans_pcie_kick_nic,
1985
1986 .free = iwl_trans_pcie_free,
1987 .stop_queue = iwl_trans_pcie_stop_queue,
1988
1989 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1990
1991 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
1992 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
1993
1994 #ifdef CONFIG_PM_SLEEP
1995 .suspend = iwl_trans_pcie_suspend,
1996 .resume = iwl_trans_pcie_resume,
1997 #endif
1998 };
Linux kernel - Deliverables
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