1 /******************************************************************************
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <net/mac80211.h>
32 #include "iwl-eeprom.h"
37 #include "iwl-helpers.h"
39 static const u16 default_tid_to_tx_fifo
[] = {
59 static inline int iwl_alloc_dma_ptr(struct iwl_priv
*priv
,
60 struct iwl_dma_ptr
*ptr
, size_t size
)
62 ptr
->addr
= pci_alloc_consistent(priv
->pci_dev
, size
, &ptr
->dma
);
69 static inline void iwl_free_dma_ptr(struct iwl_priv
*priv
,
70 struct iwl_dma_ptr
*ptr
)
72 if (unlikely(!ptr
->addr
))
75 pci_free_consistent(priv
->pci_dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
76 memset(ptr
, 0, sizeof(*ptr
));
80 * iwl_txq_update_write_ptr - Send new write index to hardware
82 int iwl_txq_update_write_ptr(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
86 int txq_id
= txq
->q
.id
;
88 if (txq
->need_update
== 0)
91 /* if we're trying to save power */
92 if (test_bit(STATUS_POWER_PMI
, &priv
->status
)) {
93 /* wake up nic if it's powered down ...
94 * uCode will wake up, and interrupt us again, so next
95 * time we'll skip this part. */
96 reg
= iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
98 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
99 IWL_DEBUG_INFO(priv
, "Requesting wakeup, GP1 = 0x%x\n", reg
);
100 iwl_set_bit(priv
, CSR_GP_CNTRL
,
101 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
105 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
106 txq
->q
.write_ptr
| (txq_id
<< 8));
108 /* else not in power-save mode, uCode will never sleep when we're
109 * trying to tx (during RFKILL, we're not trying to tx). */
111 iwl_write32(priv
, HBUS_TARG_WRPTR
,
112 txq
->q
.write_ptr
| (txq_id
<< 8));
114 txq
->need_update
= 0;
118 EXPORT_SYMBOL(iwl_txq_update_write_ptr
);
122 * iwl_tx_queue_free - Deallocate DMA queue.
123 * @txq: Transmit queue to deallocate.
125 * Empty queue by removing and destroying all BD's.
127 * 0-fill, but do not free "txq" descriptor structure.
129 void iwl_tx_queue_free(struct iwl_priv
*priv
, int txq_id
)
131 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
132 struct iwl_queue
*q
= &txq
->q
;
133 struct pci_dev
*dev
= priv
->pci_dev
;
139 /* first, empty all BD's */
140 for (; q
->write_ptr
!= q
->read_ptr
;
141 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
))
142 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
144 len
= sizeof(struct iwl_device_cmd
) * q
->n_window
;
146 /* De-alloc array of command/tx buffers */
147 for (i
= 0; i
< TFD_TX_CMD_SLOTS
; i
++)
150 /* De-alloc circular buffer of TFDs */
152 pci_free_consistent(dev
, priv
->hw_params
.tfd_size
*
153 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
155 /* De-alloc array of per-TFD driver data */
159 /* deallocate arrays */
165 /* 0-fill queue descriptor structure */
166 memset(txq
, 0, sizeof(*txq
));
168 EXPORT_SYMBOL(iwl_tx_queue_free
);
171 * iwl_cmd_queue_free - Deallocate DMA queue.
172 * @txq: Transmit queue to deallocate.
174 * Empty queue by removing and destroying all BD's.
176 * 0-fill, but do not free "txq" descriptor structure.
178 void iwl_cmd_queue_free(struct iwl_priv
*priv
)
180 struct iwl_tx_queue
*txq
= &priv
->txq
[IWL_CMD_QUEUE_NUM
];
181 struct iwl_queue
*q
= &txq
->q
;
182 struct pci_dev
*dev
= priv
->pci_dev
;
188 len
= sizeof(struct iwl_device_cmd
) * q
->n_window
;
189 len
+= IWL_MAX_SCAN_SIZE
;
191 /* De-alloc array of command/tx buffers */
192 for (i
= 0; i
<= TFD_CMD_SLOTS
; i
++)
195 /* De-alloc circular buffer of TFDs */
197 pci_free_consistent(dev
, priv
->hw_params
.tfd_size
*
198 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
200 /* 0-fill queue descriptor structure */
201 memset(txq
, 0, sizeof(*txq
));
203 EXPORT_SYMBOL(iwl_cmd_queue_free
);
205 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
208 * Theory of operation
210 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
211 * of buffer descriptors, each of which points to one or more data buffers for
212 * the device to read from or fill. Driver and device exchange status of each
213 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
214 * entries in each circular buffer, to protect against confusing empty and full
217 * The device reads or writes the data in the queues via the device's several
218 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
220 * For Tx queue, there are low mark and high mark limits. If, after queuing
221 * the packet for Tx, free space become < low mark, Tx queue stopped. When
222 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
225 * See more detailed info in iwl-4965-hw.h.
226 ***************************************************/
228 int iwl_queue_space(const struct iwl_queue
*q
)
230 int s
= q
->read_ptr
- q
->write_ptr
;
232 if (q
->read_ptr
> q
->write_ptr
)
237 /* keep some reserve to not confuse empty and full situations */
243 EXPORT_SYMBOL(iwl_queue_space
);
247 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
249 static int iwl_queue_init(struct iwl_priv
*priv
, struct iwl_queue
*q
,
250 int count
, int slots_num
, u32 id
)
253 q
->n_window
= slots_num
;
256 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
257 * and iwl_queue_dec_wrap are broken. */
258 BUG_ON(!is_power_of_2(count
));
260 /* slots_num must be power-of-two size, otherwise
261 * get_cmd_index is broken. */
262 BUG_ON(!is_power_of_2(slots_num
));
264 q
->low_mark
= q
->n_window
/ 4;
268 q
->high_mark
= q
->n_window
/ 8;
269 if (q
->high_mark
< 2)
272 q
->write_ptr
= q
->read_ptr
= 0;
278 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
280 static int iwl_tx_queue_alloc(struct iwl_priv
*priv
,
281 struct iwl_tx_queue
*txq
, u32 id
)
283 struct pci_dev
*dev
= priv
->pci_dev
;
284 size_t tfd_sz
= priv
->hw_params
.tfd_size
* TFD_QUEUE_SIZE_MAX
;
286 /* Driver private data, only for Tx (not command) queues,
287 * not shared with device. */
288 if (id
!= IWL_CMD_QUEUE_NUM
) {
289 txq
->txb
= kmalloc(sizeof(txq
->txb
[0]) *
290 TFD_QUEUE_SIZE_MAX
, GFP_KERNEL
);
292 IWL_ERR(priv
, "kmalloc for auxiliary BD "
293 "structures failed\n");
300 /* Circular buffer of transmit frame descriptors (TFDs),
301 * shared with device */
302 txq
->tfds
= pci_alloc_consistent(dev
, tfd_sz
, &txq
->q
.dma_addr
);
305 IWL_ERR(priv
, "pci_alloc_consistent(%zd) failed\n", tfd_sz
);
320 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
322 int iwl_tx_queue_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
323 int slots_num
, u32 txq_id
)
327 int actual_slots
= slots_num
;
330 * Alloc buffer array for commands (Tx or other types of commands).
331 * For the command queue (#4), allocate command space + one big
332 * command for scan, since scan command is very huge; the system will
333 * not have two scans at the same time, so only one is needed.
334 * For normal Tx queues (all other queues), no super-size command
337 if (txq_id
== IWL_CMD_QUEUE_NUM
)
340 txq
->meta
= kzalloc(sizeof(struct iwl_cmd_meta
) * actual_slots
,
342 txq
->cmd
= kzalloc(sizeof(struct iwl_device_cmd
*) * actual_slots
,
345 if (!txq
->meta
|| !txq
->cmd
)
346 goto out_free_arrays
;
348 len
= sizeof(struct iwl_device_cmd
);
349 for (i
= 0; i
< actual_slots
; i
++) {
350 /* only happens for cmd queue */
352 len
+= IWL_MAX_SCAN_SIZE
;
354 txq
->cmd
[i
] = kmalloc(len
, GFP_KERNEL
);
359 /* Alloc driver data array and TFD circular buffer */
360 ret
= iwl_tx_queue_alloc(priv
, txq
, txq_id
);
364 txq
->need_update
= 0;
366 /* aggregation TX queues will get their ID when aggregation begins */
367 if (txq_id
<= IWL_TX_FIFO_AC3
)
368 txq
->swq_id
= txq_id
;
370 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
371 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
372 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
374 /* Initialize queue's high/low-water marks, and head/tail indexes */
375 iwl_queue_init(priv
, &txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
, txq_id
);
377 /* Tell device where to find queue */
378 priv
->cfg
->ops
->lib
->txq_init(priv
, txq
);
382 for (i
= 0; i
< actual_slots
; i
++)
390 EXPORT_SYMBOL(iwl_tx_queue_init
);
393 * iwl_hw_txq_ctx_free - Free TXQ Context
395 * Destroy all TX DMA queues and structures
397 void iwl_hw_txq_ctx_free(struct iwl_priv
*priv
)
402 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
403 if (txq_id
== IWL_CMD_QUEUE_NUM
)
404 iwl_cmd_queue_free(priv
);
406 iwl_tx_queue_free(priv
, txq_id
);
408 iwl_free_dma_ptr(priv
, &priv
->kw
);
410 iwl_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
412 EXPORT_SYMBOL(iwl_hw_txq_ctx_free
);
415 * iwl_txq_ctx_reset - Reset TX queue context
416 * Destroys all DMA structures and initialize them again
421 int iwl_txq_ctx_reset(struct iwl_priv
*priv
)
424 int txq_id
, slots_num
;
427 /* Free all tx/cmd queues and keep-warm buffer */
428 iwl_hw_txq_ctx_free(priv
);
430 ret
= iwl_alloc_dma_ptr(priv
, &priv
->scd_bc_tbls
,
431 priv
->hw_params
.scd_bc_tbls_size
);
433 IWL_ERR(priv
, "Scheduler BC Table allocation failed\n");
436 /* Alloc keep-warm buffer */
437 ret
= iwl_alloc_dma_ptr(priv
, &priv
->kw
, IWL_KW_SIZE
);
439 IWL_ERR(priv
, "Keep Warm allocation failed\n");
442 spin_lock_irqsave(&priv
->lock
, flags
);
444 /* Turn off all Tx DMA fifos */
445 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
447 /* Tell NIC where to find the "keep warm" buffer */
448 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
, priv
->kw
.dma
>> 4);
450 spin_unlock_irqrestore(&priv
->lock
, flags
);
452 /* Alloc and init all Tx queues, including the command queue (#4) */
453 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
454 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
455 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
456 ret
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
459 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
467 iwl_hw_txq_ctx_free(priv
);
468 iwl_free_dma_ptr(priv
, &priv
->kw
);
470 iwl_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
476 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
478 void iwl_txq_ctx_stop(struct iwl_priv
*priv
)
483 /* Turn off all Tx DMA fifos */
484 spin_lock_irqsave(&priv
->lock
, flags
);
486 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
488 /* Stop each Tx DMA channel, and wait for it to be idle */
489 for (ch
= 0; ch
< priv
->hw_params
.dma_chnl_num
; ch
++) {
490 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
491 iwl_poll_direct_bit(priv
, FH_TSSR_TX_STATUS_REG
,
492 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
495 spin_unlock_irqrestore(&priv
->lock
, flags
);
497 /* Deallocate memory for all Tx queues */
498 iwl_hw_txq_ctx_free(priv
);
500 EXPORT_SYMBOL(iwl_txq_ctx_stop
);
503 * handle build REPLY_TX command notification.
505 static void iwl_tx_cmd_build_basic(struct iwl_priv
*priv
,
506 struct iwl_tx_cmd
*tx_cmd
,
507 struct ieee80211_tx_info
*info
,
508 struct ieee80211_hdr
*hdr
,
511 __le16 fc
= hdr
->frame_control
;
512 __le32 tx_flags
= tx_cmd
->tx_flags
;
514 tx_cmd
->stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
515 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
)) {
516 tx_flags
|= TX_CMD_FLG_ACK_MSK
;
517 if (ieee80211_is_mgmt(fc
))
518 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
519 if (ieee80211_is_probe_resp(fc
) &&
520 !(le16_to_cpu(hdr
->seq_ctrl
) & 0xf))
521 tx_flags
|= TX_CMD_FLG_TSF_MSK
;
523 tx_flags
&= (~TX_CMD_FLG_ACK_MSK
);
524 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
527 if (ieee80211_is_back_req(fc
))
528 tx_flags
|= TX_CMD_FLG_ACK_MSK
| TX_CMD_FLG_IMM_BA_RSP_MASK
;
531 tx_cmd
->sta_id
= std_id
;
532 if (ieee80211_has_morefrags(fc
))
533 tx_flags
|= TX_CMD_FLG_MORE_FRAG_MSK
;
535 if (ieee80211_is_data_qos(fc
)) {
536 u8
*qc
= ieee80211_get_qos_ctl(hdr
);
537 tx_cmd
->tid_tspec
= qc
[0] & 0xf;
538 tx_flags
&= ~TX_CMD_FLG_SEQ_CTL_MSK
;
540 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
543 priv
->cfg
->ops
->utils
->rts_tx_cmd_flag(info
, &tx_flags
);
545 if ((tx_flags
& TX_CMD_FLG_RTS_MSK
) || (tx_flags
& TX_CMD_FLG_CTS_MSK
))
546 tx_flags
|= TX_CMD_FLG_FULL_TXOP_PROT_MSK
;
548 tx_flags
&= ~(TX_CMD_FLG_ANT_SEL_MSK
);
549 if (ieee80211_is_mgmt(fc
)) {
550 if (ieee80211_is_assoc_req(fc
) || ieee80211_is_reassoc_req(fc
))
551 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(3);
553 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(2);
555 tx_cmd
->timeout
.pm_frame_timeout
= 0;
558 tx_cmd
->driver_txop
= 0;
559 tx_cmd
->tx_flags
= tx_flags
;
560 tx_cmd
->next_frame_len
= 0;
563 #define RTS_HCCA_RETRY_LIMIT 3
564 #define RTS_DFAULT_RETRY_LIMIT 60
566 static void iwl_tx_cmd_build_rate(struct iwl_priv
*priv
,
567 struct iwl_tx_cmd
*tx_cmd
,
568 struct ieee80211_tx_info
*info
,
569 __le16 fc
, int sta_id
,
574 u8 rts_retry_limit
= 0;
575 u8 data_retry_limit
= 0;
578 rate_idx
= min(ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
& 0xffff,
581 rate_plcp
= iwl_rates
[rate_idx
].plcp
;
583 rts_retry_limit
= (is_hcca
) ?
584 RTS_HCCA_RETRY_LIMIT
: RTS_DFAULT_RETRY_LIMIT
;
586 if ((rate_idx
>= IWL_FIRST_CCK_RATE
) && (rate_idx
<= IWL_LAST_CCK_RATE
))
587 rate_flags
|= RATE_MCS_CCK_MSK
;
590 if (ieee80211_is_probe_resp(fc
)) {
591 data_retry_limit
= 3;
592 if (data_retry_limit
< rts_retry_limit
)
593 rts_retry_limit
= data_retry_limit
;
595 data_retry_limit
= IWL_DEFAULT_TX_RETRY
;
597 if (priv
->data_retry_limit
!= -1)
598 data_retry_limit
= priv
->data_retry_limit
;
601 if (ieee80211_is_data(fc
)) {
602 tx_cmd
->initial_rate_index
= 0;
603 tx_cmd
->tx_flags
|= TX_CMD_FLG_STA_RATE_MSK
;
605 switch (fc
& cpu_to_le16(IEEE80211_FCTL_STYPE
)) {
606 case cpu_to_le16(IEEE80211_STYPE_AUTH
):
607 case cpu_to_le16(IEEE80211_STYPE_DEAUTH
):
608 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ
):
609 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ
):
610 if (tx_cmd
->tx_flags
& TX_CMD_FLG_RTS_MSK
) {
611 tx_cmd
->tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
612 tx_cmd
->tx_flags
|= TX_CMD_FLG_CTS_MSK
;
619 priv
->mgmt_tx_ant
= iwl_toggle_tx_ant(priv
, priv
->mgmt_tx_ant
);
620 rate_flags
|= iwl_ant_idx_to_flags(priv
->mgmt_tx_ant
);
623 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
624 tx_cmd
->data_retry_limit
= data_retry_limit
;
625 tx_cmd
->rate_n_flags
= iwl_hw_set_rate_n_flags(rate_plcp
, rate_flags
);
628 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv
*priv
,
629 struct ieee80211_tx_info
*info
,
630 struct iwl_tx_cmd
*tx_cmd
,
631 struct sk_buff
*skb_frag
,
634 struct ieee80211_key_conf
*keyconf
= info
->control
.hw_key
;
636 switch (keyconf
->alg
) {
638 tx_cmd
->sec_ctl
= TX_CMD_SEC_CCM
;
639 memcpy(tx_cmd
->key
, keyconf
->key
, keyconf
->keylen
);
640 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
641 tx_cmd
->tx_flags
|= TX_CMD_FLG_AGG_CCMP_MSK
;
642 IWL_DEBUG_TX(priv
, "tx_cmd with AES hwcrypto\n");
646 tx_cmd
->sec_ctl
= TX_CMD_SEC_TKIP
;
647 ieee80211_get_tkip_key(keyconf
, skb_frag
,
648 IEEE80211_TKIP_P2_KEY
, tx_cmd
->key
);
649 IWL_DEBUG_TX(priv
, "tx_cmd with tkip hwcrypto\n");
653 tx_cmd
->sec_ctl
|= (TX_CMD_SEC_WEP
|
654 (keyconf
->keyidx
& TX_CMD_SEC_MSK
) << TX_CMD_SEC_SHIFT
);
656 if (keyconf
->keylen
== WEP_KEY_LEN_128
)
657 tx_cmd
->sec_ctl
|= TX_CMD_SEC_KEY128
;
659 memcpy(&tx_cmd
->key
[3], keyconf
->key
, keyconf
->keylen
);
661 IWL_DEBUG_TX(priv
, "Configuring packet for WEP encryption "
662 "with key %d\n", keyconf
->keyidx
);
666 IWL_ERR(priv
, "Unknown encode alg %d\n", keyconf
->alg
);
672 * start REPLY_TX command process
674 int iwl_tx_skb(struct iwl_priv
*priv
, struct sk_buff
*skb
)
676 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
677 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
678 struct iwl_tx_queue
*txq
;
680 struct iwl_device_cmd
*out_cmd
;
681 struct iwl_cmd_meta
*out_meta
;
682 struct iwl_tx_cmd
*tx_cmd
;
684 dma_addr_t phys_addr
;
685 dma_addr_t txcmd_phys
;
686 dma_addr_t scratch_phys
;
692 u8 wait_write_ptr
= 0;
698 spin_lock_irqsave(&priv
->lock
, flags
);
699 if (iwl_is_rfkill(priv
)) {
700 IWL_DEBUG_DROP(priv
, "Dropping - RF KILL\n");
704 if ((ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
& 0xFF) ==
706 IWL_ERR(priv
, "ERROR: No TX rate available.\n");
710 fc
= hdr
->frame_control
;
712 #ifdef CONFIG_IWLWIFI_DEBUG
713 if (ieee80211_is_auth(fc
))
714 IWL_DEBUG_TX(priv
, "Sending AUTH frame\n");
715 else if (ieee80211_is_assoc_req(fc
))
716 IWL_DEBUG_TX(priv
, "Sending ASSOC frame\n");
717 else if (ieee80211_is_reassoc_req(fc
))
718 IWL_DEBUG_TX(priv
, "Sending REASSOC frame\n");
721 /* drop all non-injected data frame if we are not associated */
722 if (ieee80211_is_data(fc
) &&
723 !(info
->flags
& IEEE80211_TX_CTL_INJECTED
) &&
724 (!iwl_is_associated(priv
) ||
725 ((priv
->iw_mode
== NL80211_IFTYPE_STATION
) && !priv
->assoc_id
) ||
726 !priv
->assoc_station_added
)) {
727 IWL_DEBUG_DROP(priv
, "Dropping - !iwl_is_associated\n");
731 hdr_len
= ieee80211_hdrlen(fc
);
733 /* Find (or create) index into station table for destination station */
734 if (info
->flags
& IEEE80211_TX_CTL_INJECTED
)
735 sta_id
= priv
->hw_params
.bcast_sta_id
;
737 sta_id
= iwl_get_sta_id(priv
, hdr
);
738 if (sta_id
== IWL_INVALID_STATION
) {
739 IWL_DEBUG_DROP(priv
, "Dropping - INVALID STATION: %pM\n",
744 IWL_DEBUG_TX(priv
, "station Id %d\n", sta_id
);
746 txq_id
= skb_get_queue_mapping(skb
);
747 if (ieee80211_is_data_qos(fc
)) {
748 qc
= ieee80211_get_qos_ctl(hdr
);
749 tid
= qc
[0] & IEEE80211_QOS_CTL_TID_MASK
;
750 if (unlikely(tid
>= MAX_TID_COUNT
))
752 seq_number
= priv
->stations
[sta_id
].tid
[tid
].seq_number
;
753 seq_number
&= IEEE80211_SCTL_SEQ
;
754 hdr
->seq_ctrl
= hdr
->seq_ctrl
&
755 cpu_to_le16(IEEE80211_SCTL_FRAG
);
756 hdr
->seq_ctrl
|= cpu_to_le16(seq_number
);
758 /* aggregation is on for this <sta,tid> */
759 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
760 txq_id
= priv
->stations
[sta_id
].tid
[tid
].agg
.txq_id
;
763 txq
= &priv
->txq
[txq_id
];
764 swq_id
= txq
->swq_id
;
767 if (unlikely(iwl_queue_space(q
) < q
->high_mark
))
770 if (ieee80211_is_data_qos(fc
))
771 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
++;
773 /* Set up driver data for this TFD */
774 memset(&(txq
->txb
[q
->write_ptr
]), 0, sizeof(struct iwl_tx_info
));
775 txq
->txb
[q
->write_ptr
].skb
[0] = skb
;
777 /* Set up first empty entry in queue's array of Tx/cmd buffers */
778 out_cmd
= txq
->cmd
[q
->write_ptr
];
779 out_meta
= &txq
->meta
[q
->write_ptr
];
780 tx_cmd
= &out_cmd
->cmd
.tx
;
781 memset(&out_cmd
->hdr
, 0, sizeof(out_cmd
->hdr
));
782 memset(tx_cmd
, 0, sizeof(struct iwl_tx_cmd
));
785 * Set up the Tx-command (not MAC!) header.
786 * Store the chosen Tx queue and TFD index within the sequence field;
787 * after Tx, uCode's Tx response will return this value so driver can
788 * locate the frame within the tx queue and do post-tx processing.
790 out_cmd
->hdr
.cmd
= REPLY_TX
;
791 out_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
792 INDEX_TO_SEQ(q
->write_ptr
)));
794 /* Copy MAC header from skb into command buffer */
795 memcpy(tx_cmd
->hdr
, hdr
, hdr_len
);
798 /* Total # bytes to be transmitted */
800 tx_cmd
->len
= cpu_to_le16(len
);
802 if (info
->control
.hw_key
)
803 iwl_tx_cmd_build_hwcrypto(priv
, info
, tx_cmd
, skb
, sta_id
);
805 /* TODO need this for burst mode later on */
806 iwl_tx_cmd_build_basic(priv
, tx_cmd
, info
, hdr
, sta_id
);
807 iwl_dbg_log_tx_data_frame(priv
, len
, hdr
);
809 /* set is_hcca to 0; it probably will never be implemented */
810 iwl_tx_cmd_build_rate(priv
, tx_cmd
, info
, fc
, sta_id
, 0);
812 iwl_update_stats(priv
, true, fc
, len
);
814 * Use the first empty entry in this queue's command buffer array
815 * to contain the Tx command and MAC header concatenated together
816 * (payload data will be in another buffer).
817 * Size of this varies, due to varying MAC header length.
818 * If end is not dword aligned, we'll have 2 extra bytes at the end
819 * of the MAC header (device reads on dword boundaries).
820 * We'll tell device about this padding later.
822 len
= sizeof(struct iwl_tx_cmd
) +
823 sizeof(struct iwl_cmd_header
) + hdr_len
;
826 len
= (len
+ 3) & ~3;
833 /* Tell NIC about any 2-byte padding after MAC header */
835 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
837 /* Physical address of this Tx command's header (not MAC header!),
838 * within command buffer array. */
839 txcmd_phys
= pci_map_single(priv
->pci_dev
,
841 PCI_DMA_BIDIRECTIONAL
);
842 pci_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
843 pci_unmap_len_set(out_meta
, len
, len
);
844 /* Add buffer containing Tx command and MAC(!) header to TFD's
846 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
847 txcmd_phys
, len
, 1, 0);
849 if (!ieee80211_has_morefrags(hdr
->frame_control
)) {
850 txq
->need_update
= 1;
852 priv
->stations
[sta_id
].tid
[tid
].seq_number
= seq_number
;
855 txq
->need_update
= 0;
858 /* Set up TFD's 2nd entry to point directly to remainder of skb,
859 * if any (802.11 null frames have no payload). */
860 len
= skb
->len
- hdr_len
;
862 phys_addr
= pci_map_single(priv
->pci_dev
, skb
->data
+ hdr_len
,
863 len
, PCI_DMA_TODEVICE
);
864 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
869 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
870 offsetof(struct iwl_tx_cmd
, scratch
);
872 len
= sizeof(struct iwl_tx_cmd
) +
873 sizeof(struct iwl_cmd_header
) + hdr_len
;
874 /* take back ownership of DMA buffer to enable update */
875 pci_dma_sync_single_for_cpu(priv
->pci_dev
, txcmd_phys
,
876 len
, PCI_DMA_BIDIRECTIONAL
);
877 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
878 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
880 IWL_DEBUG_TX(priv
, "sequence nr = 0X%x \n",
881 le16_to_cpu(out_cmd
->hdr
.sequence
));
882 IWL_DEBUG_TX(priv
, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd
->tx_flags
));
883 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
884 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
886 /* Set up entry for this TFD in Tx byte-count array */
887 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
888 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
,
889 le16_to_cpu(tx_cmd
->len
));
891 pci_dma_sync_single_for_device(priv
->pci_dev
, txcmd_phys
,
892 len
, PCI_DMA_BIDIRECTIONAL
);
894 /* Tell device the write index *just past* this latest filled TFD */
895 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
896 ret
= iwl_txq_update_write_ptr(priv
, txq
);
897 spin_unlock_irqrestore(&priv
->lock
, flags
);
902 if ((iwl_queue_space(q
) < q
->high_mark
) && priv
->mac80211_registered
) {
903 if (wait_write_ptr
) {
904 spin_lock_irqsave(&priv
->lock
, flags
);
905 txq
->need_update
= 1;
906 iwl_txq_update_write_ptr(priv
, txq
);
907 spin_unlock_irqrestore(&priv
->lock
, flags
);
909 iwl_stop_queue(priv
, txq
->swq_id
);
916 spin_unlock_irqrestore(&priv
->lock
, flags
);
919 EXPORT_SYMBOL(iwl_tx_skb
);
921 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
924 * iwl_enqueue_hcmd - enqueue a uCode command
925 * @priv: device private data point
926 * @cmd: a point to the ucode command structure
928 * The function returns < 0 values to indicate the operation is
929 * failed. On success, it turns the index (> 0) of command in the
932 int iwl_enqueue_hcmd(struct iwl_priv
*priv
, struct iwl_host_cmd
*cmd
)
934 struct iwl_tx_queue
*txq
= &priv
->txq
[IWL_CMD_QUEUE_NUM
];
935 struct iwl_queue
*q
= &txq
->q
;
936 struct iwl_device_cmd
*out_cmd
;
937 struct iwl_cmd_meta
*out_meta
;
938 dma_addr_t phys_addr
;
944 cmd
->len
= priv
->cfg
->ops
->utils
->get_hcmd_size(cmd
->id
, cmd
->len
);
945 fix_size
= (u16
)(cmd
->len
+ sizeof(out_cmd
->hdr
));
947 /* If any of the command structures end up being larger than
948 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
949 * we will need to increase the size of the TFD entries */
950 BUG_ON((fix_size
> TFD_MAX_PAYLOAD_SIZE
) &&
951 !(cmd
->flags
& CMD_SIZE_HUGE
));
953 if (iwl_is_rfkill(priv
)) {
954 IWL_DEBUG_INFO(priv
, "Not sending command - RF KILL\n");
958 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
959 IWL_ERR(priv
, "No space for Tx\n");
963 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
965 idx
= get_cmd_index(q
, q
->write_ptr
, cmd
->flags
& CMD_SIZE_HUGE
);
966 out_cmd
= txq
->cmd
[idx
];
967 out_meta
= &txq
->meta
[idx
];
969 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
970 out_meta
->flags
= cmd
->flags
;
971 if (cmd
->flags
& CMD_WANT_SKB
)
972 out_meta
->source
= cmd
;
973 if (cmd
->flags
& CMD_ASYNC
)
974 out_meta
->callback
= cmd
->callback
;
976 out_cmd
->hdr
.cmd
= cmd
->id
;
977 memcpy(&out_cmd
->cmd
.payload
, cmd
->data
, cmd
->len
);
979 /* At this point, the out_cmd now has all of the incoming cmd
982 out_cmd
->hdr
.flags
= 0;
983 out_cmd
->hdr
.sequence
= cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM
) |
984 INDEX_TO_SEQ(q
->write_ptr
));
985 if (cmd
->flags
& CMD_SIZE_HUGE
)
986 out_cmd
->hdr
.sequence
|= SEQ_HUGE_FRAME
;
987 len
= sizeof(struct iwl_device_cmd
);
988 len
+= (idx
== TFD_CMD_SLOTS
) ? IWL_MAX_SCAN_SIZE
: 0;
991 #ifdef CONFIG_IWLWIFI_DEBUG
992 switch (out_cmd
->hdr
.cmd
) {
993 case REPLY_TX_LINK_QUALITY_CMD
:
994 case SENSITIVITY_CMD
:
995 IWL_DEBUG_HC_DUMP(priv
, "Sending command %s (#%x), seq: 0x%04X, "
996 "%d bytes at %d[%d]:%d\n",
997 get_cmd_string(out_cmd
->hdr
.cmd
),
999 le16_to_cpu(out_cmd
->hdr
.sequence
), fix_size
,
1000 q
->write_ptr
, idx
, IWL_CMD_QUEUE_NUM
);
1003 IWL_DEBUG_HC(priv
, "Sending command %s (#%x), seq: 0x%04X, "
1004 "%d bytes at %d[%d]:%d\n",
1005 get_cmd_string(out_cmd
->hdr
.cmd
),
1007 le16_to_cpu(out_cmd
->hdr
.sequence
), fix_size
,
1008 q
->write_ptr
, idx
, IWL_CMD_QUEUE_NUM
);
1011 txq
->need_update
= 1;
1013 if (priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl
)
1014 /* Set up entry in queue's byte count circular buffer */
1015 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
, 0);
1017 phys_addr
= pci_map_single(priv
->pci_dev
, &out_cmd
->hdr
,
1018 fix_size
, PCI_DMA_BIDIRECTIONAL
);
1019 pci_unmap_addr_set(out_meta
, mapping
, phys_addr
);
1020 pci_unmap_len_set(out_meta
, len
, fix_size
);
1022 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
1023 phys_addr
, fix_size
, 1,
1026 /* Increment and update queue's write index */
1027 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1028 ret
= iwl_txq_update_write_ptr(priv
, txq
);
1030 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
1031 return ret
? ret
: idx
;
1034 int iwl_tx_queue_reclaim(struct iwl_priv
*priv
, int txq_id
, int index
)
1036 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1037 struct iwl_queue
*q
= &txq
->q
;
1038 struct iwl_tx_info
*tx_info
;
1041 if ((index
>= q
->n_bd
) || (iwl_queue_used(q
, index
) == 0)) {
1042 IWL_ERR(priv
, "Read index for DMA queue txq id (%d), index %d, "
1043 "is out of range [0-%d] %d %d.\n", txq_id
,
1044 index
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1048 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
);
1049 q
->read_ptr
!= index
;
1050 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1052 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
1053 ieee80211_tx_status_irqsafe(priv
->hw
, tx_info
->skb
[0]);
1054 tx_info
->skb
[0] = NULL
;
1056 if (priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl
)
1057 priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl(priv
, txq
);
1059 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
1064 EXPORT_SYMBOL(iwl_tx_queue_reclaim
);
1068 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1070 * When FW advances 'R' index, all entries between old and new 'R' index
1071 * need to be reclaimed. As result, some free space forms. If there is
1072 * enough free space (> low mark), wake the stack that feeds us.
1074 static void iwl_hcmd_queue_reclaim(struct iwl_priv
*priv
, int txq_id
,
1075 int idx
, int cmd_idx
)
1077 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1078 struct iwl_queue
*q
= &txq
->q
;
1081 if ((idx
>= q
->n_bd
) || (iwl_queue_used(q
, idx
) == 0)) {
1082 IWL_ERR(priv
, "Read index for DMA queue txq id (%d), index %d, "
1083 "is out of range [0-%d] %d %d.\n", txq_id
,
1084 idx
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1088 pci_unmap_single(priv
->pci_dev
,
1089 pci_unmap_addr(&txq
->meta
[cmd_idx
], mapping
),
1090 pci_unmap_len(&txq
->meta
[cmd_idx
], len
),
1091 PCI_DMA_BIDIRECTIONAL
);
1093 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
1094 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1097 IWL_ERR(priv
, "HCMD skipped: index (%d) %d %d\n", idx
,
1098 q
->write_ptr
, q
->read_ptr
);
1099 queue_work(priv
->workqueue
, &priv
->restart
);
1106 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1107 * @rxb: Rx buffer to reclaim
1109 * If an Rx buffer has an async callback associated with it the callback
1110 * will be executed. The attached skb (if present) will only be freed
1111 * if the callback returns 1
1113 void iwl_tx_cmd_complete(struct iwl_priv
*priv
, struct iwl_rx_mem_buffer
*rxb
)
1115 struct iwl_rx_packet
*pkt
= (struct iwl_rx_packet
*)rxb
->skb
->data
;
1116 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1117 int txq_id
= SEQ_TO_QUEUE(sequence
);
1118 int index
= SEQ_TO_INDEX(sequence
);
1120 bool huge
= !!(pkt
->hdr
.sequence
& SEQ_HUGE_FRAME
);
1121 struct iwl_device_cmd
*cmd
;
1122 struct iwl_cmd_meta
*meta
;
1124 /* If a Tx command is being handled and it isn't in the actual
1125 * command queue then there a command routing bug has been introduced
1126 * in the queue management code. */
1127 if (WARN(txq_id
!= IWL_CMD_QUEUE_NUM
,
1128 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1130 priv
->txq
[IWL_CMD_QUEUE_NUM
].q
.read_ptr
,
1131 priv
->txq
[IWL_CMD_QUEUE_NUM
].q
.write_ptr
)) {
1132 iwl_print_hex_error(priv
, pkt
, 32);
1136 cmd_index
= get_cmd_index(&priv
->txq
[IWL_CMD_QUEUE_NUM
].q
, index
, huge
);
1137 cmd
= priv
->txq
[IWL_CMD_QUEUE_NUM
].cmd
[cmd_index
];
1138 meta
= &priv
->txq
[IWL_CMD_QUEUE_NUM
].meta
[cmd_index
];
1140 /* Input error checking is done when commands are added to queue. */
1141 if (meta
->flags
& CMD_WANT_SKB
) {
1142 meta
->source
->reply_skb
= rxb
->skb
;
1144 } else if (meta
->callback
)
1145 meta
->callback(priv
, cmd
, rxb
->skb
);
1147 iwl_hcmd_queue_reclaim(priv
, txq_id
, index
, cmd_index
);
1149 if (!(meta
->flags
& CMD_ASYNC
)) {
1150 clear_bit(STATUS_HCMD_ACTIVE
, &priv
->status
);
1151 wake_up_interruptible(&priv
->wait_command_queue
);
1154 EXPORT_SYMBOL(iwl_tx_cmd_complete
);
1157 * Find first available (lowest unused) Tx Queue, mark it "active".
1158 * Called only when finding queue for aggregation.
1159 * Should never return anything < 7, because they should already
1160 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1162 static int iwl_txq_ctx_activate_free(struct iwl_priv
*priv
)
1166 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
1167 if (!test_and_set_bit(txq_id
, &priv
->txq_ctx_active_msk
))
1172 int iwl_tx_agg_start(struct iwl_priv
*priv
, const u8
*ra
, u16 tid
, u16
*ssn
)
1178 unsigned long flags
;
1179 struct iwl_tid_data
*tid_data
;
1181 if (likely(tid
< ARRAY_SIZE(default_tid_to_tx_fifo
)))
1182 tx_fifo
= default_tid_to_tx_fifo
[tid
];
1186 IWL_WARN(priv
, "%s on ra = %pM tid = %d\n",
1189 sta_id
= iwl_find_station(priv
, ra
);
1190 if (sta_id
== IWL_INVALID_STATION
) {
1191 IWL_ERR(priv
, "Start AGG on invalid station\n");
1194 if (unlikely(tid
>= MAX_TID_COUNT
))
1197 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_OFF
) {
1198 IWL_ERR(priv
, "Start AGG when state is not IWL_AGG_OFF !\n");
1202 txq_id
= iwl_txq_ctx_activate_free(priv
);
1204 IWL_ERR(priv
, "No free aggregation queue available\n");
1208 spin_lock_irqsave(&priv
->sta_lock
, flags
);
1209 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1210 *ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1211 tid_data
->agg
.txq_id
= txq_id
;
1212 priv
->txq
[txq_id
].swq_id
= iwl_virtual_agg_queue_num(tx_fifo
, txq_id
);
1213 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
1215 ret
= priv
->cfg
->ops
->lib
->txq_agg_enable(priv
, txq_id
, tx_fifo
,
1220 if (tid_data
->tfds_in_queue
== 0) {
1221 IWL_DEBUG_HT(priv
, "HW queue is empty\n");
1222 tid_data
->agg
.state
= IWL_AGG_ON
;
1223 ieee80211_start_tx_ba_cb_irqsafe(priv
->hw
, ra
, tid
);
1225 IWL_DEBUG_HT(priv
, "HW queue is NOT empty: %d packets in HW queue\n",
1226 tid_data
->tfds_in_queue
);
1227 tid_data
->agg
.state
= IWL_EMPTYING_HW_QUEUE_ADDBA
;
1231 EXPORT_SYMBOL(iwl_tx_agg_start
);
1233 int iwl_tx_agg_stop(struct iwl_priv
*priv
, const u8
*ra
, u16 tid
)
1235 int tx_fifo_id
, txq_id
, sta_id
, ssn
= -1;
1236 struct iwl_tid_data
*tid_data
;
1237 int ret
, write_ptr
, read_ptr
;
1238 unsigned long flags
;
1241 IWL_ERR(priv
, "ra = NULL\n");
1245 if (unlikely(tid
>= MAX_TID_COUNT
))
1248 if (likely(tid
< ARRAY_SIZE(default_tid_to_tx_fifo
)))
1249 tx_fifo_id
= default_tid_to_tx_fifo
[tid
];
1253 sta_id
= iwl_find_station(priv
, ra
);
1255 if (sta_id
== IWL_INVALID_STATION
) {
1256 IWL_ERR(priv
, "Invalid station for AGG tid %d\n", tid
);
1260 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_ON
)
1261 IWL_WARN(priv
, "Stopping AGG while state not IWL_AGG_ON\n");
1263 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1264 ssn
= (tid_data
->seq_number
& IEEE80211_SCTL_SEQ
) >> 4;
1265 txq_id
= tid_data
->agg
.txq_id
;
1266 write_ptr
= priv
->txq
[txq_id
].q
.write_ptr
;
1267 read_ptr
= priv
->txq
[txq_id
].q
.read_ptr
;
1269 /* The queue is not empty */
1270 if (write_ptr
!= read_ptr
) {
1271 IWL_DEBUG_HT(priv
, "Stopping a non empty AGG HW QUEUE\n");
1272 priv
->stations
[sta_id
].tid
[tid
].agg
.state
=
1273 IWL_EMPTYING_HW_QUEUE_DELBA
;
1277 IWL_DEBUG_HT(priv
, "HW queue is empty\n");
1278 priv
->stations
[sta_id
].tid
[tid
].agg
.state
= IWL_AGG_OFF
;
1280 spin_lock_irqsave(&priv
->lock
, flags
);
1281 ret
= priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
, ssn
,
1283 spin_unlock_irqrestore(&priv
->lock
, flags
);
1288 ieee80211_stop_tx_ba_cb_irqsafe(priv
->hw
, ra
, tid
);
1292 EXPORT_SYMBOL(iwl_tx_agg_stop
);
1294 int iwl_txq_check_empty(struct iwl_priv
*priv
, int sta_id
, u8 tid
, int txq_id
)
1296 struct iwl_queue
*q
= &priv
->txq
[txq_id
].q
;
1297 u8
*addr
= priv
->stations
[sta_id
].sta
.sta
.addr
;
1298 struct iwl_tid_data
*tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1300 switch (priv
->stations
[sta_id
].tid
[tid
].agg
.state
) {
1301 case IWL_EMPTYING_HW_QUEUE_DELBA
:
1302 /* We are reclaiming the last packet of the */
1303 /* aggregated HW queue */
1304 if ((txq_id
== tid_data
->agg
.txq_id
) &&
1305 (q
->read_ptr
== q
->write_ptr
)) {
1306 u16 ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1307 int tx_fifo
= default_tid_to_tx_fifo
[tid
];
1308 IWL_DEBUG_HT(priv
, "HW queue empty: continue DELBA flow\n");
1309 priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
,
1311 tid_data
->agg
.state
= IWL_AGG_OFF
;
1312 ieee80211_stop_tx_ba_cb_irqsafe(priv
->hw
, addr
, tid
);
1315 case IWL_EMPTYING_HW_QUEUE_ADDBA
:
1316 /* We are reclaiming the last packet of the queue */
1317 if (tid_data
->tfds_in_queue
== 0) {
1318 IWL_DEBUG_HT(priv
, "HW queue empty: continue ADDBA flow\n");
1319 tid_data
->agg
.state
= IWL_AGG_ON
;
1320 ieee80211_start_tx_ba_cb_irqsafe(priv
->hw
, addr
, tid
);
1326 EXPORT_SYMBOL(iwl_txq_check_empty
);
1329 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1331 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1332 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1334 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv
*priv
,
1335 struct iwl_ht_agg
*agg
,
1336 struct iwl_compressed_ba_resp
*ba_resp
)
1340 u16 seq_ctl
= le16_to_cpu(ba_resp
->seq_ctl
);
1341 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1344 struct ieee80211_tx_info
*info
;
1346 if (unlikely(!agg
->wait_for_ba
)) {
1347 IWL_ERR(priv
, "Received BA when not expected\n");
1351 /* Mark that the expected block-ack response arrived */
1352 agg
->wait_for_ba
= 0;
1353 IWL_DEBUG_TX_REPLY(priv
, "BA %d %d\n", agg
->start_idx
, ba_resp
->seq_ctl
);
1355 /* Calculate shift to align block-ack bits with our Tx window bits */
1356 sh
= agg
->start_idx
- SEQ_TO_INDEX(seq_ctl
>> 4);
1357 if (sh
< 0) /* tbw something is wrong with indices */
1360 /* don't use 64-bit values for now */
1361 bitmap
= le64_to_cpu(ba_resp
->bitmap
) >> sh
;
1363 if (agg
->frame_count
> (64 - sh
)) {
1364 IWL_DEBUG_TX_REPLY(priv
, "more frames than bitmap size");
1368 /* check for success or failure according to the
1369 * transmitted bitmap and block-ack bitmap */
1370 bitmap
&= agg
->bitmap
;
1372 /* For each frame attempted in aggregation,
1373 * update driver's record of tx frame's status. */
1374 for (i
= 0; i
< agg
->frame_count
; i
++) {
1375 ack
= bitmap
& (1ULL << i
);
1377 IWL_DEBUG_TX_REPLY(priv
, "%s ON i=%d idx=%d raw=%d\n",
1378 ack
? "ACK" : "NACK", i
, (agg
->start_idx
+ i
) & 0xff,
1379 agg
->start_idx
+ i
);
1382 info
= IEEE80211_SKB_CB(priv
->txq
[scd_flow
].txb
[agg
->start_idx
].skb
[0]);
1383 memset(&info
->status
, 0, sizeof(info
->status
));
1384 info
->flags
= IEEE80211_TX_STAT_ACK
;
1385 info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
1386 info
->status
.ampdu_ack_map
= successes
;
1387 info
->status
.ampdu_ack_len
= agg
->frame_count
;
1388 iwl_hwrate_to_tx_control(priv
, agg
->rate_n_flags
, info
);
1390 IWL_DEBUG_TX_REPLY(priv
, "Bitmap %llx\n", (unsigned long long)bitmap
);
1396 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1398 * Handles block-acknowledge notification from device, which reports success
1399 * of frames sent via aggregation.
1401 void iwl_rx_reply_compressed_ba(struct iwl_priv
*priv
,
1402 struct iwl_rx_mem_buffer
*rxb
)
1404 struct iwl_rx_packet
*pkt
= (struct iwl_rx_packet
*)rxb
->skb
->data
;
1405 struct iwl_compressed_ba_resp
*ba_resp
= &pkt
->u
.compressed_ba
;
1406 struct iwl_tx_queue
*txq
= NULL
;
1407 struct iwl_ht_agg
*agg
;
1412 /* "flow" corresponds to Tx queue */
1413 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1415 /* "ssn" is start of block-ack Tx window, corresponds to index
1416 * (in Tx queue's circular buffer) of first TFD/frame in window */
1417 u16 ba_resp_scd_ssn
= le16_to_cpu(ba_resp
->scd_ssn
);
1419 if (scd_flow
>= priv
->hw_params
.max_txq_num
) {
1421 "BUG_ON scd_flow is bigger than number of queues\n");
1425 txq
= &priv
->txq
[scd_flow
];
1426 sta_id
= ba_resp
->sta_id
;
1428 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
1430 /* Find index just before block-ack window */
1431 index
= iwl_queue_dec_wrap(ba_resp_scd_ssn
& 0xff, txq
->q
.n_bd
);
1433 /* TODO: Need to get this copy more safely - now good for debug */
1435 IWL_DEBUG_TX_REPLY(priv
, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1438 (u8
*) &ba_resp
->sta_addr_lo32
,
1440 IWL_DEBUG_TX_REPLY(priv
, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1441 "%d, scd_ssn = %d\n",
1444 (unsigned long long)le64_to_cpu(ba_resp
->bitmap
),
1447 IWL_DEBUG_TX_REPLY(priv
, "DAT start_idx = %d, bitmap = 0x%llx \n",
1449 (unsigned long long)agg
->bitmap
);
1451 /* Update driver's record of ACK vs. not for each frame in window */
1452 iwl_tx_status_reply_compressed_ba(priv
, agg
, ba_resp
);
1454 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1455 * block-ack window (we assume that they've been successfully
1456 * transmitted ... if not, it's too late anyway). */
1457 if (txq
->q
.read_ptr
!= (ba_resp_scd_ssn
& 0xff)) {
1458 /* calculate mac80211 ampdu sw queue to wake */
1459 int freed
= iwl_tx_queue_reclaim(priv
, scd_flow
, index
);
1460 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1462 if ((iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
) &&
1463 priv
->mac80211_registered
&&
1464 (agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
))
1465 iwl_wake_queue(priv
, txq
->swq_id
);
1467 iwl_txq_check_empty(priv
, sta_id
, tid
, scd_flow
);
1470 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba
);
1472 #ifdef CONFIG_IWLWIFI_DEBUG
1473 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1475 const char *iwl_get_tx_fail_reason(u32 status
)
1477 switch (status
& TX_STATUS_MSK
) {
1478 case TX_STATUS_SUCCESS
:
1480 TX_STATUS_ENTRY(SHORT_LIMIT
);
1481 TX_STATUS_ENTRY(LONG_LIMIT
);
1482 TX_STATUS_ENTRY(FIFO_UNDERRUN
);
1483 TX_STATUS_ENTRY(MGMNT_ABORT
);
1484 TX_STATUS_ENTRY(NEXT_FRAG
);
1485 TX_STATUS_ENTRY(LIFE_EXPIRE
);
1486 TX_STATUS_ENTRY(DEST_PS
);
1487 TX_STATUS_ENTRY(ABORTED
);
1488 TX_STATUS_ENTRY(BT_RETRY
);
1489 TX_STATUS_ENTRY(STA_INVALID
);
1490 TX_STATUS_ENTRY(FRAG_DROPPED
);
1491 TX_STATUS_ENTRY(TID_DISABLE
);
1492 TX_STATUS_ENTRY(FRAME_FLUSHED
);
1493 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL
);
1494 TX_STATUS_ENTRY(TX_LOCKED
);
1495 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR
);
1500 EXPORT_SYMBOL(iwl_get_tx_fail_reason
);
1501 #endif /* CONFIG_IWLWIFI_DEBUG */