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Merge tag 'regulator-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-drv.h"
72 #include "iwl-trans.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-agn-hw.h"
76 #include "internal.h"
77
78 static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
79 u32 reg, u32 mask, u32 value)
80 {
81 u32 v;
82
83 #ifdef CONFIG_IWLWIFI_DEBUG
84 WARN_ON_ONCE(value & ~mask);
85 #endif
86
87 v = iwl_read32(trans, reg);
88 v &= ~mask;
89 v |= value;
90 iwl_write32(trans, reg, v);
91 }
92
93 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
94 u32 reg, u32 mask)
95 {
96 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
97 }
98
99 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
100 u32 reg, u32 mask)
101 {
102 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
103 }
104
105 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
106 {
107 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
108 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
109 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
110 ~APMG_PS_CTRL_MSK_PWR_SRC);
111 else
112 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
113 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
114 ~APMG_PS_CTRL_MSK_PWR_SRC);
115 }
116
117 /* PCI registers */
118 #define PCI_CFG_RETRY_TIMEOUT 0x041
119
120 static void iwl_pcie_apm_config(struct iwl_trans *trans)
121 {
122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
123 u16 lctl;
124
125 /*
126 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
127 * Check if BIOS (or OS) enabled L1-ASPM on this device.
128 * If so (likely), disable L0S, so device moves directly L0->L1;
129 * costs negligible amount of power savings.
130 * If not (unlikely), enable L0S, so there is at least some
131 * power savings, even without L1.
132 */
133 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
134 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
135 /* L1-ASPM enabled; disable(!) L0S */
136 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
137 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
138 } else {
139 /* L1-ASPM disabled; enable(!) L0S */
140 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
141 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
142 }
143 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
144 }
145
146 /*
147 * Start up NIC's basic functionality after it has been reset
148 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
149 * NOTE: This does not load uCode nor start the embedded processor
150 */
151 static int iwl_pcie_apm_init(struct iwl_trans *trans)
152 {
153 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
154 int ret = 0;
155 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
156
157 /*
158 * Use "set_bit" below rather than "write", to preserve any hardware
159 * bits already set by default after reset.
160 */
161
162 /* Disable L0S exit timer (platform NMI Work/Around) */
163 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
164 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
165
166 /*
167 * Disable L0s without affecting L1;
168 * don't wait for ICH L0s (ICH bug W/A)
169 */
170 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
171 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
172
173 /* Set FH wait threshold to maximum (HW error during stress W/A) */
174 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
175
176 /*
177 * Enable HAP INTA (interrupt from management bus) to
178 * wake device's PCI Express link L1a -> L0s
179 */
180 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
181 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
182
183 iwl_pcie_apm_config(trans);
184
185 /* Configure analog phase-lock-loop before activating to D0A */
186 if (trans->cfg->base_params->pll_cfg_val)
187 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
188 trans->cfg->base_params->pll_cfg_val);
189
190 /*
191 * Set "initialization complete" bit to move adapter from
192 * D0U* --> D0A* (powered-up active) state.
193 */
194 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
195
196 /*
197 * Wait for clock stabilization; once stabilized, access to
198 * device-internal resources is supported, e.g. iwl_write_prph()
199 * and accesses to uCode SRAM.
200 */
201 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
202 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
203 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
204 if (ret < 0) {
205 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
206 goto out;
207 }
208
209 /*
210 * Enable DMA clock and wait for it to stabilize.
211 *
212 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
213 * do not disable clocks. This preserves any hardware bits already
214 * set by default in "CLK_CTRL_REG" after reset.
215 */
216 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
217 udelay(20);
218
219 /* Disable L1-Active */
220 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
221 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
222
223 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
224
225 out:
226 return ret;
227 }
228
229 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
230 {
231 int ret = 0;
232
233 /* stop device's busmaster DMA activity */
234 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
235
236 ret = iwl_poll_bit(trans, CSR_RESET,
237 CSR_RESET_REG_FLAG_MASTER_DISABLED,
238 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
239 if (ret)
240 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
241
242 IWL_DEBUG_INFO(trans, "stop master\n");
243
244 return ret;
245 }
246
247 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
248 {
249 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
250 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
251
252 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
253
254 /* Stop device's DMA activity */
255 iwl_pcie_apm_stop_master(trans);
256
257 /* Reset the entire device */
258 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
259
260 udelay(10);
261
262 /*
263 * Clear "initialization complete" bit to move adapter from
264 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
265 */
266 iwl_clear_bit(trans, CSR_GP_CNTRL,
267 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
268 }
269
270 static int iwl_pcie_nic_init(struct iwl_trans *trans)
271 {
272 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
273 unsigned long flags;
274
275 /* nic_init */
276 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
277 iwl_pcie_apm_init(trans);
278
279 /* Set interrupt coalescing calibration timer to default (512 usecs) */
280 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
281
282 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
283
284 iwl_pcie_set_pwr(trans, false);
285
286 iwl_op_mode_nic_config(trans->op_mode);
287
288 /* Allocate the RX queue, or reset if it is already allocated */
289 iwl_pcie_rx_init(trans);
290
291 /* Allocate or reset and init all Tx and Command queues */
292 if (iwl_pcie_tx_init(trans))
293 return -ENOMEM;
294
295 if (trans->cfg->base_params->shadow_reg_enable) {
296 /* enable shadow regs in HW */
297 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
298 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
299 }
300
301 return 0;
302 }
303
304 #define HW_READY_TIMEOUT (50)
305
306 /* Note: returns poll_bit return value, which is >= 0 if success */
307 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
308 {
309 int ret;
310
311 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
312 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
313
314 /* See if we got it */
315 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
316 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
317 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
318 HW_READY_TIMEOUT);
319
320 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
321 return ret;
322 }
323
324 /* Note: returns standard 0/-ERROR code */
325 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
326 {
327 int ret;
328 int t = 0;
329
330 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
331
332 ret = iwl_pcie_set_hw_ready(trans);
333 /* If the card is ready, exit 0 */
334 if (ret >= 0)
335 return 0;
336
337 /* If HW is not ready, prepare the conditions to check again */
338 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
339 CSR_HW_IF_CONFIG_REG_PREPARE);
340
341 do {
342 ret = iwl_pcie_set_hw_ready(trans);
343 if (ret >= 0)
344 return 0;
345
346 usleep_range(200, 1000);
347 t += 200;
348 } while (t < 150000);
349
350 return ret;
351 }
352
353 /*
354 * ucode
355 */
356 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
357 dma_addr_t phy_addr, u32 byte_cnt)
358 {
359 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
360 int ret;
361
362 trans_pcie->ucode_write_complete = false;
363
364 iwl_write_direct32(trans,
365 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
366 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
367
368 iwl_write_direct32(trans,
369 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
370 dst_addr);
371
372 iwl_write_direct32(trans,
373 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
374 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
375
376 iwl_write_direct32(trans,
377 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
378 (iwl_get_dma_hi_addr(phy_addr)
379 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
380
381 iwl_write_direct32(trans,
382 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
383 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
384 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
385 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
386
387 iwl_write_direct32(trans,
388 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
389 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
390 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
391 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
392
393 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
394 trans_pcie->ucode_write_complete, 5 * HZ);
395 if (!ret) {
396 IWL_ERR(trans, "Failed to load firmware chunk!\n");
397 return -ETIMEDOUT;
398 }
399
400 return 0;
401 }
402
403 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
404 const struct fw_desc *section)
405 {
406 u8 *v_addr;
407 dma_addr_t p_addr;
408 u32 offset, chunk_sz = section->len;
409 int ret = 0;
410
411 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
412 section_num);
413
414 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
415 GFP_KERNEL | __GFP_NOWARN);
416 if (!v_addr) {
417 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
418 chunk_sz = PAGE_SIZE;
419 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
420 &p_addr, GFP_KERNEL);
421 if (!v_addr)
422 return -ENOMEM;
423 }
424
425 for (offset = 0; offset < section->len; offset += chunk_sz) {
426 u32 copy_size;
427
428 copy_size = min_t(u32, chunk_sz, section->len - offset);
429
430 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
431 ret = iwl_pcie_load_firmware_chunk(trans,
432 section->offset + offset,
433 p_addr, copy_size);
434 if (ret) {
435 IWL_ERR(trans,
436 "Could not load the [%d] uCode section\n",
437 section_num);
438 break;
439 }
440 }
441
442 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
443 return ret;
444 }
445
446 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
447 const struct fw_img *image)
448 {
449 int i, ret = 0;
450
451 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
452 if (!image->sec[i].data)
453 break;
454
455 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
456 if (ret)
457 return ret;
458 }
459
460 /* Remove all resets to allow NIC to operate */
461 iwl_write32(trans, CSR_RESET, 0);
462
463 return 0;
464 }
465
466 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
467 const struct fw_img *fw, bool run_in_rfkill)
468 {
469 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
470 int ret;
471 bool hw_rfkill;
472
473 /* This may fail if AMT took ownership of the device */
474 if (iwl_pcie_prepare_card_hw(trans)) {
475 IWL_WARN(trans, "Exit HW not ready\n");
476 return -EIO;
477 }
478
479 clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
480
481 iwl_enable_rfkill_int(trans);
482
483 /* If platform's RF_KILL switch is NOT set to KILL */
484 hw_rfkill = iwl_is_rfkill_set(trans);
485 if (hw_rfkill)
486 set_bit(STATUS_RFKILL, &trans_pcie->status);
487 else
488 clear_bit(STATUS_RFKILL, &trans_pcie->status);
489 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
490 if (hw_rfkill && !run_in_rfkill)
491 return -ERFKILL;
492
493 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
494
495 ret = iwl_pcie_nic_init(trans);
496 if (ret) {
497 IWL_ERR(trans, "Unable to init nic\n");
498 return ret;
499 }
500
501 /* make sure rfkill handshake bits are cleared */
502 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
503 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
504 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
505
506 /* clear (again), then enable host interrupts */
507 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
508 iwl_enable_interrupts(trans);
509
510 /* really make sure rfkill handshake bits are cleared */
511 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
512 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
513
514 /* Load the given image to the HW */
515 return iwl_pcie_load_given_ucode(trans, fw);
516 }
517
518 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
519 {
520 iwl_pcie_reset_ict(trans);
521 iwl_pcie_tx_start(trans, scd_addr);
522 }
523
524 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
525 {
526 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
527 unsigned long flags;
528
529 /* tell the device to stop sending interrupts */
530 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
531 iwl_disable_interrupts(trans);
532 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
533
534 /* device going down, Stop using ICT table */
535 iwl_pcie_disable_ict(trans);
536
537 /*
538 * If a HW restart happens during firmware loading,
539 * then the firmware loading might call this function
540 * and later it might be called again due to the
541 * restart. So don't process again if the device is
542 * already dead.
543 */
544 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
545 iwl_pcie_tx_stop(trans);
546 iwl_pcie_rx_stop(trans);
547
548 /* Power-down device's busmaster DMA clocks */
549 iwl_write_prph(trans, APMG_CLK_DIS_REG,
550 APMG_CLK_VAL_DMA_CLK_RQT);
551 udelay(5);
552 }
553
554 /* Make sure (redundant) we've released our request to stay awake */
555 iwl_clear_bit(trans, CSR_GP_CNTRL,
556 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
557
558 /* Stop the device, and put it in low power state */
559 iwl_pcie_apm_stop(trans);
560
561 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
562 * Clean again the interrupt here
563 */
564 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
565 iwl_disable_interrupts(trans);
566 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
567
568 iwl_enable_rfkill_int(trans);
569
570 /* stop and reset the on-board processor */
571 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
572
573 /* clear all status bits */
574 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
575 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
576 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
577 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
578 clear_bit(STATUS_RFKILL, &trans_pcie->status);
579 }
580
581 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
582 {
583 iwl_disable_interrupts(trans);
584
585 /*
586 * in testing mode, the host stays awake and the
587 * hardware won't be reset (not even partially)
588 */
589 if (test)
590 return;
591
592 iwl_pcie_disable_ict(trans);
593
594 iwl_clear_bit(trans, CSR_GP_CNTRL,
595 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
596 iwl_clear_bit(trans, CSR_GP_CNTRL,
597 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
598
599 /*
600 * reset TX queues -- some of their registers reset during S3
601 * so if we don't reset everything here the D3 image would try
602 * to execute some invalid memory upon resume
603 */
604 iwl_trans_pcie_tx_reset(trans);
605
606 iwl_pcie_set_pwr(trans, true);
607 }
608
609 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
610 enum iwl_d3_status *status,
611 bool test)
612 {
613 u32 val;
614 int ret;
615
616 if (test) {
617 iwl_enable_interrupts(trans);
618 *status = IWL_D3_STATUS_ALIVE;
619 return 0;
620 }
621
622 iwl_pcie_set_pwr(trans, false);
623
624 val = iwl_read32(trans, CSR_RESET);
625 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
626 *status = IWL_D3_STATUS_RESET;
627 return 0;
628 }
629
630 /*
631 * Also enables interrupts - none will happen as the device doesn't
632 * know we're waking it up, only when the opmode actually tells it
633 * after this call.
634 */
635 iwl_pcie_reset_ict(trans);
636
637 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
638 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
639
640 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
641 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
642 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
643 25000);
644 if (ret) {
645 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
646 return ret;
647 }
648
649 iwl_trans_pcie_tx_reset(trans);
650
651 ret = iwl_pcie_rx_init(trans);
652 if (ret) {
653 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
654 return ret;
655 }
656
657 *status = IWL_D3_STATUS_ALIVE;
658 return 0;
659 }
660
661 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
662 {
663 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
664 bool hw_rfkill;
665 int err;
666
667 err = iwl_pcie_prepare_card_hw(trans);
668 if (err) {
669 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
670 return err;
671 }
672
673 /* Reset the entire device */
674 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
675
676 usleep_range(10, 15);
677
678 iwl_pcie_apm_init(trans);
679
680 /* From now on, the op_mode will be kept updated about RF kill state */
681 iwl_enable_rfkill_int(trans);
682
683 hw_rfkill = iwl_is_rfkill_set(trans);
684 if (hw_rfkill)
685 set_bit(STATUS_RFKILL, &trans_pcie->status);
686 else
687 clear_bit(STATUS_RFKILL, &trans_pcie->status);
688 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
689
690 return 0;
691 }
692
693 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
694 bool op_mode_leaving)
695 {
696 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
697 bool hw_rfkill;
698 unsigned long flags;
699
700 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
701 iwl_disable_interrupts(trans);
702 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
703
704 iwl_pcie_apm_stop(trans);
705
706 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
707 iwl_disable_interrupts(trans);
708 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
709
710 iwl_pcie_disable_ict(trans);
711
712 if (!op_mode_leaving) {
713 /*
714 * Even if we stop the HW, we still want the RF kill
715 * interrupt
716 */
717 iwl_enable_rfkill_int(trans);
718
719 /*
720 * Check again since the RF kill state may have changed while
721 * all the interrupts were disabled, in this case we couldn't
722 * receive the RF kill interrupt and update the state in the
723 * op_mode.
724 */
725 hw_rfkill = iwl_is_rfkill_set(trans);
726 if (hw_rfkill)
727 set_bit(STATUS_RFKILL, &trans_pcie->status);
728 else
729 clear_bit(STATUS_RFKILL, &trans_pcie->status);
730 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
731 }
732 }
733
734 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
735 {
736 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
737 }
738
739 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
740 {
741 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
742 }
743
744 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
745 {
746 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
747 }
748
749 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
750 {
751 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
752 ((reg & 0x000FFFFF) | (3 << 24)));
753 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
754 }
755
756 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
757 u32 val)
758 {
759 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
760 ((addr & 0x000FFFFF) | (3 << 24)));
761 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
762 }
763
764 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
765 const struct iwl_trans_config *trans_cfg)
766 {
767 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
768
769 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
770 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
771 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
772 trans_pcie->n_no_reclaim_cmds = 0;
773 else
774 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
775 if (trans_pcie->n_no_reclaim_cmds)
776 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
777 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
778
779 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
780 if (trans_pcie->rx_buf_size_8k)
781 trans_pcie->rx_page_order = get_order(8 * 1024);
782 else
783 trans_pcie->rx_page_order = get_order(4 * 1024);
784
785 trans_pcie->wd_timeout =
786 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
787
788 trans_pcie->command_names = trans_cfg->command_names;
789 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
790 }
791
792 void iwl_trans_pcie_free(struct iwl_trans *trans)
793 {
794 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
795
796 synchronize_irq(trans_pcie->pci_dev->irq);
797
798 iwl_pcie_tx_free(trans);
799 iwl_pcie_rx_free(trans);
800
801 free_irq(trans_pcie->pci_dev->irq, trans);
802 iwl_pcie_free_ict(trans);
803
804 pci_disable_msi(trans_pcie->pci_dev);
805 iounmap(trans_pcie->hw_base);
806 pci_release_regions(trans_pcie->pci_dev);
807 pci_disable_device(trans_pcie->pci_dev);
808 kmem_cache_destroy(trans->dev_cmd_pool);
809
810 kfree(trans);
811 }
812
813 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
814 {
815 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
816
817 if (state)
818 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
819 else
820 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
821 }
822
823 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
824 unsigned long *flags)
825 {
826 int ret;
827 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
828
829 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
830
831 /* this bit wakes up the NIC */
832 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
833 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
834
835 /*
836 * These bits say the device is running, and should keep running for
837 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
838 * but they do not indicate that embedded SRAM is restored yet;
839 * 3945 and 4965 have volatile SRAM, and must save/restore contents
840 * to/from host DRAM when sleeping/waking for power-saving.
841 * Each direction takes approximately 1/4 millisecond; with this
842 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
843 * series of register accesses are expected (e.g. reading Event Log),
844 * to keep device from sleeping.
845 *
846 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
847 * SRAM is okay/restored. We don't check that here because this call
848 * is just for hardware register access; but GP1 MAC_SLEEP check is a
849 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
850 *
851 * 5000 series and later (including 1000 series) have non-volatile SRAM,
852 * and do not save/restore SRAM when power cycling.
853 */
854 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
855 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
856 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
857 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
858 if (unlikely(ret < 0)) {
859 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
860 if (!silent) {
861 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
862 WARN_ONCE(1,
863 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
864 val);
865 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
866 return false;
867 }
868 }
869
870 /*
871 * Fool sparse by faking we release the lock - sparse will
872 * track nic_access anyway.
873 */
874 __release(&trans_pcie->reg_lock);
875 return true;
876 }
877
878 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
879 unsigned long *flags)
880 {
881 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
882
883 lockdep_assert_held(&trans_pcie->reg_lock);
884
885 /*
886 * Fool sparse by faking we acquiring the lock - sparse will
887 * track nic_access anyway.
888 */
889 __acquire(&trans_pcie->reg_lock);
890
891 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
892 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
893 /*
894 * Above we read the CSR_GP_CNTRL register, which will flush
895 * any previous writes, but we need the write that clears the
896 * MAC_ACCESS_REQ bit to be performed before any other writes
897 * scheduled on different CPUs (after we drop reg_lock).
898 */
899 mmiowb();
900 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
901 }
902
903 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
904 void *buf, int dwords)
905 {
906 unsigned long flags;
907 int offs, ret = 0;
908 u32 *vals = buf;
909
910 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
911 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
912 for (offs = 0; offs < dwords; offs++)
913 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
914 iwl_trans_release_nic_access(trans, &flags);
915 } else {
916 ret = -EBUSY;
917 }
918 return ret;
919 }
920
921 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
922 const void *buf, int dwords)
923 {
924 unsigned long flags;
925 int offs, ret = 0;
926 const u32 *vals = buf;
927
928 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
929 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
930 for (offs = 0; offs < dwords; offs++)
931 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
932 vals ? vals[offs] : 0);
933 iwl_trans_release_nic_access(trans, &flags);
934 } else {
935 ret = -EBUSY;
936 }
937 return ret;
938 }
939
940 #define IWL_FLUSH_WAIT_MS 2000
941
942 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
943 {
944 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
945 struct iwl_txq *txq;
946 struct iwl_queue *q;
947 int cnt;
948 unsigned long now = jiffies;
949 u32 scd_sram_addr;
950 u8 buf[16];
951 int ret = 0;
952
953 /* waiting for all the tx frames complete might take a while */
954 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
955 if (cnt == trans_pcie->cmd_queue)
956 continue;
957 txq = &trans_pcie->txq[cnt];
958 q = &txq->q;
959 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
960 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
961 msleep(1);
962
963 if (q->read_ptr != q->write_ptr) {
964 IWL_ERR(trans,
965 "fail to flush all tx fifo queues Q %d\n", cnt);
966 ret = -ETIMEDOUT;
967 break;
968 }
969 }
970
971 if (!ret)
972 return 0;
973
974 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
975 txq->q.read_ptr, txq->q.write_ptr);
976
977 scd_sram_addr = trans_pcie->scd_base_addr +
978 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
979 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
980
981 iwl_print_hex_error(trans, buf, sizeof(buf));
982
983 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
984 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
985 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
986
987 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
988 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
989 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
990 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
991 u32 tbl_dw =
992 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
993 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
994
995 if (cnt & 0x1)
996 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
997 else
998 tbl_dw = tbl_dw & 0x0000FFFF;
999
1000 IWL_ERR(trans,
1001 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1002 cnt, active ? "" : "in", fifo, tbl_dw,
1003 iwl_read_prph(trans,
1004 SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1005 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1006 }
1007
1008 return ret;
1009 }
1010
1011 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1012 u32 mask, u32 value)
1013 {
1014 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1015 unsigned long flags;
1016
1017 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1018 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1019 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1020 }
1021
1022 static const char *get_csr_string(int cmd)
1023 {
1024 #define IWL_CMD(x) case x: return #x
1025 switch (cmd) {
1026 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1027 IWL_CMD(CSR_INT_COALESCING);
1028 IWL_CMD(CSR_INT);
1029 IWL_CMD(CSR_INT_MASK);
1030 IWL_CMD(CSR_FH_INT_STATUS);
1031 IWL_CMD(CSR_GPIO_IN);
1032 IWL_CMD(CSR_RESET);
1033 IWL_CMD(CSR_GP_CNTRL);
1034 IWL_CMD(CSR_HW_REV);
1035 IWL_CMD(CSR_EEPROM_REG);
1036 IWL_CMD(CSR_EEPROM_GP);
1037 IWL_CMD(CSR_OTP_GP_REG);
1038 IWL_CMD(CSR_GIO_REG);
1039 IWL_CMD(CSR_GP_UCODE_REG);
1040 IWL_CMD(CSR_GP_DRIVER_REG);
1041 IWL_CMD(CSR_UCODE_DRV_GP1);
1042 IWL_CMD(CSR_UCODE_DRV_GP2);
1043 IWL_CMD(CSR_LED_REG);
1044 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1045 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1046 IWL_CMD(CSR_ANA_PLL_CFG);
1047 IWL_CMD(CSR_HW_REV_WA_REG);
1048 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1049 default:
1050 return "UNKNOWN";
1051 }
1052 #undef IWL_CMD
1053 }
1054
1055 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1056 {
1057 int i;
1058 static const u32 csr_tbl[] = {
1059 CSR_HW_IF_CONFIG_REG,
1060 CSR_INT_COALESCING,
1061 CSR_INT,
1062 CSR_INT_MASK,
1063 CSR_FH_INT_STATUS,
1064 CSR_GPIO_IN,
1065 CSR_RESET,
1066 CSR_GP_CNTRL,
1067 CSR_HW_REV,
1068 CSR_EEPROM_REG,
1069 CSR_EEPROM_GP,
1070 CSR_OTP_GP_REG,
1071 CSR_GIO_REG,
1072 CSR_GP_UCODE_REG,
1073 CSR_GP_DRIVER_REG,
1074 CSR_UCODE_DRV_GP1,
1075 CSR_UCODE_DRV_GP2,
1076 CSR_LED_REG,
1077 CSR_DRAM_INT_TBL_REG,
1078 CSR_GIO_CHICKEN_BITS,
1079 CSR_ANA_PLL_CFG,
1080 CSR_HW_REV_WA_REG,
1081 CSR_DBG_HPET_MEM_REG
1082 };
1083 IWL_ERR(trans, "CSR values:\n");
1084 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1085 "CSR_INT_PERIODIC_REG)\n");
1086 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1087 IWL_ERR(trans, " %25s: 0X%08x\n",
1088 get_csr_string(csr_tbl[i]),
1089 iwl_read32(trans, csr_tbl[i]));
1090 }
1091 }
1092
1093 #ifdef CONFIG_IWLWIFI_DEBUGFS
1094 /* create and remove of files */
1095 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1096 if (!debugfs_create_file(#name, mode, parent, trans, \
1097 &iwl_dbgfs_##name##_ops)) \
1098 goto err; \
1099 } while (0)
1100
1101 /* file operation */
1102 #define DEBUGFS_READ_FILE_OPS(name) \
1103 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1104 .read = iwl_dbgfs_##name##_read, \
1105 .open = simple_open, \
1106 .llseek = generic_file_llseek, \
1107 };
1108
1109 #define DEBUGFS_WRITE_FILE_OPS(name) \
1110 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1111 .write = iwl_dbgfs_##name##_write, \
1112 .open = simple_open, \
1113 .llseek = generic_file_llseek, \
1114 };
1115
1116 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1117 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1118 .write = iwl_dbgfs_##name##_write, \
1119 .read = iwl_dbgfs_##name##_read, \
1120 .open = simple_open, \
1121 .llseek = generic_file_llseek, \
1122 };
1123
1124 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1125 char __user *user_buf,
1126 size_t count, loff_t *ppos)
1127 {
1128 struct iwl_trans *trans = file->private_data;
1129 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1130 struct iwl_txq *txq;
1131 struct iwl_queue *q;
1132 char *buf;
1133 int pos = 0;
1134 int cnt;
1135 int ret;
1136 size_t bufsz;
1137
1138 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1139
1140 if (!trans_pcie->txq)
1141 return -EAGAIN;
1142
1143 buf = kzalloc(bufsz, GFP_KERNEL);
1144 if (!buf)
1145 return -ENOMEM;
1146
1147 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1148 txq = &trans_pcie->txq[cnt];
1149 q = &txq->q;
1150 pos += scnprintf(buf + pos, bufsz - pos,
1151 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1152 cnt, q->read_ptr, q->write_ptr,
1153 !!test_bit(cnt, trans_pcie->queue_used),
1154 !!test_bit(cnt, trans_pcie->queue_stopped));
1155 }
1156 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1157 kfree(buf);
1158 return ret;
1159 }
1160
1161 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1162 char __user *user_buf,
1163 size_t count, loff_t *ppos)
1164 {
1165 struct iwl_trans *trans = file->private_data;
1166 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1167 struct iwl_rxq *rxq = &trans_pcie->rxq;
1168 char buf[256];
1169 int pos = 0;
1170 const size_t bufsz = sizeof(buf);
1171
1172 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1173 rxq->read);
1174 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1175 rxq->write);
1176 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1177 rxq->free_count);
1178 if (rxq->rb_stts) {
1179 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1180 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1181 } else {
1182 pos += scnprintf(buf + pos, bufsz - pos,
1183 "closed_rb_num: Not Allocated\n");
1184 }
1185 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1186 }
1187
1188 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1189 char __user *user_buf,
1190 size_t count, loff_t *ppos)
1191 {
1192 struct iwl_trans *trans = file->private_data;
1193 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1194 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1195
1196 int pos = 0;
1197 char *buf;
1198 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1199 ssize_t ret;
1200
1201 buf = kzalloc(bufsz, GFP_KERNEL);
1202 if (!buf)
1203 return -ENOMEM;
1204
1205 pos += scnprintf(buf + pos, bufsz - pos,
1206 "Interrupt Statistics Report:\n");
1207
1208 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1209 isr_stats->hw);
1210 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1211 isr_stats->sw);
1212 if (isr_stats->sw || isr_stats->hw) {
1213 pos += scnprintf(buf + pos, bufsz - pos,
1214 "\tLast Restarting Code: 0x%X\n",
1215 isr_stats->err_code);
1216 }
1217 #ifdef CONFIG_IWLWIFI_DEBUG
1218 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1219 isr_stats->sch);
1220 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1221 isr_stats->alive);
1222 #endif
1223 pos += scnprintf(buf + pos, bufsz - pos,
1224 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1225
1226 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1227 isr_stats->ctkill);
1228
1229 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1230 isr_stats->wakeup);
1231
1232 pos += scnprintf(buf + pos, bufsz - pos,
1233 "Rx command responses:\t\t %u\n", isr_stats->rx);
1234
1235 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1236 isr_stats->tx);
1237
1238 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1239 isr_stats->unhandled);
1240
1241 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1242 kfree(buf);
1243 return ret;
1244 }
1245
1246 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1247 const char __user *user_buf,
1248 size_t count, loff_t *ppos)
1249 {
1250 struct iwl_trans *trans = file->private_data;
1251 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1252 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1253
1254 char buf[8];
1255 int buf_size;
1256 u32 reset_flag;
1257
1258 memset(buf, 0, sizeof(buf));
1259 buf_size = min(count, sizeof(buf) - 1);
1260 if (copy_from_user(buf, user_buf, buf_size))
1261 return -EFAULT;
1262 if (sscanf(buf, "%x", &reset_flag) != 1)
1263 return -EFAULT;
1264 if (reset_flag == 0)
1265 memset(isr_stats, 0, sizeof(*isr_stats));
1266
1267 return count;
1268 }
1269
1270 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1271 const char __user *user_buf,
1272 size_t count, loff_t *ppos)
1273 {
1274 struct iwl_trans *trans = file->private_data;
1275 char buf[8];
1276 int buf_size;
1277 int csr;
1278
1279 memset(buf, 0, sizeof(buf));
1280 buf_size = min(count, sizeof(buf) - 1);
1281 if (copy_from_user(buf, user_buf, buf_size))
1282 return -EFAULT;
1283 if (sscanf(buf, "%d", &csr) != 1)
1284 return -EFAULT;
1285
1286 iwl_pcie_dump_csr(trans);
1287
1288 return count;
1289 }
1290
1291 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1292 char __user *user_buf,
1293 size_t count, loff_t *ppos)
1294 {
1295 struct iwl_trans *trans = file->private_data;
1296 char *buf = NULL;
1297 int pos = 0;
1298 ssize_t ret = -EFAULT;
1299
1300 ret = pos = iwl_dump_fh(trans, &buf);
1301 if (buf) {
1302 ret = simple_read_from_buffer(user_buf,
1303 count, ppos, buf, pos);
1304 kfree(buf);
1305 }
1306
1307 return ret;
1308 }
1309
1310 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1311 DEBUGFS_READ_FILE_OPS(fh_reg);
1312 DEBUGFS_READ_FILE_OPS(rx_queue);
1313 DEBUGFS_READ_FILE_OPS(tx_queue);
1314 DEBUGFS_WRITE_FILE_OPS(csr);
1315
1316 /*
1317 * Create the debugfs files and directories
1318 *
1319 */
1320 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1321 struct dentry *dir)
1322 {
1323 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1324 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1325 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1326 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1327 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1328 return 0;
1329
1330 err:
1331 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1332 return -ENOMEM;
1333 }
1334 #else
1335 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1336 struct dentry *dir)
1337 {
1338 return 0;
1339 }
1340 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1341
1342 static const struct iwl_trans_ops trans_ops_pcie = {
1343 .start_hw = iwl_trans_pcie_start_hw,
1344 .stop_hw = iwl_trans_pcie_stop_hw,
1345 .fw_alive = iwl_trans_pcie_fw_alive,
1346 .start_fw = iwl_trans_pcie_start_fw,
1347 .stop_device = iwl_trans_pcie_stop_device,
1348
1349 .d3_suspend = iwl_trans_pcie_d3_suspend,
1350 .d3_resume = iwl_trans_pcie_d3_resume,
1351
1352 .send_cmd = iwl_trans_pcie_send_hcmd,
1353
1354 .tx = iwl_trans_pcie_tx,
1355 .reclaim = iwl_trans_pcie_reclaim,
1356
1357 .txq_disable = iwl_trans_pcie_txq_disable,
1358 .txq_enable = iwl_trans_pcie_txq_enable,
1359
1360 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1361
1362 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1363
1364 .write8 = iwl_trans_pcie_write8,
1365 .write32 = iwl_trans_pcie_write32,
1366 .read32 = iwl_trans_pcie_read32,
1367 .read_prph = iwl_trans_pcie_read_prph,
1368 .write_prph = iwl_trans_pcie_write_prph,
1369 .read_mem = iwl_trans_pcie_read_mem,
1370 .write_mem = iwl_trans_pcie_write_mem,
1371 .configure = iwl_trans_pcie_configure,
1372 .set_pmi = iwl_trans_pcie_set_pmi,
1373 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1374 .release_nic_access = iwl_trans_pcie_release_nic_access,
1375 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1376 };
1377
1378 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1379 const struct pci_device_id *ent,
1380 const struct iwl_cfg *cfg)
1381 {
1382 struct iwl_trans_pcie *trans_pcie;
1383 struct iwl_trans *trans;
1384 u16 pci_cmd;
1385 int err;
1386
1387 trans = kzalloc(sizeof(struct iwl_trans) +
1388 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1389 if (!trans) {
1390 err = -ENOMEM;
1391 goto out;
1392 }
1393
1394 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1395
1396 trans->ops = &trans_ops_pcie;
1397 trans->cfg = cfg;
1398 trans_lockdep_init(trans);
1399 trans_pcie->trans = trans;
1400 spin_lock_init(&trans_pcie->irq_lock);
1401 spin_lock_init(&trans_pcie->reg_lock);
1402 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1403
1404 err = pci_enable_device(pdev);
1405 if (err)
1406 goto out_no_pci;
1407
1408 if (!cfg->base_params->pcie_l1_allowed) {
1409 /*
1410 * W/A - seems to solve weird behavior. We need to remove this
1411 * if we don't want to stay in L1 all the time. This wastes a
1412 * lot of power.
1413 */
1414 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1415 PCIE_LINK_STATE_L1 |
1416 PCIE_LINK_STATE_CLKPM);
1417 }
1418
1419 pci_set_master(pdev);
1420
1421 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1422 if (!err)
1423 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1424 if (err) {
1425 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1426 if (!err)
1427 err = pci_set_consistent_dma_mask(pdev,
1428 DMA_BIT_MASK(32));
1429 /* both attempts failed: */
1430 if (err) {
1431 dev_err(&pdev->dev, "No suitable DMA available\n");
1432 goto out_pci_disable_device;
1433 }
1434 }
1435
1436 err = pci_request_regions(pdev, DRV_NAME);
1437 if (err) {
1438 dev_err(&pdev->dev, "pci_request_regions failed\n");
1439 goto out_pci_disable_device;
1440 }
1441
1442 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1443 if (!trans_pcie->hw_base) {
1444 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1445 err = -ENODEV;
1446 goto out_pci_release_regions;
1447 }
1448
1449 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1450 * PCI Tx retries from interfering with C3 CPU state */
1451 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1452
1453 err = pci_enable_msi(pdev);
1454 if (err) {
1455 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1456 /* enable rfkill interrupt: hw bug w/a */
1457 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1458 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1459 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1460 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1461 }
1462 }
1463
1464 trans->dev = &pdev->dev;
1465 trans_pcie->pci_dev = pdev;
1466 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1467 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1468 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1469 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1470
1471 /* Initialize the wait queue for commands */
1472 init_waitqueue_head(&trans_pcie->wait_command_queue);
1473
1474 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1475 "iwl_cmd_pool:%s", dev_name(trans->dev));
1476
1477 trans->dev_cmd_headroom = 0;
1478 trans->dev_cmd_pool =
1479 kmem_cache_create(trans->dev_cmd_pool_name,
1480 sizeof(struct iwl_device_cmd)
1481 + trans->dev_cmd_headroom,
1482 sizeof(void *),
1483 SLAB_HWCACHE_ALIGN,
1484 NULL);
1485
1486 if (!trans->dev_cmd_pool) {
1487 err = -ENOMEM;
1488 goto out_pci_disable_msi;
1489 }
1490
1491 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1492
1493 if (iwl_pcie_alloc_ict(trans))
1494 goto out_free_cmd_pool;
1495
1496 err = request_threaded_irq(pdev->irq, iwl_pcie_isr_ict,
1497 iwl_pcie_irq_handler,
1498 IRQF_SHARED, DRV_NAME, trans);
1499 if (err) {
1500 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1501 goto out_free_ict;
1502 }
1503
1504 return trans;
1505
1506 out_free_ict:
1507 iwl_pcie_free_ict(trans);
1508 out_free_cmd_pool:
1509 kmem_cache_destroy(trans->dev_cmd_pool);
1510 out_pci_disable_msi:
1511 pci_disable_msi(pdev);
1512 out_pci_release_regions:
1513 pci_release_regions(pdev);
1514 out_pci_disable_device:
1515 pci_disable_device(pdev);
1516 out_no_pci:
1517 kfree(trans);
1518 out:
1519 return ERR_PTR(err);
1520 }
Linux kernel - Deliverables
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